Sony LCX037BLT Datasheet

LCX037BLT

3.4cm (1.35 Type) Black-and-White LCD Panel

Description

The LCX037BLT is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX037BLT panels
provides a full-color representation. The striped
arrangement suitable for data display is capable of
displaying fine text and vertical lines.

The adoption of a new developed dot-line inverse
drive system, CMP (Chemical Mechanical Polish)
and OCS (On Chip Spacer) structures contribute to
high picture quality.

This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.

Features

• Number of active dots: 1,049,088 (1.35 Type, 3.4cm in diagonal)

• High optical transmittance: 16% (typ.)

• Dot-line inverse drive circuit

• OCS structure

• CMP (Chemical Mechanical Polish) structure

• High contrast ratio with normally white mode: 300 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

• Antidust glass package

Element Structure

• Dots: 1366 (H) × 768 (V) = 1,049,088

• Built-in peripheral driver using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal data projectors

• Liquid crystal multimedia projectors

• Liquid crystal rear-projector TVs, etc.

– 1 –

E00231-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

∗

The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.

– 2 –

LCX037BLT

V Shift Register

V Shift Register

Up/Down and/or Right/Left

Inversion Control Circuit

H Shift Register

P Shift Register

COM
PAD

COM

PAD

COM
PAD

COM
PAD

34

33

32

31

30

29

28

27 26

25

24

23

22

21

20

19

18

17

16

15 14

13

12

11

10

9

8

7

6

5

4

3

2

1

VCOM

SOUT

VV

DD

V

SS

PST

DWN

VST

VCK

COML

V

SS

HCK2

HCK1

HST

HV

DD

ENB

SIG12

SIG11

SIG10

SIG9

SIG8

SIG7

SIG6

SIG5

SIG4

SIG3

SIG2

SIG1

COMR

PSIG4

PSIG3

PSIG2

PSIG1

V

SS

G

RGT

Input Signal
Level Shifter
Circuit

Block Diagram

– 3 –

LCX037BLT

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM, COML, COMR –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PST, –1.0 to +17 V
ENB, DWN

• Video signal input pin voltage SIG1 to 12, PSIG1 to 4 –1.0 to +15 V

• Operating temperature

∗

Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

∗

Panel temperature inside the antidust glass

Operating Conditions (VSS = 0V)

• Supply voltage

HVDD 15.5 ± 0.3V
VVDD 15.5 ± 0.3V

• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal)

Vin 5.0 ± 0.5V

– 4 –

LCX037BLT

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

VSSG
PSIG1
PSIG2
PSIG3
PSIG4
COMR
SIG1
SIG2
SIG3
SIG4
SIG5
SIG6
SIG7
SIG8
SIG9
SIG10
SIG11
SIG12
HVDD
RGT
HST
HCK1
HCK2
VSS
COML
ENB
VCK
VST
DWN
PST
VSS
VVDD
SOUT
VCOM

Symbol Description

GND for V gate
Uniformity improvement signal (for black)
Uniformity improvement signal (for black)
Uniformity improvement signal (for gray)
Uniformity improvement signal (for gray)
Voltage for right CS (Storage capacity) electrode line
Video signal 1 to panel
Video signal 2 to panel
Video signal 3 to panel
Video signal 4 to panel
Video signal 5 to panel
Video signal 6 to panel
Video signal 7 to panel
Video signal 8 to panel
Video signal 9 to panel
Video signal 10 to panel
Video signal 11 to panel
Video signal 12 to panel
Power supply for H driver
Drive direction pulse for H shift register (H: normal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive 1
Clock pulse for H shift register drive 2
GND (H, V, drivers)
Voltage for left CS (storage capacity) electrode line
Enable pulse for gate selection
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: normal, L: reverse)
Start pulse for P shift register drive
GND (H, V, P drivers)
Power supply for V, P drivers
Test pin; leave this pin open.
Common voltage of panel

Pin Description

– 5 –

LCX037BLT

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)

Input

LC

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

VV

DD

Input

Level conversion circuit

(single-phase input)

250Ω250Ω

HV

DD

Input

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

HV

DD

Input

HV

DD

250Ω

250Ω

250Ω

250Ω

Level conversion circuit

(2-phase input)

Input

HV

DD

Signal line

(1) VSIG1 to VSIG12, PSIG

(2) HCK1, HCK2

(3) RGT

(4) HST

(5) PST, VCK

(6) VST, ENB, DWN

(7) VCOM, COML, COMR

1MΩ

Input

1MΩ

1MΩ

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

VV

DD

Input

1MΩ

1MΩ

1MΩ

VVDD

1MΩ

Input

1MΩ

(8) HVDD, VSSG, VVDD

are all Vss.

Level conversion circuit

(2-phase input)

– 6 –

LCX037BLT

Input Signals

1. Input signal voltage conditions (VSS = 0V)

Item

H shift register input voltage
HST, HCK1, HCK2, RGT

(Low)
(High)

(Low)

(High)

VHIL
VHIH

VVIL

VVIH
VVC

Vsig1, 3, 5, 7, 9, 11
Vsig2, 4, 6, 8
Vcom
Vpsig1, 3
Vpsig2, 4

–0.5

4.5

–0.5

4.5

7.4
VVC ± 4.4
VVC ± 4.4
VVC – 0.8
VVC ± 4.4
VVC ± 2.3

0.0

5.0

0.0

5.0

7.5
VVC ± 4.5
VVC ± 4.5
VVC – 0.7
VVC ± 4.5
VVC ± 2.5

0.4

5.5

0.4

5.5

7.6
VVC ± 4.6
VVC ± 4.6
VVC – 0.6
VVC ± 4.6
VVC ± 2.7

V
V

V

V
V

V
V
V
V
V

V shift register input voltage
VB1, VB2, BLK, VST,
VCK, PCG, ENB, DWN

Video signal center voltage

Video signal input range

∗1

Common voltage of panel

∗2

Uniformity improvement signal
input voltage

∗3

Symbol Min. Typ. Max. Unit

∗1

Input video signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.

– 7 –

LCX037BLT

Level Conversion Circuit

The LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

Sig-Center

Vsig1, 3, 5, 7, 9, 11

Time

Sig1, 3, 5, 7, 9, 11

Sig-Center

Vpsig1, 4

Time

Psig4

Sig-Center

Vsig2, 4, 6, 8, 10, 12

Time

Sig2, 4, 6, 8, 10, 12

Sig-Center

Vpsig2, 3

Time

Psig1

Psig4
Psig1

Psig2

Psig3

Psig2
Psig3

H effective period

H blanking period

Phase relationship between video signal and uniformity improvement signal

∗3

Input video signal, and a uniformity improvement signal as shown phase like below. And the rise time trPsig
and the fall time tfPsig of Psig1 to 4 are suppressed within 400ns.

– 8 –

LCX037BLT

2. Clock timing conditions (Ta = 25°C) (fHckn = 6.67MHz, fVck = 25.6kHz, fv = 60Hz)

∗4

Hckn means Hck1 and Hck2.

∗5

The minimum value of tdEnb is 800ns. When H-BLK has a long period and has some time to spare, take
more time prior to other value.

Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time

∗4

Hckn fall time

∗4

Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
Horizontal video period completed

to Enb fall time
Enb width
Vck rise/fall to Enb rise time
Enb rise to Pst rise time
Pst rise time
Pst fall time
Pst data set-up time
Pst data hold time
Pst rise to Hst rise time

trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst

thVst
trVck
tfVck
trEnb
tfEnb

tdEnb
twEnb

toEnb
toPst
trPst
tfPst
tdPst
thPst
toHst

—
—

–10

65
—

—
–15
–15

—

—

5

5
—
—
—
—

800

∗5

900
300
390

—
—

–10

65
—

—
—

0

75

—
—

0

0
—
—

10
10

—
—
—
—

1000
1000

400
400

—
—

0

75

4

30
30
10
85
30
30
15

15
100
100

15

15
100
100
100
100

1200
1100

500
410

30

30

10

85

—

ns

µs

ns

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PST

×4 cycles of Hck