LCX037BLT
3.4cm (1.35 Type) Black-and-White LCD Panel
Description
The LCX037BLT is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX037BLT panels
provides a full-color representation. The striped
arrangement suitable for data display is capable of
displaying fine text and vertical lines.
The adoption of a new developed dot-line inverse
drive system, CMP (Chemical Mechanical Polish)
and OCS (On Chip Spacer) structures contribute to
high picture quality.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
Features
• Number of active dots: 1,049,088 (1.35 Type, 3.4cm in diagonal)
• High optical transmittance: 16% (typ.)
• Dot-line inverse drive circuit
• OCS structure
• CMP (Chemical Mechanical Polish) structure
• High contrast ratio with normally white mode: 300 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• Antidust glass package
Element Structure
• Dots: 1366 (H) × 768 (V) = 1,049,088
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal multimedia projectors
• Liquid crystal rear-projector TVs, etc.
– 1 –
E00231-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
∗
The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
– 2 –
LCX037BLT
V Shift Register
V Shift Register
Up/Down and/or Right/Left
Inversion Control Circuit
H Shift Register
P Shift Register
COM
PAD
COM
PAD
COM
PAD
COM
PAD
34
33
32
31
30
29
28
27 26
25
24
23
22
21
20
19
18
17
16
15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
VCOM
SOUT
VV
DD
V
SS
PST
DWN
VST
VCK
COML
V
SS
HCK2
HCK1
HST
HV
DD
ENB
SIG12
SIG11
SIG10
SIG9
SIG8
SIG7
SIG6
SIG5
SIG4
SIG3
SIG2
SIG1
COMR
PSIG4
PSIG3
PSIG2
PSIG1
V
SS
G
RGT
Input Signal
Level Shifter
Circuit
Block Diagram
– 3 –
LCX037BLT
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage HVDD –1.0 to +20 V
• V driver supply voltage VVDD –1.0 to +20 V
• Common pad voltage COM, COML, COMR –1.0 to +17 V
• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V
RGT
• V shift register input pin voltage VST, VCK, PST, –1.0 to +17 V
ENB, DWN
• Video signal input pin voltage SIG1 to 12, PSIG1 to 4 –1.0 to +15 V
• Operating temperature
∗
Topr –10 to +70 °C
• Storage temperature Tstg –30 to +85 °C
∗
Panel temperature inside the antidust glass
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD 15.5 ± 0.3V
VVDD 15.5 ± 0.3V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal)
Vin 5.0 ± 0.5V
– 4 –
LCX037BLT
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
VSSG
PSIG1
PSIG2
PSIG3
PSIG4
COMR
SIG1
SIG2
SIG3
SIG4
SIG5
SIG6
SIG7
SIG8
SIG9
SIG10
SIG11
SIG12
HVDD
RGT
HST
HCK1
HCK2
VSS
COML
ENB
VCK
VST
DWN
PST
VSS
VVDD
SOUT
VCOM
Symbol Description
GND for V gate
Uniformity improvement signal (for black)
Uniformity improvement signal (for black)
Uniformity improvement signal (for gray)
Uniformity improvement signal (for gray)
Voltage for right CS (Storage capacity) electrode line
Video signal 1 to panel
Video signal 2 to panel
Video signal 3 to panel
Video signal 4 to panel
Video signal 5 to panel
Video signal 6 to panel
Video signal 7 to panel
Video signal 8 to panel
Video signal 9 to panel
Video signal 10 to panel
Video signal 11 to panel
Video signal 12 to panel
Power supply for H driver
Drive direction pulse for H shift register (H: normal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive 1
Clock pulse for H shift register drive 2
GND (H, V, drivers)
Voltage for left CS (storage capacity) electrode line
Enable pulse for gate selection
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: normal, L: reverse)
Start pulse for P shift register drive
GND (H, V, P drivers)
Power supply for V, P drivers
Test pin; leave this pin open.
Common voltage of panel
Pin Description
– 5 –
LCX037BLT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
Input
LC
Level conversion circuit
(single-phase input)
2.5kΩ2.5kΩ
VV
DD
Input
Level conversion circuit
(single-phase input)
250Ω250Ω
HV
DD
Input
Level conversion circuit
(single-phase input)
2.5kΩ2.5kΩ
HV
DD
Input
HV
DD
250Ω
250Ω
250Ω
250Ω
Level conversion circuit
(2-phase input)
Input
HV
DD
Signal line
(1) VSIG1 to VSIG12, PSIG
(2) HCK1, HCK2
(3) RGT
(4) HST
(5) PST, VCK
(6) VST, ENB, DWN
(7) VCOM, COML, COMR
1MΩ
Input
1MΩ
1MΩ
1MΩ
Level conversion circuit
(single-phase input)
250Ω250Ω
VV
DD
Input
1MΩ
1MΩ
1MΩ
VVDD
1MΩ
Input
1MΩ
(8) HVDD, VSSG, VVDD
are all Vss.
Level conversion circuit
(2-phase input)
– 6 –
LCX037BLT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
H shift register input voltage
HST, HCK1, HCK2, RGT
(Low)
(High)
(Low)
(High)
VHIL
VHIH
VVIL
VVIH
VVC
Vsig1, 3, 5, 7, 9, 11
Vsig2, 4, 6, 8
Vcom
Vpsig1, 3
Vpsig2, 4
–0.5
4.5
–0.5
4.5
7.4
VVC ± 4.4
VVC ± 4.4
VVC – 0.8
VVC ± 4.4
VVC ± 2.3
0.0
5.0
0.0
5.0
7.5
VVC ± 4.5
VVC ± 4.5
VVC – 0.7
VVC ± 4.5
VVC ± 2.5
0.4
5.5
0.4
5.5
7.6
VVC ± 4.6
VVC ± 4.6
VVC – 0.6
VVC ± 4.6
VVC ± 2.7
V
V
V
V
V
V
V
V
V
V
V shift register input voltage
VB1, VB2, BLK, VST,
VCK, PCG, ENB, DWN
Video signal center voltage
Video signal input range
∗1
Common voltage of panel
∗2
Uniformity improvement signal
input voltage
∗3
Symbol Min. Typ. Max. Unit
∗1
Input video signal shall be symmetrical to VVC.
∗2
The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.
– 7 –
LCX037BLT
Level Conversion Circuit
The LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
Sig-Center
Vsig1, 3, 5, 7, 9, 11
Time
Sig1, 3, 5, 7, 9, 11
Sig-Center
Vpsig1, 4
Time
Psig4
Sig-Center
Vsig2, 4, 6, 8, 10, 12
Time
Sig2, 4, 6, 8, 10, 12
Sig-Center
Vpsig2, 3
Time
Psig1
Psig4
Psig1
Psig2
Psig3
Psig2
Psig3
H effective period
H blanking period
Phase relationship between video signal and uniformity improvement signal
∗3
Input video signal, and a uniformity improvement signal as shown phase like below. And the rise time trPsig
and the fall time tfPsig of Psig1 to 4 are suppressed within 400ns.
– 8 –
LCX037BLT
2. Clock timing conditions (Ta = 25°C) (fHckn = 6.67MHz, fVck = 25.6kHz, fv = 60Hz)
∗4
Hckn means Hck1 and Hck2.
∗5
The minimum value of tdEnb is 800ns. When H-BLK has a long period and has some time to spare, take
more time prior to other value.
Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time
∗4
Hckn fall time
∗4
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
Horizontal video period completed
to Enb fall time
Enb width
Vck rise/fall to Enb rise time
Enb rise to Pst rise time
Pst rise time
Pst fall time
Pst data set-up time
Pst data hold time
Pst rise to Hst rise time
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVck
tfVck
trEnb
tfEnb
tdEnb
twEnb
toEnb
toPst
trPst
tfPst
tdPst
thPst
toHst
—
—
–10
65
—
—
–15
–15
—
—
5
5
—
—
—
—
800
∗5
900
300
390
—
—
–10
65
—
—
—
0
75
—
—
0
0
—
—
10
10
—
—
—
—
1000
1000
400
400
—
—
0
75
4
30
30
10
85
30
30
15
15
100
100
15
15
100
100
100
100
1200
1100
500
410
30
30
10
85
—
ns
µs
ns
Item Symbol Min. Typ. Max. Unit
HST
HCK
VST
VCK
ENB
PST
×4 cycles of Hck
– 9 –
LCX037BLT
∗6
Definitions: The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.
<Horizontal Shift Register Driving Waveform>
Hst rise time
HST
HCK
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time
∗4
Hckn fall time
∗4
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
• Hckn
∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn
∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn
∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
Item Symbol Waveform Conditions
90%
10%
10%
90%
Hst
trHst tfHst
50%
50%
∗
6
Hst
Hck1
tdHst thHst
50%
50%
∗
4
Hckn
10%
10%
90%
90%
trHckn tfHckn
50%
50%
∗
6
Hck1
to2Hck to1Hck
50%
50%
Hck2
– 10 –
LCX037BLT
<Vertical Shift Register Driving Waveform>
VCK
Vck rise time
Vck fall time
trVck
tfVck
Item Symbol Waveform Conditions
Vck
10%
10%
90%
90%
trVckn tfVckn
Vst rise time
VST
Vst fall time
Vst data set-up time
Vst data hold time
trVst
tfVst
tdVst
thVst
90%
10%
10%
90%
Vst
trVst tfVst
50%
50%
∗
6
Vst
Vck
tdVst thVst
50%
50%
ENB
Enb rise time
Enb fall time
Horizontal video period
completed to Enb fall time
trEnb
tfEnb
tdEnb
Enb width
Vck rise/fall to Enb fall
time
twEnb
toEnb
Enb rise to Pst rise time
toPst
90%
90%
10%
10%
tfEnb trEnb
Enb
H blanking period
H video
period
50% 50%
50%
50%
twEnb
toEnb
toPst
tdEnb
Enb
Vck
Pst
∗
6
– 11 –
LCX037BLT
Item Symbol Waveform Conditions
Pst
50%
Hst
Hckn
50%
toPst
∗
6
1 2 3 4
50%
50%
Pst
HCKn
tdPst thPst
50%
50%
PST
Pst rise time
trPst
Pst fall time
tfPst
Pst data set-up time
tdPst
Pst data set-up time
Pst rise to Hst rise time
thPst
toHst
90%
10%
10%
90%
Pst
trPst tfPst
– 12 –
LCX037BLT
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance HCKn
HST
Input pin current HCK1
HCK2
HST
RGT
Video signal input pin capacitance
Current consumption
CHckn
CHst
Csig
IH
HCK1 = GND
HCK2 = GND
HST = GND
RGT = GND
HCKn: HCK1, HCK2 (6.67MHz)
—
—
–1000
–1000
–500
–150
—
—
15
15
–500
–500
–170
–40
180
15
20
20
—
—
—
—
250
25
pF
pF
µA
µA
µA
µA
pF
mA
Symbol Min. Typ. Max. Unit Condition
2. Vertical drivers
Item
Input pin capacitance VCK
VST, PST
Input pin current VCK, PST
VST, ENB, DWN
Current consumption
CVck
CVst
IV
—
—
–500
–150
—
15
15
–150
–35
20
20
20
—
—
30
pF
pF
µA
µA
mA
Symbol Min. Typ. Max. Unit Condition
3. Total power consumption of the panel
4. Pin input resistance
Item
Pin – VSS input resistance Rpin 0.4 1 — MΩ
Symbol Min. Typ. Max. Unit
Item
Total power consumption of the panel
PWR — 550 1000 mW
Symbol Min. Typ. Max. Unit
VCK = GND, PST = GND
VST, ENB, DWN = GND
VCK: (25.6kHz)
5. Uniformity improvement signal
Item
Input pin capacitance for uniformity
improvement signal
CPSIG1
to 4
0.5 nF
Symbol Min. Typ. Max. Unit
—
5.0
– 13 –
LCX037BLT
Reflection Preventive Processing
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
Electro-optical Characteristics
Item
Contrast ratio
25°C
25°C
25°C
60°C
25°C
60°C
25°C
60°C
0°C
25°C
0°C
25°C
60°C
25°C
25°C
CR
T
RV90-25
GV90-25
BV90-25
RV90-60
GV90-60
BV90-60
RV50-25
GV50-25
BV50-25
RV50-60
GV50-60
BV50-60
RV10-25
GV10-25
BV10-25
RV10-60
GV10-60
BV10-60
ton0
ton25
toff0
toff25
F
YT60
CTK
200
13
0.9
1.0
1.2
0.9
1.0
1.1
1.3
1.4
1.5
1.2
1.3
1.4
1.7
1.8
1.9
1.7
1.8
1.8
—
—
—
—
—
—
—
300
16
1.3
1.4
1.6
1.3
1.4
1.5
1.7
1.8
1.9
1.6
1.7
1.8
2.1
2.2
2.3
2.1
2.2
2.2
24.0
9.0
99.0
27.0
–82.0
0
—
—
—
1.6
1.7
1.9
1.6
1.7
1.8
2.0
2.1
2.2
1.9
2.0
2.1
2.4
2.5
2.6
2.4
2.5
2.5
80.0
40.0
200.0
70.0
–40.0
—
5
1
2
3
4
5
6
7
—
%
V
ms
dB
s
%
Optical transmittance
V-T
characteristics
V90
V50
ON time
OFF time
V10
Response time
Flicker
Image retention time
Cross talk
Symbol Measurement method Min. Typ. Max. Unit
– 14 –
LCX037BLT
<Electro-optical Characteristics Measurement>
• Measurement system I
• Measurement system II
Luminance
Meter
Measurement
Equipment
Light Detector
Measurement
Equipment
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent
Projection lens: Focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(×24, Sensor area: 7mmφ)
Polarizer: Side of incidence-Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T
Side of output light-Polatechno's SHC-128 or equivalent
Optical fiber
LCD panel
Light receptor lens
Drive Circuit
Light
Source
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.5V, Vcom = 6.8V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.5 ± VAC [V] (VAC = signal amplitude)
Screen
LCD Projector
Approx. 2000mm
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 5.5V.
Both luminosities are measured by System I.
– 15 –
LCX037BLT
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
White luminance
T = × 100 [%] ... (2)
Luminance of light source
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.
3. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
4. Response Time
Response time ton and toff are defined by
formulas (5) and (6) respectively.
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
90
50
10
V
90 V50 V10
VAC – Signal amplitude [V]
Transmittance [%]
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON t1
ton
tOFF t2
toff
– 16 –
LCX037BLT
5. Flicker
Flicker (F) is given by formula (7). DC and AC (SXGA: 30Hz, rms) components of the panel output signal
for gray raster∗mode are measured by a DC voltmeter and a spectrum analyzer in System II.
F [dB] = 20log
{
AC component
}
...(7)
DC component
6. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.5 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
∗
Monoscope signal conditions:
Vsig = 7.5 ± 4.5 or ±2.0 [V]
(shown in the right figure)
Vcom = 6.8V
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).
Cross talk value CTK = × 100 [%]
∗
Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
Black level
White level
Vsig waveform
7.5V
0V
5.5V
2.0V
5.5V
2.0V
W1
W1
'
W3
W3
'
W2
W2
' W4'
W4
Wi' – Wi
Wi
– 17 –
LCX037BLT
Viewing angle characteristics (Typical Value)
90
270
180
0
Theta
Phi
7050
100
150
200
250
50
20
10
CR = 5
10 30
θ
φ
φ180°
X
φ270°
Y
φ0°
φ90°
Z
θ0°
Marking
Measurement method
– 18 –
LCX037BLT
Optical transmittance of LCD panel (Typical Value)
30
20
10
0
400 500 600 700
Wavelength [nm]
Trans. [%]
Measurement method: Measurement system II
– 19 –
LCX037BLT
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
(TFT substrate view from com pad)
6 dots
2 dots
768 dots
Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW
2 dots
6 dots 6 dots6 dots1 dots1 dot 1366 dots
Video
1
2
3
4
5
6
1
2
3
4
5
6
Gate: 1st
Gate: 2nd
Gate: 767th
Gate: 768th
1 1 1 1
2 2 221 1 1 1
2 2 2
767 767 767 767
767 767 767 767
Photo-Shielding
Gate: D1st
1
1
2
Active area
D1 D1 D1 D1 D1
D1 D1 D1 D1
768 768 767 768 768
768 768 768 767768
(Upper)
(Lower)
(Left) (Right)
1
2
767
<Signal input>
Down scan: For video , , , input signal prior one line from video , , .
Up scan: For video , , , input signal prior one line from video , , .
1
2
3
4
5
6
1
2
3
4
5
6
: Pixel of transistor open and close at the D1st gate
: Pixel of transistor open and close at the 1st gate
: Pixel of transistor open and close at the 2nd gate
:
: Pixel of transistor open and close at the 767th gate
D1
– 20 –
LCX037BLT
2. LCD Panel Operations
[Description of basic operations]
• To perform dot-line inverse drive, the pixel arrangement of the same gate is as shown in the diagram.
Therefore, the input signal matched to respective orrangement is requied for input signals SIG1 to 12.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 768 gate lines sequentially in a single horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1366 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 1366 × 768 dots to display a
picture in a single vertical scanning period.
– 21 –
LCX037BLT
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
the H system must be varied. The phase relationship between the start pulse and the clock for each mode is
shown below.
V effective display period 768H
VST
VCK
Gate name
765 766 767
768
1 2 3 4D1
4 3 2 1
768 767 766 765
D1
V effective display period 768H
VST
VCK
Gate name
Vertical direction display period (DWN = L)
H display period 228V
226 227 228 D11 2 3 4
HST
HCK1
PST
225 D2
HCK2
Horizontal direction display period (RGT = L)
H display period 228V
3 2 1
D1
228 227 226 225
HST
HCK1
PST
4
D2
HCK2
Horizontal direction display period (RGT = H)
Vertical direction display period (DWN = H)
RGT Mode
Right scan
Left scan
H
L
DWN Mode
Down scan
Up scan
H
L
– 22 –
LCX037BLT
3. 12-dot Simultaneous Sampling
The horizontal shift register samples signals VSIG1 to VSIG6, VSIG7 to VSIG12 simultaneously. This
requires phase matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from
deteriorating. Thus, phase matching between each signal is required using an external signal delaying
circuit before applying the video signal to the LCD panel.
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High). For left scan (RGT = Low),
the phase settings for signals VSIG1 to VSIG12 are exactly reversed.
VSIG1
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
CK12
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
VSIG8
VSIG9
VSIG10
VSIG11
VSIG12
7
8
9
10
11
12
13
14
LCX037BLT
S/H
CK11
S/H
CK10
S/H
CK9
S/H
CK8
S/H
CK7
CK6
S/H
CK5
S/H
CK4
S/H
CK3
S/H
CK2
S/H
CK1
VSIG1
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
VSIG8
VSIG9
VSIG10
VSIG11
VSIG12
15
16
17
18
– 23 –
LCX037BLT
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
CK7
CK8
CK9
CK10
CK11
CK12
Display System Block Diagram
An example of display system is shown below.
Digital
Signal
Driver
CXD2467Q
CXD3504R
R-IN
G-IN
B-IN
VSYNC
HSYNC
16
16
16
60 60
1/2
X'tal
MCK
CXA3197R CXA3512R
CXA3197R CXA3512R
CXA3197R CXA3512R
CXA3197R CXA3512R
CXA3197R CXA3512R
CXA3197R CXA3512R
LCX037
6
6
LCX037
6
6
LCX037
6
6
FRP, PRG, ENB
Timing Pulse
Selection-type
Delay Line
D/A S/H Driver
– 24 –
LCX037BLT
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the glass panel.
c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a clean-
room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the glass panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 3kg · cm or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).
– 25 –
LCX037BLT
Package Outline Unit: mm
1
2
3
4
5
7
8
9
Output light
Polarizing Axis
42.0 ± 0.15
(30.05)
(16.90)
18.0 ± 0.15
(62.6)
101.5 ± 1.4
34.0 ± 0.1
39.0 ± 0.15
4-R2.5
17.5 ± 0.05
4.9 ± 0.1
Thickness of the connector
0.3 ± 0.05
2.2 ± 0.1
2.5 ± 0.1
21.0 ± 0.15
6.0 ± 0.1
30.0 ± 0.1
Incident
light
3-φ2.3 ± 0.05
electrode (enlarged)
PIN34
PIN1
P 0.5 ± 0.02 × 33 = 16.5 ± 0.03
0.5 ± 0.1
0.5 ± 0.15
4.0 ± 0.3
0.35 ± 0.03
The rotation angle of the active area relative to H and V is ± 1°.
Active Area
Incident light
Polarizing Axis
6
weight 13.7g
Description
Molding material
Outside frame
Reinforcing board
Reinforcing material
F P C
No
1
2
3
4
5
6
Cover 1
7
8
Cover 2
9
Glass 1
Glass 2
φ2.1 ± 0.05
2.1 ± 0.05
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