Sony LCX028AMT Datasheet

LCX028AMT
4.6cm (1.8-inch) Black-and-White LCD Panel
Description
The LCX028AMT is a 4.6cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. Use of three LCX028AMT panels provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines.
The adoption of an advanced on-chip black matrix realizes a high luminance screen. And cross talk free circuit and ghost free circuit contribute to high picture quality.
This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals.
The panel contains an active area variable circuit which supports 4:3 and 16:9 data signals by changing the active area according to the type of input signal.
Features
Number of active dots: 1,310,720 (1.8-inch, 4.6cm in diagonal)
4:3 and 16:9 aspect-ratio switching function
4:3 (1280 (H) × 960 (V))
16:9 (1280 (H) × 720 (V))
High optical transmittance: 27% (typ.)
Built-in cross talk free circuit and ghost free circuit
High contrast ratio with normally white mode: 250 (typ.)
Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
Up/down and/or right/left inverse display function
Antidust glass package
Microlens used
Element Structure
Dots: 1280 (H) × 1024 (V) = 1,310,720
Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
Liquid crystal data projectors
Liquid crystal multimedia projectors
Liquid crystal rear-projector TVs, etc.
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E99230-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
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LCX028AMT
18
COM
VSIG6
VSIG5
VSIG4
VSIG3
VSIG2
VSIG1
Vss
VV
DD
HV
DD
ENB
DWN
PCG
VCK
VST
RGT
BLK
HCK2
HCK1
HST
V
SS
G
PSIG
17
20
19
22
23
16
2
24
VB1
VB2
25
29
26
28
15
30
27
COMR
9
12
11
10
8
7
4
3
5
13
6
14
VSIG7
VSIG8
VSIG9
VSIG10
VSIG11
VSIG12
1
21
COML
32
H Shift Register (Bidirectional Scanning)
Up/Down and/or Right/Left
Inversion Control Circuit
V Shift Register
(Bidirectional Scanning)
Precharge Control
Circuit
COM PAD
V Shift Register
(Bidirectional Scanning)
Black Frame Control Circuit
Black Frame Control Circuit
Input Signal Level Shifter Circuit
31
Block Diagram
– 3 –
LCX028AMT
Absolute Maximum Ratings (VSS = 0V)
H driver supply voltage HVDD –1.0 to +20 V
V driver supply voltage VVDD –1.0 to +20 V
Common pad voltage COM, COML, COMR –1.0 to +17 V
H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V
RGT
V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V BLK, ENB, DWN VB1, VB2
Video signal input pin voltage SIG1 to 12, PSIG –1.0 to +15 V
Operating temperature
Topr –10 to +70 °C
Storage temperature Tstg –30 to +85 °C
Panel temperature inside the antidust glass
Operating Conditions (VSS = 0V)
Supply voltage
HVDD 15.5 ± 0.5V VVDD 15.5 ± 0.5V
Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)
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LCX028AMT
Pin Description
Pin No.
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PSIG COMR VSIG1 VSIG2 VSIG3 VSIG4 VSIG5 VSIG6 VSIG7 VSIG8 VSIG9 VSIG10 VSIG11 VSIG12 HVDD RGT HST HCK1 HCK2 VSS COML BLK ENB VCK VST DWN VB1 VB2 PCG VVDD VSSG COM
Symbol Description
Uniformity improvement signal Voltage for right CS (storage capacity) electrode line Video signal 1 to panel Video signal 2 to panel Video signal 3 to panel Video signal 4 to panel Video signal 5 to panel Video signal 6 to panel Video signal 7 to panel Video signal 8 to panel Video signal 9 to panel Video signal 10 to panel Video signal 11 to panel Video signal 12 to panel Power supply for H driver Drive direction pulse for H shift register (H: nomal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive 1 Clock pulse for H shift register drive 2 GND (H, V drivers) Voltage for left CS (storage capacity) electrode line Black Frame display pulse Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: nomal, L: reverse) Display area switching 1 Display area switching 2 Improvement pulse for uniformity Power supply for V driver GND for V gate Common voltage of panel
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LCX028AMT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a high resistor of 1M(typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
Input
LC
Level conversion circuit
(single-phase input)
2.5k2.5k
VV
DD
Input
Level conversion circuit
(single-phase input)
250250
HV
DD
Input
Level conversion circuit
(single-phase input)
2.5k2.5k
HV
DD
Input
HV
DD
250
250
250
250
Level conversion circuit
(2-phase input)
Input
HV
DD
Signal line
(1) VSIG1 to VSIG12, PSIG
(2) HCK1, HCK2
(3) RGT
(4) HST
(5) PCG, VCK
(6) VST, BLK, ENB, DWN, VB1, VB2
(7) COM, COML, COMR
1M
Input
1M
1M
1M
Level conversion circuit
(single-phase input)
250250
VV
DD
Input
1M
1M
1M
VVDD
1M
Input
1M
(8) HVDD, VSSG, VVDD
are all Vss.
Level conversion circuit
(2-phase input)
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LCX028AMT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
H shift register input voltage HST, HCK1, HCK2, RGT
(Low) (High)
(Low)
(High)
VHIL VHIH
VVIL
VVIH VVC
Vsig Vcom VpsigB VpsigG
–0.5
4.5
–0.5
4.5
6.9 VVC – 4.5 VVC – 0.6 VVC ± 4.4 VVC ± 1.7
0.0
5.0
0.0
5.0
7.0
7.0 VVC – 0.5 VVC ± 4.5 VVC ± 1.8
0.4
5.5
0.4
5.5
7.1 VVC + 4.5 VVC – 0.4 VVC ± 4.6 VVC ± 1.9
V V
V
V V
V V
V
V shift register input voltage VB1, VB2, BLK, VST, VCK, PCG, ENB, DWN
Video signal center voltage Video signal input range
1
Common voltage of panel
2
Uniformity improvement signal input voltage (PSIG)
3
Symbol Min. Typ. Max. Unit
1
Input video signal shall be symmetrical to VVC.
2
The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower.
3
Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 400ns (as shown in a diagram below).
Level Conversion Circuit
The LCX028AMT has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
trPSIG tfPSIG
VVC
PSIG
PCG
90%
10%
PRG
4
PsigG
PsigB
Input waveform of uniformity improvement signal PSIG
4
PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.
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LCX028AMT
2. Clock timing conditions (Ta = 25°C) (SXGA mode: fHckn = 4.5MHz, fVck = 32.0kHz, fv = 60Hz)
5
Hckn means Hck1 and Hck2.
6
The minimum value of tdEnb is 450ns. When H-BLK has a long cycle and has some time to spare, take more time prior to other value.
7
Blk is the timing during 4:3 and 16:9 aspect-ratio mode, which keeps "H" level in other modes.
Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn rise time
5
Hckn fall time
5
Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time Enb rise time Enb fall time Horizontal video period completed to Enb fall time Enb rise to horizontal video period started Enb fall to Pcg rise time Enb pulse width Pcg rise time Pcg fall time Pcg rise to Vck rise/fall time Pcg fall to horizontal video period start time Pcg pulse width PRG∗4rise to Pcg rise time PRG∗4fall to Pcg fall time PRG∗4pulse width Blk rise time Blk fall time Blk rise to Enb fall time Blk fall to Pcg rise time
trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst
thVst trVck tfVck trEnb tfEnb tdEnb toPRG
4
toPcg twEnb trPcg tfPcg toVck toVideo twPcg toPcgr toPcgf twPRG
4
trBlk tfBlk toEnb toPcg
— — 35 35 —
— –15 –15
2
2 — — — —
450
6
800 750
1800
— —
–100
200
1600
–10 400
1100
— —
2 –1
— — 45 45 — —
0
0 — —
6
6 — — — —
700 1100 1000
— — —
0
270 1800
0
600 1200
— —
1 0
30 30 55 55 30 30 15
15 100 100
10
10 100 100 100 100
30
30 100
10
— 100 100
0 1
ns
µs
ns
Item Symbol Min. Typ. Max. Unit
HST
HCK
VST
VCK
ENB
PCG
BLK
5
PRG
4
µs
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LCX028AMT
8
Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement.
<Horizontal Shift Register Driving Waveform>
Hst rise time
HST
HCK
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time
5
Hckn fall time
5
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Hckn
5
duty cycle 50% to1Hck = 0ns to2Hck = 0ns
Hckn
5
duty cycle 50% to1Hck = 0ns to2Hck = 0ns
Hckn
5
duty cycle 50% to1Hck = 0ns to2Hck = 0ns
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
Item Symbol Waveform Conditions
90%
10%
10%
90%
Hst
trHst tfHst
50%
50%
8
Hst
Hck1
tdHst thHst
50%
50%
5
Hckn
10%
10%
90%
90%
trHckn tfHckn
50%
50%
8
Hck1
to2Hck to1Hck
50%
50%
Hck2
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