Sony LCX021AM Datasheet

4.1cm (1.6-inch) LCD Panel (with microlens)

Description

The LCX021AM is a 4.1cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel allows full-color representation
without color filters through the use of a microlens.
The striped arrangement suitable for data projectors
is capable of displaying fine text and vertical lines.

The adoption of an advanced on-chip black matrix
realizes high picture quality by incorporating a high
luminance screen, cross-talk free and ghost free
circuits.

This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.

The panel contains an active area variable circuit
which supports SVGA 4:3/PC98∗18:5 data signals
by changing the active area according to the type of
input signal.

∗1

"PC98" is a trademark of NEC Corporation.

Features

• The number of active dots: 1,456,000 (1.6-inch; 4.1cm in diagonal)

• Supports SVGA (804 × 3 × 604) and PC98∗1(804 × 3 × 500)

• Effective aperture ratio: 70% (reference value)

• Built-in cross talk free and ghost free circuits

• High contrast ratio with normally white mode: 150 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

Element Structure

• Dots: 804 × 3 (H) × 604 (V) = 1,456,848

• Built-in peripheral driver using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal data projectors

• Liquid crystal projectors

• Liquid crystal rear projection TV, etc.

– 1 –

E98501A94-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

LCX021AM

For the availability of this product, please contact the sales office.

– 2 –

LCX021AM

H Shift Register (Bidirectional Scanning)

Up/Down and/or Right/Left

Inversion Control Circuit

V Shift Register

(Bidirectional Scanning)

COM

PAD

V Shift Register

(Bidirectional Scanning)

COM

SIGB6
SIGB5
SIGB4
SIGB3
SIGB2
SIGB1

TEST
V

SS

VV

DD

MODE
PCG
VST
VCK
ENB
BLK
HCK2
HCK1

HST
DWN
RGT

PSIGR

Black Frame Control Circuit

Black Frame Control Circuit

Input Signal

Level

Shifter Circuit

Precharge

Control Circuit

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

4
3

25

26

27

28

30

32

33

34

35

36

38

SIGG6
SIGG5
SIGG4
SIGG3
SIGG2
SIGG1

SIGR6
SIGR5
SIGR4
SIGR3
SIGR2
SIGR1

PSIGB

PSIGG

5

31

24

37

29

HV

DD

23

39

Block Diagram

– 3 –

LCX021AM

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V

BLK, ENB, DWN, MODE

• Video signal input pin voltage SIGB1, SIGB2, SIGB3, SIGB4, –1.0 to +15 V

SIGB5, SIGB6, SIGG1, SIGG2,
SIGG3, SIGG4, SIGG5, SIGG6,
SIGR1, SIGR2, SIGR3, SIGR4,
SIGR5, SIGR6, PSIGB, PSIGG,
PSIGR

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (VSS = 0V)

• Supply voltage

HVDD 15.5 ± 0.5V
VVDD 15.5 ± 0.5V

• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

Vin 5.0 ± 0.5V

– 4 –

LCX021AM

Pin

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

NC

NC

PSIGB

PSIGG

PSIGR

SIGB1

SIGB2

SIGB3

SIGB4

SIGB5

SIGB6

SIGG1

SIGG2

SIGG3

SIGG4

SIGG5

SIGG6

SIGR1

SIGR2

SIGR3

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

SIGR4

SIGR5

SIGR6

HVDD

RGT

HST

HCK1

HCK2

VSS

BLK

ENB

VCK

VST

DWN

PCG

MODE

VVDD

TEST

COM

NC

Video signal R4 to panel

Video signal R5 to panel

Video signal R6 to panel

Power supply for H driver
Drive direction pulse for V shift

register (H: normal, L: reverse)
Start pulse for H shift register

drive
Clock pulse 1 for H shift register

drive
Clock pulse 2 for H shift register

drive
GND (H, V drivers)

Black frame display pulse

Enable pulse for gate selection
Clock pulse for V shift register

drive
Start pulse for V shift register

drive
Drive direction pulse for V shift

register (H: normal, L: reverse)
Improvement pulse for uniformity
Display area switching

(H: SVGA, L: PC98)
Power supply for V driver

Test; Open

Common voltage of panel

Leave this pin open.

Symbol Description

Pin
No.

Symbol Description

Leave this pin open.

Leave this pin open.
Blue uniformity improvement

signal
Green uniformity improvement

signal
Red uniformity improvement

signal
Video signal B1 to panel

Video signal B2 to panel

Video signal B3 to panel

Video signal B4 to panel

Video signal B5 to panel

Video signal B6 to panel

Video signal G1 to panel

Video signal G2 to panel

Video signal G3 to panel

Video signal G4 to panel

Video signal G5 to panel

Video signal G6 to panel

Video signal R1 to panel

Video signal R2 to panel

Video signal R3 to panel

Pin Description

Note) RGB video signals of Pins 6 to 23 is an example. The order of RGB can be changed.

– 5 –

LCX021AM

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except video signal inputs. All pins are connected to VSS with a high
resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)

Input

LC

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

VV

DD

Input

Level conversion circuit

(single-phase input)

250Ω250Ω

HV

DD

Input

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

HVDD

Input

HV

DD

250Ω

250Ω

250Ω

250Ω

Level conversion circuit

(2-phase input)

Input

HV

DD

Signal line

(1) SIGB1, SIGB2, SIGB3, SIGB4, SIGB5, SIGB6, SIGG1, SIGG2, SIGG3, SIGG4, SIGG5, SIGG6,

SIGR1, SIGR2, SIGR3, SIGR4, SIGR5, SIGR6, PSIGB, PSIGG, PSIGR

(2) HCK1, HCK2

(3) RGT

(4) HST

(5) PCG, VCK

(6) VST, BLK, ENB, DWN, MODE

(7) COM

1MΩ

Input

1MΩ

1MΩ

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

VV

DD

Input

1MΩ

1MΩ

1MΩ

VVDD

1MΩ

– 6 –

LCX021AM

Input Signals

1. Input signal voltage conditions (Vss = 0V)

Item

H shift register input voltage
HST, HCK1, HCK2, RGT

(Low)
(High)

(Low)
(High)

VHIL
VHIH

VVC
Vsig
Vcom

Vpsig

–0.5

4.5

6.8
VVC – 4.5
VVC – 0.5

VVC ± 4.3

0.0

5.0

7.0

7.0

VVC – 0.4
VVC ± 4.5

0.4

5.5

7.2
VVC + 4.5
VVC – 0.3

VVC ± 4.7

V
V

V
V
V

V

V shift register input voltage
MODE, BLK, VST, VCK,
PCG, ENB, DWN

Video signal center voltage
Video signal input range

∗1

Common voltage of panel

∗2

Uniformity improvement signal input
voltage (PSIGB, PSIGG, PSIGR)

∗3

Symbol Min. Typ. Max. Unit

∗1

Video input signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signals PSIGB, PSIGG and PSIGR in the same polarity with video signals
SIGB1 to 6, SIGG1 to 6 and SIGR1 to 6 and which is symmetrical to VVC. Also, the rising and falling of
PSIGB, PSIGG and PSIGR are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall
time tfPSIG are suppressed within 800ns (as shown in a diagram below).
PSIGB, PSIGG and PSIGR may change its suitable input voltage according to the drive conditions.

Uniformity Improvement Signals PSIGB, PSIGG and PSIGR Input Waveform

Level Conversion Circuit

The LCX021AM has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

trPSIG
tfPSIG

VVC

PSIGB, G, R

PCG

90%

10%

VVIL
VVIH

–0.5

4.5

0.0

5.0

0.4

5.5

V
V

– 7 –

LCX021AM

2. Clock timing conditions (Ta = 25°C) (SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz)

∗4

Hckn means Hck1 and Hck2.

Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time

∗4

Hckn fall time

∗4

Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
Vck rise/fall to Enb rise time
Horizontal video period completed to Enb fall time
Enb fall to Pcg rise time
Pcg rise time
Pcg fall time
Pcg rise to Vck rise/fall time
Pcg pulse width
Blk rise time
Blk fall time
Blk fall to Vst rise time
Blk pulse width

trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst

thVst
trVck
tfVck
trEnb
tfEnb
toEnb
tdEnb
toPcg
trPcg
tfPcg
toVck
twPcg
trBlk
tfBlk
toVst
twBlk

—
—
50
50
—

—
–15
–15

—

—

5

5
—
—
—
—

400
900
630

—
—

0

1100

—
—

1

1

—
—
60
60
—
—

0

0
—
—
10

10
—
—
—
—

500

1000

700

—
—

1000
1200

—
—
—
—

30
30
70
70
30
30
15

15
100
100

15

15
100
100
100
100

—

—

—

30

30

1100
1300

100
100

2

—

ns

µs

ns

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PCG

BLK

line

∗5

Definitions: The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.

– 8 –

LCX021AM

90%

10%

10%

90%

Hst

trHst tfHst

50%

50%

∗

5

Hst

Hck1

tdHst thHst

50%

50%

∗

3

Hckn

10%

10%

90%

90%

trHckn tfHckn

50%

50%

∗

5

Hck1

to2Hck to1Hck

50%

50%

Hck2

<Horizontal Shift Register Driving Waveform>

Hst rise time

HST

HCK

Hst fall time

Hst data set-up time

Hst data hold time

Hckn rise time

∗3

Hckn fall time

∗3

Hck1 fall to Hck2 rise time

Hck1 rise to Hck2 fall time

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Item Symbol Waveform Conditions