Sony LCX020BK Datasheet

1.8cm (0.7-inch) Color LCD Panel

Description

The LCX020BK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral driving
circuit. This panel provides full-color representation.
RGB dots are arranged in a striped pattern optimum
for data applications and capable of displaying fine
text and vertical lines.

The adoption of an advanced on-chip black matrix
realizes a high luminance screen, and high picture
quality is possible with built-in cross talk free and
ghost free circuits.

This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. In addition, the
built-in 5V interface circuit leads to lower voltage of
timing and control signals.

The panel contains a display area varying circuit
which supports Macintosh16∗1/SVGA/VGA/PC98

∗2

data signals by changing the display area according
to the type of input signal. In addition, double-speed
processed NTSC/PAL/WIDE can also be supported.

∗1

"Macintosh" is a trademark of Apple Company Inc.

∗2

"PC98" is a trademark of NEC.

Features

• Number of active dots: 1,557,000, 1.8cm (0.7-inch) in diagonal

• Supports Macintosh16 (832 × 624), SVGA (800 × 600), VGA (640 × 480) and PC98 (640 × 400) display

• Supports NTSC (640 × 480), PAL (762 × 572) and WIDE (832 × 480) display by processing the video signal

at double speed

• High optical transmittance: 1% (typ.)

• Built-in cross talk free circuit

• High contrast ratio with normally white mode: 70 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

Element Structure

• Dots: 2496 (H) × 624 (V) = 1,557,504

• Built-in peripheral driving circuit using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal EVFs for personal PCs/DVDs

• Small monitors, etc.

– 1 –

E99210-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

LCX020BK

– 2 –

LCX020BK

H Shift Register (Bidirectional Scanning)

Up/Down and/or Right/Left

Inversion Control Circuit

V Shift Register (Bidirectional Scanning)

COM

Pad

COM

SIGR6
SIGR5
SIGR4
SIGR3
SIGR2
SIGR1

V

SS

VV

DD

HV

DD

MODE1
ENB
DWN
PCG
VCK
VST
RGT
BLK
HCK2
HCK1
HST

PSIGB

Black Frame Control Circuit

Black Frame Control Circuit

MODE2

MODE3

Input Signal

Level Shifter

Circuit

Precharge

Control Circuit

1

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

31

4

2

3

24

25
26
27

28

29

30

32

33

34
35

36
37

38

SIGG6
SIGG5
SIGG4
SIGG3
SIGG2
SIGG1

SIGB6
SIGB5
SIGB4
SIGB3
SIGB2
SIGB1

PSIGR

PSIGG

V Shift Register (Bidirectional Scanning)

Black Frame Control Circuit

Block Diagram

The Block Diagram of the panel is shown below.

– 3 –

LCX020BK

Absolute Maximum Ratings (Vss = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V
BLK, ENB, DWN
MODE1, MODE2, MODE3

• Video signal input pin voltage SIGR1 to SIGR6, –1.0 to +15 V
SIGG1 to SIGG6,
SIGB1 to SIGB6,
PSIGR, PSIGG, PSIGB

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (Vss = 0V)

• Supply voltage

HVDD 15.5 ± 0.3V
VVDD 15.5 ± 0.3V

• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

Vin 5.0 ± 0.5V

Pin Description

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14

COM
PSIGR
PSIGG
PSIGB
SIGR1
SIGR2
SIGR3
SIGR4
SIGR5
SIGR6
SIGG1
SIGG2
SIGG3
SIGG4

Common voltage of panel
Uniformity improvement signal input (R)
Uniformity improvement signal input (G)
Uniformity improvement signal input (B)
Video signal input to panel (R-1)
Video signal input to panel (R-2)
Video signal input to panel (R-3)
Video signal input to panel (R-4)
Video signal input to panel (R-5)
Video signal input to panel (R-6)
Video signal input to panel (G-1)
Video signal input to panel (G-2)
Video signal input to panel (G-3)
Video signal input to panel (G-4)

Symbol Description

– 4 –

LCX020BK

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

SIGG5
SIGG6
SIGB1
SIGB2
SIGB3
SIGB4
SIGB5
SIGB6
HVDD
RGT
MODE3
MODE2
MODE1
HST
HCK1
HCK2
VSS
BLK
ENB
VCK
VST
DWN
PCG
VVDD
SOUT

Video signal input to panel (G-5)
Video signal input to panel (G-6)
Video signal input to panel (B-1)
Video signal input to panel (B-2)
Video signal input to panel (B-3)
Video signal input to panel (B-4)
Video signal input to panel (B-5)
Video signal input to panel (B-6)
Power supply input for H driver
Drive direction input for H shift register (H: normal, L: reverse)
Display area switching 3 input
Display area switching 2 input
Display area switching 1 input
Start pulse input for H shift register drive
Clock pulse input for H shift register drive
Clock pulse input for H shift register drive
GND (H, V drivers)
Black frame display pulse input
Gate selection pulse enable input
Clock pulse input for V shift register drive
Start pulse input for V shift register drive
Drive direction input for V shift register (H: normal, L: reverse)
Uniformity improvement pulse input
Power supply input for V driver
H and V shift register drive checking (Test pin; no connection.)

Pin
No.

Symbol Description

– 5 –

LCX020BK

Input Equivalent Circuits

To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except video signal inputs. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)

Input

LC

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

VVDD

Input

Level conversion circuit

(single-phase input)

250Ω250Ω

HV

DD

Input

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

HV

DD

Input

Input

HV

DD

Signal line

(1) SIGR1 to SIGR6, SIGG1 to SIGG6, SIGB1 to SIGB6, PSIGR, PSIGG, PSIGB

(2) HCK1, HCK2

(3) RGT, MODE1, MODE2, MODE3

(4) HST

(5) PCG, VCK

(6) VST, BLK, ENB, DWN

(7) COM

1MΩ

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

VV

DD

Input

1MW

1MΩ

1MΩ

VVDD

Input

HVDD

250Ω

250Ω

250Ω

250Ω

Level conversion circuit

(2-phase input)

1MΩ

1MΩ

1MΩ

– 6 –

LCX020BK

Input Signals

1. Input signal voltage conditions (Vss = 0V)

Item

H shift register input voltage
HST, HCK1, HCK2, RGT

(Low)
(High)

(Low)

(High)

VHIL
VHIH

VVIL
VVIH
VVC

Vsig
Vcom
Vpsig1
Vpsig2

–0.5

4.5

–0.5

4.5

6.9
VVC – 4.5
VVC – 0.5
VVC ± 2.0
VVC ± 4.0

0.0

5.0

0.0

5.0

7.0

7.0
VVC – 0.4
VVC ± 3.0
VVC ± 4.5

0.4

5.5

0.4

5.5

7.1
VVC + 4.5
VVC – 0.3
VVC ± 4.0
VVC ± 4.6

V
V

V

V
V

V
V
V
V

V shift register input voltage
MODE1, MODE2, MODE3,
BLK, VST, VCK, PCG,

ENB, DWN
Video signal center voltage
Video signal input range

∗1

Common pad voltage of panel

∗2

Uniformity improvement signal input
voltage (PSIGR, PSIGG, PSIGB)

∗3

Symbol Min. Typ. Max. Unit

∗1

Video input signal shall be symmetrical to VVC.

∗2

The optimum typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the
typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signals PSIGR, PSIGG and PSIGB in the same polarity with video signals
SIGR1 to 6, SIGG1 to 6 and SIGB1 to 6 and which is symmetrical to VVC. PSIGR, PSIGG and PSIGB have
two steps as shown by the waveform in the figure below, and in the table above, the upper value indicates
the signal level of the first step, and the lower value, the signal level of the second step.
Here, the rising and falling of PSIGR, PSIGG and PSIGB are synchronized with the rising of PCG pulse,
and the rise and fall times trPSIGR, trPSIGG, trPSIGB, tfPSIGR, tfPSIGG and tfPSIGB are suppressed
within 800ns.

Input waveform of uniformity improvement signal PSIG

LCX020BK level conversion circuit

The LCX020BK has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The Vcc of external ICs are applicable to 5 ± 0.5V.

trPSIGR,
trPSIGG,
trPSIGB

10%

90%

VVC

PRG

PSIGR,
PSIGG,
PSIGB

Vpsig2

Vpsig1

tfPSIGR,
tfPSIGG,
tfPSIGB

– 7 –

LCX020BK

2. Clock timing conditions (Ta = 25°C) (Macintosh16 mode: fHckn = 4.8MHz, fVck = 24.9kHz)

∗4

Hckn means Hck1 and Hck2.

∗5

Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz).
This pulse is positive polarity other than in Macintosh16 mode. Set to L level in Macintosh16 mode.

Hst rise time
Hst fall time
Hst data setup time
Hst data hold time
Hckn rise time

∗4

Hckn fall time

∗4

Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data setup time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
Vck rise/fall to Enb rise time
Horizontal video period end to Enb fall time
Enb fall to Pcg rise time
Pcg rise time
Pcg fall time
Pcg rise to Prg rise time
Pcg fall to Prg fall time
Pcg rise to Vck rise/fall time
Pcg pulse width
Blk rise time
Blk fall time
Blk fall to Vst rise time
Blk pulse width

trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst

thVst
trVck
tfVck
trEnb
tfEnb
toEnb
tdEnb
toPcg
trPcg
tfPcg
toPrgr
toPrgf
toVck
twPcg
trBlk
tfBlk
toVst
twBlk

—
—
70
15
—

—
–15
–15

—

—

5

5
—
—
—
—

400
900
900

—
—

0

200

0

1100

—
—

1

1

—
—
80
25
—
—

0

0
—
—
10

10
—
—
—
—

500
1000
1000

—
—
—

250
1000
1200

—
—
—
—

30
30
90
35
30
30
15

15
100
100

15

15
100
100
100
100

—

—

—

30

30

—

—

1100
1300

100
100

2

—

ns

µs

ns

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PCG

BLK

∗5

line

– 8 –

LCX020BK

∗6

Definitions:
The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.

<Horizontal Shift Register Driving Waveform>

Hst rise time

HST

HCK

Hst fall time

Hst data setup time

Hst data hold time

Hckn rise time

∗3

Hckn fall time

∗3

Hck1 fall
to Hck2 rise time

Hck1 rise
to Hck2 fall time

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗3

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Item Symbol Waveform Conditions

90%

10%

10%

90%

Hst

trHst tfHst

50%

50%

∗

6

Hst

Hck1

tdHst thHst

50% 50%

∗

3

Hckn

10%

10%

90%

90%

trHckn tfHckn

50%

50%

∗

6

Hck1

to2Hck to1Hck

50%

50%

Hck2