Sony LCX018AK Datasheet

1.8cm (0.7-inch) NTSC/PAL/WID Color LCD Panel

Description

The LCX018AK is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides full­color representation in NTSC/PAL/WID mode. RGB
dots are arranged in a delta pattern featuring high
picture quality of no fixed color patterns, which is
inherent in vertical stripes and mosaic pattern
arrangements.

Features

• Number of active dots: 240,000 (0.7-inch; 1.8cm in diagonal)

• Horizontal resolution: 400 TV lines

• High optical transmittance: 4.4% (typ.)

• High contrast ratio with normally white mode: 200 (typ.)

• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)

• High quality picture representation with RGB delta arranged color filters

• Full-color representation

• NTSC/PAL/WID compatible

• Up/down and/or right/left inverse display function

• Side-black function

• 16:9 and 4:3 aspect switching function

Element Structure

• Dots

16:9 display: 1068.5 (H) × 225 (V) = 240,412
4:3 display: 803.5 (H) × 225 (V) = 180,787

• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.

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E98521-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

LCX018AK

For the availability of this product, please contact the sales office.

– 2 –

LCX018AK

Block Diagram

H Shift Register (Bidirectional Scanning)

Input Signal
Level Shifter

Up/Down and/or

Right/Left Inversion

4:3/16:9 Control Circuit

V Shift Register

(Bidirectional Scanning)

Side-Black

Control Circuit

PSIG

HST

HCK1

HCK2

WID

RGT

VST

VCK1

HV

DD

VV

DD

V

SS

SIG1

SIG2

SIG3

COM

COM

Pad

PCG

DWN

EN

VCK2

12

2

9

10

7

8

16

14

15

18

17

13

6

19

3

4

5

1

11

V Shift Register

(Bidirectional Scanning)

– 3 –

LCX018AK

Absolute Maximum Ratings (Vss = 0V)

• H driver supply voltage HVDD –1.0 to +17 V

• V driver supply voltage VVDD –1.0 to +17 V

• H driver input pin voltage HST, HCK1, HCK2 –1.0 to +17 V

RGT

• V driver input pin voltage VST, VCK1, VCK2 –1.0 to +17 V
CLR, EN

• Video signal input pin voltage GREEN, RED, BLUE –1.0 to +15 V

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (Vss = 0V)

• Supply voltage

HVDD 13.5 ± 0.5 V
VVDD 13.5 ± 0.5 V

• Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin 3.0V or more

Pin Description

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

COM
PSIG
SIG1
SIG2
SIG3
HVDD
WID
RGT
HST
HCK1
HCK2
VSS
EN
VCK2
VCK1
VST
DWN
PCG
VVDD
SOUT

Common voltage of panel
Improvement signal for uniformity
Video signal (Green) to panel
Video signal (Red) to panel
Video signal (Blue) to panel
Power supply for H driver
Aspect-ratio switching (H: 16:9, L: 4:3)
Drive direction pulse for H shift register (H: normal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive
Clock pulse for H shift register drive
GND (H, V drivers)
Enable pulse for gate selection
Clock pulse for V shift register drive
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: normal, L: reverse)
Improvement pulse for uniformity
Power supply for V driver
H, V shift register drive confirmation

Symbol

Description

– 4 –

LCX018AK

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)

VVDD

250Ω

250Ω

250Ω

250Ω

Level conversion circuit

(2-phase input)

HCK1

HCK2

1MΩ

1MΩ

2.5kΩ2.5kΩ

HV

DD

Input

Level conversion circuit

(single-phase input)

250Ω250Ω

HV

DD

Input

Input

HV

DD

From H driver

Signal line

(1) SIG1, SIG2, SIG3, SID

(2) HCK1, HCK2

(3) HST

(4) RGT, WID

(5) VCK1, VCK2

2.5kΩ

2.5kΩ

VV

DD

Input

(6) VST, DWN, EN

1MΩ

VVDD

250Ω

250Ω

250Ω

250Ω

VCK1

VCK2

1MΩ

1MΩ

1MΩ

1MΩ

1MΩ

(7) PCG

250Ω250Ω

VV

DD

Input

1MΩ

Input

LC

(8) COM

1MΩ

VVDD

Level conversion circuit

(single-phase input)

Level conversion circuit

(2-phase input)

Level conversion circuit

(single-phase input)

Level conversion circuit

(single-phase input)

– 5 –

LCX018AK

Input Signals

1.Input signal voltage conditions (Vss = 0V)

Item

H driver input voltage
(HST, HCK1, HCK2, RGT, WID)

(Low)
(High)
(Low)
(High)

VHIL
VHIH
VVIL
VVIH
VVC
VCOM

–0.30

2.7

–0.30

2.7

5.8

VVC – 0.4

0.0
3

0.0
3

6.0

VVC – 0.25

0.30

5.5

0.3

5.5

6.2

VVC – 0.1

V
V
V
V
V
V

V driver input voltage
(VST, VCK1, VCK2, DWN, PCG, EN)

Video signal center voltage
Common voltage of panel

Symbol Min. Typ. Max. Unit

Item

Video signal input range

∗1

Uniformity improvement signal PSIG input voltage
Video signal and uniformity improvement signal

input white level

Vsig
Vpsig

VsigL

VVC – 4.0
VVC – 4.0

0.5

VVC + 4.0
VVC + 4.0

V
V

V

Symbol Min. Typ. Max. Unit

(VDD = 12.0V)

∗1

Video input signal should be symmetrical to VVC.

Supplement) Video signal and uniformity improvement signal input range are set within the range shown

below for VDD and VSS.
Also, video signal white level is defined for VVC as shown below.

A

A

A

VsigL

White level
VsigL

Video signal input range
Max. VDD – 1.8 [V]
Min. VSS + 1.3 [V]

VDD

VDD – 1.8

VVC

V

DD + 1.3

V

SS

AAA
AAA
AAA

– 6 –

LCX018AK

2. Clock timing conditions (Ta = 25°C)

Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn∗2rise time
Hckn∗2fall time
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vckn∗2rise time
Vckn∗2fall time
Vck1 fall to Vck2 rise time
Vck1 rise to Vck2 fall time
Enb rise time
Enb fall time
Vck rise/fall to Enb rise time
Enb pulse width
Pcg rise time
Pcg fall time
Pcg fall to Vck rise/fall time
Pcg pulse width

trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
to1Vck
to2Vck
trEnb
tfEnb
tdEnb
twEnb
trPcg
tfPcg
toVck
twPcg

35
80

–15
–15

–5.5

49

–20
–20

—

—
2150
5950

—

—

–1050

2450

45
90

0
0

4.5
59

0

0
—
—

2200
6000

—
—

–1000

2500

30
30
55

100

30
30
15

15
100
100

14.5
69

100
100

20
20

100

100
2250
6050

20

20
–950
2550

ns

µs

ns

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PCG

∗2

Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 3.72MHz, fVckn = 7.81kHz)

– 7 –

LCX018AK

<Horizontal Shift Register Driving Waveform>

Hst rise time

HST

HCK

Hst fall time

Hst data set-up time

Hst data hold time

Hckn∗2rise time

Hckn∗2fall time

Hck1 fall to
Hck2 rise time

Hck1 rise to
Hck2 fall time

• Hckn

∗2

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗2

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗2

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns

• tdHst = 60ns
thHst = –120ns

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Item Symbol Waveform Conditions

90%

10%

10%

90%

Hst

trHst tfHst

Hst

Hck1

tdHst

thHst

∗2

Hckn

10%

10%

90%

90%

trHckn tfHckn

50%

50%

∗3

Hck1

to2Hck to1Hck

50%

50%

Hck2

50%

50%

50%

50%