Sony LCX012BL Datasheet

LCX012BL

3.3cm (1.3-inch) Black-and-White LCD Panel

Description

The LCX012BL is a 3.3cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. Use of three panels in combination with the LCX012BL provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines.

The adoption of advanced on-chip black matrix realizes high picture quality without cross talk by incorporating high luminance screen and cross talk free circuit.

This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals.

Using Sony’s timing generator “CXD2442Q” sends timing signal necessary for LCD panel drive by identificating computer supporting VGA automatically, and supports double-speed processed NTSC/PAL.

Features

• The number of active dots: 312,000 (1.3-inch; 3.3cm in diagonal)

• Accepts the computer requirements of VGA platform (640 x 480)

• High optical transmittance: 25% (typ.)

• Supports NTSC/PAL by processing the video signal at double speed

• Built-in cross talk free circuit

• High contrast ratio with normally white mode: 250 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

Element Structure

• Dots: 644 (H) × 484 (V) = 311,696

• Built-in peripheral driver using polycrystalline silicon super thin film transistors.

Applications

• Liquid crystal data projectors

• Liquid crystal projectors, etc.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96512-ST

Block Diagram

NC

1

Up/Down or Right/Left

PSIG

2

11

Inversion

HST

HCK1

13

12

Input Signal

Level

Shifter

HCK2

17

NC

21

PCG

20

DWN

16

ENB

VST

RGT

10

VCK

19

18

H Shift Register (Bidrectional Scanning)

15

CLR

LCX012BL

DD

SIG2

VV

22

14

Vss

8

HV

9

SIG1

7

SIG3

6

5

SIG4

4

SIG5

3

SIG6

23

COM

V Shift Register

(Bidrectional Scanning)

Signal Control Circuit

Uniformity Improvement

V Shift Register

(Bidrectional Scanning)

COM PAD

– 2 –

LCX012BL

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V CLR, ENB, DWN

• Video signal input pin voltage SIG1, SIG2, SIG3, SIG4, –1.0 to +15 V SIG5, SIG6, PSIG

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (VSS = 0V)

Supply voltage

HVDD 15.5 ±0.5 V VVDD 15.5 ±0.5 V

Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

Vin 5.0 ±0.5 V

Pin Description

Pin No.

1

2

3

4

5

6

7

8

Symbol Description

NC

PSIG

SIG6

SIG5

SIG4

SIG3

SIG2

SIG1

NC; Open

Uniformity improvement signal

Video signal 6 to panel

Video signal 5 to panel

Video signal 4 to panel

Video signal 3 to panel

Video signal 2 to panel

Video signal 1 to panel

Pin No.

13

14

15

16

17

18

19

20

Symbol Description

HCK2

VSS

CLR

ENB

NC

VCK

VST

DWN

Clock pulse for H shift register drive

GND (H, V drivers) Improvement pulse (1) for

uniformity Enable pulse for gate selection

NC; Open Clock pulse for V shift register

drive Start pulse for V shift register

drive Drive direction pulse for V shift

register (H: normal, L: reverse)

9

10

11

12

HVDD

RGT

HST

HCK1

Power supply for H driver Driver direction pulse for H shift

register (H: normal, L: reverse) Start pulse for H shift register

drive Clock pulse for H shift register

drive

– 3 –

21

22

23

24

PCG

VVDD

COM

TEST

Improvement pulse (2) for uniformity

Power supply for V driver

Common voltage of panel

Test; Open

LCX012BL

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to VSS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)

(1) SIG1, SIG2, SIG3, SIG4, SIG5, SIG6, PSIG

DD

HV

Input

1MΩ

(2) HCK1, HCK2

Input

(3) RGT

(4) HST

(5) PCG, VCK

HV

Input

DD

250Ω

HV

VV

DD

1MΩ

2.5kΩ2.5kΩ

1MΩ

250Ω

250Ω250Ω

Signal line

Level conversion circuit

(2-phase input)

Level conversion circuit

(single-phase input)

Level conversion circuit

(single-phase input)

Input

(6) VST, CLR, ENB, DWN

Input

(7) COM

Input

VV

VVDD

DD

250Ω250Ω

1MΩ

2.5kΩ2.5kΩ

1MΩ

Level conversion circuit

(single-phase input)

Level conversion circuit

(single-phase input)

LC

– 4 –

Input Signals

1. Input signal voltage conditions (VSS = 0V)

LCX012BL

Item

(Low)

Symbol Min. Typ. Max. Unit

VHIL

–0.5

0.0

0.4

V

H driver input voltage

(High) (Low)

VHIH VVIL

4.5

–0.5

5.0

0.0

5.5

0.4

V V

V driver input voltage

(High) Video signal center voltage Video signal input range∗1(SIG1 to 6) Common voltage of panel

∗2

Uniformity improvement signal input voltage (PSIG)

∗1

input signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set

∗3

VVIH VVC Vsig Vcom

Vpsig

4.5

6.8 VVC – 4.5 VVC – 0.5

VVC ± 3.3

5.0

7.0

VVC – 0.4

VVC ± 3.5

5.5

7.2 VVC + 4.5 VVC – 0.3

VVC ± 3.7

V V V V

V

construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below).

Input waveform of uniformity improvement signal PSIG

90%

PSIG

10%

trPSIG tfPSIG

PCG

VVC

Level Conversion Circuit

The LCX012BL has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

– 5 –

LCX012BL

2. Clock timing conditions (Ta = 25°C) (VGA mode: fHCKn = 2.5MHz, fVCK = 15.7kHz) Item Symbol Min. Typ. Max. Unit

HST

HCK

CLR

VST

VCK

Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn rise time Hckn fall time

∗4

Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Clr rise time Clr fall time Vck rise/fall → Clr fall time Clr pulse width Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time

trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trClr tfClr Tdclr twClr trVst tfVst tdVst thVst trVck tfVck

— — 30 30 —

— –15 –15

—

–100 2400

—

5

5 — —

—

— 100 100

—

0

0 — —

0

2500

— —

15 15

— —

30

30 170 170

30

15

ns

15 100 100 100

2600

100 100

25

µs

25 100 100

Enb rise time Enb fall time

ENB

Vck rise/fall to Enb rise time Enb pulse width Pcg rise time Pcg fall time

PCG

Pcg rise to Vck rise/fall time Pcg pulse width

∗4

Hckn means Hck1 and Hck2.

trEnb tfEnb toEnb twEnb trPcg tfPcg toVck twPcg

— —

400

2400

—

— 500 900

— —

500

2500

— —

800

1000

100 100 600

2600

30

30 1000 1100

ns

– 6 –

Item Symbol Waveform Conditions

LCX012BL

HST

HCK

Hst rise time

Hst fall time

Hst data set-up time

Hst data hold time

Hckn rise time

Hckn fall time

∗4

Hck1 fall to Hck2 rise time

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

Hst

5

∗

Hst

Hck1

Hckn

5

∗

Hck1

90%

10%

trHst tfHst

50%

tdHst thHst

90%

∗4

10%

trHckn tfHckn

50%

90%

50%

90%

10%

50%

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

Hck1 rise to Hck2 fall time

Clr rise time

Clr fall time

to2Hck

trClr

tfClr

CLR

Clr pulse width

Vck rise/fall → Clr fall time

∗5

Definitions: The right-pointing arrow ( ) means +.

twClr

tdClr

The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement.

Hck2

Clr

Vck

Clr

∗5

50%

to2Hck to1Hck

90%

10%

trClr tfClr

50%

twClr

50%

tdClr

50%

90%

10%

O Hckn

∗4

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

– 7 –