Sony LCX009AKB Datasheet

LCX009AKB

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1.8cm (0.7-inch) NTSC/PAL Color LCD Panel

Description

The LCX009AKB is a 1.8cm diagonal active matrix
TFT-LCD panel addressed by the polycrystalline
silicon super thin film transistors with built-in
peripheral driving circuit. This panel provides full­color representation in NTSC/PAL mode. RGB dots
are arranged in a delta pattern featuring high picture
quality of no fixed color patterns, which is inherent in
vertical stripes and mosaic pattern arrangements.

Features

• The number of active dots: 180,000 (0.7-inch; 1.8cm in diagonal)

• Horizontal resolution: 400 TV lines

• High optical transmittance: 3.5% (typ.)

• High contrast ratio with normally white mode: 200 (typ.)

• Built-in H and V driving circuit (built-in input level conversion circuit, TTL drive possible)

• High quality picture representation with RGB delta arranged color filters

• Full-color representation

• NTSC/PAL compatible

• Right/left inverse display function

Element Structure

• Dots

Total dots : 827 (H) × 228 (V) = 188,556
Active dots : 800 (H) × 225 (V) = 180,000

• Built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94501C64-ST

Block Diagram

LCX009AKB

DD

VV

16

V Level
Shifter

15

SS

V

H Level
Shifter

14

VST

VCK1

VCK2

13

12

CS LC

11

EN

CLR

10

HST

RGT

9

8

H Shift Register

HCK2

7

HCK1

6

DD

RED

BLUE

HV

5

4

GREEN

COM

1

2

3

V Shift Register

COM
Pad

– 2 –

Absolute Maximum Ratings (Vss = 0V)

• H driver supply voltage HVDD –1.0 to +17 V

• V driver supply voltage VVDD –1.0 to +17 V

• H driver input pin voltage HST, HCK1, HCK2 –1.0 to +17 V

RGT

• V driver input pin voltage VST, VCK1, VCK2 –1.0 to +17 V
CLR, EN

• Video signal input pin voltage GREEN, RED, BLUE –1.0 to +15 V

• Operating temperature Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

Operating Conditions (Vss = 0V)

• Supply voltage

HVDD 13.5 ± 0.5 V
VVDD 13.5 ± 0.5 V

• Input pulse voltage (Vp-p of all input pins except video signal input pins)
Vin 3.0V or more

LCX009AKB

Pin Description

Pin
No.

1

2

3

4

5

6

7

8

Symbol Description

COM

GREEN

RED

BLUE

HVDD

HCK1

HCK2

HST

Common voltage of panel

Video signal (G) to panel

Video signal (R) to panel

Video signal (B) to panel

Power supply for H driver
Clock pulse for

H shift register drive
Clock pulse for

H shift register drive
Start pulse for

H shift register drive

Pin
No.

9

10

11

12

13

14

15

16

Symbol Description

RGT

CLR

EN

VCK1

VCK2

VST

Vss

VVDD

Drive direction pulse for H shift
register (H: normal, L: reverse)

Improvement pulse
for uniformity

Enable pulse for gate selection
Clock pulse for

V shift register drive
Clock pulse for

V shift register drive
Start pulse for

V shift register drive
GND (H, V drivers)

Power supply for V driver

– 3 –

LCX009AKB

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. The equivalent circuit of each input pin is
shown below. (The resistor value: typ.)

(1) Video signal input

From H driver

Input

HV

DD

(2) HCK1, HCK2

(3) HST

(4) RGT

(5) VCK1, VCK2

HCK1

HCK2

VCK1

VCK2

Input

Input

HV

250Ω

250Ω

VV

2.5kΩ

DD

DD

1kΩ

HV

HV

DD

DD

250Ω250Ω

2.5kΩ2.5kΩ

250Ω

250Ω

2.5kΩ

1kΩ

Signal line

Level conversion

circuit

(2-phase input)

Level conversion

circuit

(single-phase input)

Level conversion

circuit

(single-phase input)

Level conversion

circuit

(2-phase input)

(6) VST, CLR, EN

(7) COM

Input

Input

VV

DD

1MΩ

2.5kΩ2.5kΩ

Level conversion

circuit

(single-phase input)

LC

– 4 –

LCX009AKB

Level Conversion Circuit

The LCX009AKB has a built-in level conversion circuit in the clock input unit located inside the panel. The
circuit voltage is stepped up to 13.5V. This level conversion circuit meets the specifications of a 3.0V to 5.0V
power supply of the externally-driven IC mainly. However, this circuit can operate even with a 12V power
supply of the IC.

1. I/O characteristics of level conversion circuit

HVDD

(For a single-phase input unit)

An example of the I/O voltage characteristics of a
level conversion circuit is shown in the figure to the
right. The input voltage value that becomes half the

HVDD

2

Example of single-phase
I/O characteristics

output voltage (after voltage conversion) is defined
as Vth.

Output voltage (inside panel)

The Vth value varies depending on the HVDD and
VVDD voltages.
The Vth values under standard conditions are

Vth

Input voltage [V]

indicated in the table below. (HST, VST, EN, CLR, and RGT in the case of a single-phase input)

HVDD = VVDD = 13.5V

Item

Symbol Min. Typ. Max. Unit

Vth voltage of circuit Vth 0.35 1.50 2.70 V

(For a differential input unit)

An example of I/O voltage characteristics of a

HVDD

level conversion circuit for a differential input is
shown in the figure to the right. Although the
characteristics, including those of the Vth voltage,
are basically the same as those for a single­phased input, the two-phased input phase is
defined. (Refer to clock timing conditions.)

HVDD

2

Output voltage (inside panel)

Example of differential
I/O characteristics

2. Current characteristics at the input pin of level
conversion circuit

A slight pull-in current is generated at the input
pin of the level conversion circuit. (The equivalent
circuit diagram is shown to the right.) The current
volume increases as the voltage at the input pin
decreases, and is maximized when the pin is
grounded.) (Electrical characteristics are defined
by the grounded input.)

0

0

Input pin current

Max. value

Input pin voltage [V]

Pull-in current
characteristics at the
input pin

10

– 5 –

HCK1
input

Vth

Input voltage [V]

VDD

Output

HCK2
input

Level conversion equivalent circuit

Input Signals

1. Input signal voltage conditions (Vss = 0V)

LCX009AKB

Item

(Low)

Symbol Min. Typ. Max. Unit

VHIL

H driver input voltage

(High)
(Low)

VHIH
VVIL

V driver input voltage

(High)

Video signal center voltage
Video signal input range

∗1

Common voltage of panel

∗1

Video input signal should be symmetrical to VVC.

VVIH
VVC
Vsig
Vcom

2. Clock timing conditions (Ta = 25°C)
Item Symbol Min. Typ. Max. Unit

Hst rise time
Hst fall time

HST

Hst data set-up time
Hst data hold time
Hckn∗2rise time

–0.3

3.0

–0.3

3.0

5.8

VVC – 4.5

VVC – 0.55

trHst
tfHst
tdHst
thHst
trHckn

0.0

5.0

0.0

5.0

6.0

VVC – 0.40

–100
–200

0.3

5.5

0.3

5.5

6.2

VVC + 4.5

VVC – 0.25

60

–120

V
V
V
V
V
V
V

30

30
100
–50

30

HCK

CLR

VST

VCK

EN

Hckn∗2fall time
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Clr rise time
Clr fall time
Clr pulse width
Clr fall to Hst rise time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vckn∗2rise time
Vckn∗2fall time
Vck1 fall to Vck2 rise time
Vck1 rise to Vck2 fall time
En rise time
En fall time
Vck2 rise to En fall time

tfHckn
to1Hck
to2Hck
trClr
tfClr
twClr
toHst
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
to1Vck
to2Vck
trEn
tfEn
tdVck2

–15
–15

3400
1850

–50
–50

–20
–20

–20

0
0

3500
1950

32

–32

0
0

0

30

15

15
100
100

3600
2050

100
100

50
–20
100
100

20

20
100
100

20

ns

µs

ns

Vck1 rise to En rise time

∗2

Hckn and Vckn mean Hck1, Hck2 and Vck1, Vck2. (fHckn = 2.75MHz, fVckn = 7.81kHz)

tdVck1

–20

– 6 –

0

20

<Horizontal Shift Register Driving Waveform>

Item Symbol Waveform Conditions

LCX009AKB

HST

HCK

Hst rise time

Hst fall time

Hst data set-up time

Hst data hold time

Hckn∗2rise time

Hckn∗2fall time

Hck1 fall to
Hck2 rise time

Hck1 rise to
Hck2 fall time

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Hst

∗3

Hst

Hck1

Hckn

∗3

Hck1

Hck2

90%

10%

trHst tfHst

50%

50%

tdHst thHst

90%

∗2

10%

trHckn tfHckn

50%

50%

to2Hck to1Hck

90%

50%

50%

50%

90%

10%

10%

50%

∗2

• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

∗2

• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗2

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 60ns
thHst = –120ns

• tdHst = 60ns
thHst = –120ns

CLR

Clr rise time

Clr fall time

Clr pulse width

Clr fall to
Hst rise time

trClr

tfClr

twClr

toHst

Clr

Hst

Clr

90%

10%

trClr tfClr

50%

50% 50%

twClr toHst

90%

10%

∗2

• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

∗2

• Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

– 7 –