Sony ILX703A Datasheet
ILX703A
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2048-pixel CCD Linear Image Sensor (B/W) with Shutter Function
Description
The ILX703A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads B4 size documents at a density of
200 DPI (Dot Per Inch). Featuring a shutter function,
correspondences with the sensitivity correction, etc,
is possible. A built-in timing generator and clockdrivers ensure direct drive at 5V logic for easy use.
Features
• Number of effective pixels: 2048 pixels
• Pixel size: 14µm × 14µm (14µm pitch)
• Built-in timing generator and clock-drivers
• Shutter function
• Ultra low lag
• Maximum clock frequency: 5MHz
22 pin DIP (Ceramic)
Absolute Maximum Ratings
• Supply voltage VDD1 11 V
VDD2 6V
•Operating temperature –10 to +55 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
OUT
V
GND
GND
SHSW
φCLK
DD1
V
GND
DD2
V
SHUT
NC
φROG
10
11
1
2
3
4
5
6
7
8
9
1
2048
22
21
20
19
18
17
16
15
14
13
12
DD2
V
EXRS
VDD1
RSSW
VGG
GND
GND
VDD1
NC
NC
GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93124D78-PS
ILX703A
DD1
DD1
NC
GND
NC
NC
V
GND
GND
V
10
12
13
1415
16
17
20
Shutter gate
Shutter drain
D39
D38
D37
D36
D35
D34
S2048
S2047
S2
S1
D33
D15
D14
Read out gate
CCD analog shift register
Clock-drivers
Shutter gate
pulse generator
Read out gate
pulse generator
Mode
selector
9
11
4
21
19
5
SHUT
φROG
SHSW
EXRS
RSSW
φCLK
Block Diagram
DD2
V
DD2
V
22
.
Output amplifier
Sample-and-hold
circuit
1
VOUT
18
VGG
Clock pulse generator
Sample-and-hold pulse
generator
8
GND
7
V
DD1
6
GND
3
GND
2
– 2 –
Pin Description
ILX703A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
VOUT
GND
GND
SHSW
φCLK
VDD1
GND
VDD2
SHUT
NC
φROG
GND
NC
NC
VDD1
Signal output
GND
GND
Switch
Clock pulse
9V power supply
GND
5V power supply
Shutter pulse
NC
Clock pulse
GND
NC
NC
9V power supply
with S/H → GND
{
without S/H → VDD2
Description
16
17
18
19
20
21
22
GND
GND
VGG
RSSW
VDD1
EXRS
VDD2
GND
GND
Output circuit gate bias
Reset pulse swithover pin
(External RS → VDD2, Internal RS → GND)
9V power supply
RS input pin during external RS pulse usage
5V power supply
– 3 –
Recommended Voltage
ILX703A
Item
VDD1
VDD2
Min.
8.5
4.75
Typ.
9.0
5.0
Max.
9.5
5.25
Unit
V
V
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Mode Description
Mode in use Pin condition
21 pin EXRS
Yes
4 pin SHSWS/HRS
GND
19 pin RSSW
GND
Internal
GND
VDD2
Externel
No
No
VDD2
VDD2
Input Capacity of Pins
VDD2
VDD2
φRS
Item
Input capacity of φCLK pin
Input capacity of φROG pin
Input capacity of SHUT pin
Input capacity of EXRS pin
Symbol
CφCLK
CφROG
CSHUT
CEXRS
Recommended Input Pulse Voltage
Parameter
Input clock high level
Input clock low level
Min.
4.5
0.0
Typ.
5.0
—
Min.
—
—
—
—
Max.
5.5
0.5
Typ.
10
10
10
10
Unit
Max.
—
—
—
—
Unit
pF
pF
pF
pF
V
V
– 4 –
Electro-optical Characteristics
ILX703A
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz,
Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)),
When Internal RS (Pin 19 = GND, Pin 21 = VDD2)
Item
Sensitivity 1
Sensitivity 2
Sensitivity 3
Sensitivity 4
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
9V supply current
5V supply current
Total transfer efficiency
Output impedance
Offset level
Symbol
R1
R2
R3
R4
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD1
IVDD2
TTE
ZO
VOS
Min.
22.5
—
—
—
—
1.5
—
—
—
—
—
—
—
92.0
—
—
Typ.
30
95
20
500
2.0
1.8
0.3
0.5
0.02
6000
0.060
8.0
3.0
97.0
600
4.5
Max.
37.5
—
—
—
8.0
—
2.0
3.0
—
—
—
14.0
6.0
—
—
—
Unit
V/(lx · s)
V/(lx · s)
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
mA
%
Ω
V
Remarks
Note 1
Note 2
Note 3
Note 4
Note 5
—
Note 6
Note 6
Note 7
Note 8
Note 9
—
—
—
—
Note 10
Shutter lag
SHUT
0
1.0
5.0
%
Notes)
1) For the sensitivity test light is applied with a uniform intensity of illumination.
2) W lamp (2854K)
3) Light source: LED λ = 570nm
4) Light source: LED λ = 660nm
5) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU = × 100 [%]
(VMAX – VMIN)/2
VAVE
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE.
6) Integration time is 10ms.
7) VOUT = 500mV
8) DR = VSAT/VDRK
When optical accumulated time is shorter, the dynamic range gets wider because dark voitage is in
proportion to optical accumulated time.
9) SE = VSAT/R1
Note 11
– 5 –
10) VOS is defined as indicated below.
D32 D33 S1D31
OS
OS
V
GND
11) To stipulate the lag during shutter operation, use the formula below.
Place the output voltage average value during shutter operation at VSHUT and the output voltage average
value when the shutter is not in operation at VAVE. (Refer to Figure 7.)
SHUT = × 100 [%]
VSHUT
VAVE
Please note that the shutter pulse at this time accord with Figure 6.
ILX703A
– 6 –
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