Sony ILX551A Datasheet
2048-pixel CCD Linear Sensor (B/W)
Description
The ILX551A is a reduction type CCD linear sensor
designed for facsimile, image scanner and OCR use.
This sensor reads B4 size documents at a density of
200DPI (Dot Per Inch). A built-in timing generator
and clock-drivers ensure direct drive at 5V logic for
easy use.
Features
• Number of effective pixels: 2048 pixels
• Pixel size: 14µm × 14µm (14µm pitch)
• Built-in timing generator and clock-drivers
• Ultra low lag
• Maximum clock frequency: 5MHz
Absolute Maximum Ratings
• Supply voltage VDD1 11 V
VDD2 6V
•Operating temperature –10 to +55 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
Block Diagram
– 1 –
E00439-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ILX551A
22 pin DIP (Cer-DIP)
22 20 17 16 15 14 13 12 10
91142119587632
1
VOUT
Output amplifier
Sample-and-hold
circuit
V
DD2
18
NC V
DD1 GND NC NC NC NC GND NC
V
DD2φROG
SHSWV
DD2
GND
φCLK
V
DD2NCNC
NC
NC
Clock pulse generator
Sample-and-hold pulse generator
Mode
selector
Read out gate
pulse generator
Clock-drivers
CCD analog shift register
Read out gate
D14
D15
S1
D33
S2
S2047
S2048
D34
D35
D36
D37
D38
D39
1 22
V
OUT
2
NC
3
NC
4
SHSW
5
φCLK
6
NC
7
NC
8
V
DD2
9
V
DD2
10
NC
11
21
20
19
18
17
16
15
14
13
12
φROG
V
DD2
VDD2
VDD1
GND
NC
GND
NC
NC
NC
NC
GND
1
2048
– 2 –
ILX551A
Unit
pF
pF
Max.
—
—
Typ.
10
10
Min.
—
—
Symbol
CφCLK
CφROG
Item
Input capacity of φCLK pin
Input capacity of φROG pin
Input Capacity of Pins
Item
Unit
V
V
Max.
9.5
5.25
Typ.
9.0
5.0
Min.
8.5
4.75
Item
VDD1
VDD2
Recommended Supply Voltage
Pin condition
Pin 4 SHSW
GND
VDD2
Mode in use
S/H
Yes
No
Mode Description
Unit
V
V
Max.
5.5
0.5
Typ.
5.0
—
Min.
4.5
0.0
Input clock high level
Input clock low level
Recommended Input Pulse Voltage
Pin Description
Pin
No.
Symbol Description
1
2
3
4
5
6
7
8
9
10
11
VOUT
NC
NC
SHSW
φCLK
NC
NC
VDD2
VDD2
NC
φROG
Signal output
NC
NC
with S/H → GND
Switch
without S/H → VDD2
Clock pulse
NC
NC
5V power supply
5V power supply
NC
Clock pulse
Pin
No.
Symbol Description
12
13
14
15
16
17
18
19
20
21
22
GND
NC
NC
NC
NC
GND
NC
GND
VDD1
VDD2
VDD2
GND
NC
NC
NC
NC
GND
NC
GND
9V power supply
5V power supply
5V power supply
Note) Rules for raising and lowering power supply voltage
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
{
– 3 –
ILX551A
Unit Remarks
Max.
50
8.0
—
2.0
3.0
—
—
—
8.0
5.0
—
—
—
Typ.
40
2.0
1.8
0.3
0.5
0.02
6000
0.045
4.0
1.8
97.0
600
4.0
Min.
30
—
1.5
—
—
—
—
—
—
—
92.0
—
—
Symbol
R
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD1
IVDD2
TTE
ZO
VOS
Item
Electrooptical Characteristics
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm))
Notes)
1. For the sensitivity test light is applied with a uniform intensity of illumination.
2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1.
PRNU = × 100 [%]
The maximum output is set to VMAX, the minimum output to VMIN and the average output to VAVE.
3. Integration time is 10ms.
4. VOUT = 500mV
5. DR =
When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in
proportion to optical accumulated time.
6. SE =
7. Vos is defined as indicated below.
(VMAX – VMIN)/2
VAVE
VSAT
R
GND
OS
D31 D32 D33 S1
V
OS
,
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
mA
%
Ω
V
Note 1
Note 2
—
Note 3
Note 3
Note 4
Note 5
Note 6
—
—
—
—
Note 7
Secsitivity
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
9V supply current
5V supply current
Total transfer efficiency
Output impedance
Offset level
VSAT
VDRK
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