Sony ILX508A Datasheet

7926-pixel CCD Linear Image Sensor (B/W)

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Description

The ILX508A is a reduction type CCD linear sensor developed for high resolution copiers. This sensor reads A3-size documents at a density of 600 DPI (Dot Per Inch). A built-in timing generator and clock-drivers ensure direct drive at 5V logic for easy use. In addition reset pulse can switch between internal generation and external input.

Features

• Number of effective pixels: 7926 pixels

• Pixel size: 7µm × 7µm (7µm pitch)

• Built-in timing generator and clock-drivers

• Ultra high sensitivity

• Ultra low lag/low dark voltage

• Output method

• Maximum operating frequency: 12.5MHz

ILX508A

24 pin DIP (Ceramic)

Absolute Maximum Ratings

• Supply voltage VDD1 11 V

VDD2 6V

•Operation temperature –10 to +60 °C

• Storage temperature –30 to +80 °C

1

GG

Pin Configuration (Top View)

V

GND

VDD1

VOUT

GND

φROG

DD2

V

VDD2

RSSW

T1

2

3

4

5

6

7

8

9

10

1

24

23

22

21

20

19

18

17

16

15

φCLK

V

DD1

RS/SH

DD1

V

DD1

GND

DD2

V

GND

T4

T3

11

GND

12

NC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

7926

14

13

T2

NC

– 1 –

E96X33-PS

ILX508A

NC 12

13

NCT2T3T4GNDV

D116

1415

16

D115

pulse generator

D99

S7926 S7925

Mode selector Read out gate

6

11

10

22

9

DD2GNDVDD1VDD1VDD1

17

18

19

20

21

23

Clock-drivers

CCD analog shift register

Read out gate

S2 S1

D98

D18

D17

Read out gate

CCD analog shift register

Clock-drivers

24

8

Clock-pulse generator

Sample-and-hold pulse generator

7

5

3

VDD1GND VDD2GND φCLKVDD2 RSSW RS/SH T1 GND φROG

Block Diagram

• Output amplifier

• Sample-and-hold circuit

• Feed through suppression

circuit

4

OUT

V

– 2 –

2

1

VGG

Pin Description

ILX508A

Pin No.

1 2 3 4 5 6 7 8

9

10 11 12 13 14 15

Symbol VGG GND VDD1 VOUT GND φROG VDD2 VDD2

RSSW T1

GND NC NC T2 T3

Description Output circuit gate bias GND 9V power supply Signal output GND Clock pulse 5V power supply 5V power supply RS pulse external, internal selection

∗

(External RS → VDD1, Internal RS → GND) Test pin (5V) GND NC NC Test pin (GND) Test pin (5V)

16 17 18 19 20 21 22 23 24

∗

Output mode is changeable as follows.

9pin GND

VDD1

22pin

T4 GND VDD2 GND VDD1 VDD1 RS/SH VDD1 φCLK

Internal RS without S/H

Test pin (GND) GND 5V power supply GND 9V power supply 9V power supply

∗

Clock pulse or S/H switch 9V power supply Clock pulse

GND

Internal RS

with S/H

—

VDD1

—

φRS

—

External RS

without S/H

– 3 –

Recommended Voltage

ILX508A

Item VDD1 VDD2

Min.

8.5

4.75

Typ.

9.0

5.0

Max.

9.5

5.25

Note) Rules for raising and lowering power supply voltage.

To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

Clock Characteristics

Item Input capacity of φCLK Input capacity of φROG Input capacity of RS/SH

φCLK frequency φRS frequency

Symbol CφCLK CφROG C RS/SH fφCLK fφRS

Min.

— — — — —

Typ.

10 10 10

1 1

Unit

V V

Max.

— — —

12.5

Unit

pF pF

pF MHz MHz

– 4 –

ILX508A

Electrooptical Characteristics

∗1

(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Light source = 3200K, φCLK = 1MHz, Internal φRS mode without S/H,

IR cut filter, CM-500S (t = 1.0mm))

Item Sensitivity1 Sensitivity2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level

DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency

Symbol R1 R2 PRNU VSAT SE

∆V VDRK

DSNU IL IVDD1 IVDD2 TTE

Min.

7.5 — —

1.0

0.072 — —

— — — — 90

Typ.

10.8

24.6 5

1.5

0.139

1.0

0.3

0.6

0.02

16

5

97

Max.

13.9 —

12.5 — —

10.0

2

5 — 32 16 —

Unit V/(lx · s) V/(lx · s)

%

V

lx · s

mV mV

mV

% mA mA

%

Remarks

∗2 ∗3 ∗4 ∗5 ∗6

∗7 ∗8

∗9

∗10

— —

— Output impedance Offset level Dynamic range

∗1

In accorcance with the given electrooptical characteristics, the even black level is defined as the mean

ZO VOS DR

— —

500

600

3.0

5000

— — —

Ω

V

—

value of D8, D10, D12, D14, and D16.

∗2

For the sensitivity test light is applied with a uniform intensity of illumination.

∗3

W lamp (2854K).

∗4

PRNU is defined as indicated below. Ray incidence conditions are the same as for ∗2.

PRNU = × 100 [%]

(VMAX – VMIN)/2

VAVE

Where the 7926 pixels are divided into blocks of 102, even and odd pixels, respectively (Even and odd last blocks are 87.) The maximum output of each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.

∗5

Use below the minimum value of the saturation output voltage.

∗6

Saturation exposure is defined as follows.

VSAT

SE =

R1

—

∗11 ∗12

∗7

Indicates the DC difference in value between odd black level and even black level.

∗8

optical signal accumulated time τ int stands at 10ms.

∗9

The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time τ int stands at 10ms.

∗10

VOUT = 500mV (Typ.)

– 5 –