Sony CXP864P61 Datasheet

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CXP864P61

E97740A84

CMOS 8-bit Single Chip Microcomputer

Description

The CXP864P61 is the CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter, watchdog timer, 32kHz timer/counter besides the basic configurations of 8-bit CPU, PROM, RAM, I/O ports.

The CXP864P61 also provides a sleep function that enables to lower the power consumption.

The CXP864P61 is the PROM-incorporated version of the CXP86461 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V)

122µs at 32kHz operation (2.7 to 5.5V)

• Incorporated PROM 60K bytes

• Incorporated RAM 1536 bytes (Excludes VRAM for on-screen display and sprite RAM)

• Peripheral functions

— A/D converter 8 bits, 6 channels, successive approximation method

(Conversion time of 3.25µs at 16 MHz) — Serial interface 8-bit clock sync type, 1 channel — Timer 8-bit timer

8-bit timer/counter

19-bit time-base timer

32kHz timer/counter — On-screen display (OSD) function 12 × 16 dots, 52 character types

15 character colors, 2 lines × 24 characters,

frame background 8 colors/ half blanking,

background on full screen 15 colors/ half blanking

edging/ shadowing/ rounding for every line,

background with shadow for every character, double scanning,

sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot — I2C bus interface — PWM output 8 bits, 8 channels

14 bits, 1 channel — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — HSYNC counter 2 channels — Watchdog timer

• Interruption 13 factors, 13 vectors, multi-interruption possible

• Standby mode Sleep

• Package 52-pin plastic SDIP

Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

52 pin SDIP (Plastic)

Structure

Silicon gate CMOS IC

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CXP864P61

A/D CONVERTER

6CH

FIFOREMOCON

SERIAL INTERFACE

UNIT

8BIT TIMER 1

8BIT TIMER/

COUNTER 0

ON SCREEN

DISPLAY

HSYNC COUNTER 0

HSYNC COUNTER 1

C BUS

INTERFACE UNIT

8BIT PWM 14BIT PWM

PRESCALER/

TIME BASE TIMER

WATCHDOG TIMER

32kHz

TIMER/COUNTER

PROM

60K BYTES

RAM

1536 BYTES

SPC700 CPU CORE

CLOCK GENERATOR

/SYSTEM CONTROL

INTERRUPT CONTROLLER

PWM

PORT G

PG7 1

PORT E

PE4 to PE6 3

PE2 to PE3 2

PE0 to PE1 2

PORT D

PD0 to PD7

PORT B

PB0 to PB7 8

PORT A

PA0 to PA7 8

PWM0 to PWM5

ADJ

SCL1 SCL0

SDA1 SDA0

HS1

HS0

VSYNC

HSYNC

EXLC

XLC

SCK

RMC

AN0 to AN5

INT0

INT1

INT2

TEX

EXTAL

XTAL

RST

PORT F

PF0 to PF7 8

Block Diagram

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CXP864P61

40 39 38 37 36 35 34 33

2 3 4

5 6 7 8 9

10 11 12 13 14 15 16 17 18 19

20 21 22 23

24 25 26

HS0/PD4

EC/PD7

RMC/PD6

HS1/PD5

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

PA0/AN0

XTAL

EXTAL PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1

PB7 PB6 PB5 PB4 PB3

INT1/PG7

VSS VDD Vpp EXLC XLC PE4/YM PE5/YS PE6/I B G R PB0 PB1 PB2

PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0 PF5/SCL1/PWM4 PF6/SDA0 PF7/SDA1/PWM5 PE0/TO/ADJ PE1/PWM PE2/TEX/INT0 PE3/TX

Pin Assignment (Top View)

Note)

1. Vpp (Pin 38) is left open.

2. Vss (Pins 12 and 40) are both connected to GND.

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CXP864P61

(Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)

(Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)

(Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins)

(Port E) Bits 0 and 1 are I/O port; I/O can be set in a unit of single bit. Bits 2 and 3 are input port. Bits 4, 5 and 6 are output port. (7 pins)

Pin Description

Symbol

PA0/AN0

PA5/AN5 PA6/VSYNC PA7/HSYNC

PB0 to PB7

PD0/INT2 PD1/SCK

PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC

PE0/TO/ADJ PE1/PWM

PE2/TEX/INT0

PE3/TX

PE4/YM PE5/YS PE6/I B G R PF0/PWM0 to

PF3/PWM3 PF4/SCL0 PF5/SCL1/

PWM4 PF6/SDA0 PF7/SDA1/

PWM5

I/O/ Analog input

I/O/Input I/O/Input

I/O

I/O/Input I/O/I/O

I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input I/O/Output/

Output I/O/Output

Input/Input/ Input

Input/Output

Output/Output Output/Output Output/Output Output Output Output

Output/Output Output/I/O

Output/I/O/ Output

Output/I/O Output/I/O/

Output

I/O

Description

Analog inputs to A/D converter. (6 pins)

OSD display vertical sync signal input. OSD display horizontal sync signal input.

External interruption request input. Active at the falling edge.

Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input. Remote control reception circuit input. External event input for timer/counter. Rectangular wave output

for 8-bit timer/counter. 14-bit PWM output.

Connects a crystal for 32kHz timer/counter clock oscillation. When used as an event counter, input to TEX pin and leave TX pin open.

32kHz oscillation frequency dividing output.

External interruption request input. Active at the falling edge.

OSD display 6-bit output. (6 pins)

(Port F) 8-bit output port. Open drain output of large current (12mA) and N channel. Lower 4 bits are medium drive voltage (12V); upper 4 bits are 5V drive. (8 pins)

8-bit PWM output. (4 pins)

I2C bus interface transfer clock I/O. (2 pins)

I2C bus interface transfer data I/O. (2 pins)

8-bit PWM output.

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CXP864P61

(Port G) 1-bit I/O port. I/O can be set in a unit of single bits. (1 pin)

Connects a crystal for system clock oscillation. When a clock is supplied externally, input to EXTAL pin and input a reversed phase clock to XTAL pin.

System reset; active at Low level. OSD display clock oscillation I/O. Oscillation frequency is determined

by the external L and C. Positive power supply.

GND. Connect two Vss pins to GND. Positive power supply for incorporated-PROM writing.

No connected for normal operation.

Symbol

PG7/INT1

EXTAL XTAL

RST EXLC XLC VDD Vss

Vpp

I/O/Input

Input Output Input

Input Output

I/O Description

External interruption request input. Active at the falling edge.

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CXP864P61

Input/Output Circuit Formats for Pins

Port A

Port B Port G

6 pins

2 pins

9 pins

Hi-Z

Pin When resetCircuit format

PA6/VSYNC PA7/HSYNC

PB0 to PB7 PG7/INT1

PA0/AN0

PA5/AN5

Port F data

Port F function selection

“0” when reset

“1” when reset

PWM0 to PWM3

∗

12V drive voltage

Large current 12mA

∗

Port F

4 pins

PF0/PWM0

PF3/PWM3

Hi-Z

Data bus

Port A function selection

“0” when reset

A/D converter

Data bus

RD (Port A)

Input multiplexer

RD (Port A)

Port A data

Port A direction

“0” when reset

Port A data

Port A direction

"0" when reset

Schmitt input

Input protection circuit

HSYNC, VSYNC

Data bus

RD (Ports B, C, G)

INT1

Ports B, G data

Ports B, G direction

“0” when reset

Input polarity

"0" when reset

Schmitt input for PB0, PB1, PB2, and PG7

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CXP864P61

Port D

Port E

6 pins

2 pins

1 pin

Hi-Z

High level (with the resistor of pull-up transister ON when reset)

Pin When resetCircuit format

PD1/SCK PD2/SO

PE0/TO/ADJ

PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC

Data bus

INT2, SI, HS0, HS1, RMC, EC

SCK, SO

SIO output enable

Port D data

Port D direction

“0” when reset

Data bus

RD (Port D)

Port D data

Port D direction

“0” when reset

Schmitt input

∗

Large current 12mA

∗

SCK only

Port E data

“1” when reset

ADJ16K

ADJ2K

Port E function selection (Upper) Port E function selection (Lower)

“00” when reset

Port E direction

“1” when reset

Data bus

RD (Port E)

RD (Port D)

Internal reset signal

∗

01 10 11

PD2 is not Schmitt input.

MPX

∗

ADJ signals are frequency dividing outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output.

∗

Pull-up resistors approx. 150kΩ

∗

Large current 12mA

∗2

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