Sony CXP858P56A Datasheet

CXP858P56A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP858P56A is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen display function, I2C bus interface, PWM output, remote control reception circuit, HSYNC counter and watchdog timer as well as basic configuration like 8-bit CPU, PROM, RAM and I/O port.
Also this IC provides a power-on reset function and sleep function that enables to lower power consumption.
The CXP858P56A is the PROM-incorporated version of the CXP85856A with built-in mask ROM. This provides the additional feature of being able to write directly into the program (also into the OSD character ROM or caption character ROM possible). Thus, system development and for small-quantity production.
Features
A wide instruction set (213 instructions) which covers various types of data
Minimum instruction cycle 333ns at 12MHz operation
Incorporated PROM 56K bytes (Programming)
Incorporated RAM 2176 bytes (Excludes the closed caption decoder and on-screen display VRAM)
Peripheral functions
Interruption 15 factors, 15 vectors, multi-interruption possible
Standby mode Sleep
Package 64-pin plastic SDIP/QFP
it is most suitable for evaluation use during
– 16-bit operation/multiplication and division/Boolean bit operation instructions
4.5K bytes (OSD) 3K bytes (Caption)
– A/D converter 8-bit 6-channel successive approximation method
(Conversion time of 26.7µs at 12MHz) – Serial interface 8-bit clock sync type, 1 channel – Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer – Closed caption decoder
Incorporated data slicer,
conforming to FCC (EDS supported), 8 × 13 dots, 192 character types,
15 character colors, 4 lines × 34 characters, italic, underline, vertical scrolling,
15 frame background colors/half blanking – On-screen display (OSD) function
12 × 16 dots, 192 character types, 15 character colors, 2 lines × 24 characters,
8 frame background colors/half blanking,
15 background colors on full screen/half blanking,
edging and vertical scrolling for every line,
jitter elimination circuit,
sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot – I2C bus interface – PWM output 8 bits, 8 channels – Remote control reception circuit
8-bit pulse measurement counter, 6-stage FIFO – HSYNC counter 2 channels – Watchdog timer
64 pin SDIP (PIastic) 64 pin QFP (PIastic)
Structure
Silicon gate CMOS IC
urchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97738-PS
CXP858P56A
DD
Vpp Vss V MP
RST XTAL EXTAL
INT2 INT1 INT0
CLOCK G ENERATOR^
PA0‘PA7
8
SYSTEM CO NTROL
SPC700 CPU CORE
PB0‘PB6
7
PO R T A
PO R T B
PC0‘PC7
8
PO R T C
PD0‘PD7
8
PO R T D
PE0‘PE2
3
PF0‘PF7
8
PO R T E
PO R T F
RAM
2176 BYTES
8
PW M 0‘PW M 7
8BIT PW M
PROM
56K BYTES
PRESC ALER^
TIME BASE TIMER
W ATCHDOG TIMER
SCL1 SCL0
C BUS
2
I
SDA1
SDA0
INTERFACE UNIT
INTERRUPT CONTROLLER
CVss CV
DD
Cap LFC 2
DATA SLICER
LFC 1
Block Diagram
3
2
FIFO
2
8BIT TIM ER^COUNTER 0
EC
8BIT TIMER 1
TO
A^D CO NVERTER
REMO CON
RM C
HSYNC COUNTER 0
HSC0
HSYNC COUNTER 1
6
HSC1
CC DECODER
ON SCR EEN DISPLAY
I
B
R
VIN
XLC
G
EXLC
YS
YM
HSYN C
SERIAL INTERFACE UNIT
SI
SO
SCK
VSYNC
AN0‘AN5
– 2 –
Pin Assignment (Top View) 64-pin SDIP
CXP858P56A
PC3 PC2
PC1 PC0
EC/PD7
RMC/PD6
HS1/PD5 HS0/PD4
SI/PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
Vss
XTAL
EXTAL PA5/AN5 PA4/AN4 PA3/AN3
PA2/AN2 PA1/AN1 PA0/AN0
CVss LFC2 LFC1
VIN
CV
Cap
INT1/PB6
PB5
DD
10 11 12
14 15
26
29 30
32
13
16 17 18 19 20 21 22 23 24 25
27 28
31
1
2 3 4
5 6 7 8 9
64 63 62 61 60
59
58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
43
42
41 40 39
38 37 36 35
34 33
PC4 PC5
PC6 PC7 PF0/PWM0 PF1/PWM1 PF2/PWM2 PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0/TO PE1 PE2/INT0 MP Vss
DD
V Vpp EXLC XLC
YM YS I B G
R PB0 PB1 PB2
PB3 PB4
Note) 1. Vpp (Pin 46) must be connected to VDD.
2. Vss (Pins 16 and 48) must be connected to GND.
3. MP (Pin 49) must be connected to GND.
– 3 –
Pin Assignment (Top View) 64-pin QFP
CXP858P56A
HS1/PD5 HS0/PD4
SI/PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7 VSYNC/PA6
RST
Vss
XTAL
EXTAL
PA5/AN5
PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0
CVss
12 13 14 15 16 17 18 19
10 11
PD6/RMC
PC0
62
64
63
61
60
1
2 3 4
5 6 7 8 9
PC2
59
PC3
58
PC4
57
PC1
PD7/EC
PC5
56
PC6
55
PC7
54
PF2/PWM2
PF1/PWM1
PF0/PWM0
52
53
51 50 49 48 47 46 45 44
42
40 39
37 36 35
33
43
41
38
34
PF3/PWM3 PF4/SCL0/PWM4 PF5/SCL1/PWM5 PF6/SDA0/PWM6 PF7/SDA1/PWM7 PE0//TO PE1 PE2/INT0
MP Vss
V
DD
Vpp EXLC XLC
YM YS I B G
20
21
LFC2
22
LFC1
VIN
23
DD
CV
24
Cap
25
26
INT1/PB6
27
PB5
28
PB4
29
PB3
PB2
Note) 1. Vpp (Pin 40) must be connected to VDD.
2. Vss (Pins 10 and 42) must be connected to GND.
3. MP (Pin 43) must be connected to GND.
30
PB1
31
32
R
PB0
– 4 –
Pin Description
CXP858P56A
Symbol
PA0/AN0
to
PA5/AN5 PA6/VSYNC PA7/HSYNC
PB0 to PB5
PB6/INT1
PC0 to PC7
PD0/INT2 PD1/SCK
PD2/SO PD3/SI PD4/HS0 PD5/HS1 PD6/RMC
I/O
I/O/Analog input
I/O/Input I/O/Input
I/O
I/O/Input
I/O
I/O/Input I/O/I/O
I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input
Description
(Port A) 8-bit I/O port. I/O
Analog inputs to A/D converter. (6 pins)
can be set in a unit of single bits. (8 pins)
OSD display vertical sync signal input. OSD display horizontal sync signal input.
(Port B) 7-bit I/O port. I/O can be set in a unit of single bits. (7 pins)
External interruption request input. Active at the falling edge.
(Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)
External interruption request input. Active at the falling edge.
(Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA synk current. (8 pins)
Serial clock I/O. Serial data output. Serial data input. HSYNC counter (CH0) input. HSYNC counter (CH1) input.
Remote control reception circuit input. PD7/EC PE0/TO PE1
PE2/INT0 PF0/PWM0
to
PF3/PWM3 PF4/SCL0/PWM4
PF5/SCL1/PWM5 PF6/SDA0/PWM6
PF7/SDA1/PWM7 R, G, B, I, YS, YM
I/O/Input I/O/Output I/O
I/O/Input
Output/Output
Output/I/O
Output/I/O
Output
External event input for timer/counter.
(Port E)
Rectangular wave output for timer/counter.
3-bit I/O port. I/O can be set in a unit of single bits. (3 pins)
(Port F) 8-bit output port and large current
Input for external interruption request.
Active at the falling edge.
8-bit PWM outputs.
(8 pins)
(12mA) N-ch open drain output. Lower 4 bits are
Transfer clock I/O for I2C bus interface.
(2 pins)
medium drive voltage (12V);upper 4 bits are
5V drive. (8 pins)
Transfer data I/O for I2C bus interface.
(2 pins)
6-bit OSD display outputs. (6 pins)
– 5 –
CXP858P56A
Symbol EXLC XLC
VIN Cap
LFC1, LFC2 CVDD CVSS EXTAL XTAL
RST
MP Vpp VDD
I/O Description Input Output
Input
OSD display clock oscillation I/O. Oscillator frequency is determined by the external L and C.
External composite video signal input. Input a 2Vp-p signal via a capacitor.
Connects a capacitor for the data slicer between Cap and CVSS. Connects a capacitor for the PLL circuit LPF between LFC1 and LFC2. Positive power supply for data slicer.
GND for data slicer. Input Output
Connects a crystal for system clock oscillation. When an external
clock is supplied, input it to EXTAL and leave XTAL open.
System reset; active at Low level. I/O pin. I/O
Outputs a Low level when the power is turned on and the power-on
reset function operates. Input
Test mode input. Must be connected to GND.
Positive power supply for internal PROM writing.
Under normal conditions, connect to VDD.
Positive power supply.
Vss
GND. Connect two VSS pins to GND.
– 6 –
Input/Output Circuit Format for Pins
Pin When resetCircuit format
Port A
CXP858P56A
Port A data
PA0/AN0
to
PA5/AN5
6 pins
PA6/VSYNC PA7/HSYNC
Data bus
Port A function selection
“0” when reset
A/D converter
Port A
Data bus
Port A direction “0” when reset
RD (Port A)
RD (Port A)
Input multiplexer
Port A data
Port A direction
“0” when reset
Schmitt input
IP
IP
Input protection circuit
Hi-Z
Hi-Z
2 pins
PB0 to PB5 PB6/INT1 PC0 to PC7
15 pins
VSYNC, HSYNC
Port B
Port C
Data bus
Ports B, C data
Ports B, C direction
“0” when reset
RD (Ports B, C)
INT1
Input polarity
“0” when reset
IP
Hi-Z
Schmitt input
– 7 –
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