Sony CXP85856A, CXP85848A, CXP85840A Datasheet
Description
The CXP85840A/85848A/85856A are the CMOS 8-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, closed caption decoder, data slicer, on-screen
display function, I2C bus interface, PWM output,
remote control reception circuit, HSYNC counter and
watchdog timer, besides the basic configurations of
8-bit CPU, ROM, RAM, I/O ports.
The CXP85840A/85848A/85856A also provide a
power-on reset function and sleep function that
enables to lower the power consumption.
Features
• A wide instruction set (213 instructions) which covers
various types of data
– 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle 333ns at 12MHz operation
• Incorporated ROM 40K bytes (CXP85840A)
48K bytes (CXP85848A)
56K bytes (CXP85856A)
• Incorporated RAM 2176 bytes (Excludes closed caption decoder and VRAM for on-screen display)
• Peripheral functions
– A/D converter 8-bit 6-channel successive approximation method
(Conversion time of 26.7µs at 12MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer
8-bit timer/counter
19-bit time-base timer
– Closed caption decoder Data slicer
Corresponds to FCC (EDS supported), 8 × 13 dots, 192 character types
15 character colors, 4 lines × 34 characters
frame background 15 colors/ half blanking
italic, underline, vertical scrolling
– On-screen display (OSD) function 12 × 16 dots, 192 character types, 15 character colors
2 lines × 24 characters
frame background 8 colors/ half blanking
background on full screen 15 colors/ half blanking
edging and vertical scrolling for every line
jitter elimination circuit
sprite OSD, 12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output 8 bits, 8 channels
– Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter 2 channels
– Watchdog timer
• Interruption 15 factors, 15 vectors, multi-interruption possible
• Standby mode Sleep
• Package 64-pin plastic SDIP/QFP
• Piggyback/evaluator CXP85890A 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
– 1 –
CXP85840A/85848A/85856A
E97739A86
CMOS 8-bit Single Chip Microcomputer
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin SDIP (Plastic) 64 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
– 2 –
CXP85840A/85848A/85856A
VIN
XLC
EXLC
R
G
B
I
YS
YM
HSYNC
VSYNC
SI
SO
SCK
EC
TO
RMC
HSC0
HSC1
AN0 to AN5
CVss
CV
DD
Cap
LFC2
DATA SLICER
CC DECODER
ON SCREEN DISPLAY
SERIAL INTERFACE UNIT
8BIT TIMER/COUNTER 0
REMOCON
HSYNC COUNTER 0
HSYNC COUNTER 1
A/D CONVERTER
FIFO
3
2
INT2
INT1
INT0
SCL1
SCL0
SDA1
SDA0
I
2
C BUS
INTERFACE UNIT
8BIT PWM
WATCHDOG TIMER
PRESCALER/
TIME BASE TIMER
SPC700 CPU CORE
ROM
40K/48K/56K BYTES
CLOCK GENERATOR/
SYSTEM CONTROL
RAM
2176 BYTES
Vss
V
DD
MP
RST
XTAL
EXTAL
PWM0 to PWM7
PORT A
PA0 to PA7
8
PB0 to PB6
7
PC0 to PC7
8
PD0 to PD7
8
PE0 to PE2
3
PF0 to PF7
8
INTERRUPT CONTROLLER
PORT BPORT CPORT DPORT EPORT F
8BIT TIMER 1
2
LFC1
8
6
Block Diagram
– 3 –
CXP85840A/85848A/85856A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
PC3
PC2
PC1
PC0
EC/PD7
RMC/PD6
HS1/PD5
HS0/PD4
SI/ PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
Vss
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
CVss
LFC2
LFC1
VIN
CV
DD
Cap
INT1/PB6
PB5
PC4
PC5
PC6
PC7
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7
PE0/TO
PE1
PE2/INT0
MP
Vss
V
DD
NC
EXLC
XLC
YM
YS
I
B
G
R
PB0
PB1
PB2
PB3
PB4
Note)
1. NC (Pin 46) is always connected to VDD.
2. Vss (Pins 16 and 48) are both connected to GND.
3. MP (Pin 49) is always connected to GND.
Pin Assignment (Top View) 64-pin SDIP
– 4 –
CXP85840A/85848A/85856A
Note)
1. NC (Pin 40) is always connected to VDD.
2. Vss (Pins 10 and 42) are both connected to GND.
3. MP (Pin 43) is always connected to GND.
HS1/PD5
HS0/PD4
SI/PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
Vss
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
CVss
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1
PF3/PWM3
PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7
PE0/TO
PE1
PE2/INT0
MP
Vss
V
DD
NC
EXLC
XLC
YM
YS
I
B
G
40
39
38
37
36
35
34
33
41
42
43
44
45
46
47
48
49
50
51
PD6/RMC
PD7/EC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PF0/PWM0
PF1/PWM1
PF2/PWM2
52
53
54
55
56
57
58
59
60
63
64
61
62
LFC2
LFC1
VIN
CV
DD
Cap
INT1/PB6
PB5
PB4
PB3
PB2
PB1
PB0
R
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Assignment (Top View) 64-pin QFP
– 5 –
CXP85840A/85848A/85856A
(Port A)
8-bit I/O port. I/O
can be set in a unit
of single bits.
(8 pins)
(Port B)
7-bit I/O port. I/O can be set in a unit of single bits.
(7 pins)
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port D)
8-bit I/O port.
I/O can be set in a
unit of single bits.
Can drive 12mA
synk current.
(8 pins)
(Port E)
3-bit I/O port.
I/O can be set in a
unit of single bits.
(3 pins)
(Port F)
8-bit output port
and large current
(12mA) N-channel
open drain output.
Lower 4 bits are
medium drive voltage
(12V); upper 4 bits
are 5V drive.
(8 pins)
6-bit OSD display output. (6 pins)
Pin Description
Symbol
PA0/AN0
to
PA5/AN5
PA6/VSYNC
PA7/HSYNC
PB0 to PB5
PB6/INT1
PC0 to PC7
PD0/INT2
PD1/SCK
PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
PD7/EC
PE0/TO
PE1
PE2/INT0
PF0/PWM0
to
PF3/PWM3
PF4/SCL0/PWM4
PF5/SCL1/PWM5
PF6/SDA0/PWM6
PF7/SDA1/PWM7
R, G, B, I, YS, YM
I/O/
Analog input
I/O/Input
I/O/Input
I/O
I/O/Input
I/O
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Output
I/O
I/O/Input
Output/Output
Output/I/O
Output/I/O
Output
I/O
Description
Analog inputs to A/D converter.
(6 pins)
OSD display vertical sync signal input.
OSD display horizontal sync signal input.
External interruption request input.
Active at the falling edge.
External interruption request input.
Active at the falling edge.
Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.
Remote control reception circuit input.
External event input for timer/counter.
Rectangular wave output for timer/counter
External interruption request input.
Active at the falling edge.
8-bit PWM output. (8 pins)
I2C bus interface transfer clock I/O.
(2 pins)
I2C bus interface transfer data I/O.
(2 pins)
– 6 –
CXP85840A/85848A/85856A
Symbol
EXLC
XLC
VIN
Cap
LFC1, LFC2
CVDD
CVss
EXTAL
XTAL
RST
MP
NC
VDD
Vss
Input
Output
Input
—
—
Input
Output
I/O
Input
OSD display clock oscillation I/O.
Oscillation frequency is determined by the external L and C.
External composite video signal input.
Input the 2Vp-p signal via a capacitor.
Connects a data slicer capacitor between Cap and CVss.
Connects a low-pass filter capacitor for PLL circuit between LFC1 and
LFC2.
Positive power supply for data slicer.
GND for data slicer.
Connects a crystal for system clock oscillation. When a clock is
supplied externally, input it to EXTAL and leave XTAL open.
System reset; active at Low level. I/O pin. Outputs a Low level when the
power is turned on and the internal power-on reset function operates.
(Mask option)
Test mode pin. Always connect to GND.
No connected.
Under normal operation, connect to VDD.
Positive power supply.
GND. Connect two Vss pins to GND.
I/O Description
– 7 –
CXP85840A/85848A/85856A
Input/Output Circuit Formats for Pins
Port A
Port A
Port B
Port C
2 pins
6 pins
15 pins
Hi-Z
Hi-Z
Hi-Z
Pin When resetCircuit format
PA0/AN0
to
PA5/AN5
PB0 to PB5
PB6/INT1
PC0 to PC7
PA6/VSYNC
PA7/HSYNC
Data bus
RD (Port A)
Port A function selection
“0” when reset
A/D converter
Port A data
Port A direction
“0” when reset
Port A data
Port A direction
“0” when reset
Input multiplexer
IP
Input
protection
circuit
IP
VSYNC, HSYNC
Data bus
Data bus
RD (Port A)
Ports B, C data
Ports B, C direction
“0” when reset
RD (Ports B, C)
Schmitt input
Input polarity
“0” when reset
IP
Schmitt input
INT1
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