Sony CXP856P40 Datasheet

CMOS 8-bit Single Chip Microcomputer

For the availability of this product, please contact the sales office.

Description

The CXP856P40 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time-base timer, closed caption decoder,
data slicer, on-screen display function, I2C bus
interface, PWM output, remote control reception
circuit, HSYNC counter and watchdog timer as well
as basic configuration like 8-bit CPU, PROM, RAM
and I/O port.

Also this IC provides a power-on reset function
and SLEEP function that enables to lower power
consumption.

CXP856P40 is the PROM-incorporated version of
the CXP85640 with built-in mask ROM. This
provides the additional feature of being able to
write directly into the program (also into the OSD
character ROM or caption character ROM
possible). Thus, it is most suitable for evaluation
use during system development and for small­quantity production.

64 pin SDIP (PIastic) 64 pin QFP (PIastic)

Structure

Silicon gate CMOS IC

CXP856P40

Features

• A wide instruction set (213 instructions) to cover various types of data

— 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 333ns at 12MHz operation

• Incorporated PROM 40K bytes (Programming)

3K bytes (OSD)
3K bytes (Caption)

•Incorporated RAM 1888 bytes (Excludes the closed caption decoder and on-screen display VRAM)

• Peripheral functions

— A/D converter 8 bits, 6 channels, successive approximation method

(Conversion time of 26.7µs/12MHz)
— Serial interface 8-bit clock sync type, 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
— Closed caption decoder

Incorporated decode slicer,

conforming to FCC, 8 × 13 dots, 192 character types, 15 character colors,

4 lines × 34 characters, italic, underline, vertical scrolling,

15 frame background colors/half blanking
— On-screen display (OSD) function

12 × 16 dots, 128 character types, 15 character colors, 4 lines × 24 characters,

edging (half dot) vertical scrolling for every line

8 frame background colors/half blanking, jitter elimination circuit
— I2C bus interface
— PWM output 8 bits, 4 channels
— Remote control receiver circuit

8-bit pulse measurement counter, 6-stage FIFO
— HSYNC counter 2 channels
— Watchdog timer

• Interruption 15 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep

• Package 64-pin plastic SDIP/QFP

Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96740-PS

Vpp
Vss
V

DD

MP
RST
XTAL
EXTAL

PA0 to PA78PB0 to PB78PC0 to PC78PD0 to PD78PE0 to PE23PF0 to PF7

8

PORT A

PORT B

PORT C

PORT D

PORT E

PORT F

RAM

1888 BYTES

SYSTEM CONTROL

CLOCK GENERATOR/

CXP856P40

PWM0 to PWM3

DD

INT2
INT1
INT0

CVss
CV
Cap
Rex

SPC700 CPU CORE

2

DATA SLICER

CC DECODER

PROM

40K BYTES

3

2

PRESCALER/

TIME BASE TIMER

INTERRUPT CONTROLLER

ON SCREEN DISPLAY

SERIAL INTERFACE UNIT

WATCHDOG TIMER

FIFO

8BIT TIMER 1

8BIT TIMER/COUNTER 0

REMOCON

HSYNC COUNTER 0

8BIT PWM 4CH

C BUS

2

I

INTERFACE UNIT

HSYNC COUNTER 1

A/D CONVERTER 6CH

SCL1
SCL0

SDA1
SDA0

VIN

Block Diagram

XLC

R

EXLC

I

B

G

YS

YM

VSYNC

HSYNC

SI

SO

SCK

EC

TO

RMC

HSC0

HSC1

AN0 to AN5

– 2 –

Pin Assignment (Top View) 64-pin SDIP

CXP856P40

PC3
PC2

PC1
PC0

EC/PD7

RMC/PD6

HS1/PD5
HS0/PD4

SI/PD3

SO/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7

VSYNC/PA6

RST

Vss

XTAL

EXTAL
PA5/AN5
PA4/AN4
PA3/AN3

PA2/AN2
PA1/AN1
PA0/AN0

CVss

Cap
Rex

VIN

CV

INT1/PB7

PB6
PB5

DD

10
11
12
13
14
15
16
17
18
19
20

23

26

29
30

32

21
22

24
25

27
28

31

1

2
3
4

5
6
7
8
9

64

63

62

61
60

59

58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

42

41
40
39

38
37
36
35

34
33

PC4
PC5

PC6
PC7

PF0/PWM0

PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO

PE1
PE2/INT0
MP
Vss
VDD
Vpp
EXLC
XLC
YM

YS
I
B
G
R

PB0
PB1
PB2

PB3
PB4

Note) 1. Vpp (Pin 46) must be connected to VDD.

2. Vss (Pins 16 and 48) must be connected to GND.

3. MP (Pin 49) must be connected to GND.

4. Cap (Pin 26) must be connected to CVSS via a capacitor.

5. Rex (Pin 27) must be connected to CVDD via a resistor of 33kΩ.

– 3 –

Pin Assignment (Top View) 64-pin QFP

PD7/EC

PD6/RMC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PF0/PWM0

PF2/PWM2

PF1/PWM1

CXP856P40

HS1/PD5
HS0/PD4

SI/PD3

S0/PD2

SCK/PD1

INT2/PD0

HSYNC/PA7
VSYNC/PA6

RST

Vss

XTAL

EXTAL

PA5/AN5

PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0

CVss

10

11
12
13
14
15
16
17
18
19

62

64

63

61

60

59

1
2

3

4
5

6

7
8

9

58

57

56

55

54

53

52

51
50
49
48
47
46
45
44

42

40
39

37
36
35

33

43

41

38

34

PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO
PE1

PE2/INT0
MP
Vss

V

DD

Vpp
EXLC
XLC
YM
YS
I

B
G

20

Cap

21

Rex

22

VIN

23

DD

CV

25

24

PB6

INT1/PB7

26

PB5

27

PB4

28

PB3

29

PB2

30

PB1

31

PB0

Note) 1. Vpp (Pin 40) must be connected to VDD.

2. Vss (Pins 10 and 42) must be connected to GND.

3. MP (Pin 43) must be connected to GND.

4. Cap (Pin 20 ) must be connected to CVSS via a capacitor.

5. Rex (Pin 21) must be connected to CVDD via a resistor of 33kΩ.

32

R

– 4 –

Pin Description

CXP856P40

Symbol

PA0/AN0

to

PA5/AN5
PA6/VSYNC
PA7/HSYNC

PB0 to PB6

PB7/INT1

PC0 to PC7

PD0/INT2
PD1/SCK

PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC

I/O

I/O/Analog input

I/O/Input
I/O/Input

I/O

I/O/Input

I/O

I/O/Input
I/O/I/O

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Description

(Port A)
8-bit I/O port. I/O

Analog inputs to A/D converter. (6 pins)

can be set in a unit
of single bits.
(8 pins)

OSD display vertical sync signal input.
OSD display horizontal sync signal input.

(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

External interruption request input.
Active at the falling edge.

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)

External interruption request input.
Active at the falling edge.

(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Can drive 12mA
sync current.
(8 pins)

Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.

Remote control reception circuit input.
PD7/EC
PE0/TO
PE1

PE2/INT0
PF0/PWM0

to

PF3/PWM3
PF4/SCL0

PF5/SCL1
PF6/SDA0

PF7/SDA1
R, G, B, I, YS, YM

I/O/Input
I/O/Output
I/O

I/O/Input

Output/Output

Output/I/O

Output/I/O

Output

External event input for timer/counter.

(Port E)

Rectangular wave output for timer/counter.

3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)

(Port F)
8-bit output port
with large current

Input for external interruption request.

Active at the falling edge.

8-bit PWM outputs.

(4 pins)

(12mA) N-ch open
drain output.
Lower 4 bits are

Transfer clock I/O for I2C bus interface. (2 pins)

12V drive and upper
4 bits are 5V drive.
(8 pins)

Transfer data I/O for I2C bus interface. (2 pins)

6-bit OSD display outputs. (6 pins)

– 5 –

CXP856P40

Symbol
EXLC
XLC

VIN
Cap

Rex
CVDD
CVSS
EXTAL
XTAL

RST

MP
Vpp
VDD

I/O Description
Input
Output

Input

—

—

OSD display clock oscillation I/O.
Oscillator frequency is determined by the external L and C.

External composite video signal input.
Input a 2Vp-p signal via a capacitor.

Connects a capacitor for the data slicer between Cap and CVSS.
Connects a 33kΩ resistor for the data slicer between Rex and CVDD.
Positive power supply for data slicer.

GND for data slicer.
Input
Output

Connects a crystal for system clock oscillation. When an external

clock is supplied, input it to EXTAL and leave XTAL open.

System reset; active at Low level I/O pin.
I/O

Outputs a Low level when the power is turned on and the power-on

reset function operates.
Input

Test mode input. Must be connected to GND.

Positive power supply for internal PROM writing.

Under normal conditions, connect to VDD.

Positive power supply.

Vss

GND. Connect two VSS pins to GND.

– 6 –

Input/Output Circuit Formats for Pins

Pin When resetCircuit format

Port A

CXP856P40

Port A data

PA0/AN0

to

PA5/AN5

6 pins

PA6/VSYNC
PA7/HSYNC

Data bus

Port A function selection

“0” when reset

A/D converter

Port A

Data bus

Port A direction
“0” when reset

RD (Port A)

RD (Port A)

Input multiplexer

Port A data

Port A direction

“0” when reset

Schmitt input

IP

IP

Input
protection
circuit

Hi-Z

Hi-Z

2 pins

PB0 to PB6
PB7/INT1
PC0 to PC7

16 pins

VSYNC, HSYNC

Port B
Port C

Data bus

Port B, C data

Port B, C direction

“0” when reset

RD (Port B, C)

INT1

Input polarity

“0” when reset

IP

Hi-Z

Schmitt input

– 7 –