Sony CXP85640, CXP85632 Datasheet
CXP85632/85640
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CMOS 8-bit Single Chip Microcomputer
Description
The CXP85632/85640 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time-base timer, closed
caption decoder, data slicer, on-screen display
function, I2C bus interface, PWM output, remote
control receiver, HSYNC counter and watchdog
timer as well as basic configuration like 8-bit CPU,
ROM, RAM and I/O port.
Also this IC provides power-on reset function and
sleep function which enables to lower power
consumption.
Features
• A wide instruction set (213 instructions) to cover various types of data.
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 333ns at 12MHz operation
• Incorporated ROM 32K bytes (CXP85632)
40K bytes (CXP85640)
• Incorporated RAM 1888 bytes
(excluding the closed caption decoder and on-screen display VRAM)
• Peripheral functions
— A/D converter 8 bits, 6 channels, successive approximation method
(Conversion time of 26.7µs/12MHz)
— Serial interface 8-bit clock, sync type, 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
— Closed caption decoder
Incorporated decode slicer,
conforming to FCC, 8 × 13 dots, 192 character types, 15 character colors,
4 lines of 34 characters, italic, underline, vertical scroll,
15 frame background colors/half blanking
— On-screen display (OSD) function
12 × 16 dots, 128 character types, 15 character colors, 4 lines of 24 characters,
8 frame background colors/half blanking, edging per line (half dot), vertical scroll
jitter elimination circuit
— I2C bus interface
— PWM output 8 bits, 4 channels
— Remote control receiver circuit
Incorporated 6-stage FIFO 8-bit pulse measurement counter
— HSYNC counter 2 channels
— Watchdog timer
• Interruption 15 factors, 15 vectors, multi-interruption possible
• Standby mode SLEEP
• Package 64-pin plastic SDIP/QFP
• Piggyback/evaluation chip CXP85690 64-pin ceramic PSDIP (accommodates custom font)
64 pin SDIP (PIastic) 64 pin QFP (PIastic)
Structure
Silicon gate CMOS IC
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conform to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95510-PS
Vss
V
DD
MP
RST
XTAL
EXTAL
PA0 to PA78PB0 to PB78PC0 to PC78PD0 to PD78PE0 to PE23PF0 to PF7
8
PORT A
PORT B
PORT C
PORT D
PORT E
PORT F
RAM
1888 BYTES
SYSTEM CONTROL
CLOCK GENERATOR/
CXP85632/85640
PWM0 to PWM3
DD
INT2
INT1
INT0
CVss
CV
Cap
Rex
SPC700 CPU CORE
2
DATA SLICER
CC DECODER
ROM
32K/40K BYTES
3
2
ON SCREEN DISPLAY
PRESCALER/
TIME BASE TIMER
INTERRUPT CONTROLLER
SERIAL INTERFACE UNIT
WATCHDOG TIMER
FIFO
8BIT TIMER 1
8BIT TIMER/COUNTER 0
REMOCON
HSYNC COUNTER 0
8BIT PWM 4CH
C BUS
2
I
INTERFACE UNIT
HSYNC COUNTER 1
A/D CONVERTER 6CH
SCL1
SCL0
SDA1
SDA0
VIN
Block Diagram
XLC
R
EXLC
I
B
G
YS
YM
VSYNC
HSYNC
SI
SO
SCK
EC
TO
RMC
HSC0
HSC1
AN0 to AN5
– 2 –
Pin Assignment (Top View) 64-pin SDIP
CXP85632/85640
PC3
PC2
PC1
PC0
EC/PD7
RMC/PD6
HS1/PD5
HS0/PD4
SI/PD3
SO/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
Vss
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
CVss
Cap
Rex
VIN
CV
INT1/PB7
PB6
PB5
DD
10
11
12
13
14
15
16
17
18
19
20
23
26
29
30
32
21
22
24
25
27
28
31
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PC4
PC5
PC6
PC7
PF0/PWM0
PF1/PWM1
PF2/PWM2
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO
PE1
PE2/INT0
MP
Vss
VDD
NC
EXLC
XLC
YM
YS
I
B
G
R
PB0
PB1
PB2
PB3
PB4
Note) 1. NC (Pin 46) must be connected to VDD.
2. Vss (Pins 16 and 48) must be connected to GND.
3. MP (Pin 49) must be connected to GND.
4. Cap (Pin 26) must be connected to CVSS via a capacitor.
5. Rex (Pin 27) must be connected to CVDD via a resistor of 33kΩ.
– 3 –
Pin Assignment (Top View) 64-pin QFP
PD6/RMC
PD7/EC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PF0/PWM0
PF2/PWM2
PF1/PWM1
CXP85632/85640
HS1/PD5
HS0/PD4
SI/PD3
S0/PD2
SCK/PD1
INT2/PD0
HSYNC/PA7
VSYNC/PA6
RST
Vss
XTAL
EXTAL
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
CVss
10
11
12
13
14
15
16
17
18
19
62
64
63
61
60
59
1
2
3
4
5
6
7
8
9
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
42
40
39
37
36
35
33
43
41
38
34
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
PE0/TO
PE1
PE2/INT0
MP
Vss
V
DD
NC
EXLC
XLC
YM
YS
I
B
G
20
Cap
21
Rex
22
VIN
23
DD
CV
25
24
PB6
INT1/PB7
26
PB5
27
PB4
28
PB3
29
PB2
30
PB1
31
PB0
Note) 1. NC (Pin 40) must be connected to VDD.
2. Vss (Pins 10 and 42) must be connected to GND.
3. MP (Pin 43) must be connected to GND.
4. Cap (Pin 20 ) must be connected to CVSS via a capacitor.
5. Rex (Pin 21) must be connected to CVDD via a resistor of 33kΩ.
32
R
– 4 –
Pin Functions
CXP85632/85640
Pin name
PA0/AN0
to
PA5/AN5
PA6/VSYNC
PA7/HSYNC
PB0 to PB6
PB7/INT1
PC0 to PC7
PD0/INT2
PD1/SCK
PD2/SO
PD3/SI
PD4/HS0
PD5/HS1
PD6/RMC
I/O
I/O/Analog input
I/O/Input
I/O/Input
I/O
I/O/Input
I/O
I/O/Input
I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
Functions
(Port A)
8-bit I/O port. I/O
Analog inputs to A/D converter. (6 pins)
can be set in a unit
of single bits.
(8 pins)
OSD display vertical sync signal input.
OSD display horizontal sync signal input.
(Port B)
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
Input for external interruption request. Active at
the falling edge.
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. (8 pins)
Input for external interruption request. Active at
the falling edge.
(Port D)
8-bit I/O port. I/O
can be set in a unit
of single bits.
Capable of driving
12mA sync current.
(8 pins)
Serial clock I/O.
Serial data output.
Serial data input.
HSYNC counter (CH0) input.
HSYNC counter (CH1) input.
Remote control receiver circuit input.
PD7/EC
PE0/TO
PE1
PE2/INT0
PF0/PWM0
to
PF3/PWM3
PF4/SCL0
PF5/SCL1
PF6/SDA0
PF7/SDA1
R, G, B, I, YS, YM
I/O/Input
I/O/Output
I/O
I/O/Input
Output/Output
Output/I/O
Output/I/O
Output
External event input for timer/counter.
(Port E)
Rectangular wave output for timer/counter.
3-bit I/O port. I/O
can be set in a unit
of single bits.
(3 pins)
(Port F)
8-bit output port
with large current
Input for external interruption request.
Active at the falling edge.
8-bit PWM outputs.
(4 pins)
(12mA) N-ch open
drain output.
Transfer clock I/O for I2C bus interface. (2 pins)
Lower 4 bits are
12V drive and upper
4 bits are 5V drive.
Transfer data I/O for I2C bus interface. (2 pins)
OSD display 6-bit outputs. (6 pins)
– 5 –
CXP85632/85640
Pin name
EXLC
XLC
VIN
Cap
Rex
CVDD
CVSS
EXTAL
XTAL
RST
MP
NC
I/O Functions
Input
Output
Input
—
—
OSD display clock oscillation I/O.
Oscillator frequency is determined by external L and C.
Input of external composite video signal. Input a 2Vp-p signal via a
capacitor.
Capacitor connection for the data slicer. Connect a capacitor between
Cap and CVSS.
Resistor connection for the data slicer. Connect a 33kΩ resistor
between Rex and CVDD.
Positive power supply for data slicer.
GND for data slicer.
Input
Output
System clock oscillator crystal connection. When using an external
clock, input to EXTAL pin and leave XTAL pin open.
Low level active system reset. This pin acts as I/O pin and outputs low
I/O
level through incorporated power-on reset function when the power
turned on. (Mask option)
Input
Test mode input. Must be connected to GND.
Not connected.
Under normal conditions, connect to VDD.
VDD
Vss
Positive power supply.
GND. Connect two VSS pins to GND.
– 6 –
I/O Circuit Format for Pins
Pin When resetCircuit format
Port A
CXP85632/85640
Port A data
PA0/AN0
to
PA5/AN5
6 pins
PA6/VSYNC
PA7/HSYNC
Data bus
Port A function selection
“0” when reset
A/D converter
Port A
Data bus
Port A direction
“0” when reset
RD (Port A)
RD (Port A)
Input multiplexer
Port A data
Port A direction
Schmitt input
IP
IP
Input
protection
circuit
Hi-Z
Hi-Z
2 pins
PB0 to PB6
PB7/INT1
PC0 to PC7
16 pins
VSYNC, HSYNC
Port B
Port C
Data bus
Port B, C data
Port B, C direction
“0” when reset
RD (Port B, C)
INT1
Input polarity
"0" when reset
IP
Hi-Z
Schmitt input
– 7 –
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