Sony ACX306AK Datasheet
ACX306AK
3.86cm (1.5 Type) NTSC/PAL Color LCD Panel
Description
The ACX306AK is a 3.86cm diagonal active matrix
TFT-LCD panel addressed by low temperature polycrystalline silicon transistors with built-in peripheral
driving circuitry. This panel provides full-color
representation for NTSC and PAL systems. In
addition, RGB dots are arranged in a delta pattern
that provides smooth picture quality without fixed
color patterns compared to vertical stripe and
mosaic patterns.
Features
• Number of active dots: 118,000, 3.86cm (1.5 Type) in diagonal
• Horizontal resolution: 240 TV lines
• Optical transmittance: 6.5% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
• Low voltage, low power consumption: 12V drive: 43mW (panel block, typ.)
• Smooth pictures with a RGB delta arrangement
• Supports NTSC/PAL
• Built-in picture quality improvement circuit
• Up/down and/or right/left inverse display function
• LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
• Dirt-resistant surface treatment
• Narrow frame
Element Structure
• Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
• Number of pixels
Total number of dots: 494 (H) × 242 (V) = 119,548
Number of active dots: 490 (H) × 240 (V) = 117,600
• Module dimensions
Package dimensions: 38 (W) × 32.6 (D) × 2.2 (H) (mm)
Effective display dimensions: 31.115 (H) × 30.360 (V) (mm)
Applications
LCD monitors, etc.
– 1 –
E00143-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 2 –
ACX306AK
Block Diagram
The panel block diagram is shown below.
TESTL
TESTR
COM
VST
VCK
EN
DWN
V
DD
V
SS
VDDG
VSSG
TEST2
WIDE
HST
REF
TEST
Cext/Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
Level Shifter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
V Shift Register
H Level Shifter & Shift Register
LC
C
S
COM
Common
Voltage
Boost,
Negative Voltage
Generation Circuit
– 3 –
ACX306AK
Absolute Maximum Ratings (Vss = 0V)
• H driver supply voltage VDD, Cext/Rext –1.0 to +17 V
• V driver boost supply voltage VDDG VDD – 1.0 to +18 V
• V driver negative supply voltage VSSG –3.0 to +1.0 V
• Common voltage of panel COM –1.0 to +17 V
• H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE –1.0 to +17 V
• V driver input pin voltage VST, VCK, EN, DWN, REF –1.0 to +15 V
• Video signal, uniformity improvement signal input pin voltage
GREEN, RED, BLUE, PSIG –1.0 to +13 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –30 to +85 °C
Operating Conditions of Panel Block
1. Input/output supply voltage conditions
∗1
(VSS = 0V)
Item
Supply voltage
VDD
Cext/Rext
∗2
VDDG
VSSG
Rext
11.4
VDD – 3.4
14.0
–2.3
—
12.0
12.0
15.0
–1.8
10
12.6
—
16.3
–1.5
160
V
V
V
V
kΩ
VDDG output voltage setting
VSSG output voltage setting
∗3
Resistor connected to Cext/Rext pin
∗2
Symbol
Min. Typ.
Max.
Unit
∗1
The VDD typical voltage setting is noted as 12.0V in these specifications.
∗2
Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
∗3
For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing
Zener diode as shown in the figure below.
VDD – Cext/Rext
Cext/Rext
VDD
VDD
7
Voltage
Time
text
Set a Cext value that satisfies
text > 1ms.
The Cext/Rext value differs
according to the rising time
of the panel supply voltage.
Rext
ACX306AK
V
DD
VSSG
VSS
Cext/Rext
1µF
Cext
1µF
VDDG
Recommended
voltage applied
example Zener
diode.
(RD4.3UM is
recommended)
Recommended
voltage applied
example Zener
diode.
(RD2.7UM is
recommended)
– 4 –
ACX306AK
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
TESTL
COM
VST
VCK
EN
DWN
VDD
VSS
VDDG
VSSG
TEST2
WIDE
13
14
15
16
17
18
19
20
21
22
23
24
HST
REF
TEST
Cext/
Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Start pulse input for H shift register
drive
Level shifter circuit REF voltage
input
Panel test output; no connection
Time constant power supply input
for H shift register drive
Clock input for H shift register drive
Clock input for H shift register drive
Uniformity improvement signal input
Video signal (G) input to panel
Video signal (R) input to panel
Video signal (B) input to panel
H shift register drive direction signal
input
Panel test output; no connection
Symbol Description
Pin
No.
Symbol Description
Panel test output; no connection
Common voltage input of panel
Start pulse input for V shift register
drive
Clock input for V shift register drive
Gate selection pulse enable input
V shift register drive direction signal
input
Power supply input for V driver
H and V driver GND
Boost power supply setting for
V driver
Negative power supply setting for
V driver
No connection inside the panel.
(with 1MΩ terminating resistor)
Uniformity improvement signal
control pulse input
Pin Description of Panel Block
∗4
Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC
as shown in Fig. 1.
PSIG waveform
VVC
Vpsig
Fig. 1
Item
H/V driver input voltage
(Low)
(High)
VIL
VIH
VREF
VVC
Vsig
Vpsig
Vcom
–0.3
2.6
VIH/2 – 0.3
5.8
1.0
VVC ± 2.3
VVC – 0.6
0.0
3.0
VIH/2
6.0
VVC ± 4.0
VVC ± 2.5
VVC – 0.5
0.3
5.5
VIH/2 + 0.3
6.2
VDDG – 4.0
(10.5V or less)
VVC ± 2.7
VVC – 0.4
V
V
V
V
V
V
V
REF input voltage
Video signal center voltage
∗4
Video signal input range
∗4
Uniformity improvement signal
∗4
Common voltage of panel (Ta = 25°C)
Symbol Min. Typ. Max. Unit
2. Panel input signal voltage conditions (VSS = 0V)
– 5 –
ACX306AK
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with a
high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
VDD
1MΩ
Input
Signal line
(2) HCK1, HCK2
1MΩ
1MΩ
V
DD
VDD
HCK1
HCK2
H level shifter and
shift register circuit
(3) WIDE, REF
1MΩ
350Ω
1MΩ
350Ω
V
DD
VDD
Input
REF
Level conversion
circuit
(5) RGT, REF
1MΩ
2kΩ
1MΩ
2kΩ
V
DD
VDD
Input
REF
Level conversion
circuit
(4) HST
1MΩ
175Ω
1MΩ
175Ω
V
DD
VDD
Input
REF
Level conversion
circuit
– 6 –
ACX306AK
(11) TEST, TEST2
VDD
TEST
350Ω
1M
Ω
350Ω
TEST2
1MΩ
(12) TESTL, TESTR
TESTL
TESTR
4MΩ
V
DD
(7) DWN, REF
1MΩ
1MΩ
V
DD
VDD
2kΩ2kΩ
Input
REF
Level conversion
circuit
(8) VDDG, VSSG
VDD
VDDG, VSSG
Boost, Negative
voltage
generation circuit
(9) COM
1MΩ
Input
LC
(10) Cext/Rext
VDD
Cext/Rext
H driver
1MΩ
(6) VST, VCK, EN, REF
1MΩ
800Ω
1MΩ
800Ω
V
DD
VDD
Input
REF
Level conversion
circuit
– 7 –
ACX306AK
Clock Timing Conditions of Panel Block (VIH = 3.0V, VDD = 12V, Ta = 25°C)
HST rise time
HST fall time
HST data setup time
HST data hold time
HCKn∗5rise time
HCKn∗5fall time
HCK1 fall to HCK2 rise time
HCK1 rise to HCK2 fall time
VST rise time
VST fall time
VST data setup time
VST data hold time
VCK rise time
VCK fall time
EN rise time
EN fall time
EN fall to VCK rise/fall time
EN pulse width
WIDE rise time
WIDE fall time
WIDE (H) rise to VCK rise/fall time
WIDE (H) pulse width
trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst
thVst
trVckn
tfVckn
trEn
tfEn
tdEn
twEn
trWide
tfWide
tdhWide
twhWide
—
—
300
–30
—
—
–15
–15
—
—
30
–30
—
—
—
—
500
2900
—
—
–0.4
1.4
—
—
333
0
—
—
0
0
—
—
32
–32
—
—
—
—
600
3000
—
—
–0.5
1.5
30
30
363
30
30
30
15
15
100
100
34
–34
100
100
100
100
700
3100
100
100
–0.6
1.6
ns
µs
ns
µs
Item
Symbol
Min. Typ. Max. Unit
HST
HCK
VST
VCK
EN
WIDE
∗5
HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
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