SONY 24AF41 Service Manual



24C04A

2

4K 5.0V I

™

C

Serial EEPROM

FEATURES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I

• 5.0V only operation

• Self-timed write cycle (including auto-erase)

• Page-write buffer

• 1 ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

• 8-pin DIP/SOIC packages

• Available for extended temperature ranges

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

- Automotive (E): -40˚C to +125˚C

2

C™ compatible

DESCRIPTION

The Microchip Technology Inc. 24C04A is a 4K bit
Electrically Erasable PROM. The device is organized
as with a standard two wire serial interface. Adv anced
CMOS technology allows a significant reduction in
power over NMOS serial devices. A special feature
provides hardware write protection for the upper half of
the block. The 24C04A has a page write capability of
up to eight bytes, and up to four 24C04A devices may
be connected to the same two wire bus.

This device offers fast (1ms) byte write and
extended (-40 ° C to 125 ° C) temperature operation.
It is recommended that all other applications use
Microchip’s 24LC04B.

PACKA GE TYPES

DIP

8-lead
SOIC

14-lead
SOIC

V

A0
A1

A2

V

SS

NC

A0

A1

NC

A2

Vss

NC

A0
A1

A2

SS

1
2

3

4

1
2

3

4

1
2
3
4
5
6
7

24C04A

24C04A

24C04A

14
13
12

11

10

V

8

CC

7

WP

6

SCL

5

SDA

8

V

CC

7

WP

6

SCL

5

SDA

NC
Vcc

WP
NC
SCL

9
8

SDA
NC

BLOCK DIAGRAM

Vcc
Vss

SDA

SCL

2

I

C is a trademark of Philips Corporation.

1998 Microchip Technology Inc. DS11183E-page 1

Data
Buffer
(FIFO)

Data Reg.

Slave Addr.

Control

Logic

A0 A1 A2 WP

VPP R/W Amp

A

P

d

o

d

i

r

n

e

t

s

e

s

r
Increment

A0 to
A7

Memory

Array

A8



24C04A

µ

µ

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maximum Ratings*

V

...................................................................................7.0V

CC

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied.................-65˚C to +125˚C

Soldering temperature of leads (10 seconds)............. +300˚C

ESD protection on all pins................................................4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

............... -0.6V to V

SS

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A1, A2 Chip Address Inputs

V

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input

V

TABLE 1-2: DC CHARACTERISTICS

V

CC

= +5V ( ± 10%) Commercial (C): Tamb = 0 ° C to +70 ° C

Industrial (I): Tamb = -40 ° C to +85 ° C
Automotive (E): Tamb = -40 ° C to +125 ° C

Parameter Symbol Min. Max. Units Conditions

CC

V

detector threshold V

SCL and SDA pins:

High level input voltage
Low level input voltage
Low level output voltage

A1 & A2 pins:

High level input voltage

Low level input voltage
Input leakage current I
Output leakage current I
Pin capacitance

(all inputs/outputs)
Operating current I

Standby current I

Note: This parameter is periodically sampled and not 100% tested

TH

V

IH
IL

V

OL

V

V

IH
IL

V

LI

LO

C

IN

C

OUT
CC

Write

I

CC

Write

I

CC

Read

CCS

2.8 4.5 V

CC

V

x 0.7

-0.3

CC

V

- 0.5

-0.3

CC

V

+ 1

CC

V

x 0.3

0.4

CC

V

+ 0.5

0.5

V
V
VI

V

V
—10 µ AV
—10 µ AV

,

— 7.0 pF V

— 3.5 mA F

— 4.25 mA F

— 750

— 100

AV

A SDA=SCL=V

A0 No Function - Must be connected to

V

or V

CC

SS

CC

Ground

+5V Power Supply

OL

= 3.2 mA (SDA only)

= 0V to V

IN
OUT

= 0V to V

/V

IN

OUT

SS

CC

CC

= 0V (Note)

Tamb = +25˚C, f = 1 MHz

CLK

= 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

= 100 kHz, program cycle time = 1 ms,

CLK

Vcc = 5V, Tamb = (I) and (E)

= 5V, Tamb= (C), (I) and (E)

CC

CC

=5V (no PROGRAM active)

WP/TEST = V

SS

, A0, A1, A2 = V

SS

FIGURE 1-1: BUS TIMING START/STOP

SCL

TSU:STA

SDA

START STOP

DS11183E-page 2

THD:STA

VHYS

TSU:STO

1998 Microchip Technology Inc.



24C04A

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol Min. Typ Max. Units Remarks

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

START condition setup time T

Data input hold time T
Data input setup time T
Data output delay time T
STOP condition setup time T
Bus free time T

Input filter time constant

HD

SU

HD
SU

SU

CLK
HIGH
LOW

R
F

:S

:S

:D
:D

AA

:S

BUF

T

I

TA

TA

AT
AT

TO

(SDA and SCL pins)
Program cycle time T

WC

Endurance — 1M — — cycles 25 ° C, Vcc = 5.0V, Block

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

— — 100 kHz
4000 — — ns
4700 — — ns

— — 1000 ns

— — 300 ns
4000 — — ns After this period the first

clock pulse is generated

4700 — — ns Only relevant for repeated

START condition

0—— ns
250 — — ns
300 — 3500 (Note 1)

4700 — — ns
4700 — — ns Time the bus must be free

before a new transmission
can start

— — 100 ns

— .4 1 ms Byte mode

.4N N ms Page mode, N=# of bytes

Mode (Note 2)

FIGURE 1-2: BUS TIMING DATA

TF

TLOW

SCL

TSU:STA

THD:STA

SDA

IN

SDA

OUT

TSP

TAA

THD:STA

THIGH

THD:DAT TSU:DAT

TAA

TR

TSU:STO

TBUF

1998 Microchip Technology Inc. DS11183E-page 3

24C04A

2.0 FUNCTIONAL DESCRIPTION

The 24C04A supports a bidirectional two wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be con­trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24C04A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter­mines which mode is activated.

Up to four 24C04As can be connected to the bus,
selected by A1 and A2 chip address inputs. A0 must
be tied to V

CC or VSS.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenev er the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi­tion.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24C04A does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must lea ve the data line HIGH to enab le
the master to generate the STOP condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A) (B) (D) (D) (A)(C)

SCL

SDA

START

CONDITION

DS11183E-page 4  1998 Microchip Technology Inc.

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION