SMSC USB3500 Technical data

USB3500

Hi-Speed USB Host,
Device or OTG PHY
With UTMI+ Interface

PRODUCT FEATURES

 USB-IF “Hi -Speed” certified to the Universal Serial

Bus Specification Rev 2.0

 Interface compl iant with the UTMI+ Specification,

Revision 1.0.

 Inclu des full support for the optional On-The-Go

(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification.

 Function al as a host, device or OTG PHY.
 Sup ports HS, FS, and LS data rates.
 Sup ports FS pre-amble fo r FS hu bs with a LS device

attached (UTMI+ Level 3)

 Sup ports HS SOF and LS keep alive pulse.
 Supports Host Negotiation Protocol (HNP) and

Session Request protocol (SRP.)

 Internal comparators support OTG monitoring of

VBUS levels.

 Low Latency Hi-Speed Receiver (43 Hi-Speed clocks

Max)

Datasheet

 Interna l 1.8 volt regulators allow operation from a

single 3.3 volt supply

 Interna l short circuit protection of ID, DP and DM

lines to VBUS or ground.

 Integrated 24MHz Crystal Oscillator supports either

crystal operation or 24MHz external clock input.

 Interna l PLL for 480MHz Hi-Speed USB operation.
 Su pports USB 2.0 and legacy USB 1.1 devices
 55mA Unconfigured Current (typical) - ideal for bus

powered applications.

 8 3uA suspend current (typical) - ideal for battery

powered applications.

 Full Commercial operating temperature range from

0C to +70C

 56 Pin, QFN lead-free RoHS compliant package

(8 x 8 x 0.90 mm height)

SMSC USB3500 DATASHEET Revision 1.0 (06-05-08)

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

ORDER NUMBER:

USB3500-ABZJ FOR 56 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE

Datasheet

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]

Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a mean s of illustrating typical applications. Conse quently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently da ted
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.0 (06-05-08) 2 SMSC USB3500

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

0.1 Reference Documents

 Universal Serial Bus Specification, Revision 2.0, April 27, 2000
 USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000
 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003
 UTMI+ Specification, Revision 1.0, February 2, 2004

SMSC USB3500 3 Revision 1.0 (06-05-08)

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

Table of Contents

0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Pin Configuration and Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 USB3500 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 6 Detailed Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 8bit Bi-Directional Data Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3 RX Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 USB 2.0 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.1 High Speed and Full Speed Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.4.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.5 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.6.2 Power On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.7 USB On-The-Go (OTG) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.7.1 ID Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.7.2 VBUS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Chapter 7 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1 Linestate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.3 Test Mode Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.8 HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.9 HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.14 USB Reset and Chirp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.15 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision 1.0 (06-05-08) 4 SMSC USB3500

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

List of Figures

Figure 1.1 Basic UTMI+ USB Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1.2 UTMI+ Level 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.1 USB3500 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.1 USB3500 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 6.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 6.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6.8 USB3500 On-the-Go Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 7.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 7.9 USB Reset and Chirp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 7.10 USB3500 Application Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 8.1 USB3500-ABZJ 56 Pin QFN Package Outline, 8 x 8 x 0.9 mm Body (Lead Free) . . . . . . . . 46

SMSC USB3500 5 Revision 1.0 (06-05-08)

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

List of Tables

Table 3.1 USB3500 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5.1 DC Electrical Characteristics: Supply Pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.2 Electrical Characteristics: CLKOUT Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.3 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5.6 Dynamic Characteristics: Digital UTMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5.7 OTG Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5.8 Regulator Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6.1 DP/DM termination vs. Signaling Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 6.2 IdGnd vs. USB Cable Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7.1 Device Linestate States (DPPD & DMPD = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7.2 Host Linestate States (DPPD & DMPD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 7.3 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7.4 USB 2.0 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7.5 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 7.6 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7.7 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 7.8 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 7.9 HS Detection Handshake Timing Values from Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 7.10 Resume Timing Values (HS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 7.11 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 8.1 56 Terminal QFN Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision 1.0 (06-05-08) 6 SMSC USB3500

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

Chapter 1 General Description

The USB3500 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3500 uses
a UTMI+ interface to connect to an SOC or FPGA or custom ASIC. The USB3500 provides a flexible
alternative to integrating the analog PHY block for new d esigns.

SOC/FPGA/ASIC

Including Device Cont roller

Hi-Speed

USB App.

The USB3500 provides a fully compliant USB 2.0 interface, and supports High-Speed (HS), Full-Speed
(FS), and Low-Speed (LS) USB. The USB3500 supports all levels of the UTMI+ specification as shown
in Figure 1.2.

The USB3500 can also, as an option, fully support the On-the-Go (OTG) protocol defined in th e On­The-Go Supplement to the USB 2.0 Specification. On-the-Go allows the Link to dyn amically configure
the USB3500 as host or peripheral configured dynam ically by software. For example, a cell phone may
connect to a computer as a peripheral to exchange address information or connect to a printer as a
host to print pictures. Finally the OTG enabled device can connect to another OTG enabled device to
exchange information. All this is supported using a single low profile Mini-AB USB connector.

Designs not needing OTG can ignore the OTG feature set.

UTMI+

Link

Figure 1.1 Basic UTMI+ USB Device Block Diagram

UTMI+

Interface

USB3500

UTMI+
Digital

Logic

USB 2.0

Analog
w/ OTG

V

DM

DP

BUS

ID

USB

Connector

(Standard

or Mini)

SMSC USB3500 7 Revision 1.0 (06-05-08)

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

The USB3500 uses SMSC’s advanced proprietary technology to minimize power dissipation, resulting
in maximized battery life in portable applications.

UTMI+ Level 3

USB2.0 Peripheral, host controllers, On-the-

Go devices

USB3500

(HS, FS, LS, preamble packet)

UTMI+ Level 2

USB2.0 Peripheral, host controllers, On-

the-Go devices

(HS, FS, and LS but no preamble packet)

UTMI+ Level 1

USB2.0 Peripheral, host controllers, and

ADDED FEATURES

On-the-Go devices

(HS and FS Only)

1.1 Applications

The USB3500 is targeted for any application where a hi-speed USB connection is desired.
The USB3500 is well suited for:

 Cell Phones
 MP3 Players
 Scanners
 Printers
 External Hard Drives
 Still and Video Cameras
 Portable Media Players
 Entertainment Devices

UTMI+ Level 0

USB2.0 Peripherals Only

Figure 1.2 UTMI+ Level 3 Support

USB3280
USB3250

Revision 1.0 (06-05-08) 8 SMSC USB3500

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

Chapter 2 Functional Overview

The USB3500 is a highly integrated USB tra nsceiver syste m. It contains a complete USB 2.0 PHY with
the UTMI+ industry standard interface to support fast time to market for a USB controller. The
USB3500 is composed of the functional blocks shown in Figure 2.1 below.

VDD3.3

XCVRSEL[1:0]

TERMSEL
TXREADY

SUSPENDN

TXVALID

RESET

CHRGVBUS

RXACTIVE

OPMODE[1:0]

ID_DIG

IDPULLUP

CLKOUT

LINESTATE[1:0]

HOSTDISC

DISCHRGVBUS

SESSEND

DATA[7:0]

RXVALID

SESSVLD

DPPD
DMPD

RXERROR

VBUSVLD

VDD1.8

VDDA1.8

Internal

Regulators

& POR

TX

Logic

RX

Logic

UTMI+
Digital

m

24 MHz

XI

XTAL

XO

XTAL &

PLL

HS XCVR

FS/LS
XCVR

USB3500

OTG

Module

Rpu_dp

Rpu_dm

Rpd_dp

Rpd_dm

Resistors

Bias
Gen.

VBUS

ID

VDD3.3

DP

DM

RBIAS

5V

Power

Supply

Mini-AB

USB

Connector

Figure 2.1 USB3500 Block Diagram

SMSC USB3500 9 Revision 1.0 (06-05-08)

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Chapter 3 Pin Configuration and Pin Definitions

The USB3500 is offered in a 56 pin QFN package. The pin definitions and locations are documented
below.

3.1 USB3500 Pin Locations

RBIAS

VDD3.3

VDD3.3

VDDA1.8XIXO

VSS

VDD1.8

VBUSVLD

VDD3.3

VSS

RXERROR

DMPD

DPPD

Datasheet

VSS

XCVRSEL0

TERMSEL
TXREADY

VBUS

SUSPENDN

TXVALID

RESET

VDD3.3

DP

DM

VSS

VDD3.3

56555453525150

1
2
3
4
5
6

ID

7
8
9
10
11
12
13
14

15161718192021222324252627

XCVRSEL1

CHRGVBUS

USB3500

Hi-Speed USB

UTMI+ PHY

56 Pin QFN

GND FLAG

ID_DIG

RXACTIVE

OPMODE[1]

OPMODE[0]

4847464544

49

VSS

CLKOUT

IDPULLUP

VSS

LINESTATE[1]

43

SESSVLD

42

RXVALID

41

VSS

40

DATA[0]

39

DATA[1]

38

DATA[2]

37

DATA[3]

36

DATA[4]

35

DATA[5]

34

DATA[6]

33

DATA[7]

32

SESSEND

31

DISCHRGVBUS

30

HOSTDISC

29

28

VDD1.8

VDD3.3

LINESTATE[0]

Figure 3.1 USB3500 Pinout - Top View

The flag of the QFN package must be connected to ground with a via array.

Revision 1.0 (06-05-08) 10 SMSC USB3500

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Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

3.2 Pin Definitions

T able 3.1 USB3500 Pin Definitions

DIRECTION,

PIN NAME

1 VSS Ground N/A PHY ground.
2 XCVRSEL[0] Input N/A Transceiver Select. These signals select between

3 TERMSEL Input N/A Termination Select. This signal selects between the

4 TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the

5 VBUS I/O,

6 ID Input,

TYPE

Analog

Analog

ACTIVE

LEVEL DESCRIPTION

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

FS and HS terminations:
0: HS termination enabled
1: FS termination enabled

Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.

N/A VBUS pin of the USB cable.

N/A ID pin of the USB cable.

7 SUSPENDN Input Low Suspend. Places the transceiver in a mode that

8TXVALID Input High Transmit Valid. Indicates that the DATA bus is valid

9 RESET Input High Rese t. Reset all state machines. After coming out

10 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for USB 2.0

11 DP I/O,

Analog

N/A D+ pin of the USB cable.

draws minimal power from supplies. In host mode,
R

is removed during suspend. In device mode,

PU

R

is controlled by TERMSEL. In suspend mode

PD

the clocks are off.
0: PHY in suspend mode
1: PHY in normal operation

for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.

Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.

of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

SMSC USB3500 11 Revision 1.0 (06-05-08)

DATASHEET

Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Table 3.1 USB3500 Pin Definitions (continued)

Datasheet

DIRECTION,

PIN NAME

TYPE

12 DM I/O,

ACTIVE

LEVEL DESCRIPTION

N/A D- pin of the USB cable.

Analog

13 VSS Ground N/A PHY ground.
14 VDD3.3 N/A N/A 3.3V PHY Supply.
15

XCVRSEL[1] Input N/A Transceiver Select. These signals select between

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

16 CHRGVBUS Input High

Charge VBUS through a resistor to VDD3.3.
0: do not charge VBUS
1: charge VBUS

17 RXACTIVE Output High Receive Active. Indicates that the receive state

machine has detected Start of Packet and is active.

18 OPMODE[1] Input N/A Operatio nal Mode. These signals select between

the various operational modes:

19

OPMODE[0] Input N/A

[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved

20 ID_DIG Output High ID Digital. Indicates the state of the ID pin .

0: connected plug is a mini-A
1: connected plug is a mini-B

21 IDPULLUP Input High

ID Pull-up. Enables sampling of the analog ID line.
Disabling the ID line sampler will reduce PHY power
consumption.
0: Disable sampling of ID line.
1: Enable sampling of ID line.

22
23

24
25

VSS Ground N/A PHY ground.

CLKOUT Output,

CMOS

N/A 60MHz reference clock output. All UTMI+ signals are

driven synchronous to this clock.

VSS Ground N/A PHY ground.

LINESTATE[1] Output N/A Line State. These signals reflect the current state of

the USB data bus in FS mode. Bit [0] reflects the

26

LINESTATE[0] Output N/A

state of DP and bit [1] reflects the state of DM. When
the device is suspended or resuming from a
suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0 0 0: SEO
0 1 1: J State
1 0 2: K State
1 1 3: SE1

27 VDD1.8 N/A N/A 1.8V regulator output for digital circuitry on chip.

Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 27
to pin 49.

Revision 1.0 (06-05-08) 12 SMSC USB3500

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Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Datasheet

Table 3.1 USB3500 Pin Definitions (continued)

PIN NAME

DIRECTION,

TYPE

ACTIVE

LEVEL DESCRIPTION

28 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for USB 2.0

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

29 HOSTDISC Output High Host Disconnect. In HS Host mode this indicates to

that a downstream device has been disconnected.
Automatically reset to 0b when Low Power Mode is
entered.

30 DISCHRGVBUS Input High Discharge VBUS through a resistor to ground.

0: do not discharge VBUS
1: discharge VBUS

31 SESSEND Output High Session End. Indicates that the vol tage on Vbus is

below its B-Device Session End threshold.

32 DATA[7] I/O,

CMOS,

0: VBUS > V
1: VBUS < V

N/A 8-bit bi-directional data bus. Data[7] is the MSB and

Data[0] is the LSB.

SessEnd
SessEnd

Pull-low

33

DATA[6] I/O,

N/A

CMOS,

Pull-low

34

DATA[5] I/O,

N/A

CMOS,

Pull-low

35

DATA[4] I/O,

N/A

CMOS,

Pull-low

36

DATA[3] I/O,

N/A

CMOS,

Pull-low

37

DATA[2] I/O,

N/A

CMOS,

Pull-low

38

DATA[1] I/O,

N/A

CMOS,

Pull-low

39

DATA[0] I/O,

N/A

CMOS,

Pull-low

40

VSS Ground N/A PHY ground.

41 RXVALID Output High Receive Data Valid. Indicates that the DATA bus has

received valid data. The Receive Data Holding
Register is full and ready to be unloaded. The Link
is expected to register the DATA bus on the next
rising edge of CLKOUT.

42 SESSVLD Output High Session Valid. Indicates that the voltage on Vbus is

above the indicated threshold.
0: VBUS < V
1: VBUS > V

SessVld
SessVld

SMSC USB3500 13 Revision 1.0 (06-05-08)

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Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface

Table 3.1 USB3500 Pin Definitions (continued)

Datasheet

PIN NAME

DIRECTION,

TYPE

ACTIVE

LEVEL DESCRIPTION

43 DPPD Input N/A DP Pull-down Sele ct. This signal enables the 15k

Ohm pull-down resistor on the DP line.
0: Pull-down resistor not connected to DP
1: Pull-down resistor connected to DP

44

DMPD Input N/A DM Pull-down Sele ct. This signal enables the 15k

Ohm pull-down resistor on the DM line.
0: Pull-down resistor not connected to DM
1: Pull-down resistor connected to DM

45 RXERROR Output High Receive Error. This output is clocked with the same

timing as the receive DATA lines and can occur at
anytime during a transfer.
0: Indicates no error.
1: Indicates a receive error has been detected.

46 VSS Ground N/A PHY ground.
47 VBUSVLD Output High VBUS Valid. Indicates that the voltage on Vbus is

above the indicated threshold.
0: VBUS < V
1: VBUS > V

VbusVld
VbusVld

48 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for USB 2.0

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

49 VDD1.8 N/A N/A 1.8V regulator output for digital circuitry on chip.

Place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground.
Connect pin 49 to pin 27. See Section 6.6, "Internal

Regulators and POR," on page 27.

50 VSS Ground N/A PHY ground.
51

52

XO Output,

Analog

XI Input,

Analog

N/A Crystal pin. If using an external clock on XI this pin

should be floated.

N/A Crystal pin. A 24MHz crystal is supported. The

crystal is placed across XI and XO. An external
24MHz clock source may be driven into XI in place
of a crystal.

53 VDDA1.8 N/A N/A 1.8V regulator output for analog circuitry on chip.

Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. In parallel,
place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground. See

Section 6.6, "Internal Regulators and POR".

54 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for USB 2.0

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

55 VDD3.3 N/A N/A 3.3V PHY Supply. Should be connected directly to

pin 54.

56

RBIAS Analog,

CMOS

N/A External 1% bias resistor. Requires a 12KΩ resistor

to ground.

GND FLAG Ground N/A Ground. The flag must be connecte d to the ground

plane.

Revision 1.0 (06-05-08) 14 SMSC USB3500

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