SMSC USB3450 Technical data

查询USB3450供应商

USB3450

Hi-Speed USB Host or
Device PHY With UTMI+
Interface

PRODUCT FEATURES

■ USB-IF “Hi-Speed” certified to the Universal Serial

Bus Specification Rev 2.0

■ Interface compliant with the UTMI+ Specification,

Revision 1.0.

■ Functional as a host or device PHY.

■ Supports HS, FS, and LS data rates.

■ Supports FS pre-amble for FS hubs with a LS device

attached (UTMI+ Level 3)

■ Supports HS SOF and LS keep alive pulse.

■ Low Latency Hi-Speed Receiver (43 Hi-Speed clocks

Max)

■ Internal 1.8 volt regulators allow operation from a

single 3.3 volt supply

■ Internal short circuit protection of DP and DM lines to

VBUS or ground.

Datasheet

■ Integrated 24MHz Crystal Oscillator supports either

crystal operation or 24MHz external clock input.

■ Internal PLL for 480MHz Hi-Speed USB operation.

■ Supports Hi-Speed USB and legacy USB 1.1 devices

■ 55mA Unconfigured Current (typical) - ideal for bus

powered applications.

■ 83uA suspend current (typical) - ideal for battery

powered applications.

■ Full Commercial operating temperature range from

°C to +70°C

0

■ 40 pin QFN package; green, lead-free (6 x 6 x 0.9mm

height)

SMSC USB3450 DATASHEET Revision 0.1 (05-11-05)

y

r

r

Y

Hi-Speed USB Host or Device PHY With UTMI+ Interface

ORDER NUMBER(S): USB3450-FZG FOR 40 PIN, QFN PACKAGE (GREEN, LEAD-FREE)

Datasheet

Hauppauge, NY 11788
[phone]
FAX [phone]

80 Arkay Drive

Copyright © 2005 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently,
complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be
accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any
time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this
information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual
property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product ma
contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or othe
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written
approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or othe
SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a
registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective
holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE,
AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE
LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA,
PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT;
NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMED
OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.

Revision 0.1 (05-11-05) 2 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

0.1 Reference Documents

■ Universal Serial Bus Specification, Revision 2.0, April 27, 2000

■ Hi-Speed Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000

■ UTMI+ Specification, Revision 1.0, February 2, 2004

SMSC USB3450 3 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Table of Contents

0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Pin Configuration and Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 USB3450 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 6 Detailed Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 8bit Bi-Directional Data Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4 Hi-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.1 High Speed and Full Speed Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 7 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1 Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3 Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.8 HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.9 HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.14 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision 0.1 (05-11-05) 4 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

List of Figures

Figure 1.1 Basic UTMI+ USB Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1.2 UTMI+ Level 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.1 USB3450 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.1 USB3450 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7.9 USB3450 Application Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline, 6 x 6 x 0.9 mm Body (Lead Free) . . . . . . . . . 40

SMSC USB3450 5 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

List of Tables

Table 3.1 USB3450 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5.1 Electrical Characteristics: Supply Pins (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.2 Electrical Characteristics: CLKOUT Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.3 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5.6 Regulator Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6.1 DP/DM termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7.3 Hi-Speed Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 7.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision 0.1 (05-11-05) 6 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Chapter 1 General Description

The USB3450 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3450 uses
a UTMI+ interface to connect to an SOC or ASIC or FPGA. SMSC’s advanced proprietary technology
minimizes power dissipation, resulting in maximum battery life for portable applications. The USB3450
is a flexible solution for adding USB to new designs without integrating the analog PHY block.

SOC/FPGA/ASIC

Including Device Controller

Hi-Speed

USB App.

The USB3450 provides a fully compliant Hi-Speed interface, and supports Hi-Speed (HS), Full-Speed
(FS), and Low-Speed (LS) USB. The USB3450 supports all levels of the UTMI+ specification as shown
in Figure 1.2.

UTMI+

Link

Figure 1.1 Basic UTMI+ USB Device Block Diagram

Hi-Speed Peripheral, host controllers, On-

(HS, FS, LS, preamble packet)

UTMI+

Interface

UTMI+
Digital

Logic

UTMI+ Level 3

the-Go devices

USB3450

Hi-

Speed

Analog

V

DM

BUS

ID

DP

USB

Connector

(Standard

or Mini)

USB3450

USB3500

UTMI+ Level 2

Hi-Speed Peripheral, host controllers, On-

the-Go devices

(HS, FS, and LS but no preamble packet)

UTMI+ Level 1

Hi-Speed Peripheral, host controllers,

ADDED FEATURES

and On-the-Go devices

(HS and FS Only)

UTMI+ Level 0

Hi-Speed Peripherals Only

Figure 1.2 UTMI+ Level 3 Support

SMSC USB3450 7 Revision 0.1 (05-11-05)

USB3280
USB3250

DATASHEET

1.1 Applications

The USB3450 is targeted for any application where a high speed USB connection is desired.

The USB3450 is well suited for:

■ Cell Phones

■ MP3 Players

■ Scanners

■ Set Top Boxes

■ Printers

■ External Hard Drives

■ Still and Video Cameras

■ Portable Media Players

■ Entertainment Devices

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Revision 0.1 (05-11-05) 8 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Chapter 2 Functional Overview

The USB3450 is a highly integrated USB transceiver system. It contains a complete Hi-Speed PHY
with the UTMI+ industry standard interface to support fast time to market for a USB controller. The
USB3450 is composed of the functional blocks shown in Figure 2.1 below.

m

24 MHz

XI

VDD1.8

VDDA1.8

XTAL

XO

VDD3.3

XCVRSEL[1:0]

TERMSEL
TXREADY

SUSPENDN

TXVALID

RESET

RXACTIVE

OPMODE[1:0]

CLKOUT

LINESTATE[1:0]

HOSTDISC

DATA[7:0]

HOST

RXERROR

Internal

Regulator &

POR

UTMI+

Digital

Figure 2.1 USB3450 Block Diagram

XTAL &

PLL

HS XCVR

FS/LS
XCVR

USB3450

Rpu_dp

Rpu_dm

Rpd_dp

Rpd_dm

Resistors

Bias
Gen.

VDD3.3

DP
DM

RBIAS

Mini-AB

USB

Connector

SMSC USB3450 9 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Chapter 3 Pin Configuration and Pin Definitions

The USB3450 is offered in a 40 pin QFN package. The pin definitions and locations are documented
below.

3.1 USB3450 Pin Locations

RBIAS

VDD3.3

VDD3.3

VDDA1.8

XI

XO

VDD1.8

VDD3.3

RXERROR

HOST

34

33

32

31

30

RXVALID

XCVRSEL0

40

39

38

37

36

35

1

Datasheet

TERMSEL

TXREADY

SUSPENDN

TXVALID

RESET

VDD3.3

DM

DP

NC

2

3

4

5

6

7

8

9

10

11

VDD3.3

USB3450

Hi-Speed USB

UTMI+ PHY

40 Pin QFN

GND FLAG

12

13

14

RXACTIVE

XCVRSEL1

OPMODE[1]

15

OPMODE[0]

16

CLKOUT

17

LINESTATE[1]

18

LINESTATE[0]

Figure 3.1 USB3450 Pinout - Top View

The flag of the QFN package must be connected to ground.

19

VDD1.8

20

VDD3.3

29

28

27

26

25

24

23

22

21

DATA[0]

DATA[1]

DATA[2]

DATA[3]

DATA[4]

DATA[5]

DATA[6]

DATA[7]

HOSTDISC

Revision 0.1 (05-11-05) 10 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

3.2 Pin Definitions

Table 3.1 USB3450 Pin Definitions

PIN NAME

1 XCVRSEL[0] Input N/A Transceiver Select. These signals select between

2 TERMSEL Input N/A Termination Select. This signal selects between the

3 TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the

4 SUSPENDN Input Low Suspend. Places the transceiver in a mode that

DIRECTION,

TYPE

ACTIVE

LEVEL DESCRIPTION

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

FS and HS terminations:
0: HS termination enabled
1: FS termination enabled

Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.

draws minimal power from supplies. In host mode,
R

is removed during suspend. In device mode,

PU

R

is controlled by TERMSEL. In suspend mode

PD

the clocks are off.
0: PHY in suspend mode
1: PHY in normal operation

5 TXVALID Input High Transmit Valid. Indicates that the DATA bus is valid

6 RESET Input High Reset. Reset all state machines. After coming out

7 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

8 DP I/O,

Analog

9 DM I/O,

Analog

10 NC N/A N/A No Connect.

11 VDD3.3 N/A N/A 3.3V PHY Supply.

N/A D+ pin of the USB cable.

N/A D- pin of the USB cable.

for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.

Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.

of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

SMSC USB3450 11 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Table 3.1 USB3450 Pin Definitions (continued)

Datasheet

PIN NAME

12 XCVRSEL[1] Input N/A Transceiver Select. These signals select between

13 RXACTIVE Output High Receive Active. Indicates that the receive state

14 OPMODE[1] Input N/A Operational Mode. These signals select between

15

16 CLKOUT Output,

17 LINESTATE[1] Output N/A Line State. These signals reflect the current state of

18

OPMODE[0] Input N/A

LINESTATE[0] Output N/A

DIRECTION,

TYPE

CMOS

ACTIVE

LEVEL DESCRIPTION

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

machine has detected Start of Packet and is active.

the various operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved

N/A 60MHz reference clock output. All UTMI+ signals are

driven synchronous to this clock.

the USB data bus in FS mode. Bit [0] reflects the
state of DP and bit [1] reflects the state of DM. When
the device is suspended or resuming from a
suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0 0 0: SEO
0 1 1: J State
1 0 2: K State
1 1 3: SE1

19 VDD1.8 N/A N/A 1.8V regulator output for digital circuitry on chip.

20 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

21 HOSTDISC Output High Host Disconnect. Indicates that a downstream

Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 19
to pin 34.

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

device has been disconnected from this host PHY
when operating in HS host mode. Automatically
reset to 0b when Low Power Mode is entered.

Revision 0.1 (05-11-05) 12 SMSC USB3450

DATASHEET