SMSC USB3450 Technical data

查询USB3450供应商

USB3450

Hi-Speed USB Host or
Device PHY With UTMI+
Interface

PRODUCT FEATURES

■ USB-IF “Hi-Speed” certified to the Universal Serial

Bus Specification Rev 2.0

■ Interface compliant with the UTMI+ Specification,

Revision 1.0.

■ Functional as a host or device PHY.

■ Supports HS, FS, and LS data rates.

■ Supports FS pre-amble for FS hubs with a LS device

attached (UTMI+ Level 3)

■ Supports HS SOF and LS keep alive pulse.

■ Low Latency Hi-Speed Receiver (43 Hi-Speed clocks

Max)

■ Internal 1.8 volt regulators allow operation from a

single 3.3 volt supply

■ Internal short circuit protection of DP and DM lines to

VBUS or ground.

Datasheet

■ Integrated 24MHz Crystal Oscillator supports either

crystal operation or 24MHz external clock input.

■ Internal PLL for 480MHz Hi-Speed USB operation.

■ Supports Hi-Speed USB and legacy USB 1.1 devices

■ 55mA Unconfigured Current (typical) - ideal for bus

powered applications.

■ 83uA suspend current (typical) - ideal for battery

powered applications.

■ Full Commercial operating temperature range from

°C to +70°C

0

■ 40 pin QFN package; green, lead-free (6 x 6 x 0.9mm

height)

SMSC USB3450 DATASHEET Revision 0.1 (05-11-05)

y

r

r

Y

Hi-Speed USB Host or Device PHY With UTMI+ Interface

ORDER NUMBER(S): USB3450-FZG FOR 40 PIN, QFN PACKAGE (GREEN, LEAD-FREE)

Datasheet

Hauppauge, NY 11788
[phone]
FAX [phone]

80 Arkay Drive

Copyright © 2005 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently,
complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be
accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any
time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this
information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual
property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product ma
contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or othe
application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written
approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or othe
SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a
registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective
holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE,
AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE
LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA,
PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT;
NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMED
OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.

Revision 0.1 (05-11-05) 2 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

0.1 Reference Documents

■ Universal Serial Bus Specification, Revision 2.0, April 27, 2000

■ Hi-Speed Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000

■ UTMI+ Specification, Revision 1.0, February 2, 2004

SMSC USB3450 3 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Table of Contents

0.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Pin Configuration and Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 USB3450 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 6 Detailed Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 8bit Bi-Directional Data Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.3 RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4 Hi-Speed Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.1 High Speed and Full Speed Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.6.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 7 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.1 Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.3 Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.8 HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.9 HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.14 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision 0.1 (05-11-05) 4 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

List of Figures

Figure 1.1 Basic UTMI+ USB Device Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 1.2 UTMI+ Level 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2.1 USB3450 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.1 USB3450 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 6.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 6.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 7.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7.9 USB3450 Application Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline, 6 x 6 x 0.9 mm Body (Lead Free) . . . . . . . . . 40

SMSC USB3450 5 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

List of Tables

Table 3.1 USB3450 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5.1 Electrical Characteristics: Supply Pins (Note 5.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.2 Electrical Characteristics: CLKOUT Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.3 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5.6 Regulator Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6.1 DP/DM termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 7.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7.3 Hi-Speed Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 7.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 7.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision 0.1 (05-11-05) 6 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Chapter 1 General Description

The USB3450 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3450 uses
a UTMI+ interface to connect to an SOC or ASIC or FPGA. SMSC’s advanced proprietary technology
minimizes power dissipation, resulting in maximum battery life for portable applications. The USB3450
is a flexible solution for adding USB to new designs without integrating the analog PHY block.

SOC/FPGA/ASIC

Including Device Controller

Hi-Speed

USB App.

The USB3450 provides a fully compliant Hi-Speed interface, and supports Hi-Speed (HS), Full-Speed
(FS), and Low-Speed (LS) USB. The USB3450 supports all levels of the UTMI+ specification as shown
in Figure 1.2.

UTMI+

Link

Figure 1.1 Basic UTMI+ USB Device Block Diagram

Hi-Speed Peripheral, host controllers, On-

(HS, FS, LS, preamble packet)

UTMI+

Interface

UTMI+
Digital

Logic

UTMI+ Level 3

the-Go devices

USB3450

Hi-

Speed

Analog

V

DM

BUS

ID

DP

USB

Connector

(Standard

or Mini)

USB3450

USB3500

UTMI+ Level 2

Hi-Speed Peripheral, host controllers, On-

the-Go devices

(HS, FS, and LS but no preamble packet)

UTMI+ Level 1

Hi-Speed Peripheral, host controllers,

ADDED FEATURES

and On-the-Go devices

(HS and FS Only)

UTMI+ Level 0

Hi-Speed Peripherals Only

Figure 1.2 UTMI+ Level 3 Support

SMSC USB3450 7 Revision 0.1 (05-11-05)

USB3280
USB3250

DATASHEET

1.1 Applications

The USB3450 is targeted for any application where a high speed USB connection is desired.

The USB3450 is well suited for:

■ Cell Phones

■ MP3 Players

■ Scanners

■ Set Top Boxes

■ Printers

■ External Hard Drives

■ Still and Video Cameras

■ Portable Media Players

■ Entertainment Devices

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Revision 0.1 (05-11-05) 8 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Chapter 2 Functional Overview

The USB3450 is a highly integrated USB transceiver system. It contains a complete Hi-Speed PHY
with the UTMI+ industry standard interface to support fast time to market for a USB controller. The
USB3450 is composed of the functional blocks shown in Figure 2.1 below.

m

24 MHz

XI

VDD1.8

VDDA1.8

XTAL

XO

VDD3.3

XCVRSEL[1:0]

TERMSEL
TXREADY

SUSPENDN

TXVALID

RESET

RXACTIVE

OPMODE[1:0]

CLKOUT

LINESTATE[1:0]

HOSTDISC

DATA[7:0]

HOST

RXERROR

Internal

Regulator &

POR

UTMI+

Digital

Figure 2.1 USB3450 Block Diagram

XTAL &

PLL

HS XCVR

FS/LS
XCVR

USB3450

Rpu_dp

Rpu_dm

Rpd_dp

Rpd_dm

Resistors

Bias
Gen.

VDD3.3

DP
DM

RBIAS

Mini-AB

USB

Connector

SMSC USB3450 9 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Chapter 3 Pin Configuration and Pin Definitions

The USB3450 is offered in a 40 pin QFN package. The pin definitions and locations are documented
below.

3.1 USB3450 Pin Locations

RBIAS

VDD3.3

VDD3.3

VDDA1.8

XI

XO

VDD1.8

VDD3.3

RXERROR

HOST

34

33

32

31

30

RXVALID

XCVRSEL0

40

39

38

37

36

35

1

Datasheet

TERMSEL

TXREADY

SUSPENDN

TXVALID

RESET

VDD3.3

DM

DP

NC

2

3

4

5

6

7

8

9

10

11

VDD3.3

USB3450

Hi-Speed USB

UTMI+ PHY

40 Pin QFN

GND FLAG

12

13

14

RXACTIVE

XCVRSEL1

OPMODE[1]

15

OPMODE[0]

16

CLKOUT

17

LINESTATE[1]

18

LINESTATE[0]

Figure 3.1 USB3450 Pinout - Top View

The flag of the QFN package must be connected to ground.

19

VDD1.8

20

VDD3.3

29

28

27

26

25

24

23

22

21

DATA[0]

DATA[1]

DATA[2]

DATA[3]

DATA[4]

DATA[5]

DATA[6]

DATA[7]

HOSTDISC

Revision 0.1 (05-11-05) 10 SMSC USB3450

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

3.2 Pin Definitions

Table 3.1 USB3450 Pin Definitions

PIN NAME

1 XCVRSEL[0] Input N/A Transceiver Select. These signals select between

2 TERMSEL Input N/A Termination Select. This signal selects between the

3 TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the

4 SUSPENDN Input Low Suspend. Places the transceiver in a mode that

DIRECTION,

TYPE

ACTIVE

LEVEL DESCRIPTION

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

FS and HS terminations:
0: HS termination enabled
1: FS termination enabled

Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.

draws minimal power from supplies. In host mode,
R

is removed during suspend. In device mode,

PU

R

is controlled by TERMSEL. In suspend mode

PD

the clocks are off.
0: PHY in suspend mode
1: PHY in normal operation

5 TXVALID Input High Transmit Valid. Indicates that the DATA bus is valid

6 RESET Input High Reset. Reset all state machines. After coming out

7 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

8 DP I/O,

Analog

9 DM I/O,

Analog

10 NC N/A N/A No Connect.

11 VDD3.3 N/A N/A 3.3V PHY Supply.

N/A D+ pin of the USB cable.

N/A D- pin of the USB cable.

for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.

Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.

of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Table 3.1 USB3450 Pin Definitions (continued)

Datasheet

PIN NAME

12 XCVRSEL[1] Input N/A Transceiver Select. These signals select between

13 RXACTIVE Output High Receive Active. Indicates that the receive state

14 OPMODE[1] Input N/A Operational Mode. These signals select between

15

16 CLKOUT Output,

17 LINESTATE[1] Output N/A Line State. These signals reflect the current state of

18

OPMODE[0] Input N/A

LINESTATE[0] Output N/A

DIRECTION,

TYPE

CMOS

ACTIVE

LEVEL DESCRIPTION

the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times

machine has detected Start of Packet and is active.

the various operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved

N/A 60MHz reference clock output. All UTMI+ signals are

driven synchronous to this clock.

the USB data bus in FS mode. Bit [0] reflects the
state of DP and bit [1] reflects the state of DM. When
the device is suspended or resuming from a
suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0 0 0: SEO
0 1 1: J State
1 0 2: K State
1 1 3: SE1

19 VDD1.8 N/A N/A 1.8V regulator output for digital circuitry on chip.

20 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

21 HOSTDISC Output High Host Disconnect. Indicates that a downstream

Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. Connect pin 19
to pin 34.

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

device has been disconnected from this host PHY
when operating in HS host mode. Automatically
reset to 0b when Low Power Mode is entered.

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Datasheet

Table 3.1 USB3450 Pin Definitions (continued)

PIN NAME

22 DATA[7] I/O,

23 DATA[6] I/O,

24

25

26

27

28

DATA[5] I/O,

DATA[4] I/O,

DATA[3] I/O,

DATA[2] I/O,

DATA[1] I/O,

DIRECTION,

TYPE

CMOS,

Pull-low

CMOS,

Pull-low

CMOS,

Pull-low

CMOS,

Pull-low

CMOS,

Pull-low

CMOS,

Pull-low

CMOS,

Pull-low

ACTIVE

LEVEL DESCRIPTION

N/A 8-bit bi-directional data bus. Data[7] is the MSB and

Data[0] is the LSB.

N/A

N/A

N/A

N/A

N/A

N/A

29

30 RXVALID Output High Receive Data Valid. Indicates that the DATA bus has

31

32 RXERROR Output High Receive Error. This output is clocked with the same

33 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

34 VDD1.8 N/A N/A 1.8V regulator output for digital circuitry on chip.

35

DATA[0] I/O,

CMOS,

Pull-low

HOST Input N/A Host Pull-down Select. This signal enables the 15k

XO Output,

Analog

N/A

received valid data. The Receive Data Holding
Register is full and ready to be unloaded. The Link
is expected to register the DATA bus on the rising
edge of CLKOUT.

Ohm pull-down resistor on the DM line.
0: Pull-down resistor not connected to DM
1: Pull-down resistor connected to DM

timing as the receive DATA lines and can occur at
anytime during a transfer.
0: Indicates no error.
1: Indicates a receive error has been detected.

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

Place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground.
Connect pin 34 to pin 19. See Section 6.6.1,

"Internal Regulators".

N/A Crystal pin. If using an external clock on XI this pin

should be floated.

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Table 3.1 USB3450 Pin Definitions (continued)

Datasheet

PIN NAME

36 XI Input,

37 VDDA1.8 N/A N/A 1.8V regulator output for analog circuitry on chip.

38 VDD3.3 N/A N/A 3.3V PHY Supply. Provides power for Hi-Speed

39 VDD3.3 N/A N/A 3.3V PHY Supply. Should be connected directly to

40

RBIAS Analog,

GND FLAG Ground N/A Ground. The flag must be connected to the ground

DIRECTION,

TYPE

Analog

CMOS

ACTIVE

LEVEL DESCRIPTION

N/A Crystal pin. A 24MHz crystal is supported. The

crystal is placed across XI and XO. An external
24MHz clock source may be driven into XI in place
of a crystal.

Place a 0.1uF capacitor near this pin and connect
the capacitor from this pin to ground. In parallel,
place a 4.7uF low ESR capacitor near this pin and
connect the capacitor from this pin to ground. See

Section 6.6.1, "Internal Regulators".

Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.

pin 39.

N/A External 1% bias resistor. Requires a 12KΩ resistor

to ground.

plane.

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Datasheet

Chapter 4 Limiting Values

Table 4.1 Maximum Guaranteed Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maximum VBUS, ID, DP,
and DM voltage to GND

Maximum VDD1.8 and
VDDA1.8 voltage to

V

MAX_5V

V

MAX_1.8V

-0.5 +5.5 V

-0.5 2.5 V

Ground

Maximum 3.3V supply
voltage to Ground

Maximum I/O voltage to
Ground

Operating Temperature T

Storage Temperature T

V

MAX_3.3V

V

MAX_IN

MAX_OP

MAX_STG

-0.5 4.0 V

-0.5 4.0 V

070C

-55 150 C

Note: Stresses above those listed could cause damage to the device. This is a stress rating only and

functional operation of the device at any other condition above those indicated in the operation
sections of this specification is not implied. When powering this device from laboratory or
system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies exhibit voltage spikes on their outputs when the
AC power is switched on or off. In addition, voltage transients on the AC power line may appear
on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.

Table 4.2 Recommended Operating Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

3.3V Supply Voltage V

Input Voltage on Digital Pins V

Input Voltage on Analog I/O
Pins (DP, DM)

Ambient Temperature T

DD3.3

I

V

I(I/O)

A

3.0 3.3 3.6 V

0.0 V

0.0 V

DD3.3

DD3.3

0+70

V

V

o

C

Table 4.3 Recommended External Clock Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

System Clock Frequency XI driven by the external clock;

and no connection at XO

System Clock Duty Cycle XI driven by the external clock;

45 50 55 %

(±

100ppm)

2 4

MHz

and no connection at XO

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Chapter 5 Electrical Characteristics

Table 5.1 Electrical Characteristics: Supply Pins (Note 5.1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Datasheet

Unconfigured Current I

FS Idle Current I

FS Transmit Current I

FS Receive Current I

HS Idle Current I

HS Transmit Current I

HS Receive Current I

Low Power Mode I

Note 5.1 V

= 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.

DD3.3

Table 5.2 Electrical Characteristics: CLKOUT Start-Up

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVG (UC FG )

AVG (FS)

AVG(FSTX)

AVG (FSR X)

AVG (HS )

AVG (HS TX )

AVG(HSRX)

DD(LPM)

Device Unconfigured 55 mA

FS idle not data transfer 55 mA

FS current during data

60.5 mA

transmit

FS current during data

57.5 mA

receive

FS idle not data transfer 60.6 mA

FS current during data

62.4 mA

transmit

FS current during data

61.5 mA

receive

VBUS 15kΩ pull-down and

83 uA

1.5kΩ pull-up resistor
currents not included.

Suspend Recovery Time T

START

2.25 3.5 ms

Table 5.3 DC Electrical Characteristics: Logic Pins

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Low-Level Input Voltage V

High-Level Input Voltage V

Low-Level Output Voltage V

High-Level Output Voltage V

Input Leakage Current I

IL

IH

OL

OH

LI

IOL = 8mA 0.4 V

IOH = -8mA V

V

SS

2.0 V

DD3.3

- 0.4

0.8 V

DD3.3

V

V

±10 uA

Pin Capacitance Cpin 4 pF

Note: V

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= 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.

DD3.3

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Datasheet

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS FUNCTIONALITY

Input levels

Differential Receiver Input
Sensitivity

Differential Receiver
Common-Mode Voltage

Single-Ended Receiver Low
Level Input Voltage

Single-Ended Receiver High
Level Input Voltage

Single-Ended Receiver
Hysteresis

Output Levels

Low Level Output Voltage V

High Level Output Voltage V

Termination

Driver Output Impedance for
HS and FS

Input Impedance Z

Pull-up Resistor Impedance Z

Pull-up Resistor Impedance Z

Pull-dn Resistor Impedance Z

HS FUNCTIONALITY

V

DIFS

V

CMFS

V

ILSE

V

IHSE

V

HYSSE

FSOL

FSOH

Z

HSDRV

INP

PU

PURX

PD

| V(DP) - V(DM) | 0.2 V

0.8 2.5 V

0.8 V

2.0 V

0.050 0.150 V

Pull-up resistor on DP;
RL = 1.5kΩ to V

DD3.3

Pull-down resistor on DP,

2.8 3.6 V

0.3 V

DM;
RL = 15kΩ to GND

Steady state drive 40.5 45 49.5 Ù

TX, RPU disabled 1.0 MΩ

Bus Idle 0.900 1.24 1.575 kΩ

Device Receiving 1.425 2.26 3.09 kΩ

14.25 15.0 15.75 kΩ

Input levels

HS Differential Input
Sensitivity

HS Data Signaling Common
Mode Voltage Range

HS Squelch Detection
Threshold (Differential) V

V

DIHS

V

CMHS

HSSQ

| V(DP) - V(DM) | 100 mV

-50 500 mV

Squelch Threshold 100 mV

Un-squelch Threshold 150 mV

Output Levels

Hi-Speed Low Level
Output Voltage (DP/DM

V

HSOL

45Ω load -10 10 mV

referenced to GND)

Hi-Speed High Level
Output Voltage (DP/DM

V

HSOH

45Ω load 360 440 mV

referenced to GND)

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Datasheet

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Hi-Speed IDLE Level
Output Voltage (DP/DM

V

OLHS

45Ω load -10 10 mV

referenced to GND)

Chirp-J Output Voltage
(Differential)

V

CHIRPJ

HS termination resistor
disabled, pull-up resistor

700 1100 mV

connected. 45Ω load.

Chirp-K Output Voltage
(Differential)

V

CHIRPK

HS termination resistor
disabled, pull-up resistor

-900 -500 mV

connected. 45Ω load.

Leakage Current

OFF-State Leakage Current I

LZ

±10 uA

Port Capacitance

Transceiver Input
Capacitance

Note: V

DD3.3

C

IN

Pin to GND 5 10 pF

= 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS Output Driver Timing

Rise Time T

Fall Time T

Output Signal Crossover
Voltage

Differential Rise/Fall Time
Matching

HS Output Driver Timing

Differential Rise Time T

Differential Fall Time T

Driver Waveform
Requirements

Hi-Speed Mode Timing

Receiver Waveform
Requirements

Data Source Jitter and
Receiver Jitter Tolerance

Note: V

= 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified.

DD3.3

CL = 50pF; 10 to 90% of
|VOH - VOL|

CL = 50pF; 10 to 90% of
|VOH - VOL|

Excluding the first
transition from IDLE state

V

FSR

FFF

CRS

FRFM Excluding the first

transition from IDLE state

HSR

HSF

Eye pattern of Template 1
in Hi-Speed specification

Eye pattern of Template 4
in Hi-Speed specification

Eye pattern of Template 4
in Hi-Speed specification

420ns

420ns

1.3 2.0 V

90 111.1 %

500 ps

500 ps

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Datasheet

Table 5.6 Regulator Output Voltages

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

DDA1.8

V

DDA1.8

V

DD1.8

Note: V

V

DDA1.8

V

DDA1.8

V

DD1.8

= 3.0 to 3.6V; VSS = 0V; TA = 0C to +70C; unless otherwise specified

DD3.3

Normal Operation
(SUSPENDN = 1)

Low Power mode
(SUSPENDN = 0)

1.6 1.8 2.0 V

1.6 1.8 2.0 V

0V

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Chapter 6 Detailed Functional Overview

Figure 2.1 on page 9 shows the functional block diagram of the USB3450. Each of the functions is

described in detail below.

6.1 8bit Bi-Directional Data Bus Operation

The USB3450 supports an 8-bit bi-directional parallel interface.

■ CLKOUT runs at 60MHz

■ The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1

■ The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0

Figure 6.1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode.

TXREADY is only asserted for one CLKOUT per byte time to signal the Link that the data on the DATA
lines has been read by the PHY. The Link may hold the data on the DATA lines for the duration of the
byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT.

Datasheet

Figure 6.1 FS CLK Relationship to Transmit Data and Control Signals

Figure 6.2 shows the relationship between CLKOUT and the receive data control signals in FS mode.

RXACTIVE “frames” a packet, transitioning only at the beginning and end of a packet. However
transitions of RXVALID may take place any time 8 bits of data are available. Figure 6.2 also shows
how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be
presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing
relationship is applied to the data and control signals.

Figure 6.2 FS CLK Relationship to Receive Data and Control Signals

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6.2 TX Logic

This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the Link and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in Figure 6.3.

Figure 6.3 Transmit Timing for a Data Packet

The behavior of the Transmit State Machine is described below.

■ The Link asserts TXVALID to begin a transmission.

■ After the Link asserts TXVALID it can assume that the transmission has started when it detects

TXREADY has been asserted.

■ The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID

are asserted on the rising edge of CLKOUT.

■ The Link must have valid packet information (PID) asserted on the DATA bus coincident with the

assertion of TXVALID.

■ TXREADY is sampled by the Link on the rising edge of CLKOUT.

■ The Link negates TXVALID to complete a packet. Once negated, the transmit logic will never

reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALD asserts again.

■ The USB3450 is ready to transmit another packet immediately, however the Link must conform to

the minimum inter-packet delays identified in the Hi-Speed specification.

■ Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3450

will sample the disconnect comparator at the 32nd bit of the 40 bit long EOP during SOF packets.

■ Supports FS pre-amble for FS hubs with a LS device.

■ Supports LS keep alive by receiving the SOF PID.

■ Supports Host mode resume K which ends with two low speed times of SE0 followed by 1 FS “J”.

6.3 RX Logic

This block receives serial data from the clock recovery circuits and processes it to be transferred to
the Link on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial
to parallel conversion. Upon valid assertion of the proper RX control lines, the RX Logic block will
provide bytes to the DATA bus as shown in the figures below. The behavior of the receiver is described
below.

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Figure 6.4 Receive Timing for Data with Unstuffed Bits

The assertion of RESET will cause the USB3450 to deasserts RXACTIVE and RXVALID. When the
RESET signal is deasserted the Receive State Machine starts looking for a SYNC pattern on the USB.
When a SYNC pattern is detected the receiver will assert RXACTIVE. The length of the received Hi­Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end
of five hubs.

After valid serial data is received, the data is loaded into the RX Holding Register on the rising edge
of CLKOUT and RXVALID is asserted. The Link must clock the data off the DATA bus on the next
rising edge of CLKOUT. In normal mode (OPMODE = 00), then stuffed bits are stripped from the data
stream. Each time 8 stuffed bits are accumulated the USB3450 will negate RXVALID for one clock
cycle, thus skipping a byte time.

When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has
been stripped the USB3450 will begin looking for the next packet.

The behavior of the USB3450 receiver is described below:

■ RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.

■ After a EOP is complete the receiver will begin looking for SYNC.

■ The USB3450 asserts RXACTIVE when SYNC is detected.

■ The USB3450 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty.

■ When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.

■ RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.

This will occur if 8 stuffed bits have been accumulated.

■ The Link must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data

state).

■ Figure 6.5 shows the timing relationship between the received data (DP/DM), RXVALID,

RXACTIVE, RXERROR and DATA signals.

Notes:

■ Figure 6.5, Figure 6.6 and Figure 6.7 are timing examples of a HS/FS PHY when it is in HS mode.

When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time.
The Receive State Machine assumes that the Link captures the data on the DATA bus if RXACTIVE
and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte
time.

■ In Figure 6.5, Figure 6.6 and Figure 6.7 the SYNC pattern on DP/DM is shown as one byte long.

The SYNC pattern received by a device can vary in length. These figures assume that all but the
last 12 bits have been consumed by the hubs between the device and the host controller.

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Datasheet

Figure 6.5 Receive Timing for a Handshake Packet (no CRC)

Figure 6.6 Receive Timing for Setup Packet

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Datasheet

Figure 6.7 Receive Timing for Data Packet (with CRC-16)

The receivers connect directly to the USB cable. The block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE.
For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.

6.4 Hi-Speed Transceiver

The SMSC Hi-Speed Transceiver consists of four blocks in the lower left corner of Figure 2.1 on

page 9. These four blocks are labeled HS XCVR, FS/LS XCVR, Resistors, and Bias Gen.

6.4.1 High Speed and Full Speed Transceivers

The USB3450 transceiver meets all requirements in the Hi-Speed specification.

The receivers connect directly to the USB cable. This block contains a separate differential receiver
for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream
through the multiplexer to the RX Logic block. The FS mode section of the FS/HS RX block also
consists of a single-ended receiver on each of the data lines to determine the correct FS linestate. For
HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never
interpreted as data.

The transmitters connect directly to the USB cable. The block contains a separate differential FS and
HS transmitter which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit
it on the USB cable.

6.4.2 Termination Resistors

The USB3450 transceiver fully integrates all of the USB termination resistors. The USB3450 includes
two 1.5kΩ pull-up resistors on DP and DM and a 15kΩ pull-down resistor on both DP and DM. In
addition the 45Ω high speed termination resistors are also integrated. These integrated resistors
require no tuning or trimming by the Link. The state of the resistors is determined by the operating
mode of the PHY. The possible valid resistor combinations are shown in Ta bl e 6 .1 . Operation is
guaranteed in the configurations given in Table 6.1, "DP/DM termination vs. Signaling Mode".

■ RPU_DP_EN activates the 1.5kΩ DP pull-up resistor

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

■ RPU_DM_EN activates the 1.5kΩ DM pull-up resistor

■ RPD_DP_EN activates the 15kΩ DP pull-down resistor

■ RPD_DM_EN activates the 15kΩ DM pull-down resistor

■ HSTERM_EN activates the 45Ω DP and DM high speed termination resistors

Table 6.1 DP/DM termination vs. Signaling Mode

UTMI+ INTERFACE

SETTINGS RESISTOR SETTINGS

HOST

SIGNALING MODE

TERMSEL

XCVRSEL[1:0]

OPMODE[1:0]

RPU_DP_EN

RPD_DP_EN

RPU_DM_EN

RPD_DM_EN

General Settings

Tri-State Drivers XXb Xb 01b Xb 0b 0b 0b 0b 0b

Power-up or Vbus < V

SESSEND

01b 0b 00b 1b 0b 0b 1b 1b 0b

Host Settings

Host Chirp 00b 0b 10b 1b 0b 0b 1b 1b 1b

Host Hi-Speed 00b 0b 00b 1b 0b 0b 1b 1b 1b

Host Full Speed X1b 1b 00b 1b 0b 0b 1b 1b 0b

Host HS/FS Suspend 01b 1b 00b 1b 0b 0b 1b 1b 0b

Host HS/FS Resume 01b 1b 10b 1b 0b 0b 1b 1b 0b

Host low Speed 10b 1b 00b 1b 0b 0b 1b 1b 0b

Host LS Suspend 10b 1b 00b 1b 0b 0b 1b 1b 0b

Host LS Resume 10b 1b 10b 1b 0b 0b 1b 1b 0b

Host Test J/Test_K 00b 0b 10b 1b 0b 0b 1b 1b 1b

Peripheral Settings

HSTERM_EN

Peripheral Chirp 00b 1b 10b 0b 1b 0b 0b 0b 0b

Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 1b

Peripheral FS 01b 1b 00b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Resume 01b 1b 10b 0b 1b 0b 0b 0b 0b

Peripheral LS 10b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral LS Suspend 10b 1b 00b 0b 0b 1b 0b 0b 0b

Peripheral LS Resume 10b 1b 10b 0b 0b 1b 0b 0b 0b

Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 1b

SMSC USB3450 25 Revision 0.1 (05-11-05)

DATASHEET

6.4.3 Bias Generator

This block consists of an internal bandgap reference circuit used for generating the high speed driver
currents and the biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance,
external reference resistor connected from RBIAS to ground.

6.5 Crystal Oscillator and PLL

The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.

The USB3450 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.9. If a clock
oscillator is used the clock should be connected to the XI input and the XO pin left floating. When an
external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an
external clock the user needs to take care to ensure the external clock source is clean enough to not
degrade the high speed eye performance.

Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz
clock. The USB3450 is guaranteed to start the clock within the time specified in Ta b le 5 .2 .

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

6.6 Internal Regulators and POR

The USB3450 includes an integrated set of built in power management functions. These power
management features include a POR generation and allow the USB3450 to be powered from a single

3.3 volt power supply. This reduces the bill of materials and simplifies product design.

6.6.1 Internal Regulators

The USB3450 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8)
from the 3.3volt power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low
ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they
exhibit an ESR lower that 0.1ohm at frequencies greater than 10kHz..

The specific capacitor recommendations for each pin are detailed in Table 3.1, “USB3450 Pin

Definitions,” on page 11, and shown in Figure 7.9 USB3450 Application Diagram (Top View) on
page 39.

Note: The USB3450 regulators are designed to generate a 1.8 volt supply for the USB3450 only.

Using the regulators to provide current for other circuits is not recommended and SMSC does
not guarantee USB performance or regulator stability.

6.6.2 Power On Reset (POR)

The USB3450 provides an internal POR circuit that generates a reset pulse once the PHY supplies
are stable. The UTMI+ Digital can be reset at any time with the RESET pin.

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Chapter 7 Application Notes

The following sections consist of select functional explanations to aid in implementing the USB3450
into a system. For complete description and specifications consult the Hi-Speed Transceiver Macrocell
Interface Specification and Universal Serial Bus Specification Revision 2.0.

7.1 Linestate

The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend
on the state of XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is
enabled (XCVRSELECT = 0) and FS thresholds when the FS transceiver is enabled (XCVRSELECT
= 1). There is not a concept of variable single-ended thresholds in the Hi-Speed specification for HS
mode.

The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified
with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3450, as an
alternative to using variable thresholds for the single-ended receivers, the following approach is used.

Table 7.1 Linestate States

STATE OF DP/DM LINES

LINESTATE[1:0]

0 0 SE0 Squelch Squelch

01J

1 0 K Invalid

1 1 SE1 Invalid Invalid

In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The Link monitors LINESTATE[1:0]
for the IDLE state. To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of

Squelch is used to force LINESTATE[1:0] to a J state.

FULL SPEED

XCVRSELECT =1

TERMSELECT=1

HIGH SPEED

XCVRSELECT =0

TERMSELECT=0

Squelch

7.2 OPMODES

The OPMODE[1:0] pins allow control of the operating modes.

Table 7.2 Operational Modes

MODE[1:0] STATE# STATE NAME DESCRIPTION

CHIRP MODE

XCVRSELECT =0

TERMSELECT=1LS[1] LS[0]

Squelch &

HS Diff. Receiver Output

Squelch &

HS Diff. Receiver Output

00 0 Normal Operation Transceiver operates with normal USB data encoding and

01 1 Non-Driving Allows the transceiver logic to support a soft disconnect feature

SMSC USB3450 27 Revision 0.1 (05-11-05)

decoding

which tri-states both the HS and FS transmitters, and removes
any termination from the USB making it appear to an upstream
port that the device has been disconnected from the bus

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Table 7.2 Operational Modes (continued)

MODE[1:0] STATE# STATE NAME DESCRIPTION

Datasheet

10 2 Disable Bit Stuffing

11 3 Reserved N/A

The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are
quiescent, i.e. when entering a test mode or for a device initiated resume.

When using OPMODE[1:0] = 10 the SYNC and EOP patterns are not transmitted.

The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted
(the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the
USB3450 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also
be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other
conditions, while the transceiver is transmitting or receiving data will generate undefined results.

and NRZI encoding

7.3 Test Mode Support

Table 7.3 Hi-Speed Test Modes

HI-SPEED TEST MODES

SE0_NAK State 0 No transmit HS

OPERATIONAL MODE

Disables bitstuffing and NRZI encoding logic so that 1's loaded
from the DATA bus become 'J's on the DP/DM and 0's become
'K's

USB3450 SETUP

LINK TRANSMITTED

DATA

XCVRSELECT &

TERMSELECT

J State 2 All '1's HS

K State 2 All '0's HS

Test_Packet State 0 Test Packet data HS

7.4 SE0 Handling

For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset.
When asserted in an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for
more than 2.5us is interpreted as a reset by the device operating in FS mode.

For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS
device cannot use the 2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the
bus is often in this state between packets. If no bus activity (IDLE) is detected for more than 3ms, a
HS device must determine whether the downstream facing port is signaling a suspend or a reset. The
following section details how this determination is made. If a reset is signaled, the HS device will then
initiate the HS Detection Handshake protocol.

7.5 Reset Detection

If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
Link must then check LINESTATE for the SE0 condition. If SE0 is asserted at time T2, then the
upstream port is forcing the reset state to the device (i.e., a Driven SE0). The device will then initiate
the HS detection handshake protocol.

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Datasheet

Figure 7.1 Reset Timing Behavior (HS Mode)

Table 7.4 Reset Timing Values (HS Mode)

TIMING

PARAMETER DESCRIPTION VALUE

HS Reset T0 Bus activity ceases, signaling either a reset

or a SUSPEND.

T1 Earliest time at which the device may place

itself in FS mode after bus activity stops.

T2 Link samples LINESTATE. If LINESTATE =

SE0, then the SE0 on the bus is due to a
Reset state. The device now enters the HS
Detection Handshake protocol.

0 (reference)

HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms

T1 + 100µs < T2 <
T1 + 875µs

7.6 Suspend Detection

If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This
enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The
Link must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream
port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4 the
device must be fully suspended.

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Figure 7.2 Suspend Timing Behavior (HS Mode)

Table 7.5 Suspend Timing Values (HS Mode)

Datasheet

TIMING

PARAMETER DESCRIPTION VALUE

HS Reset T0 End of last bus activity, signaling either a reset

or a SUSPEND.

T1 The time at which the device must place itself

in FS mode after bus activity stops.

T2 Link samples LINESTATE. If LINESTATE = 'J',

then the initial SE0 on the bus (T0 - T1) had
been due to a Suspend state and the Link
remains in HS mode.

T3 The earliest time where a device can issue

Resume signaling.

T4 The latest time that a device must actually be

suspended, drawing no more than the
suspend current from the bus.

0 (reference)

HS Reset T0 + 3. 0ms < T1 < HS Reset T0
+ 3.125ms

T1 + 100 µs < T2 <
T1 + 875µs

HS Reset T0 + 5ms

HS Reset T0 + 10ms

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Datasheet

7.7 HS Detection Handshake

The High Speed Detection Handshake process is entered from one of three states: suspend, active
FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS
Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4
ms before initiating the HS Detection Handshake. These states are described in the Hi-Speed
specification.

There are three ways in which a device may enter the HS Handshake Detection process:

1. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS
handshake detection process.

2. If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS
handshake detection process.

3. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the
HS handshake detection process. In HS mode, a device must first determine whether the SE0 state
is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing
XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms
before the reversion to FS mode. After reverting to FS mode, no less than 100µs and no more
than 875µs later the Link must check the LINESTATE signals. If a J state is detected the device
will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake
detection process.

In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval
is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion
of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms.

This transceiver design pushes as much of the responsibility for timing events on to the Link as
possible, and the Link requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3
above, CLKOUT has been running and is stable, however in case 1 the USB3450 is reset from a
suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered
down. A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K.

7.8 HS Detection Handshake – FS Downstream Facing Port

Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the host port.

If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and
the alternating sequence of HS Chirp K’s and J’s is not generated. If no chirps are detected (T4) by
the device, it will enter FS mode by returning XCVRSELECT to FS mode.

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Datasheet

Figure 7.3 HS Detection Handshake Timing Behavior (FS Mode)

Table 7.6 HS Detection Handshake Timing Values (FS Mode)

TIMING

PARAMETER DESCRIPTION VALUE

T0 HS Handshake begins. DP pull-up enabled, HS

terminations disabled.

T1 Device enables HS Transceiver and asserts Chirp

K on the bus.

T2 Device removes Chirp K from the bus. 1ms

minimum width.

T3 Earliest time when downstream facing port may

assert Chirp KJ sequence on the bus.

T4 Chirp not detected by the device. Device reverts to

FS default state and waits for end of reset.

T5 Earliest time at which host port may end reset HS Reset T0 + 10ms

Notes:

■ T0 may occur to 4ms after HS Reset T0.

■ The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.

0 (reference)

T0 < T1 < HS Reset T0 + 6.0ms

T1 + 1.0 ms < T2 <
HS Reset T0 + 7.0ms

T2 < T3 < T2+100µs

T2 + 1.0ms < T4 <
T2 + 2.5ms

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

7.9 HS Detection Handshake – HS Downstream Facing Port

Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to Disable
Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the downstream facing port. If the downstream facing port is HS capable then it will
begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the
chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it
will enter HS mode by setting TERMSELECT to HS mode (T7).

Figure 7.4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the

device port must terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note
that the sequence of Chirp K’s and Chirp J’s constitutes bus activity.

Start Chirp

K-J-K-J-K-J

detection

Chirp Count
= 0

Detect K?

!K

Chirp Count != 6

& !SE0

K State

INC Chirp
Count

Chirp
Invalid

SE0

!J

Detect J?

J State

INC Chirp
Count

Chirp Count

Chirp Valid

Chirp Count != 6

& !SE0

Figure 7.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram

The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore
LINESTATE signal transitions must be used by the Link to step through the Chirp K-J-K-J-K-J state
diagram, where “K State” is equivalent to LINESTATE = K State and “J State” is equivalent to
LINESTATE = J State. The Link must employ a counter (Chirp Count) to count the number of Chirp K
and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus
state must be “continuously asserted for 2.5µs” must be verified by the Link sampling the LINESTATE
signals.

SMSC USB3450 33 Revision 0.1 (05-11-05)

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Datasheet

Figure 7.5 HS Detection Handshake Timing Behavior (HS Mode)

Table 7.7 Reset Timing Values

TIMING

PARAMETER DESCRIPTION VALUE

T0 HS Handshake begins. DP pull-up enabled, HS

terminations disabled.

T1 Device asserts Chirp K on the bus. T0 < T1 < HS Reset T0 + 6.0ms

T2 Device removes Chirp K from the bus. 1 ms

minimum width.

T3 Downstream facing port asserts Chirp K on the

bus.

T4 Downstream facing port toggles Chirp K to Chirp J

on the bus.

T5 Downstream facing port toggles Chirp J to Chirp K

on the bus.

T6 Device detects downstream port chirp. T6

T7 Chirp detected by the device. Device removes DP

pull-up and asserts HS terminations, reverts to HS
default state and waits for end of reset.

0 (reference)

T0 + 1.0ms < T2 <
HS Reset T0 + 7.0ms

T2 < T3 < T2+100µs

T3 + 40µs < T4 < T3 + 60µs

T4 + 40µs < T5 < T4 + 60µs

T6 < T7 < T6 + 500µs

T8 Terminate host port Chirp K-J sequence (Repeating

T4 and T5)

T9 The earliest time at which host port may end reset.

The latest time, at which the device may remove
the DP pull-up and assert the HS terminations,
reverts to HS default state.

Revision 0.1 (05-11-05) 34 SMSC USB3450

T9 - 500µs < T8 < T9 - 100µs

HS Reset T0 + 10ms

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Notes:

■ T0 may be up to 4ms after HS Reset T0.

■ The Link must use LINESTATE to detect the downstream port chirp sequence.

■ Due to the assertion of the HS termination on the host port and FS termination on the device port,

between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are
less than FS signaling levels.

7.10 HS Detection Handshake – Suspend Timing

If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are
assumed to be powered down. Figure 7.6 shows how CLKOUT is used to control the duration of the
chirp generated by the device.

When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE),
SUSPENDN is combinatorially negated at time T0 by the Link. It takes approximately 5 milliseconds
for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLKOUT
signal until it is “usable” (where “usable” is defined as stable to within ±10% of the nominal frequency
and the duty cycle accuracy 50±5%).

The first transition of CLKOUT occurs at T1. The Link then sets OPMODE to Disable Bit Stuffing and
NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to
ensure a 1ms minimum duration. If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If
CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first
CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete
before T3. Once the Chirp K is completed (T3) the Link can begin looking for host chirps and use
CLKOUT to time the process. At this time, the device follows the same protocol as in Section 7.9, "HS

Detection Handshake – HS Downstream Facing Port" for completion of the High Speed Handshake.

time

OPMODE 0

OPMODE 1

XCVRSELECT

TERMSELECT

SUSPENDN

TXVALID

CLK60

DP/DM

Figure 7.6 HS Detection Handshake Timing Behavior from Suspend

T0

J

SE0

CLK power up time

T1

T2

Device Chirp K

T3 T4

Look for host chirps

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {T
the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles.

}, the Link must see

FILT

Table 7.8 HS Detection Handshake Timing Values from Suspend

TIMING

PARAMETER DESCRIPTION VALUE

Datasheet

T0 While in suspend state an SE0 is detected on the USB. HS

Handshake begins. D+ pull-up enabled, HS terminations
disabled, SUSPENDN negated.

T1 First transition of CLKOUT. CLKOUT "Usable" (frequency

accurate to ±10%, duty cycle accurate to 50±5).

T2 Device asserts Chirp K on the bus. T1 < T2 < T0 + 5.8ms

T3 Device removes Chirp K from the bus. (1 ms minimum width)

and begins looking for host chirps.

T4 CLK "Nominal" (CLKOUT is frequency accurate to ±500

ppm, duty cycle accurate to 50±5).

7.11 Assertion of Resume

In this case, an event internal to the device initiates the resume process. A device with remote wake­up capability must wait for at least 5ms after the bus is in the idle state before sending the remote
wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for
propagating resume signaling.

The device has 10ms where it can draw a non-suspend current before it must drive resume signaling.
At the beginning of this period the Link may negate SUSPENDN, allowing the transceiver (and its
oscillator) to power up and stabilize.

0 (HS Reset T0)

T0 < T1 < T0 + 5.6ms

T2 + 1.0 ms < T3 <
T0 + 7.0 ms

T1 < T3 < T0 + 20.0ms

Figure 7.7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a

device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high.

To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI
encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS
mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2).

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Datasheet

Figure 7.7 Resume Timing Behavior (HS Mode)

Table 7.9 Resume Timing Values (HS Mode)

TIMING

PARAMETER DESCRIPTION VALUE

T0 Internal device event initiating the resume

process

T1 Device asserts FS 'K' on the bus to signal

resume request to downstream port

T2 The device releases FS 'K' on the bus. However

by this time the 'K' state is held by downstream
port.

T3 Downstream port asserts SE0. T1 + 20ms

T4 Latest time at which a device, which was

previously in HS mode, must restore HS mode
after bus activity stops.

0 (reference)

T0 < T1 < T0 + 10ms.

T1 + 1.0ms < T2 < T1 + 15ms

T3 + 1.33µs {2 Low-speed bit times}

7.12 Detection of Resume

Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled),
so the behavior for a HS device is identical to that of a FS device. The Link uses the LINESTATE
signals to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating
FS EOP (SE0 for 1.25us-1.5µs.).

The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the
Link may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize.

The FS EOP condition is relatively short. Links that simply look for an SE0 condition to exit suspend
mode do not necessarily give the transceiver’s clock generator enough time to stabilize. It is
recommended that all Link implementations key off the 'J' to 'K' transition for exiting suspend mode
(SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the Link
must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in
when it was suspended.

SMSC USB3450 37 Revision 0.1 (05-11-05)

DATASHEET

If the device was in FS mode: then the Link leaves the FS terminations enabled. After the SE0 expires,
the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle
state (maintained by the FS terminations).

If the device was in HS mode: then the Link must switch to the FS terminations before the SE0 expires
(< 1.25µs). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS
terminations).

7.13 HS Device Attach

Figure 7.8 demonstrates the timing of the USB3450 control signals during a device attach event. When

a HS device is attached to an upstream port, power is asserted to the device and the device sets
XCVRSELECT and TERMSELECT to FS mode (time T1).

V

is the +5V power available on the USB cable. Device Reset in Figure 7.8 indicates that V

BUS

within normal operational range as defined in the Hi-Speed specification. The assertion of Device
Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the Link state
machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1).

The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is
employed. The Link must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted
at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device
will then reset itself before initiating the HS Detection Handshake protocol.

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

is

BUS

Figure 7.8 Device Attach Behavior

Table 7.10 Attach and Reset Timing Values

TIMING

PARAMETER DESCRIPTION VALUE

T0 Vbus Valid. 0 (reference)

T1 Maximum time from Vbus valid to when the device

T2

(HS Reset T0)

Revision 0.1 (05-11-05) 38 SMSC USB3450

must signal attach.

Debounce interval. The device now enters the HS
Detection Handshake protocol.

T0 + 100ms < T1

T1 + 100ms < T2

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Datasheet

7.14 Application Diagram

4.7uF

VDD3.3

0.1uF

3.3 Volt
Supply

C

4.7uF

12KΩ

0.1uF

LOAD

24MHz

C

LOAD

4.7uF

1MΩ

5 Volt

Supply

Host Only

USB

Connector

(Standard

or Mini)

C

VBUS

Host
Device
OTG Device

Min

100uF

1uF
1uF

VBUS

ID

DP

DM

C

Max

10uF

6.5uF

VBUS

XCVRSEL0

TERMSEL

TXREADY

SUSPENDN

TXVALID

RESET

VDD3.3

DP

DM

NC

RBIAS

1

2

3

4

5

6

7

8

9

10

VDD3.3

VDD3.3

VDD3.3

40

VDDA1.8

XI

XO

39

38

37

36

35

USB3450

Hi-Speed USB

UTMI+ PHY

40 Pin QFN

GND FLAG

15

11

12

13

14

RXACTIVE

XCVRSEL1

OPMODE[1]

16

CLKOUT

OPMODE[0]

Figure 7.9 USB3450 Application Diagram (Top View)

VDD3.3

RXERROR

VDD1.8

34

17

LINESTATE[0]

LINESTATE[1]

HOST

33

32

31

RXVALID

30

DATA[0]

29

DATA[1]

28

DATA[2]

27

DATA[3]

26

DATA[4]

25

DATA[5]

24

DATA[6]

23

DATA[7]

22

HOSTDISC

21

18

19

20

0.1uF

VDD1.8

VDD3.3

25

UTMI+

Interface

to Link

SMSC USB3450 39 Revision 0.1 (05-11-05)

DATASHEET

Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

REV

SHEET

CATALOG PART

DRAWN

MATERIAL

40 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH

10/29/04

S.K.ILIEV

-

JEDEC: MO-220 1 OF 1

STD COMPLIANCE

MO-40-QFN-6x6

SCALE

DWG NUMBER

10/29/04 1:1

10/29/04 A

S.K.ILIEV

S.K.ILIEV

APPROVED

CHECKED

-

DO NOT SCALE DRAWING

PRINT WITH "SCALE TO FIT"

FINISH

REVISION HISTORY

DESCRIPTIONREVISION RELEASED BYDATE

D2 / E2 VARIATIONS

A INITI AL RELEASE 10/29/04 S.K .ILIEV

3

TERMINAL #1

(D/2 X E/2)

IDENTIFIER AREA

D2

e

2

THIRD ANGLE PROJECTION

EXPOSED PAD

40X L

2

40X b

UNLESS OTHERWISE SPECIFIED

BOTTOM VIEW

E2EE1

40X 0.2 MIN

A

PACKAGE OUTLINE

80 ARKAY DRIVE

HAUPPAUGE, NY 11788

USA

TITLE

DATE

NAME

±1°

ANGULAR

±0.025

±0.05

±0.1

AND TOLERANCES ARE:

DIMENSIONS ARE IN MILLIMETERS

DIM AND TOL PER ASME Y14.5M - 1994

X.X

X.XX

X.XXX

DECIMAL

A1

3-D VIEWS

D

D1

4X 45°x0.6MAX (OPTIONAL)

TOP VIEW

3

(D1/2 X E1/2)

TERMINAL #1

IDENTIFIER AREA

Chapter 8 Package Outline

Revision 0.1 (05-11-05) 40 SMSC USB3450

DATASHEET

SIDE VIEW

A2

2. POSITION TOLERANCE OF EACH TERMINA L AND EXPOSED PAD IS ± 0.05mm AT

MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS

AND IT IS MEASURED BETWEE N 0.15 AND 0. 30 mm FROM THE TERMINAL TIP.

THE AREA INDICATED.

3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETER.

Figure 8.1 USB3450-FZG 40 Pin QFN Package Outline, 6 x 6 x 0.9 mm Body (Lead Free)