SMSC USB3280 User Manual

USB3280

Hi-Speed USB Device
PHY with UTMI Interface

PRODUCT FEATURES

 Available in a 36-pin lead-free RoHS compliant (6 x 6

x 0.90mm) QFN package

 Interface compl iant with the UTMI specification

(60MHz, 8-bit bidirectional interface)

 Only o ne required power supply (+3.3V)
 USB-IF “Hi -Speed” certified to USB 2.0 electrical

specification

 Sup ports 480Mbps Hi-Speed (HS) and 12Mbps Full

Speed (FS) serial data transmission rates

 Integra ted 45Ω and 1.5kΩ termination resistors

reduce external component count

 Internal short circuit protection of DP and DM lines
 On-chip oscillator operates with low cost 24MHz

crystal

 Latch-up performance exceeds 150mA per EIA/JESD

78, Class II

 ESD p rotection levels of 5kV HBM without external

protection devices

 SYNC an d EOP generation on transmit packets and

detection on receive packets

 NR ZI encoding and decoding
 Bit stuffing and unstuffing with error detection
 Sup ports the USB suspend state, HS detection, HS

Chirp, Reset and Resume

 Sup port for all test modes defined in the USB 2.0

specification

 5 5mA Unconfigured Current (typical) - ideal for bus

powered applications.

 8 3uA suspend current (typical) - ideal for battery

powered applications.

 Indu strial Operating Temperature -40

o

C to +85oC

Datasheet

Applications

The USB3280 is the ideal companion to any ASIC, SoC
or FPGA solution designed with a UTMI Hi-Speed USB
device (peripheral) core.

The USB3280 is well suited for:

 C ell Phones
 MP3 Pl ayers
 Scanners
 Externa l Hard Drives
 D igital Still and Video Cameras
 Po rtable Media Players
 En tertainment Devices
 Printers

SMSC USB3280 DATASHEET Revision 1.5 (11-15-07)

Hi-Speed USB Device PHY with UTMI Interface

ORDER NUMBER(S):

USB3280-AEZG FOR 36-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE

USB3280-AEZG-TR FOR 36-PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)

Reel Size is 3000 pieces.

Datasheet

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]

Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a mean s of illustrating typical applications. Conse quently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently da ted
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.5 (11-15-07) 2 SMSC USB3280

DATASHEET

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

Table of Contents

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers. . . . . . . . . . . . 16

6.2 High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2 System Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3 Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.4 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5 RX Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.6 USB 2.0 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.6.1 High Speed and Full Speed Transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.6.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.6.3 Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.7 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8.2 Power On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.8.3 Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 8 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.1 Linestate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.3 Test Mode Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.8 HS Detection Handshake – FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8.9 HS Detection Handshake – HS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8.10 HS Detection Handshake – Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.14 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SMSC USB3280 3 Revision 1.5 (11-15-07)

DATASHEET

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

List of Figures

Figure 2.1 USB3280 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.1 USB3280 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3.2 USB3280 Pinout - Bottom View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 17

Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 17

Figure 6.3 Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7.1 FS CLK Relationship to Transmit Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7.2 FS CLK Relationship to Receive Data and Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.3 Transmit Timing for a Data Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.4 Receive Timing for Data with Unstuffed Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.5 Receive Timing for a Handshake Packet (no CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7.6 Receive Timing for Setup Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7.7 Receive Timing for Data Packet (with CRC-16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 8.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 8.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 8.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 8.9 USB3280 Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 9.1 USB3280-AEZG 36-Pin QFN Package Outline and Parameters, 6 x 6 x 0.90 mm Body (Lead-

Free RoHS Compliant) 42

Figure 9.2 QFN, 6x6 Tape & Reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 9.3 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision 1.5 (11-15-07) 4 SMSC USB3280

DATASHEET

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

List of Tables

Table 4.1 System Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4.4 Biasing and Clock Oscillator Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) . . . . . . . . . . . . . . . . . . . . 14

Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) (Note 6.4). . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7.1 DP/DM Termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8.1 Linestate States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8.3 USB 2.0 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 8.8 HS Detection Handshake Timing Values from Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SMSC USB3280 5 Revision 1.5 (11-15-07)

DATASHEET

Chapter 1 General Description

The USB3280 provides the Physical Layer (PHY) interface to a USB 2.0 Device C ontroller. The IC is
available in a 36-pin lead-free RoHS compliant QF N package.

1.1 Product Description

The USB3280 is an industrial temperature USB 2.0 physical layer transceiver (PHY) in tegrated circuit.
SMSC’s proprietary technology results in low power dissipation, which is ideal for building a bus
powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which compl ies
with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate,
while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps.

All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip.
The USB3280 also has an integrated 1.8V regulator so that only a 3.3V sup ply is required.

While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

Revision 1.5 (11-15-07) 6 SMSC USB3280

DATASHEET

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

Chapter 2 Functional Block Diagram

XO

VDD3.3

XI

RESET

SUSPENDN

XCVRSELECT

TERMSELECT

:

M

D

[

1

O

P

O

E

LINESTATE[1:0]

CLKOUT

]

D

0

A

A

:

T

[

7

TXVALID

T

D

R

A

Y

E

X

R

D

A

I

V

L

X

R

E

A

I

V

C

X

T

R

R

X

R

O

E

R

PWR

Control

1.8V

Regulator

PLL and

XTAL OSC

TX

LOGIC

TX State

Machine

Parallel to

Serial

Conversion

Bit Stuff

NRZI

Encode

]

0

RPU_EN

VPO

VMO

OEB

HS_DATA

HS_DRIVE_ENABLE

HS_CS_ENABLE

1.5k

FS

TX

HS

TX

System
Clocking

TX

Ω

R

DP

DM

X

UTMI

Interface

RX

LOGIC

RX State

Machine

Serial to

Parallel

Conversion

Bit Unstuff

NRZI

Decode

VP

VM

Clock

Recovery Unit

Clock

and
Data

Recovery

Elasticity

Buffer

MUX

FS SE+

FS SE-

FS RX

HS RX

BIASING

Bandgap Voltage Reference

Current Reference

RBIAS

HS SQ

Figure 2.1 USB3280 Block Diagram

SMSC USB3280 7 Revision 1.5 (11-15-07)

DATASHEET

R

Chapter 3 Pinout

XCVRSELECT
TERMSELECT

TXREADY

SUSPENDN

TXVALID

RESET

VDD3.3

DP

DM

REG_EN

RBIAS

VDD3.3

VDDA1.8

XIXOVDD1.8

30

31

32

34

353633

1
2
3
4
5
6
7
8
9

USB2.0

USB3280

PHY IC

101112131415161718

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

VDD3.3

RXERRO

28

29

27
26
25
24
23
22
21
20
19

RXVALID
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
DATA[7]

VDD3.3

RXACTIVE

CLKOUT

OPMODE0

OPMODE1

LINESTATE1

Figure 3.1 USB3280 Pinout - Top View

EXPOSED

GND PAD

Figure 3.2 USB3280 Pinout - Bottom View

LINESTATE0

VDD1.8

VDD3.3

The flag of the QFN package must be connected to ground.

Revision 1.5 (11-15-07) 8 SMSC USB3280

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Chapter 4 Interface Signal Definition

T able 4.1 System Interface Signals

ACTIVE

NAME DIRECTION

LEVEL DESCRIPTION

RESET

(RST)

XCVRSELECT

(XSEL)

TERMSELECT

(TSEL)

SUSPENDN

(SPDN)

CLKOUT

(CLK)

OPMODE[1:0]

(OM1)
(OM0)

Input High Reset. Reset all state machines. After coming out of

reset, must wait 5 rising edges of clock before asserting
TXValid for transmit.
See Section 7.8.3

Input N/A Transceiver Select. This signal selects between the FS

and HS transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.

Input N/A Termination Select. This signal selects between the FS

and HS terminations:
0: HS termination enabled
1: FS termination enabled

Input Low Suspend. Places the transceiver in a mode that draws

minimal power from supplies. Shuts down all blocks not
necessary for Suspend/Resume operation. While
suspended, TERMSELECT must always be in FS mode
to ensure that the 1.5kΩ pull-up on DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current

Output Rising Edge System Clock. This output is used for clocking receive

and transmit parallel data at 60MHz.

Input N/A Operational Mode. These signals select between the

various operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved

LINESTATE[1:0]

(LS1)
(LS0)

SMSC USB3280 9 Revision 1.5 (11-15-07)

Output N/A Line State. These signals reflect the current state of the

USB data bus in FS mode, with [0] reflecting the state of
DP and [1] reflecting the state of DM. When the device is
suspended or resuming from a suspended state, the
signals are combinatorial. Otherwise, the signals are
synchronized to CLKOUT.

[0] Description

[1]
0 0 0: SE0
0 1 1: J State
1 0 2: K State
1 1 3: SE1

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NAME DIRECTION

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

T ab le 4.2 Data Interface Signals

ACTIVE

LEVEL DESCRIPTION

DATA[7:0]

(D7)

.
.
.

(D0)

TXVALID

(TXV)

TXREADY

(TXR)

RXVALID

(RXV)

RXACTIVE

(RXA)

RXERROR

(RXE)

Bidirectional High Data bus. 8-bit Bidirectional mode.

TXVALID DATA[7:0]

0 output
1 input

Input High Transmit Valid. Indicates that the DATA bus is valid for transmit. The

assertion of TXVALID initiates the transmission of SYNC on the USB
bus. The negation of TXVALID initiates EOP on the USB.

Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must
not be changed on the de-assertion or assertion of T XVALID. The
PHY must be in a quiescent state when these inputs are changed.

Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always

have data available for clocking into the TX Holding Register on the
rising edge of CLKOUT. TXREADY is an acknowledgement to the
SIE that the transceiver has clocked the data from the bus and is
ready for the next transfer on the bus. If TXVALID is negated,
TXREADY can be ignored by the SIE.

Output High Receive Data Valid. Indicates that the DATA bus has received valid

data. The Receive Data Holding Register is full and ready to be
unloaded. The SIE is expected to latch the DATA bus on the rising
edge of CLKOUT.

Output High Receive Active. Indicates that the receive state machine has

detected Start of Packet and is active.

Output High Receive Error.

0: Indicates no error.
1: Indicates a receive error has been detected.
This output is clocked with the same timing as the rece ive DATA lines
and can occur at anytime during a transfer.

Table 4.3 USB I/O Signals

ACTIVE

NAME DIRECTION

DP I/O N/A USB Positive Data Pin.
DM I/O N/A USB Negative Data Pin.

NAME DIRECTION

RBIAS

(RB)

XI/XO Input N/A External crystal. 24MHz crystal connected from XI to XO.

Revision 1.5 (11-15-07) 10 SMSC USB3280

Input N/A External 1% bias resistor. Requires a 12kΩ resistor to ground.

LEVEL DESCRIPTION

Table 4.4 Biasing and Clock Oscillator Signals

ACTIVE

LEVEL DESCRIPTION

Used for setting HS transmit current level and on-chip
termination impedance.

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Hi-Speed USB Device PHY with UTMI Interface

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Table 4.5 Power and Ground Signals

ACTIVE

NAME DIRECTION

LEVEL DESCRIPTION

VDD3.3

(V33)

REG_EN

(REN)

VDD1.8

(V18)

VSS

(GND)

VDDA1.8

(V18A)

N/A N/A 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+

Digital, Digital I/O, and Regulators.

Input High On-Chip 1.8V regulator enable. Connect to ground to disable

both of the on chip (VDDA1.8 and VDD1.8) regulators. When
regulators are disabled:

 External 1.8V must be suppl ied to VDDA1.8 and VDD1.8 pins.

When the regulators are disabled, VDDA1.8 may be connected
to VDD1.8 and a bypass capacitor (0.1μF recommended)
should be connected to each pin.

 The voltage at VD D3.3 must be at least 2.64V (0.8 * 3.3V)

before voltage is applied to VDDA1.8 and VDD1.8.

N/A N/A 1.8V Digital Supply. Supplied by On-Chip Regulator when

REG_EN is active. Low ESR 4.7uF minimum capacitor
requirement when using internal regulators. Do not connect
VDD1.8 to VDDA1.8 when using internal regulators. When the
regulators are disabled, VDD1.8 may be connected to VDD1.8A.

N/A N/A Common Ground.

N/A N/A 1.8V Analog Supply. Supplied by On-Chip Regulator when

REG_EN is active. Low ESR 4.7uF minimum capacitor
requirement when using internal regulators. Do not connect
VDD1.8A to VDD1.8 when using internal regulators. When the
regulators are disabled, VDD1.8A may be connected to VDD1.8.

SMSC USB3280 11 Revision 1.5 (11-15-07)

DATASHEET

Chapter 5 Limiting Values

Table 5.1 Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Hi-Speed USB Device PHY with UTMI Interface

Datasheet

Maximum DP and DM
voltage to Ground

Maximum VDD1.8 and
VDDA1.8 voltage to Ground

Maximum 3.3V Supply
Voltage to Ground

Maximum I/O Voltage to
Ground

Storage Temperature T

V

MAX_5V

V

MAX_1.8V

V

MAX_3.3V

V

I

STG

-0.3 5.5 V

-0.3 2.5 V

-0.3 4.0 V

-0.3 4.0 V

-55 150

ESD PERFORMANCE

All Pins V

HBM

Human Body Model ±5 kV

LATCH-UP PERFORMANCE

All Pins I

LTCH_UP

EIA/JESD 78, Class II 150 mA

Note: In accordance with the Absolute Maximum Rating system (IEC 60134)

Table 5.2 Recommended Operating Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

o

C

3.3V Supply Voltage
(VDD3.3 and VDDA3.3)

Input Voltage on Digital Pins V
Input Voltage on Analog I/O

Pins (DP, DM)
Ambient Temperature T

V

DD3.3

I

V

I(I/O)

A

3.0 3.3 3.6 V

0.0 V

0.0 V

-40 85

DD3.3

DD3.3

o

V
V

C

Table 5.3 Recommended External Clock Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

System Clock Frequency XO driven by the external

clock; and no connection at XI

System Clock Duty Cycle XO driven by the external

45 50 55 %

24

(±100ppm)

MHz

clock; and no connection at XI

Revision 1.5 (11-15-07) 12 SMSC USB3280

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Hi-Speed USB Device PHY with UTMI Interface

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Chapter 6 Electrical Characteristics

Table 6.1 Electrical Characteristics: Supp ly Pins (Note 6.1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Unconfigured Current I
FS Idle Current I
FS Transmit Current I

FS Receive Current I

HS Idle Current I
HS Transmit Current I

HS Receive Current I

Low Power Mode I

AVG(UCFG)

AVG(FS)

AVG(FSTX)

AVG(FSRX)

AVG(HS)

AVG(HSTX)

AVG(HSRX)

DD(LPM)

Device Unconfigured 55 mA
FS idle not data transfer 55 mA
FS current during data

60.5 mA

transmit
FS current during data

57.5 mA

receive
HS idle not data transfer 60.6 mA
HS current during data

62.4 mA

transmit
HS current during data

61.5 mA

receive
VBUS 15kΩ pull-down and

83 uA

1.5kΩ pull-up resistor
currents not included.

Note 6.1 V

= 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.

DD3.3

T able 6.2 DC Electrical Characteristics: Logic Pins (Note 6.2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Low-Level Input Voltage V
High-Level Input Voltage V
Low-Level Output Voltage V
High-Level Output Voltage V

Input Leakage Current I

IL

IH

OL

OH

LI

IOL = 8mA 0.4 V
IOH = -8mA V

V

SS

2.0 V

DD3.3

- 0.5

0.8 V

DD3.3

± 1 uA

V

V

Pin Capacitance Cpin 4 pF

Note 6.2 V

SMSC USB3280 13 Revision 1.5 (11-15-07)

= 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.

DD3.3

DATASHEET

Table 6.3 DC Electrical Character istics: Analog I/O Pins (DP/DM) (Note 6.3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS FUNCTIONALITY
Input levels

Hi-Speed USB Device PHY with UTMI Interface

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Differential Receiver Input
Sensitivity

Differential Receiver
Common-Mode Voltage

Single-Ended Receiver Low
Level Input Voltage

Single-Ended Receiver High
Level Input Voltage

Single-Ended Receiver
Hysteresis

Output Levels

Low Level Output Voltage V

High Level Output Voltage V

Termination

Driver Output Impedance for
HS and FS

Input Impedance Z
Pull-up Resistor Impedance Z
Pull-up Resistor Impedance Z
Termination Voltage For Pull-

up
Resistor On Pin DP

V

DIFS

V

CMFS

V

ILSE

V

IHSE

V

HYSSE

FSOL

FSOH

Z

HSDRV

INP

PU

PURX

V

TERM

| V(DP) - V(DM) | 0.2 V

0.8 2.5 V

0.8 V

2.0 V

0.050 0.150 V

Pull-up resistor on DP;
RL = 1.5kΩ to V

DD3.3

Pull-down resistor on DP,

2.8 3.6 V

0.3 V

DM;
RL = 15kΩ to GND

Steady state drive

40.5 45 49.5 Ω

(See Figure 6.1)
TX, RPU disabled 10 MΩ
Bus Idle 0.900 1.24 1.575 kΩ
Device Receiving 1.425 2.26 3.09 kΩ

3.0 3.6 V

HS FUNCTIONALITY
Input levels

HS Differential Input Sensitivity V
HS Data Signaling Common

Mode Voltage Range
HS Squelch Detection

Threshold (Differential)

DIHS

V

CMHS

V

HSSQ

| V(DP) - V(DM) | 100 mV

-50 500 mV

Squelch Threshold 100 mV
Unsquelch Threshold 150 mV

Output Levels

High Speed Low Level
Output Voltage (DP/DM

V

HSOL

45Ω load -10 10 mV

referenced to GND)

Revision 1.5 (11-15-07) 14 SMSC USB3280

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