construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently da ted
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
The SMSC 7-Port Hub is fully compliant with the USB 2.0 Specification and will attach to a USB host
as a Full-Speed Hub or as a Full-/High-Speed Hub. The 7-Port Hub supports Low-Speed, Full-Speed,
and High-Speed (if operating as a High-Speed Hub) downstream devices on all of the enabled
downstream ports.
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture
ensures maximum USB throughput for each connected device when operating with mixed-speed
peripherals.
Integrated USB 2.0 Compatible 7-Port Hub
Datasheet
The Hub works with an external USB power distribution switch device to control V
downstream ports, and to limit current and sense over-current conditions.
All required resistors on the USB ports are integrated into the Hub. This includes all seri es termination
resistors on D+ and D– pins and all require d pull-down and pull-up resistors on D+ and D– pins. The
over-current sense inputs for the downstream facing ports have internal pull-up resistors.
Throughout this document the upstream facing port of the hub will be referred to as the upstream port,
and the downstream facing ports will be called the downstream ports.
1.1OEM Selectable Features
A default configuration is available in the USB2507 following a reset. This configuration may be
sufficient for some applications. Strapping option pins make it possible to modify a limited sub-set of
the configuration options.
The USB2507 may also be configured by an external EEPROM or a microcontroller. When using the
microcontroller interface, the Hub appears as an SMBus slave device. If the Hub is pin-strapped for
external EEPROM configuration but no external EEPROM is present, then a value of ‘0’ will be written
to all configuration data bit fields (the hub will attach to the ho st with all ‘0’ values).
The 7-Port Hub supports several OEM selectable features:
Operation as a Self-Powered USB Hub or as a Bus-Powered USB Hub.
Operation as a Dynamic-Powered Hub (Hub operate s as a Bus-Powered device if a local power
source is not available and switches to Self-Powered opera tion when a local power source is
available).
Optional OEM configuration via I2C EEPROM or via the industry standard SMBus interface from
an external SMBus Host.
LED indicator support.
Compound device support (port is permanently hardwired to a down strea m USB perip heral device).
Hardware strapping options enable configuration of the following feature s.
Non-Removable Ports
Port Power Polarity (active high or active low logic)
Port Disable
LED support
MTT enable
Ganged Vs Port power switching and over-current sensing
IO-UThese pins connect to the upstream USB bus data signals.
USBDP0
Detect Upstream
VBUS Power
VBUS_DETI/O12Detects state of Upstream VBUS power. The SMSC Hub
monitors VBUS_DET to determine when to assert the
internal D+ pull-up resistor (signalling a connect event).
When designing a detachable hub, this pin must be
connected to the VBUS power pin of the USB port that is
upstream of the hub. (Use of a weak pull-down resistor is
recommended.)
For self-powered applications with a permanently attached
host, this pin must be pulled-up to either 3.3V or 5.0V
(typically VDD33).
SMSC USB25079Revision 2.3 (08-27-07)
DATASHEET
Integrated USB 2.0 Compatible 7-Port Hub
Table 4.1 7-Port Hub Pin Descriptions (continued)
NAMESYMBOLTYPEFUNCTION
7-PORT USB 2.0 HUB INTERFACE
Datasheet
High-Speed USB
Data
USB Power
Enable
Ports [7:5] Green
LED
Port 4:3 Green
LED
&
Port Disable
strapping option.
USBDN[7:1]
USBDP[7:1]
IO-UThese pins connect to the downstream USB peripheral
devices attached to the Hub’s ports.
PRTPWR[7:1]O12Enables power to USB peripheral devices (downstream).
The active signal level of the PRTPWR7:1 pins is
determined by the Power Polarity Strapping function of the
PRTPWR_POL pin.
GR[7:5]I/O12Green indicator LED’s for ports[7:5]. LED is active low
GR[4:3]/
PRT_DIS[1:0]
I/O12Green indicator LED for ports 4 and 3. Will be active low
when LED support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
these pins will be sampled at RESET_N negation to
determine if ports [7:5] will be permanently disabled. Also,
the active state of the LED’s will be determined as follows:
PRT_DIS[1:0] = ‘00’, All ports are enabled,
GR4 is active high,
GR3 is active high.
PRT_DIS[1:0] = ‘01’, Port 7 is disabled,
GR4 is active high,
GR3 is active low.
PRT_DIS[1:0] = ‘10’, Ports 7 & 6 are disabled,
GR4 is active low,
GR3 is active high.
Port [2:1] Green
LED
&
Port Non-
Removable
strapping option.
Ports [7:5] Amber
LED
PRT_DIS[1:0] = ‘11’, Ports 7, 6 & 5 are disabled,
GR4 is active low,
GR3 is active low.
GR[2:1]/
NON_REM[1:0]
I/O12Green indicator LED for ports 2 and 1. Will be active low
when LED support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
these pins will be sampled at RESET_N negation to
determine if ports [3:1] contain permanently attached (nonremovable) devices. Also, the active state of the LED’s will
be determined as follows:
NON_REM[1:0] = ‘00’, All ports are removable,
GR2 is active high,
GR1 is active high.
NON_REM[1:0] = ‘01’, Port 1 is non-removable,
GR2 is active high,
GR1 is active low.
NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable,
GR2 is active low,
GR1 is active high.
NON_REM[1:0] = ‘11’, Ports 1, 2, & 3 are non-removable,
GR2 is active low,
GR1 is active low.
AM[7:5]I/O12Amber indicator LED’s for ports [7:5], LED is active low.
Revision 2.3 (08-27-07)10SMSC USB2507
DATASHEET
Integrated USB 2.0 Compatible 7-Port Hub
Datasheet
Table 4.1 7-Port Hub Pin Descriptions (continued)
NAMESYMBOLTYPEFUNCTION
Port 4 Amber
LED
&
LED Enable
strapping option
Port 3 Amber
LED
Port 2 Amber
LED
&
MTT Disable
Port 1 Amber
LED
&
Gang Power
Switching and
Current Sensing
strapping option.
AM4/
LED_EN
I/O12Amber indicator LED for port 4. Will be active low when LED
support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
this pin will be sampled at RESET_N negation to determine
if LED support is enabled or disabled. Also, the active state
of the LED will be determined as follows:
‘0’ = LED support is disabled, LED is inactive
‘1’ = LED Support is enabled, LED is active low.
AM3I/O12Amber indicator LED for port 3. Signal will be active low.
AM2/
MTT_EN
I/O12Amber indicator LED for port 2. Will be active low when LED
support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
this pin will be sampled at RESET_N negation to determine
if MTT support is disabled (STT only). Also, the active state
of the LED will be determined as follows:
‘0’ = MTT support is disabled, LED is active high
‘1’ = MTT support is enabled, LED is active l ow.
AM1/
GANG_EN
I/O12Amber indicator LED for port 1, Will be active low when LED
support is enabled via EEPROM or SMBus.
If the hub is configured by the internal default configuration,
this pin will be sampled at RESET_N negation to determine
if downstream port power switching and current sensing are
ganged, or individual port-by-port. Also, the active state of
the LED will be determined as follows:
Port Power
Polarity strapping.
Over Current
Sense
USB Transceiver
Bias
‘0’ = Port-by-port sensing & switching, LED is active high
‘1’ = Ganged sensing & switching, LED is active low.
PRTPWR_POLI/O12Port Power Polarity strapping determination for the active
signal polarity of the 7:1PRTPWR pins.
While RESET_N is asserted, the logic state of this pin will
(though the use of internal combinatorial logic) determine
the active state of the 7:1PRTPWR pins in order to ensure
that downstream port power is not inadvertently enabled to
inactive ports during a hardware reset.
On the rising edge of RESET_N (see the applicable
RESET_N timing table in Section 5.6.1), the logi c value will
be latched internally, and will retain the active signal polarity
for the PRTPWR7:1 pin.
‘1’ = PRTPWR7:1 pins have an active ‘high’ polarity
‘0’ = PRTPWR7:1 pins have an active ‘low’ polarity
OCS7:1_NIPUInput from external current monitor indicating an over-
current condition. {Note: Contains internal pull-up to 3.3V
supply}
RBIASI-RA 12.0kΩ (+/− 1%) resistor is attached from ground to this
pin to set the transceiver’s internal bias settings.
SMSC USB250711Revision 2.3 (08-27-07)
DATASHEET
Integrated USB 2.0 Compatible 7-Port Hub
Table 4.1 7-Port Hub Pin Descriptions (continued)
NAMESYMBOLTYPEFUNCTION
SERIAL PORT INTERFACE
Datasheet
Serial Data/SMB
Data
Serial Clock/SMB
Clock
&
Config Select 0
Configuration
Programming
Select
SDA/SMBDATAIOSD12(Serial Data)/(SMB Data) signal.
SCL/SMBCLK/
CFG_SEL0
IOSD12(Serial Clock)/(SMB Clock) signal. This multifunction pin is
read on the rising edge of RESET_N (see the applicable
RESET_N timing table in Section 5.6.1) and will dete rmine
the hub configuration method as described in Table 4.2.
CFG_SEL1IThis multifunction pin is read on the risi ng edge of
RESET_N (see the applicable RESET_N timing table in
Section 5.6.1) and will determine the hub config uration
method as described in Table 4.2.
Table 4.2 SMBus or EEPROM Interface Behavior
CFG_SEL1CFG_SEL0SMBus or EEPROM interface behavior.
00Reserved
01Configured as an SMBus slave for external download of user-
defined descriptors. SMBus slave address is 0101100
10Internal Default Configuration via strapping options.
112-wire (I2C) EEPROMS are supported,
Table 4.3 Miscellaneous Pins
NAMESYMBOLTYPEFUNCTION
Crystal
Input/External
Clock Input
XTAL1/
CLKIN
ICLKx24MHz crystal or external clock input.
This pin connects to either one terminal of the crystal or
to an external 24MHz clock when a crystal is not used.
Crystal OutputXTAL2OCLKx24MHz Crystal
This is the other terminal of the crystal, or left
unconnected when an external clock source is used to
drive XTAL1/CLKIN. It must not be used to drive any
external circuitry other than the crystal circuit.
Clock Input
Enable
CLKIN_ENIClock In Enable:
Low = XTAL1 and XTAL2 pins configured for use with
external crystal
High = XTAL1 pin configured as CLKIN, and must be
driven by an external CMOS clock.
RESET InputRESET_NISThis active low signal is used by the system to reset the
chip. The minimum active low pulse is 1us.
Self-Power /
Bus-Power
Detect
SELF_PWRIDetects availability of local self-power source.
Low = Self/local power source is NOT available (i.e., Hub
gets all power from Upstream USB VBus).
High = Self/local power source is available.
TEST PinsTEST[1:0]IPDUsed for testing the chip. User must treat as a no-
connect or connect to ground.
Revision 2.3 (08-27-07)12SMSC USB2507
DATASHEET
Integrated USB 2.0 Compatible 7-Port Hub
Datasheet
Table 4.3 Miscellaneou s Pin s (continued)
NAMESYMBOLTYPEFUNCTION
Analog Test
&
Internal 1.8V
voltage
regulator
enable
ATEST/
REG_EN
AIOThis signal is used for testing the analog section of the
chip, and to enable or disable the internal 1.8v regulator.
This pin must be connected to VDDA33 to enable the
internal 1.8V regulator, or to VSS to disable the internal
regulator.
When the internal regulator is enabled, the 1.8V power
pins must be left unconnected, except for the required
bypass capacitors.When the PHY is in test mode, the
internal regulator is disabled and the ATEST pin
functions as a test pin.
Table 4.4 Power, Ground, and No Connect
NAMESYMBOLTYPEFUNCTION
VDDCORE3P3VDD33CR+3.3V I/O Power.
If the internal core 1.8V regulator is enabled, then this pin
acts as the regulator input
VDD1P8VDD18+1.8V core power.
If the internal regulator is enabled, then VDD18 pin 50
must have a 4.7μF (or greater) ±20% (ESR <0.1Ω)
capacitor to VSS
VDDAPLL3P3VDDA33PLL+3.3V Filtered analog power for the internal PLL
If the internal PLL 1.8V regulator is enabled, then this pin
acts as the regulator input
VDDAPLL1P8VDDA18PLL+1.8V Filtered analog power for internal PLL.
If the internal regulator is enabled, then this pin must
have a 4.7μF (or greater) ±20% (ESR <0.1Ω) capacitor
to VSS
VDDIO3P3VDD33+3.3V I/O power.
VDDA3P3VDDA33+3.3V Filtered analog power.
VSSVSSGround.
Table 4.5 Buffer Type Descriptions
BUFFERDESCRIPTION
IInput.
IPDInput, with a weak Internal pull-down.
IPUInput, with a weak Internal pull-up.
ISInput with Schmitt trigger.
O12Output 12mA.
SMSC USB250713Revision 2.3 (08-27-07)
DATASHEET
Table 4.5 Buffer Type Descriptions (continued)
BUFFERDESCRIPTION
I/O12Input/Output, 12mA
Integrated USB 2.0 Compatible 7-Port Hub
Datasheet
IOSD12Open drain….12mA sink with Schmitt trigger, and must meet I2C-Bus Specification Version 2.1
requirements.
ICLKxXTAL Clock Input
OCLKxXTAL Clock Output
I-RRBIAS
IO-UDefined in USB Specification.
Note: Meets USB 1.1 requirements when operating as a 1.1-compliant device and meets USB
2.0 requirements when operating as a 2.0-compliant device.
AIOAnalog Input/output. Per PHY test requirements.
Revision 2.3 (08-27-07)14SMSC USB2507
DATASHEET
Loading...
+ 30 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.