SMSC TMC2072 Technical data
TMC2072
Peripheral Mode
CircLink
PRODUCT FEATURES
™
Controller
Datasheet
Low Power CMOS, 3.3 Volt Power Supply with 5
Volt Tolerant I/O
Supports 8/16-Bit Data Bus
− Both 86xx and 68hxx Platforms
1K On-chip Dual Port Buffer Memory
− Sequential I/O Mapped Access
Enhanced Token Passing Protocol from ARCNET
− Maximum 31 Nodes per Network
− Token Retry Mechanism
− Maximum 256 Bytes per Packet
− Consecutive Node ID Assignment
Memory Mirror
− Shared Memory within Network
Network Standard Time
− Network Time Synchronization
− Automatic Time Stamping
Coded Mark Inversion
− Intelligent 1-Bit Error Correction
− Magnetic Saturation Prevention
Single Operation Mode
− Supports Only Peripheral (Host) Mode Operates
with MCU
Supports 8 Bit Programmable General Purpose
I/O
Dual Communication Modes (with Peripheral
Mode)
− Free Format Mode
− Remote Buffer Mode
3 Port Hub Integrated
− 1 Internal and 2 External
Flexible Topologies
− Bus, Star, and Tree
Low-Cost Media can be Used
− RS485 Differential Driver
Fiber Optics and Twisted Pair Cable Supported
100-Pin, TQFP Lead-Free RoHS Compliant
Package
Temperature Range from 0 to 70 Degrees C
SMSC TMC2072 Page 1 Revision 0.1 (06-07-07)
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
ORDERING INFORMATION
Order Number:
TMC2072-MT for 100 pin, TQFP Lead-Free RoHS Compliant Package
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2007 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
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could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMS C is a re gis te red trademark of Standard Microsystems
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Revision 0.1 (06-07-07) Page 2 SMSC TMC2072
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
TABLE OF CONTENTS
Chapter 1 General Description.............................................................................................................6
1.1 About CircLink.....................................................................................................................................6
1.2 About the TMC2072............................................................................................................................7
1.3 Pin Configuration.................................................................................................................................9
1.4 Pin Description by Functions.............................................................................................................14
1.4.1 CPU Interface (27)..................................................................................................................................14
1.4.2 Transceiver Interface (5).........................................................................................................................14
1.4.3 Setup Pin (33).........................................................................................................................................14
1.4.4 External Output or Input/output (10) .......................................................................................................15
1.4.5 Other Input (5) ........................................................................................................................................15
1.4.6 Clock (3) .................................................................................................................................................16
1.5 User Setup Pins ................................................................................................................................16
1.5.1 CPU Type Selection ...............................................................................................................................16
1.5.2 Address Multiplex Selection....................................................................................................................17
1.5.3 Write Timing Selection............................................................................................................................19
1.5.4 Read Timing Selection............................................................................................................................20
1.5.5 Data Bus Width Selection.......................................................................................................................21
1.5.6 Data Bus Byte Swap...............................................................................................................................21
1.5.7 Data Strobe Polarity Specification ..........................................................................................................21
1.5.8 Page Size Selection................................................................................................................................21
1.5.9 MAXID Number Setup ............................................................................................................................21
1.5.10 Node ID Setup.....................................................................................................................................22
1.5.11 NST Resolution Setup.........................................................................................................................22
1.5.12 Standalone Mode Specification (Not supported).................................................................................22
1.5.13 Warning Timer Resolution...................................................................................................................22
1.5.14 Diagnosis Mode ..................................................................................................................................22
1.5.15 Prescaler Setup for Communication Speed ........................................................................................23
1.5.16 CPU Interface Bus Timing Selection...................................................................................................23
1.5.17 CMI Bypass Specification....................................................................................................................23
1.5.18 ON/OFF of HUB Function...................................................................................................................23
1.5.19 Optical Transceiver Mode ...................................................................................................................24
1.5.20 TXEN Polarity Select...........................................................................................................................24
1.5.21 Extension Timer Setting 1...................................................................................................................24
1.5.22 Test Pins.............................................................................................................................................24
Chapter 2 Functional Description.......................................................................................................25
2.1 Communication Specification............................................................................................................25
2.2 Message Class..................................................................................................................................25
2.3 CircLink Network Communication Protocol Overview ......................................................................26
2.4 CircLink Protocol Enhancement........................................................................................................27
2.4.1 Reducing Token Loss.............................................................................................................................27
2.4.2 Reduction of Network Reconfiguration Time...........................................................................................27
2.4.3 Reduction of Reconfiguration Burst Signal Send Time...........................................................................28
2.5 RAM Page Expansion.......................................................................................................................28
2.5.1 RAM Access........................................................................................................................................... 29
2.5.2 Packet Buffer Structure...........................................................................................................................31
2.5.3 Packet Data Structure............................................................................................................................. 32
2.6 CPU Interface....................................................................................................................................33
2.6.1 CPU Identification and Compatibility Between Intel and Motorola Processors........................................33
2.6.2 Interface Restrictions..............................................................................................................................34
2.7 Operation and Communication Modes of CircLink ...........................................................................35
2.7.1 Operation Mode......................................................................................................................................35
2.7.2 Communication Mode.............................................................................................................................36
2.8 Sending in Peripheral Mode..............................................................................................................38
2.8.1 Example of Sending Control from CPU in Free Format Mode ................................................................38
2.8.2 TX Control from CPU in Remote Buffer Mode........................................................................................39
SMSC TMC2072 Page 3 Revision 0.1 (06-07-07)
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Peripheral Mode CircLink™ Controller
Datasheet
2.9 Receive in Peripheral Mode..............................................................................................................39
2.9.1 Temporary Receive and Direct Receive .................................................................................................41
2.9.2 Example of Receive Flow in Free Format Mode.....................................................................................43
2.9.3 Example of Receive Flow in Remote Buffer Mode..................................................................................44
2.9.4 Warning Timer (WT) at Remote Buffer Receive .....................................................................................44
2.10 Diagnostic Mode ............................................................................................................................47
2.11 Network Standard Time (NST).......................................................................................................47
2.11.1 Functions Provided by NST.................................................................................................................48
2.11.2 Time-Synchronous Sequence.............................................................................................................49
2.11.3 Phase Error.........................................................................................................................................50
2.11.4 nNSTCOUT Pulse Generation Cycle ..................................................................................................53
2.12 CMI Modem....................................................................................................................................55
2.13 HUB Function.................................................................................................................................56
2.13.1 Operation Example of HUB Function..................................................................................................57
2.13.2 Timer Expansion in Multi-Stage Cascade Connection ........................................................................58
2.14 8bit General-purpose I/O Port (New Function)..............................................................................59
Chapter 3 Register Descriptions.........................................................................................................60
3.1 Register Map.....................................................................................................................................60
3.2 Register Details.................................................................................................................................63
3.2.1 COMR0 Register: Status/interrupt Mask Register ..................................................................................63
3.2.2 COMR1 Register: Diagnostic/Command Register..................................................................................65
3.2.3 COMR2 Register: Page Register............................................................................................................67
3.2.4 COMR3 Register: Page-Internal Address Register.................................................................................68
3.2.5 COMR4 Register: Data Register............................................................................................................. 69
3.2.6 COMR5 Register: Sub-address Register................................................................................................69
3.2.7 COMR6 register: Configuration Register ................................................................................................70
3.2.8 COMR7 Register ....................................................................................................................................71
3.2.9 NST register: Network Standard Time....................................................................................................75
3.2.10 INTSTA Register: EC Interrupt Status.................................................................................................75
3.2.11 INTMSK Register: EC Interrupt Mask .................................................................................................78
3.2.12 ECCMD Register: EC Command Register..........................................................................................78
3.2.13 RSID Register: Receive SID ...............................................................................................................79
3.2.14 SSID Register: SID .............................................................................................................................80
3.2.15 RXFH Register: Receive Flag (higher side) ........................................................................................80
3.2.16 RXFL Register: Receive Flag (lower side) ..........................................................................................81
3.2.17 CMID register: Clock Master Node ID.................................................................................................82
3.2.18 MODE Register: Operation Mode Setup Register...............................................................................83
3.2.19 CARRY Register: Carry Selection for External Output........................................................................85
3.2.20 RXMH Register: Receive Mode (higher side)......................................................................................86
3.2.21 RXML Register: Receive Mode (lower side)........................................................................................87
3.2.22 MAXID Register: Selection of Max. ID ................................................................................................88
3.2.23 NID Register: Selection of the Node ID...............................................................................................88
3.2.24 PS Register: Page Size Selection.......................................................................................................88
3.2.25 CKP Register: Communication Rate Selection ...................................................................................89
3.2.26 NSTDIF Register: NST Phase Difference ...........................................................................................89
3.2.27 PININFO Register: Pin Setup Information...........................................................................................90
3.2.28 ERRINFO Register: Error Information.................................................................................................90
Appendix A. CMI Modem....................................................................................................................93
Appendix B. Crystal Oscillation Circuit ...........................................................................................100
Appendix C. Package Outline............................................................................................................101
Appendix D. Marking Specifications.................................................................................................102
Appendix E. Electrical Characteristics.............................................................................................103
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DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
LIST OF FIGURES
Figure 1 - TMC2072 Internal Block Diagram...........................................................................................................8
Figure 2 - TMC2072 Pin Configuration ...................................................................................................................9
Figure 3 - MOTOROLA CPU Mode (68hXX) ........................................................................................................17
Figure 4 - INTEL CPU MODE (86XX)...................................................................................................................17
Figure 5 - Non-multiplex Bus ................................................................................................................................18
Figure 6 - Multiplex (ALE falling-edge Type).........................................................................................................18
Figure 7 - Multiplex (ALE rising-edge Type).......................................................................................................... 18
Figure 8 - Packet Structure of Free Format Mode (Example of 32 bytes/page)....................................................36
Figure 9 - Packet Structure of Remote Buffer Mode (Example of 32 bytes/page).................................................37
Figure 10 - CMI Coding State transition diagram....................................................................................................93
Figure 11 - CMI Modem Block Diagram..................................................................................................................94
Figure 12 - Example of unstable Comparator output ..............................................................................................98
Figure 13 - TMC2072 Package Outline.................................................................................................................101
Figure 14 - Timing Measurement Points...............................................................................................................105
LIST OF TABLES
Table 1 - Pin Description.........................................................................................................................................10
Table 2 - Number of Nodes and RAM Page Size....................................................................................................28
Table 3 - CPU Type ................................................................................................................................................33
Table 4 - Distinction and Matching of the CPU type................................................................................................33
Table 5 - Page Format of Packet Buffer..................................................................................................................42
Table 6 - CircLink Register Map..............................................................................................................................60
Table 7 - TMC2072 Package Parameters.............................................................................................................101
SMSC TMC2072 Page 5 Revision 0.1 (06-07-07)
DATASHEET
Chapter 1 General Description
1.1 About CircLink
The CircLink networking controller was developed for small control-oriented local network data
communication based on ARCNET’s token-passing protocol that guarantees message integrity and
calculatable maximum delivery times.
In a CircLink network, when a node receives the token it becomes the temporary master of the network for
a fixed, short period of time. No node can dominate the network since token control must be relinquished
when transmission is complete. Once a transmission is completed the token is passed on to the next node
(logical neighbor), allowing it to be come the master.
Because of this token passing scheme, maximum waiting time for network access can be calculated and
the time performance of the network is predictable or deterministic. Industrial network applications require
predictable performance to ensure that controlled events occur when required.
However, reconfiguration of a regular ARCNET network becomes necessary when the token is missed due
to electronic and magnetic noise. In these cases, the maximum wait time for sending datagrams cannot be
guaranteed and the real-time characteristic is impaired. CircLink makes several modification to the original
ARCNET protocol (such as maximum and consecutive node ID assignment) to avoid token missing as
much as possible and reduce the network reconfiguration time.
Peripheral Mode CircLink™ Controller
Datasheet
CircLink implements other enhancements to the ARCNET protocol including a smaller-sized network ,
shorter packet size, and remote buffer mode operation that enable more efficient and reliable small,
control-oriented LANs. In addition, CircLink introduces several unique features for reducing overall system
cost while increasing system reliability.
CircLink can operate under a special mode called “Standalone” or “I/O” mode. In this mode, CircLink does
not need an administrating CPU for each node. Only one CPU is needed to manage a CircLink network
composed of several nodes, reducing cost and complexity.
In a CircLink network, the data sent by the source node is received by all other nodes in the network and
stored according to node source ID. For the target node the received data is executed per ARCNET flow
control and the data is stored in its buffer RAM. The receiving node processes the data while the remaining
nodes on the network discard the data when the receiving node has completed. This memory-mirroring
function assures higher reliability and significantly reduces network traffic.
Network Standard Time (NST) is also a unique CircLink feature. NST is realized by synchronizing the
individual local time on each network node to the clock master in the designated node from which the
packet is sent. CircLink also uses CMI code for transmitting signals, rather than the dipulse or bipolar
signals that are the standard ARCNET signals. Since CMI encoding eliminates the DC element, a simple
combination of a standard RS485 IC and a pulse transformer can be used to implement a transformercoupled network.
Revision 0.1 (06-07-07) Page 6 SMSC TMC2072
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
1.2 About the TMC2072
The TMC2072 network controller is CircLink technology’s flagship product. The TMC2072’s flexibility and
rich feature set enable a high-reliability and high-performance, real-time and control-oriented network
without the cumbersome middle layer protocol stacks and complex packet prioritization schemes typically
required.
TMC2072 operates at network data transfer rates up to 5 Mbps. Its embedded 1k Byte RAM can be
configured into a maximum of 32 pages to implement a 31-node network where each node in the network
has the same local memory.
TMC2072 supports “Peripheral Mode” operation, which includes two selectable communication modes:
“Free Format Mode” and “Remote Buffer Mode”. Free Format mode, retained from ARCNET, is “packet
oriented” communication. Remote Buffer mode communication is a CircLink-specific feature, and is a
token oriented communication, which includes automatic data transmission when the token arrives.
The TMC2072 has a flexible 8-bit or 16-bit data bus to interface various CPU types including X86, 68XX,
and SHx with multiplexed or non-multiplexed address/data. When operating in Peripheral mode, the
TMC2072 has 8-bit programmable I/O available. When operating in Standalone mode, the TMC2072’s I/O
configuration is16-bit. The TMC2072 also integrates a 3-port hub (two ports for external connection) to
accommodate various network topologies (Bus, Star, etc.) and combinations.
SMSC TMC2072 Page 7 Revision 0.1 (06-07-07)
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
Micro-Controller bus
Register Ac cess
Control Circuit
Mode Setting
Interrupt Sta tu s
Interrupt Mask
EC Command
Receive Mode(#01-#31)
Receive Flag(#01-#31)
Clock Master SID
Net. Standard Time
Alarm Setting
Receive SID
Search SID
MAX ID Setting (MAXID)
nMUX nRWM W16 nSWAP
Memory Access Mediation Circuit
Address pointer
Page Register
Address Register
Diag. Register
Data Register H
Data Register L
Data Latch
TENT-ID Register
CONFIG Register
SETUP Registers
Others
Address
Multiplexer
Buffer Memory
512B 512B
RECON Timer
Clock
Address Pointer
Improved ARCNET Protocol
Micro Sequencer
Working Registers
Data Latch Shift Register
TX Signal
Generator
RX Synchronous
FLASHO nNSTCOUT
circuit
Node ID Setting (NID)
Page Size Setting (PS)
Data Rate Setting
PIN-INFO
ERR-INFO
MAXID NID PS CKP
Reset Circuit
nSTALONE nDIAG
OSC
nHUBON nCMIBYP
TXEN2 RXIN2
3Port HUB Circuit
CMI Decode CMI Encode
CMI Synchro
TXEN TXD RXIN
Figure 1 - TMC2072 Internal Block Diagram
Revision 0.1 (06-07-07) Page 8 SMSC TMC2072
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
1.3 Pin Configuration
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GPIO0
*2 *3 *3 *1 *3 *2 *1
FLASHO
nNSTCOUT
VSSX2X1
VDD
MCKIN
VSS
CKP2
CKP1
CKP0
MAXID4
MAXID3
MAXID2
VDD
MAXID1
MAXID0
WPRE0 NID4
WPRE1 NID3
*1
VDD NID2
nTEST0 NID1
nTEST1 NID0
nTEST2 PS1
nTEST3 PS0
(High) NSTPRE1
nEHRD NSTPRE0
nEHWR VDD
*1
VDD VSS
nCMIBYP nDIAG
nOPMD RXIN2
nHUBON ET1
*2
VSS RXIN
NSTPRE2 TXENPOL
nMUX TXEN2
nRWM TXD
W16 TXEN
nSWAP
nCS VSS
A0 nRESET
A1 VDD
A2 (ALE) D15
*2
VSS D14
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
12345678910111213141516171819202122232425
A3 (ALEPOL) / PO3A4VDDA5nDSINV
nRD (nDS)
nTMODE
nWR (DIR)
VDD
D0 (AD0)
D1 (AD1)
D2 (AD2)
D3 (AD3)
VSS
VSS
D4 (AD4)
D5 (AD5)D6D7D8D9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
nINTR
30
29
28
27
26
D10
D11
D12
D13
*1
*2
*2
*4
*1
*1 *1 *2 *2 *1
Power Supply (VDD)
Power Supply (VSS)
*2
Clock Signal
*3
Reset Signal
*4
Figure 2 - TMC2072 Pin Configuration
SMSC TMC2072 Page 9 Revision 0.1 (06-07-07)
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
Table 1 - Pin Description
PIN
COUNT PIN NO.
CPU Interface
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
29
96
97
98
99
1
2
4
6
8
10
11
12
13
16
17
18
19
20
21
22
23
24
25
26
27
31
Total 27
PERIPHERAL MODE
INPUT BUFFER
OUTPUT BUFFER
PULL-
PIN NAME DIRECTION
UP TYPE DRIVE TYPE
nRESET IN Internal T-NRM --- -- nCS IN Internal T-NRM --- -- A0 IN Internal T-NRM --- -- A1 IN Internal T-NRM --- -- A2/ALE IN Internal T-NRM --- -- A3/ALEPOL IN Internal T-NRM --- -- A4 IN Internal T-NRM --- -- A5 IN Internal T-NRM --- -- nRD/nDS IN Internal T-NRM --- -- nWR/DIR IN Internal T-NRM --- -- D0/AD0 BI Internal T-NRM 4mA
D1/AD1 BI Internal T-NRM 4mA
D2/AD2 BI Internal T-NRM 4mA
D3/AD3 BI Internal T-NRM 4mA
D4/AD4 BI Internal T-NRM 4mA
D5/AD5 BI Internal T-NRM 4mA
D6 BI Internal T-NRM 4mA
D7 BI Internal T-NRM 4mA
D8 BI Internal T-NRM 4mA
D9 BI Internal T-NRM 4mA
D10 BI Internal T-NRM 4mA
D11 BI Internal T-NRM 4mA
D12 BI Internal T-NRM 4mA
D13 BI Internal T-NRM 4mA
D14 BI Internal T-NRM 4mA
D15 BI Internal T-NRM 4mA
nINTR OUT --- --- 2mA
Revision 0.1 (06-07-07) Page 10 SMSC TMC2072
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Peripheral Mode CircLink™ Controller
Datasheet
PIN
COUNT PIN NO.
Transceiver Interface
1
2
3
4
5
36
32
33
38
34
Total 5
Clock
1
2
3
63
64
61
Total 3
Setting Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
92
93
94
95
42
43
91
44
45
46
47
48
49
50
51
52
54
55
56
57
58
59
39
PERIPHERAL MODE
INPUT BUFFER
OUTPUT BUFFER
PULL-
PIN NAME DIRECTION
UP TYPE DRIVE TYPE
RXIN IN Internal T-NRM --- -- TXEN OUT --- --- 4mA
TXD OUT --- --- 4mA
RXIN2 IN Internal T-NRM --- -- TXEN2 OUT --- --- 4mA
X1 IN --- --- --- --X2 OUT
--- --- --- ---
MCKIN IN Internal T-NRM --- ---
nMUX IN Internal T-NRM --- -- nRWM IN Internal T-NRM --- -- W16 IN Internal T-NRM --- -- nSWAP IN Internal T-NRM --- -- NSTPRE0 IN Internal T-NRM --- -- NSTPRE1 IN Internal T-NRM --- -- NSTPRE2 IN Internal T-NRM --- -- PS0 IN Internal T-NRM --- -- PS1 IN Internal T-NRM --- -- NID0 IN Internal T-NRM --- -- NID1 IN Internal T-NRM --- -- NID2 IN Internal T-NRM --- -- NID3 IN Internal T-NRM --- -- NID4 IN Internal T-NRM --- -- MAXID0 IN Internal T-NRM --- -- MAXID1 IN Internal T-NRM --- -- MAXID2 IN Internal T-NRM --- -- MAXID3 IN Internal T-NRM --- -- MAXID4 IN Internal T-NRM --- -- CKP0 IN Internal T-NRM --- -- CKP1 IN Internal T-NRM --- -- CKP2 IN Internal T-NRM --- -- nDIAG IN Internal T-NRM --- ---
SMSC TMC2072 Page 11 Revision 0.1 (06-07-07)
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
PIN
COUNT PIN NO.
24
25
26
27
28
29
30
31
32
33
34
35
76
77
83
84
85
5
87
89
88
37
Total 34
Output Pins
1
2
3
4
5
6
7
8
9
10
66
67
68
69
70
71
72
73
74
75
Total 10
Test Pins
PERIPHERAL MODE
INPUT BUFFER
OUTPUT BUFFER
PULL-
PIN NAME DIRECTION
UP TYPE DRIVE TYPE
TXENPOL IN Internal T-NRM --- -- WPRE0 IN Internal T-NRM --- -- WPRE1 IN Internal T-NRM --- -- Un-USE(High) IN Internal T-NRM --- -- nEHRD IN Internal T-NRM --- -- nEHWR IN Internal T-NRM --- -- nDSINV IN Internal T-NRM --- -- nCMIBYP IN Internal T-NRM --- -- nHUBON IN Internal T-NRM --- -- nOPMD IN Internal T-NRM --- -- ET1 IN Internal T-NRM --- ---
nNSTCOUT OUT --- --- 4mA
FLASHO 3s.O --- --- 4mA
GPIO0 3s.O Internal T-NRM 4mA
GPIO1 3s.O Internal T-NRM 4mA
GPIO2 3s.O Internal T-NRM 4mA
GPIO3 3s.O Internal T-NRM 4mA
GPIO4 3s.O Internal T-NRM 4mA
GPIO5 3s.O Internal T-NRM 4mA
GPIO6 3s.O Internal T-NRM 4mA
GPIO7 3s.O Internal T-NRM 4mA
1
2
3
4
5
79
80
81
82
7
nTEST0 IN Nothing T-NRM --- -- nTEST1 IN Nothing T-NRM --- -- nTEST2 IN Nothing T-NRM --- -- nTEST3 IN Nothing T-NRM --- -- nTMODE IN Internal T-NRM --- ---
Total 5
Revision 0.1 (06-07-07) Page 12 SMSC TMC2072
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
PIN
COUNT PIN NO.
Power Pins
3, 9,
1-8
9-16
Total 16
Total Pin = 100
28, 41,
53, 62,
78, 86
14, 15,
30, 40,
60, 65,
90, 100
PIN NAME DIRECTION
VDD PWR
PERIPHERAL MODE
VSS PWR
(High) : Connect to VDD
(Open) : Not connected
INPUT BUFFER
PULL-
UP TYPE DRIVE TYPE
--- --- --- ---
--- --- --- ---
--- --- --- ---
--- --- --- ---
--- --- --- ---
--- --- --- ---
--- --- --- ---
--- --- --- ---
T-NRM TTL Level Input w/o Schmitt
3s/O Tri-state Output or Normal Output
3s.O Tri-state Output
OUTPUT BUFFER
SMSC TMC2072 Page 13 Revision 0.1 (06-07-07)
DATASHEET
1.4 Pin Description by Functions
NOTE: * A pin name starting with “n” indicates an active-low pin.
1.4.1 CPU Interface (27)
D[15:6]/ Data Bus (bit15-6)
D[5:0]/AD[5:0] Data Bus / Address Data Bus (bit5-0)
nCS Chip Select Input
nWR/DIR Write Signal Input / Access Direction
nRD/nDS Read Signal Input / Data strobe
A[5:4] Address Input
A[3]/ALEPOL Address Input / ALE Designate Polarity
Peripheral Mode CircLink™ Controller
Datasheet
A[2]/ALE Address Input / ALE
A[1:0] Address (bit1-0)
nINTR Interrupt Output (Active Low)
nRESET Reset Input (Active Low)
1.4.2 Transceiver Interface (5)
RXIN Port1 Receive Data Input
TXEN Port1 Transmit Enable Output
TXD Transmit Data Output (Port1, 2 Common)
RXIN2 Port2 Receive Data Input
TXEN2 Port2 Tr ansmit Enable Output
1.4.3 Setup Pin (33)
nMUX Select Address Multiplex Mode
nRWM Select R/W Mode
W16 Select Data Bus Width
nSWAP Select Swap Mode
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Datasheet
nDSINV nDS Designate Polarity
PS[1:0] Determine Page Size (*1)
NID[4:0] Determine MyID Number (*1)
MAXID[4:0] Determine MAXID Number (*1)
CKP[2:0] Determine Data Rate (*1)
NSTPRE[2:0] NST Resolution
WPRE[1:0] Select Warning Timer Resolution
nDIAG Select Diagnostics Mode
ET1 Determine ARCNET Extended Timer (*1)
nEHWR Select Enhanced Write Mode
nEHRD Select Enhanced Read Mode
TXENPOL TXEN,TXEN2 Designate Polarity
nOPMD Select Optical Transceiver Mode
nCMIBYP Bypass CMI Modem
nHUBON ON/OFF Determine of Internal HUB function
NOTE: (*1) Could be also determined by the register at the Peripheral Mode
1.4.4 External Output or Input/output (10)
nNSTCOUT NST Carry Output
FLASHO Outside Output for FLASH
GPIO[7:0] General-purpose I/O port (bit7-0)
1.4.5 Other Input (5)
nTEST[3:0] Test Pins
nTMODE Test Mode
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1.4.6 Clock (3)
X1 Crystal Oscillator
X2 Crystal Oscillator
MCKIN Master Clock Input
X1
Peripheral Mode CircLink™ Controller
Datasheet
X2
MCKIN
- Using an external clock :
X1 is connected to GND with MCKIN connected to the input of the external clock
- Using XTAL :
MCKIN is connected to VDD with X1, X2 connected to the Crystal Oscillator
1.5 User Setup Pins
Setup pins are strapped high or low to configure options according to system design. For low, strap to
ground. Many pins have internal pullups on their input buffers. These pins can be left unconnected to keep
them in high state.
1.5.1 CPU Type Selection
(nRWM: Pin)
MCK
(Internal MasterClock)
In Peripheral mode, this pin selects the CPU type; in this case, the definition of nWR/DIR (pin) and
nRD/nDS (pin) are selected. (Refer to Figure 3 - MOTOROLA CPU Mode (68hXX) and Figure 4 - INTEL
CPU MODE (86XX).
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Peripheral Mode CircLink™ Controller
Datasheet
[nRWM=H, nDSINV=H]
DIR
nDS
nWR
nRD
Read Cycle
Figure 3 - MOTOROLA CPU Mode (68hXX)
[nRWM=L, nDSINV=L or H]
Read Cycle
Figure 4 - INTEL CPU MODE (86XX)
Write C ycle
Write Cycle
1.5.2 Address Multiplex Selection
(nMUX: Pin)
In Peripheral mode, this pin specifies the system data bus from bit 5 to 0 and whether the addresses are
multiplexed (Refer to Figure 5 - Non-multiplex Bus, Figure 6 - Multiplex (ALE falling-edge Type) and Figure
7 - Multiplex (ALE rising-edge Type). When the multiplexing bus option is selected, the polarity of A2/ALE
is specified based on A3/ALEPOL.
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[In case of nMUX=H]
Peripheral Mode CircLink™ Controller
Datasheet
D15-8
D7-0
A5-0
Figure 5 - Non-multiplex Bus
[In Case of nMUX=L, ALEPOL=H]
D ata High B yte
D ata L o w By te
Address
1 Bus C ycle
D15-8
D7-6
AD5-0
Address
Data High Byte
D a ta bit7- 6
D a ta b it5 - 0
ALE
Figure 6 - Multiplex (ALE falling-edge Type)
[In case of nMUX=L, ALEPOL=L]
1 Bus C ycle
D15-8
D7-6
AD5-0
ALE
Address
Figure 7 - Multiplex (ALE rising-edge Type)
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D a ta High Byte
D a ta b it7 - 6
D a ta b it5 - 0
DATASHEET
Peripheral Mode CircLink™ Controller
Datasheet
1.5.3 Write Timing Selection
(nEHWR: Pin)
In Peripheral mode, this pin selects the write timing.
[ Example: nMUX=H,nEHWR=H ]
nCS
Write Signal
Tie to Hi for CPU’s where nCS goes Hi before the write signal goes Hi.
[ Example: nMUX=H,nEHWR=L ]
nCS
Write Signal
Tie to Low for CPUs where nCS goes Hi after the write signal goes Hi.
The write signal differs depending on the CPU types.
nRWM = H: nDS signal at DIR = L
nRWM = L: nWR signal
NOTE: Refer to the AC timing specifications (in another document) for details (setup time, hold time, etc.).
Compare timing specifications for nEHWR=L and nEHWR=H.
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1.5.4 Read Timing Selection
(nEHRD: Pin)
In Peripheral mode, this pin selects the read timing type.
[ In case of nMUX=H,nEHRD=H ]
A[5:0]
nCS
Read Signal
Address Samplin g
timing
Tie to Hi for CPUs with valid address before nCS and the read signal go low.
Peripheral Mode CircLink™ Controller
Datasheet
[ Example: nMUX = H and nEHRD = L ]
A[5:0]
nCS
Read Signal
Address Sampling
timing
Tie to L for the CPU’s where nCS is enabled and addresses are valid after the read signal goes low.
NOTE: Address acquisition timing in the CircLink delays about 50 ns (with 20 MHz-XTAL).
The read signal differs depending on the CPU type:
nRWM = H: nDS signal at DIR = H
nRWM = L: nRD signal
NOTE: Refer to the AC timing specifications (in another document) for details (setup time, hold time, etc.).
Compare timing specifications for nEHRD=L and nEHRD=H.
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Datasheet
1.5.5 Data Bus Width Selection
(W16: Pin)
This pin selects the bit width of the data bus in Peripheral mode; H: 16-bit mode, L: 8-bit mode. In the 16bit mode, the LSB address in the CircLink is fixed to 0.
1.5.6 Data Bus Byte Swap
(nSWAP: Pin)
In Peripheral mode, this pin selects the data order at 8-bit access. CircLink registers are defined as 16-bit
width, but 8-bit access is available and in this case the assignment of lower/upper byte of registers and
odd/even numbers of the address can be changed. nSWAP=L assigns the lower byte to even number
address and the upper byte to odd number address, and nSWAP=H assigns the lower byte to odd number
address and the upper byte to even number address.
1.5.7 Data Strobe Polarity Specification
(nDSINV: pin)
In Peripheral mode, this pin selects the pin polarity of data strobe (nDS). It is active low with nDSINV = H
and active high with nDSINV = L.
1.5.8 Page Size Selection
(PS[1:0]: Pin/Register)
Selects page size per packet. The maximum number of nodes depends on the page size selection since
the packet buffer size is limited to 1 kBytes. There are two methods to specify the page size: either through
pin or register settings depending on INIMODE (bit 9); 0: selects pin, 1: selects register (The default is 0).
PS[1:0] Page Size Max Node Number
00 256 Byte 3 Node
01 128 Byte 7 Node
10 64 Byte 15 Node
11 32 Byte 31 Node
1.5.9 MAXID Number Setup
(MAXID[4:0]: Pin/Register)
The maximum node ID is set based on the number of nodes on the network. All nodes in a CircLink
network, therefore, should have the same maximum node ID. This optimizes the time required to
reconfigure the network. There are two methods to specify the maximum node ID, Either through pin or
register settings depending on INIMODE (bit 9); 0: selects pin, 1: selects register (The default is 0). If the
nDIAG pin is set to L as the exception, however, the maximum node ID is automatically set to the largest
value. For more details, refer to section 2.10 - Diagnostic Mode.
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Peripheral Mode CircLink™ Controller
Datasheet
1.5.10 Node ID Setup
(NID[4:0]: Pin/Register)
Sets node ID. A unique number must be assigned to each node in the network in ascending order starting
from ID=01. However, ID = 00 and an ID that is larger than the maximum node ID are not valid. There are
two methods to assign the node ID, either through pin or register, settings depending on INIMODE (bit 7)
0: selects pin, 1: select register (The default is 0).
MAXID[4:0] determines the maximum node ID value. The token will only be passed around the nodes
whose IDs are equal to or less than the maximum ID value. In the CircLink network, a node whose
MAXID[4:0] and NID[4:0] matches is the node initiating the token passing.. Even if this particular node is
absent from the network, the network reconfiguration time is greatly reduced because the network will be
reconfigured only for the nodes with IDs less than MAXID[4:0]. Also, given that the maximum number of
nodes is fixed to 31 in a CircLink network, the original priority time of ARCNET, (255 – ID) x 146 μs* ,
which determines the waiting time for network reconfiguration initiation, is modified to (31-ID) x 146 μs,
greatly reducing reconfiguration time. Refer to section 2.4.2 - Reduction of Network Reconfiguration Time
for more details.
NOTE: * 146 μs is defined under operation at 2.5 Mbps based on the ARCNET protocol. The time is half at 5
Mbps.
1.5.11 NST Resolution Setup
(NSTPRE[2:0]: Pin)
Selects the resolution of the network standard time counter (NST). Refer to section 2.11 - Network
Standard Time (NST) for details.
1.5.12 Standalone Mode Specification (Not supported)
TMC2072 does not support standalone mode.
1.5.13 Warning Timer Resolution
(WPRE[1:0]: Pin]
These pins select the warning timer resolution in Peripheral mode. Refer to section 2.9.4 - Warning Timer
(WT) at Remote Buffer Receive for more details.
1.5.14 Diagnosis Mode
(nDIAG: Pin)
This pin sets CircLink to the diagnosis mode. nDIAG to 0 forcibly fixes the MAXID to “1Fh”. Refer to
section 2.10 - Diagnostic Mode for details.
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Datasheet
1.5.15 Prescaler Setup for Communication Speed
(CKP[2:0]: Pin/Register)
CKP2-0 Prescale
40MH z XTA L 20M H z XTAL 32MH z XTA L 16MH z XTA L
Com m unication Speed
000 8 5M bps 2.5Mbps 4Mbps 2Mbps
001 16 2.5Mbps 1.25Mbps 2Mbps 1Mbps
010 32 1.25Mbps 625Kbps 1M bps 500Kbps
011 64 625Kbps 312.5Kbps 500Kbps 250Kbps
100 128 312.5Kbps 156.25Kbps 250Kbps 125Kbps
101 256 156.25Kbps 78.125Kbps 125K bps 62 .5K bps
11 0 res erv ed res erv ed re se rve d res erv ed re s erve d
11 1 res erv ed res erv ed re se rve d res erv ed re s erve d
Communication speed (transfer rate) selection for CircLink. There are two methods to determine the
communication speed, either through pin or register settings, depending on the specification of INIMODE
(bit 9); 0: pin, 1: register (Default is 0).
1.5.16 CPU Interface Bus Timing Selection
(nEHWR, nEHRD: Pin)
For the functions using Peripheral mode, refer to sections 1.5.3 and 1.5.4.
1.5.17 CMI Bypass Specification
(nCMIBYP: Pin)
Selects bypassing the CMI code/encoding. nCMIBYP = L bypasses the CMI coding/decoding circuit so that
encoding is RZ form signal interface, equivalent to the ARCNET back plane mode.
1.5.18 ON/OFF of HUB Function
(nHUBON: Pin)
Selects ON/OFF ; nHUBON=H selects the HUB function OFF, nHUBON=L selects the HUB function ON
and enables the port 2 (RXIN2 and TXEN2) available. ( in nHUBON = H, RXIN2 should be fixed to High.)
Refer to section 2.13 - HUB Function for the detailed operations.
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1.5.19 Optical Transceiver Mode
(nOPMD: Pin)
Selects the output mode of the sending-enable; nOPMD = H makes the optical transceiver mode
unavailable and allows the TXEN and TXEN2 output pins to function as “sending-enable”. Setting nOPMD
= L allows TXEN and TXEN2 output pins to function as “sending-enable and sending pulse” to be able to
be directly connected to the TTL input pin of the optical transceiver.
1.5.20 TXEN Polarity Select
(TXENPOL: Pin)
Selects the output polarities of the TXEN and TXEN2 signals. TXENPOL = L selects negative logic and
TXENPOL = H selects positive logic.
1.5.21 Extension Timer Setting 1
(ET1: Pin/Register)
Peripheral Mode CircLink™ Controller
Datasheet
Refer to section 2.13 - HUB Function for operational details.
1.5.22 Test Pins
(nTEST[3:0], nTMODE: Pin)
All pins must be connected to VDD.
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Chapter 2 Functional Description
2.1 Communication Specification
- Data transfer bit rate 78.125 kbps to 2.5 Mbps (at 20 MHz Xtal), (5 Mbps at 40-MHz Xtal)
- The max. number of nodes 31 (ID = 00 is not available for user)
- Data transfer check Only the destination node can check data transfer. Other nodes,
however, can receive (monitor) the same data.
- Protocol Enhanced version of ARCNET (token passing)
- Packet size 256 bytes max. (User area: 253 bytes max.)
2.2 Message Class
The following five classes of messages are identical to those in the ARCNET protocol. Refer to the
ARCNET Controller COM20020 Rev. D Datasheet for more details.
ITT (Token)
ALERT EOT
DID
FBE (Free Buffer Enquiries)
ALERT ENQ
DID
ACK (Acknowledgements)
ALERT ACK
NAK (Negative Acknowledgements)
ALERT NAK
PACKET (Data Packets)
ALERT SOH
SID
DID
DID
DID
DID CP CRC CRC
DATA X n
N : MAX253
(ARCNET Layer)
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Peripheral Mode CircLink™ Controller
2.3 CircLink Network Communication Protocol Overview
CircLink is derived from the ARCNET protocol. This section explains the ARCNET basic communication
protocol.
A token (ITT Invitation to Transmit) is a unique signaling sequence that is passed in an orderly fashion
among all the active nodes in the network. When a particular node receives the token, it has the sole right
to initiate a transmission sequence or it must pass the token to it’s logical neighbor. This neighbor can be
physically located anywhere on the network and has the 2nd highest address. Once the token is passed to
the recipient, it has the right to initiate transmission. This token-passing sequence continues in a logical
ring fashion serving all nodes equally. Node addresses must be unique and can range from 0 – 255 with 0
reserved for broadcast messages. In a transmission sequence the node with the token becomes the
source node and any other node selected becomes the destination node. First the source node inquires if
the destination node is in a mode to receive a transmission by sending out a free buffer enquiry (FBE). The
destination node responds by returning an Acknowledgement (ACK) meaning that the buffer is available or
by returning a negative Acknowledgement (NAK) meaning that no buffer is available. Upon receiving the
ACK, the source node sends out the data transmission (PAC) with either 0 – 507 bytes of data (PAC). If
the data was properly received by the destination node as evidenced by a successful CRC test, the
destination node sends another ACK. If the transmission was unsuccessful, the destination node does
nothing causing the source node to timeout. The source node will therefore, infer that the transmission
failed and will retry after it receives the token on the next token pass. The transmission sequence
terminates and the token is passed to the next node. If the desired message exceeds 507 bytes the
message is sent in a series of packets-one packet every token pass.
Datasheet
The ARCNET protocol comprises the reconfiguration process to ensure the complete token passing for
every node linked to the network.
ARCNET has the ability to reconfigure the network automatically if a node is either added or removed from
the network. If a node joins the network it does not automatically participate in the token passing
sequence. Being excluded from receiving the token the new node will generate a reconfiguration burst that
destroys the token passing sequence. Once the token is lost all nodes will cease transmitting and begin a
timeout sequence (Priority Timer, (255-ID) x 146 μs , based on their own node address. The node (Node
ID=N) with the highest address will timeout first and pass the token to the next higher address (Node
ID=N+1).. If that node does not respond, it is assumed that node does not exist. Then the destination node
address is incremented (Node ID=N+2) and the token resent. This process is repeated until a node
responds. At that time the token is released to the responding node and the address of the responding
node is noted as the logical neighbor of the originating node. This process is repeated by all nodes until
each node learns its logical neighbor. This eliminates wasting time in sending datagrams to absent
addresses once the network has been re-established.
When a node leaves the network the reconfiguration process is slightly different. When a node releases
the token to its logical neighbor, it expects its logical neighbor will respond within the respond timeout
window (78 μs) either a token pass or the start of a transmission sequence. If no response within the
response time out window, it assumes that its neighbor has left the network and immediately begins a
search for a new logical neighbor by incrementing the node address of its logical neighbor and initiating a
token pass. Network activity is again monitored and the increment process and resending of the token
continues until a new logical neighbor is found. Once found the network returns to the normal logical ring
routine of passing token to logical neighbors.
These reconfiguration sequences of the network are automatic and seamless without software intervention
required.
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2.4 CircLink Protocol Enhancement
Since the communication of ARCNET is controlled by a token, a token loss and the corresponding
reconfiguration significantly reduce the throughput of the network. In order to maintain the throughput,
modification of the ARCNET protocol is required to realize even higher real-time performance.
2.4.1 Reducing Token Loss
The primary source of token loss is caused by the burst signal. The burst signal is part of the sequence for
new nodes joining the network as described in section 2.3. In the CircLink, however, any new nodes do not
join because all nodes join to the network at the system start-up. In exceptional cases, the node leaves the
network due to token loss and a burst signal sent to r re-join the network. In order to avoid this burst signal,
the ARCNET protocol has been modified to specify node IDs as consecutive numbers starting from 01.
When a node other than the node having the largest node ID (NID [4:0] and MAXID[4:0]) sends a token
with the starting address being the node ID +1, this avoids sending a burst because a token can be
received in the next polling, even if a node has accidentally dropped out from the network.
The token retry function has been added to CircLink such that the possibility of not receiving the response
from the logical neighbor is greatly reduced due to token corruption . . Since the node ID in the CircLink is
consecutive and the retry does not occur in normal conditions, the token retry function does not degrade
the total performance. This function can be set to ON or OFF using software settings. (The default is ON)
Another cause of the token loss is the corruption of ACK/NAK. In the ARCNET flow (refer to page 12 in the
ARCNET controller COM20020I datasheet), if the node receives other signals other than the anticipated
ACK/NAK response (such as noise or, data-deformed ACK/NAK and the like), this node returns to the
receive-wait state with a token being held by the node. The network considers this as a token loss because
the token disappears from the network. To avoid this problem, ARCNET protocol has been modified to
send a token even after the detection of ACK/NAK corruption This function against the ACK/NAK
deformation can be set to ON or OFF. (The default is ON.)
2.4.2 Reduction of Network Reconfiguration Time
To reduce the waiting duration of (255 - ID) x 146 μs* during the network reconfiguration time, CircLink
designates a the node with the maximum ID as the maximum node (MAX_NODE). The node designated to
the maximum node immediately starts sending a token. The destination number starts from 00. The token
sending to 00 is not received by any node but triggers the other nodes to enter into the receive state out of
the (255 - ID) x 146 μs* timer. In addition, the 255 of (255 - ID) x 146 μs* timer formula, derived from
ARCNET, the is modified to
(The maximum number of nodes –ID) x 146 μs depending on the maximum number of nodes, which is
specified by the MAXID [4:0] pin. This modification makes significant reduction of the time required for
network reconfiguration even in the absence of the node set as MAX_NODE.
NOTE: * 146 μs is the time under operation at 2.5 Mbps. The time is half at 5 Mbps..
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Peripheral Mode CircLink™ Controller
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Datasheet
2.4.3 Reduction of Reconfiguration Burst Signal Send Time.
Since the CircLink maximum packet size is smaller than for ARCNET, the reconfiguration burst signal is of
shorter duration, reducing the time required for network reconfiguration as listed in the table below:
CircLink
PS[1:0] MAX Packet Size Burst Signal Sending Time
00 256(253)Byte 1.63ms
01 128(125)Byte 1.07ms
10 64(61)Byte 0.79ms
11 32(29)Byte 0.65ms
RCNET
-- MAX Packet Size Burst Signal Sending Time
-- 512(508)Byte 2.75ms
() : Data Size
NOTE: Above “Burst Signal Sending Time” is the time for operation at 2.5 Mbps. The time is half at 5 Mbps.
2.5 RAM Page Expansion
The original ARCNET buffer RAM is divided into 256 or 512-byte per a page. This configuration has a
maximum of four pages available in 1 kByte increments, leaving the majority of the RAM unused when
small data packets are used The CircLink RAM addressing has been modified to significantly expand the
available RAM page numbers and to store pages corresponding to the node IDs on the network as listed in
the table below.
Table 2 - Number of Nodes and RAM Page Size
PAGE SIZE PS[1:0] NODE ID (MIN)
256 Byte 00 01h 03h 100h X ID
128 Byte 01 01h 07h 80h X ID
64 Byte 10 01h 0Fh 40h X ID
32 Byte 11 01h 1Fh 20h X ID
NOTE: *1 : Node ID = 00 is used only for the system development and is not available for users.
*1
NODE ID(MAX) PAGE ADDRESS
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.
Datasheet
2.5.1 RAM Access
The CPU accesses the packet buffer (RAM) through the COMR4 register. Prior to access, a read or write
and page number need to be specified using the COMR2 register, as well as the address specification in
the page using the COMR3 register. The accessing method varies depending on the bit width of data bus,
word mode, and swap mode.
(1) Data bus = 16bits (W16 pin=H)
COMR2 Register : RDDATA, AUTOINC, nWRAPAR, PAGE[4;0]
A/AD[5:0] = 04h - - - - - - - - RD
COMR3 Register : Address Within a page RAMADR[7:0]
A/AD[5:0] = 06h - - - - - - - - 7 6 5 4 3 2 1 X
COM4 Register : Packet Data RAMDT[15:0]
A/AD[5:0] = 08h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(2-a) Data bus = 8bits , Word mode=OFF
A.I.
W.A43210
Bit0 is fixed in 0 in the inside.
(W16 pin=L, WDMD=0 in MODE REG.)
COMR2 Register : RDDATA AUTOINC nWRAPAR PAGE[4:0]
A/AD[5:0] = 04h (05h) * RD. A.I.
COMR3 Register : Address within a page RAMADR[7:0]
A/AD[5:0] = 06h (07h) * 76543210
COMR4 Register : Packet Data RAMDT[7:0]
A/AD[5:0] = 08h or 09h 76543210
( )*:nSWAP=L
W.A43210
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(2-b) Data bus = 8bits , Word mode=ON
(W16 pin=L, WDMD=1 in MODE REG.)
COMR2 Register : RDDATA AUTOINC nWRAPAR PAGE[4:0]
Peripheral Mode CircLink™ Controller
Datasheet
A/AD[5:0] = 04h (05h) * RD. A.I.
W.A43210
COMR3 Register : Address within a page RAMADR[7:0]
A/AD[5:0] = 06h (07h) * 7 6 5 4 3 2 1 X
Bit0 is fixed in 0 in the inside.
COMR4 Register : Packet Data RAMDT[15:0]
A/AD[5:0] = 08h (09h) * 7 6 543210
A/AD[5:0] = 09h (08h) * 151413121110 9 8
( )*:nSWAP=L
NOTE: In word mode = ON, to preserve the upper and lower bytes of word data as in the identical packet, COMR4
must be accessed in order of 08h first and 09h second. This restriction applies to both read and write.
Moreover, it is impossible to independently access CP (address = 02h) in RAM independently To access
the CP, a dummy cycle is necessary. Refer to section 2.5.3 - Packet Data Structure for detail.
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