Able to Connect Various Transceivers Directly
Device Includes TX/RX Timing Circuit for 5 Port
Hub and Direction Control Circuit, Jitter Correct
Circuit and Noise Cancel Circuit
Easy to Design 8 or 12 Port Hub
GENERAL DESCRIPTION
When configuring a network, the maximum number of nodes and the maximum cable length are limited by the electric
capacity of the transceiver. In this case, the network is expanded by an equipment called a “HUB” or “repeater”. It
maybe necessary to have a converter between coax, T/P and the fiber cable. It is easy to design a HUB or a repeater
because the TMC2005 has various features for expanding such network.
It can connect with HYC9088, RS485 transceiver, HYC5000/4000/2000 and TTL interface for optical module. It can
connect with three different transceivers at the same time and convert the media of each. (The data rate cannot be
converted. It is necessary to operate all nodes in the same network at the same data rate). The Hubs can be
expanded by connecting two or more TMC2005 chips. By setting one of 5 ports to open-drain output, the Hub can be
expanded to either 12 or 16 ports.
ORDERING INFORMATION
Order Number(s):
TMC2005-JT for 64 pin, TQFP Lead-Free RoHS Compliant Package
Can Connect with HYC9088 in Normal Mode
Can Connect with RS485 Transceiver,
HYC5000/4000/2000, Opt Module and TTL
Interface in Backplane Mode
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
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OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY
DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR
REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC
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HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES.
GENERAL DESCRIPTION.......................................................................................................................................1
OTHER SIGNALS ........................................................................................................................................................9
DIRECTION DETERMINATION...................................................................................................................................10
DIRECTION RELEASE ...............................................................................................................................................10
PORT GROUP...........................................................................................................................................................20
VARIOUS SETUP.......................................................................................................................................................20
EXAMPLE FOR OPERATION MODE SETUP TO EACH PORT........................................................................................20
NOTE FOR UNUSED PORT .........................................................................................................................................20
EXAMPLE FOR POWER-ON RESET CIRCUIT..............................................................................................................20
CONNECTING THE TMC2005 WITH INTERNAL PLL...................................................................................21
METHOD TO CONNECT ACRYSTAL CLOCK.............................................................................................................22
be open for normal operation.) Pull-up
Port EXT. Polar assignment for EXTRX
input (0:active Hi, 1:active Low) Pull-up
Port EXT. Polar assignment of EXTTX
output (0:active Low, 1:active Hi) Pull-up
Port EXT. RX-Data input from media
transceiver. Pull-up
Port EXT. Output mode assignment of
EXTTX (0:pulse output, 1:Tx control
output) Pull-up
Test Pin for PLL.. It should connected to
VDD (Set to high)
Connection pin to loop filter for internal
PLL.
Port EXT. Open-drain mode (0:opendrain output, 1:normal output) Pull-up
50 SA INPUT
51 TXENA0 OUTPUT Port A-0 Tx output to media transceiver.
52 LA INPUT
53 RXINA1 INPUT
54 MA INPUT
55 TXENA1 OUTPUT Port A-1 Tx output to media transceiver.
56 VDD6 Power Supply
57 NC Reserved. It should be open.
58 VSS8 Ground
59 RXINB0 INPUT
60 SB INPUT
61 TXENB0 OUTPUT Port B-0 Tx output to media transceiver.
62 LB INPUT
63 RXINB1 INPUT
64 MB INPUT
Port A-0 Rx-data input from media
transceiver. Pull-up
Port A. Polar assignment for RXINA0/A1
output (0:active Hi, 1:active Low) Pull-up
Port A. Polar assignment for TXENA0/A1
output (0:active Low, 1:active Hi) Pull-up
Port A-1 Rx-data input from media
transceiver. Pull-up
Port A. Mode assignment for
TXENA0/A1 (0:pulse output, 1:Tx control
output) Pull-up
Port B-0 Rx-data input from media
transceiver. Pull-up
Port B. Polar assignment for RXINA0/A1
input (0:active Hi, 1:Active Low) Pull-up
Port B. Polar assignment for TXENA0/A1
output (0:active Low, 1:active Hi) Pull-up
Port B-1 Rx-data input from media
transceiver. Pull-up
Port B. Mode assignment for
TXENA0/A1 (0:pulse output, 1:TX control
output) Pull-up
Note: Pull-up: Input with a pull-up resistor 70KΩ ± 30%
TX/RX Interface
FEATURE NAME INPUT/OUTPUT DESCRIPTION
RX Port RXINA [0:1]
RXINB [0:1]
EXTRX
RX Port Polar
Assignment
TX Port TX Control TXENA [0:1]
TX Port TX Data
Output
TX Port nP1BAK OUTPUT TX pulse data into RS485 driver
SMSC TMC2005-JT Page 7 Revision 1.1 (07-24-07)
SA, SB, SE INPUT Setup the polarity of RXINA [0:1],
TXENB [0:1]
EXTTX
nPULSE [1:2] OUTPUT TX pulse data into HYC9068S-
INPUT Setup the polarity by SA, SB, SE.
RXINB [0:1], EXTTX.
0 : active H
1: active L
OUTPUT TX data pulse (Mx=0) or TX
enable signal (Mx=1).
Setup TX mode by MA, MB, ME.
Setup the polarity by LA, LB, LE
SK/9088S-SK when ARCNET
chip is at normal mode.
The pulse is always active Low.
or HYC2485S/2488S when
ARCNET chip is at backplane
DATASHEET
ARCNET 5 Port HUB Controller
Datasheet
FEATURE NAME INPUT/OUTPUT DESCRIPTION
mode.
The pulse is always active Low.
TX Port Polarity
Setup
TX Port Mode Setup MA, MB, ME INPUT Setup the mode of TXENA [0:1],
Operating Mode Setup
FEATURE NAME
Data rate
CKM [0:2] INPUT
setup
Noise cut
mode
nMBA
nMBB
nMBE
Big jitter
mode
nBJA
nBJB
nBJE
Open drain
nEXTOD INPUT Setup a the use of EXTTX port.
mode
PLL
FEATURE NAME
LP OUTPUT
RO OUTPUT VCO output
AGS INPUT Analog sense input.
Revision 1.1 (07-24-07) Page 8 SMSC TMC2005-JT
LA, LB, LE INPUT Setup the polarity of TXENA
[0:1], TXENB [0:1], EXTTX.
0 : active L
1: active H
TXENB [0:1], EXTTX.
0: Output TX pulse. (It is
equivalent to nTXEN “OR”
nP1BAK)
1: Output TX enable
0: Set EXTTX as open drain output and use as Ext.
1: Set EXTTX as normal output and use as 5
DESCRIPTION
th
port.
Using PLL: Connect to an external condenser
“C1” for loop filter.
Using no PLL: must be open.
Using PLL: Connect to an external resistor “R0” for
loop filter.
Using no PLL: must be open.
Using PLL: Connect to loop filter.
Using no PLL: Connect to ground.
DATASHEET
ARCNET 5 Port HUB Controller
Datasheet
FEATURE NAME
nPLLTST INPUT Test pin for PLL.
AVDD Analog power supply
AVSS Analog ground
INPUT/
OUTPUT
DESCRIPTION
Must always connect to VDD.
Using PLL: Analog power supply. There are some
limits on PCB pattern.
Using no PLL: Power supply (+5V) same as VDD1~6.
Using PLL: Analog ground. There are some limits on
PCB pattern.
Using no PLL: Use a ground same as VSS1~8.
Other Signals
FEATURES
CRYSTAL
INTERFACE
CRYSTAL
INTERFACE
SYSTEM RESET
INTERFACE
TEST PIN CKO OUTPUT Output internal clock of TMC2005.
TEST PIN nCKOEN INPUT Output control of CKO.
TEST PIN RXFLT INPUT It must be open
TEST PIN NC [1:2] It must be open
POWER SUPPLY VDD [1:6] Power supply (+5V)
GROUND VSS [1:8] Ground
NAME
XTLI INPUT Connect a 20MHz crystal.
XTLO OUTPUT Connect a 20MHz crystal.
nRST INPUT Reset for initializing TMC2005. (active
INPUT/
OUTPUT
DESCRIPTION
When supplying an external clock,
input the clock to this pin.
When supplying an external clock, it
must be open.
Low)
0: Output internal clock on CKO.
1: Always output Low level on CKO.
Set “1” Normally.
SMSC TMC2005-JT Page 9 Revision 1.1 (07-24-07)
DATASHEET
ARCNET 5 Port HUB Controller
Datasheet
OPERATIONAL DESCRIPTION
Direction Determination
All TX ports are set to disable mode in the initial state. When a signal is received from any RX ports, the circuit holds
the port on receiving mode (disable TX) and changes the other ports to sending mode (disable RX). One port stays in
RX and the rest change into TX after all. The circuit initializes the internal DPLL on the timing of received RX pulse,
and the RX buffer circuit stores the RX data and filters its jitter. TX controlling circuit regenerates the stored RX pulse
on nPULSE1, nPULSE2 and nP1BAK. The nPULSE1 and nPULSE2 are pulse output pins for transceivers
(HYC9088A) of ARCNET normal mode. The nP1BAK is a pulse output pin for transceiver (HYC5000/4000/2000 and
RS485 driver) of ARCNET back plane mode. When using optical transceiver, instead of these signals, TXENA [0:1],
TXENB [0:1], EXTTX (MA, MB, ME = 0) must be used as TX data inputs of the optical transceiver.
Direction Release
On ARCNET protocol, each TX message starts with 6-bits of “1” ALERT and each data byte is lead by three bits (1, 1,
0) preamble. To control the HUBs direction, the circuit monitors this bit pattern and holds the state. If the end of the bit
pattern comes, all TX ports return receiving mode (disable TX) again. The interval timer detects the end of the bit
pattern. During data is on line, silent period is less than 4 uS* because at least one bit “1” among 10-bits is received
while receiving the data. The minimum silent interval from the end of received data to the alert of the next data (the
minimum time of changing the direction) is the chip turn around time (12.6 uS*) of ARCNET controller. The interval
timer to detect the data end is set to 5.6uS by adding some margin to the above interval for neglecting the reflection
on a cable.
[Note] Numbers marked * are at 2.5Mbps operation.
Jitter Filter
To build a network with transceivers that introduce big jitter like ones for optical fiber, the old HUB that has direction
control only may cause a transmission error because jitters on each HUB are added when several HUBs were
connected in serial. The TMC2005 fixes that problem with jitter filtering and wave shaping through the following three
steps.
1) Input Sampling
The TMC2005 samples a data on a network by eight times clock of the network data.
2) Jitter Filtering (DPLL)
The TMC2005 filters the jitter (± 100nS at 2.5Mbps) of network data sampled by 8X clock through the internal digital
PLL and stores the data into the buffer.
3) Wave Shaping Output
The TMC2005 re-synchronizes and regenerates the network data at the same clock as the data rate.
The capability of the jitter filtering is shown below.
DATA RATE CAPABILITY OF JITTER FILTERING
10Mbps ± 25nS
5Mbps ± 50nS
2.5Mbps ± 100nS
1.25Mbps ± 200nS
625Kbps ± 400nS
312.5Kbps ± 800nS
156.25Kbps ± 1.6uS
Revision 1.1 (07-24-07) Page 10 SMSC TMC2005-JT
DATASHEET
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