SMSC LPC47N217N User Manual

LPC47N217N

64-Pin Super I/O with
LPC Interface

PRODUCT FEATURES

 3.3 Volt Operation (5V tolerant)
 Programmable Wakeup Event Interface (IO_PME#

Pin)

 SMI Support (IO_SMI# Pin)
 GPIOs (14)
 Two IRQ Input Pins
 XNOR Chain
 PC2001
 ACPI 2.0 Compliant
 64-pin TQFP Package
 Intelligent Auto Power Management
 Serial Port

— One Full Function Serial Port
— High Speed 16C550A Compatible UART with

Send/Receive 16-Byte FIFO
— Supports 230k and 460k Baud
— Programmable Baud Rate Generator
— Modem Control Circuitry
— Multiple Base I/O Address options and 15 IRQ Options

Data Brief

 Multi-Mode Parallel Port with ChiProtect™

— Standard Mode IBM PC/XT®, PC/AT®, and PS/2™

Compatible Bidirectional Parallel Port

— Enhanced Parallel Port (EPP) Compatible - EPP 1.7

and EPP 1.9 (IEEE 1284 Compliant)

— IEEE 1284 Compliant Enhanced Capabilities Port

(ECP)

— ChiProtect Circuitry for Protection Against Damage Due

to Printer Power-On

— 192 Base I/O Address, 15 IRQ and 3 DMA Options

 LPC Bus Host Interface

— Multiplexed Command, Address and Data Bus
— 8-Bit I/O Transfers
—8-Bit DMA Transfers
— 16-Bit Address Qualification
— Serial IRQ Interface Compatible with Serialized IRQ

Support for PCI Systems
— PCI CLKRUN# Support
— Power Management Event (IO_PME#) Interface Pin

SMSC LPC47N217N 64TQFP PRODUCT PREVIEW Revision 0.2 (09-25-08)

64-Pin Super I/O with LPC Interface

ORDER NUMBER(S):

LPC47N217N-JV FOR 64 PIN, TQFP LEAD-FREE ROHS COMPLIANT PACKAGE

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]

Copyright © 2008 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
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Revision 0.2 (09-25-08) 2 SMSC LPC47N217N 64TQFP

PRODUCT PREVIEW

64-Pin Super I/O with LPC Interface

General Description

The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The
LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or
better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes
14 GPIO pins.

The LPC47N217N incorporates a 16C550A compatible UART and one Multi-Mode parallel port with
ChiProtect™ circuitry plus EPP and ECP support. The LPC47N217N is easy to use and offers lower
system cost and reduced board area.

The LPC47N217N offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.

The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP.
The parallel port ChiProtect™ circuitry prevents damage caused by an attached powered printer when
the LPC47N217N is not powered.

The LPC47N217N features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the parallel port and UART.

The LPC47N217N supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides
the recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the LPC47N217N may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.

SMSC LPC47N217N 64TQFP 3 Revision 0.2 (09-25-08)

PRODUCT PREVIEW

Block Diagram

TXD1, nRTS1, nDTR1

SER_IRQ

PCI_CLK

Vcc

Vss

IO_PME#

Denotes Multifunction Pins

SERIAL

IRQ

LPC BUS

INTERFACE

V

TR

CLOCK

GEN

CLOCKI

SMI PME WDT

*

16C550

COMPATIBLE

SERIAL
PORT 1

nCTS1, RXD1,
nDSR1, nDCD1, nRI1

CONFIGURATION

REGISTERS

GENERAL
PURPOSE

I/O

GP10, GP11,
GP12*, GP13*,
GP14*,
GP23,
GP4[0:7]

MULTI-MODE

PARALLEL

PORT

PD[0:7],

BUSY, SLCT,
PE, nERROR, nACK

nSLCTIN, nALF
nINIT, nSTROBE

CONTROL, ADDRESS, DATA

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ#

LPCPD#

PCI_RESET#

ACPI

BLOCK

IO_SMI#*

CLKRUN#

IRQIN1*, IRQIN2*

64-Pin Super I/O with LPC Interface

Figure 1 LPC47N217N Block Diagram

Revision 0.2 (09-25-08) 4 SMSC LPC47N217N 64TQFP

PRODUCT PREVIEW

64-Pin Super I/O with LPC Interface

Package Outline

Figure 2 64 Pin TQFP Package Outline, 7X7X1.4 Body, 2 MM Footprint

Table 1 64 Pin TQFP Package Parameters

MIN NOMINAL MAX REMARKS

A ~ ~ 1.60 Overall Package Height
A1 0.05 ~ 0.15 Standoff
A2 1.35 1.40 1.45 Body Thickness

D 8.80 9.00 9.20 X Span

D1 6.80 7.00 7.20 X body Size

E 8.80 9.00 9.20 Y Span
E1 6.80 7.00 7.20 Y body Size

H 0.09 ~ 0.20 Lead Frame Thickness

L 0.45 0.60 0.75 Lead Foot Length

L1 ~ 1.00 REF. ~ Lead Length

e 0.40 Basic Lead Pitch

0

W 0.13 0.18 0.23 Lead Width

ccc ~ ~ 0.08 Coplanarity

Notes:

1. Controlling Unit: millimeter.

2. Tolerance on the true position of the leads is ± 0.035 mm maximum.

3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm per side. D1 and E1 dimensions determined at datum plane H.

4. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.

5. 5 Details of pin 1 identifier are optional but must be located within the zone indicated.

o

~7oLead Foot Angle

SMSC LPC47N217N 64TQFP 5 Revision 0.2 (09-25-08)

PRODUCT PREVIEW