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Revision 0.3 (01-23-09)2SMSC LPC47N217N 56QFN
PRODUCT PREVIEW
56-Pin Super I/O with LPC Interface
General Description
The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The
LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or
better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes
13 GPIO pins.
The LPC47N217N incorporates a 16C550A compatible UART and one Multi-Mode parallel port with
ChiProtect™ circuitry plus EPP and ECP support. The LPC47N217N is easy to use and offers lower
system cost and reduced board area.
The LPC47N217N offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.
The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The
parallel port ChiProtect™ circuitry prevents damage caused by an attached powered printer when the
LPC47N217N is not powered.
The LPC47N217N features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the parallel port and UART.
The LPC47N217N supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides
the recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the LPC47N217N may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.
SMSC LPC47N217N 56QFN3Revision 0.3 (01-23-09)
PRODUCT PREVIEW
Block Diagram
TXD1, nRTS1, nDTR1
SER_IRQ
PCI_CLK
Vcc
GND
IO_PME#
Denotes Multifunction Pins
SERIAL
IRQ
LPC BUS
INTERFACE
V
TR
CLOCK
GEN
CLOCKI
SMI PME WDT
*
16C550
COMPATIBLE
SERIAL
PORT 1
nCTS1, RXD1,
nDSR1, nDCD1, nRI1
CONFIGURATION
REGISTERS
GENERAL
PURPOSE
I/O
GP10, GP11,
GP12*, GP13*,
GP14*,
GP23,
GP4[1:7]
MULTI-MODE
PARALLEL
PORT
PD[0:7],
BUSY, SLCT,
PE, nERROR, nACK
nSLCTIN, nALF
nINIT, nSTROBE
CONTROL, ADDRESS, DATA
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
LPCPD#
PCI_RESET#
ACPI
BLOCK
IO_SMI#*
CLKRUN#
IRQIN1*, IRQIN2*
56-Pin Super I/O with LPC Interface
Figure 1 LPC47N217N Block Diagram
Revision 0.3 (01-23-09)4SMSC LPC47N217N 56QFN
PRODUCT PREVIEW
56-Pin Super I/O with LPC Interface
AINITI AL RELEASE2/07/ 04S.K.I LIEV
DECIMAL
X.X
X.XX
X.XXX
MATERIAL
FINISH
STD COMPLIANCE
THIRD ANGLE PROJECTION
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
APPROVED
ANGULAR
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DIM A ND TO L PER ASM E Y14.5M - 1994
DRAWN
CHECKED
NAME
SCALE
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
DWG NUMBER
TITLE
DATE
SHEET
REV
REVISION HISTORY
DESCRIPTIONREVISIONRELEASED BYDATE
S.K.ILIEV
S.K.ILIEV
S.K.ILIEV
±1°
-
-
±0.025
±0.05
±0.1
2/07/041:1
2/06/04
2/07/04C
JEDEC: MO-2201 OF 1
56 TERMINAL QFN , 8x8mm BODY, 0. 5mm PITCH
PACKAGE OUTLINE
MO-56-QFN-8x8
SIDE VIEW
3-D VIEWS
TOP VIEW
3
2
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPO SED PAD IS ± 0.05mm AT MAXIMUM MATERIAL
CON DITION. DI MENSIONS "b" APP LIES TO PLATED T ERMINALS AND IT IS MEASURED BETWE EN 0.15 AND
0.30 m m FROM THE TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
E2EE1
D
D1
TERMINAL #1
IDENTIFIE R AREA
(D1/2 X E1/2)
56X b
56X L
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
D2
e
EXPOSED PAD
3
A1
A2
A
4X 45°X0.6 MAX (OPTIONAL)
2
D2 / E2 VARIATIONS
CATALOG PART
BREMOVE "PRELIMINARY" NOTE10/7/04S.K.ILIEV
C
L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE