LPC47M172
Advanced I/O Controller
with Motherboard GLUE
Logic
Datasheet
Product Features
3.3V Operation (5V tolerant)
LPC Interface
− Multiplexed Command, Address and Data Bus
− Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
ACPI 1.0b/2.0 Compliant
Programmable Wake-up Event Interface
PC99a/PC2001 Compliant
General Purpose Input/Output Pins (13)
Fan Tachometer Inputs (2)
Green and Yellow Power LEDs
ISA Plug-and-Play Compatible Register Set
Motherboard GLUE Logic
− 5V Reference Generation
− 5V Standby Reference Generation
− IDE Reset/Buffered PCI Reset Outputs
− Power OK Signal Generation
− Power Sequencing
− Power Supply Turn On Circuitry
− Resume Reset Signal Generation
− Hard Drive Front Panel LED
− Voltage Translation for DDC to VGA Monitor
− SMBus Isolation Circuitry
− CNR Dynamic Down Control
2.88MB Super I/O Floppy Disk Controller
− Licensed CMOS 765B Floppy Disk Controller
− Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
− Supports One Floppy Drive
− Configurable Open Drain/Push-Pull Output Drivers
− Supports Vertical Recording Format
16-Byte Data FIFO
− 100% IBM Compatibility
− Detects All Overrun and Underrun Conditions
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
− DMA Enable Logic
− Data Rate and Drive Control Registers
480 Address, Up to Eight IRQ and Three DMA
Options
Enhanced Digital Data Separator
− 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
− Programmable Precompensation Modes
Keyboard Controller
− 8042 Software Compatible
− 8 Bit Microcomputer
− 2k Bytes of Program ROM
− 256 Bytes of Data RAM
− Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
− Asynchronous Access to Two Data Registers and
One Status Register
− Supports Interrupt and Polling Access
− 8 Bit Counter Timer
− Port 92 Support
− Fast Gate A20 and KRESET Outputs
Serial Ports
− Two Full Function Serial Ports
− High Speed 16C550A Compatible UART with
Send/Receive 16-Byte FIFOs
− Supports 230k and 460k Baud
− Programmable Baud Rate Generator
− Modem Control Circuitry
− 480 Address and 15 IRQ Options
Infrared Port
− Multiprotocol Infrared Interface
− 32-Byte Data FIFO
− IrDA 1.0 Compliant
− SHARP ASK IR
− HP-SIR
− 480 Address, Up to 15 IRQ and Three DMA Options
Multi-Mode Parallel Port with ChiProtect
− Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bi-directional Parallel Port
− Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
− IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
− ChiProtect Circuitry for Protection
− 960 Address, Up to 15 IRQ and Three DMA Options
Interrupt Generating Registers
− Registers Generate IRQ1 – IRQ15 on Serial IRQ
Interface.
XOR-Chain Board Test
128 Pin MQFP Package, 3.2 mm Footprint
SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
ORDERING INFORMATION
Order Number(s):
LPC47M172-NR for 128 MQFP (3.2mm footprint) package
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
80 Arkay Drive
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 2 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
LPC47M172 Datasheet Revision History
REVISION LEVEL
AND DATE
Rev. 02-27-04
Rev. 02-27-04 Ordering Information Added.
Rev. 02-27-04
Rev. 02-26-04 Chapter 1 - General Description, page 12
Rev. 02-23-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04 Chapter 2 - Pin Layout, page 13 Note for pin 117
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Table 12.2 - S3-S5 Standby Current, page
201
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Chapter 12 - Electrical Characteristics,
page 196
Section 3.1 - Buffer Name Descriptions,
page 23
Table 3.1 - LPC47M172 Pin Description,
page 15
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Table 7.31 - Voltage Translation DDC Pins,
page 137
Figure 7.10 - VGA DDC Voltage
Translation Circuit, page 139
Table 7.34 - SMBus Isolation Pins, page
139
Figure 7.11 - SMBUS Isolation Circuit,
page 140
Table 12.1 - Operational DC
Characteristics, page 196
Table 7.7 - Programming for Configuration
Register B (Bits 5:3), page 106; Table 7.8 Programming for Configuration Register B
(Bits 2:0), page 106
Table 11.2 - LPC47M172 Configuration
Register Summary, page 178
Table 11.3 - Chip Level Registers, page
180
Table 3.1 - LPC47M172 Pin Description,
page 15
Chapter 8 Power Control Runtime
Registers, page 151
Chapter 9 GPIO Runtime Registers, page
158
Chapter 10 Runtime Register Block
Runtime Registers, page 162
Table 11.3 - Chip Level Registers, page
180
SECTION/FIGURE/ENTRY CORRECTION
Added note above table.
Revised heading to include “standard
SMSC” and “non-standard SMSC” register
sets.
Revised General Description adding AMITM
BIOS to keyboard interface.
Lead Temperature Range, lead and leadfree; reference to spec name J-STD-020B.
Added I0_SW.
Buffer names revised for pins 87 – 90,
113 – 116.
Note 8 under table revised.
Added table.
Replaced buffer IOD8 with IO_SW.
Revised figure.
Replaced buffer IOD8 with IO_SW.
First paragraph under table revised.
Revised figure.
Added IO_SW buffer and description;
updated parameters for Icc and Itr.
Titles added to tables.
Value of TEST 7 reg for LD_NUM=1
changed to 0x01.
Definition of TEST 7 value:
Default = 0x00 (when pin 117 is NC), 0x01
(when pin 117 is connected to VTR) on
VCC POR, VTR POR, and HARD RESET
No Connect Pin 117,
Pin 117 described in Note 11.
Table added.
Table added.
Added paragraph describing runtime
registers tables.
Register 0x29
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 3 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
LPC47M172 Datasheet Revision History .................................................................................................3
Chapter 1 General Description.............................................................................................................. 12
Chapter 2 Pin Layout ............................................................................................................................13
Chapter 3 Description of Pin Functions ................................................................................................15
3.1 Buffer Name Descriptions ..........................................................................................................................23
3.2 Pins With Internal Resistors .......................................................................................................................24
3.3 Pins That Require External Resistors.........................................................................................................24
3.4 Default State of Pins...................................................................................................................................25
Chapter 4 Block Diagram ......................................................................................................................29
Chapter 5 Power and Clock Functionality............................................................................................. 30
5.1 3 Volt Operation / 5 Volt Tolerance ............................................................................................................30
5.2 VCC Power ................................................................................................................................................30
5.3 VTR Power.................................................................................................................................................30
5.3.1 Trickle Power Functionality .................................................................................................................31
5.4 V5P0_STBY Power....................................................................................................................................31
5.5 32.768 kHz Trickle Clock Input...................................................................................................................31
5.5.1 Indication of 32KHZ Clock...................................................................................................................31
5.6 14.318 MHz Clock Input .............................................................................................................................32
5.7 Internal PWRGOOD...................................................................................................................................32
5.8 Maximum Current Values...........................................................................................................................32
5.9 Power Management Events (PME/SCI) .....................................................................................................32
Chapter 6 Functional Description..........................................................................................................33
6.1 Super I/O Registers....................................................................................................................................33
6.2 Host Processor Interface (LPC) .................................................................................................................34
6.3 LPC Interface .............................................................................................................................................34
6.3.1 LPC Interface Signal Definition ...........................................................................................................34
6.3.2 LPC Cycles .........................................................................................................................................34
6.3.3 Field Definitions...................................................................................................................................34
6.3.4 NLFRAME Usage................................................................................................................................35
6.3.5 I/O Read and Write Cycles..................................................................................................................35
6.3.6 DMA Read and Write Cycles ..............................................................................................................35
6.3.7 DMA Protocol ......................................................................................................................................35
6.3.8 Power Management ............................................................................................................................36
6.3.9 SYNC Protocol ....................................................................................................................................36
6.3.10 I/O and DMA START Fields.............................................................................................................37
6.3.11 LPC Transfers .................................................................................................................................37
6.4 Floppy Disk Controller ................................................................................................................................38
6.4.1 FDC Configuration Registers ..............................................................................................................38
6.4.2 FDC Internal Registers........................................................................................................................38
6.4.3 Status Register A (SRA) .....................................................................................................................39
6.4.4 Status Register B (SRB) .....................................................................................................................40
6.4.5 Digital Output Register (DOR).............................................................................................................42
6.4.6 Tape Drive Register (TDR) .................................................................................................................43
6.4.7 Data Rate Select Register (DSR)........................................................................................................44
6.4.8 Main Status Register...........................................................................................................................46
6.4.9 Data Register (FIFO)...........................................................................................................................47
6.4.10 Digital Input Register (DIR)..............................................................................................................48
6.4.11 Configuration Control Register (CCR) .............................................................................................49
6.4.12 Status Register Encoding ................................................................................................................50
6.5 Modes of Operation....................................................................................................................................52
6.5.1 PC/AT Mode .......................................................................................................................................52
6.5.2 PS/2 Mode ..........................................................................................................................................52
6.5.3 Model 30 Mode ...................................................................................................................................52
6.6 DMA Transfers ...........................................................................................................................................52
6.7 Controller Phases.......................................................................................................................................53
6.7.1 Command Phase ................................................................................................................................53
6.7.2 Execution Phase .................................................................................................................................53
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 4 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.8 Data Transfer Termination .........................................................................................................................54
6.9 Result Phase..............................................................................................................................................54
6.10 Command Set/Descriptions....................................................................................................................54
6.10.1 Instruction Set..................................................................................................................................57
6.11 Data Transfer Commands ......................................................................................................................63
6.11.1 Read Data .......................................................................................................................................63
6.12 Read Deleted Data .................................................................................................................................64
6.13 Read A Track..........................................................................................................................................65
6.14 Write Data...............................................................................................................................................66
6.15 Write Deleted Data .................................................................................................................................66
6.16 Verify ......................................................................................................................................................66
6.17 Format A Track.......................................................................................................................................67
6.18 Control Commands.................................................................................................................................69
6.18.1 Read ID ...........................................................................................................................................69
6.18.2 Recalibrate ......................................................................................................................................69
6.18.3 Seek ................................................................................................................................................69
6.19 Sense Interrupt Status............................................................................................................................70
6.20 Sense Drive Status.................................................................................................................................71
6.21 Specify....................................................................................................................................................71
6.22 Configure................................................................................................................................................71
6.22.1 Configure Default Values.................................................................................................................71
6.23 Version ...................................................................................................................................................72
6.24 Relative Seek .........................................................................................................................................72
6.25 Perpendicular Mode................................................................................................................................73
6.26 Lock........................................................................................................................................................74
6.27 Enhanced DUMPREG ............................................................................................................................75
6.27.1 Compatibility....................................................................................................................................75
6.28 Serial Port (UART)..................................................................................................................................75
6.28.1 Register Description ........................................................................................................................75
6.28.2 Receive Buffer Register (RB) ..........................................................................................................76
6.28.3 Transmit Buffer Register (TB)..........................................................................................................76
6.28.4 Interrupt Enable Register (IER) .......................................................................................................76
6.28.5 FIFO Control Register (FCR)...........................................................................................................77
6.28.6 Interrupt Identification Register (IIR)................................................................................................77
6.28.7 Line Control Register (LCR) ............................................................................................................79
6.28.8 Modem Control Register (MCR) ......................................................................................................80
6.28.9 Line Status Register (LSR)..............................................................................................................81
6.28.10 Modem Status Register (MSR) ........................................................................................................82
6.28.11 Scratchpad Register (SCR) .............................................................................................................83
6.29 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL) .................................................83
6.29.1 Effect Of The Reset on Register File ...............................................................................................84
6.29.2 FIFO Interrupt Mode Operation .......................................................................................................84
6.29.3 FIFO Polled Mode Operation...........................................................................................................85
Chapter 7 Notes On Serial Port Operation ...........................................................................................89
7.1 FIFO Mode Operation: ...............................................................................................................................89
7.1.1 General ...............................................................................................................................................89
7.1.2 TX and RX FIFO Operation.................................................................................................................89
7.2 Infrared Interface........................................................................................................................................90
7.3 Parallel Port................................................................................................................................................90
7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................92
7.4.1 Data Port.............................................................................................................................................92
7.4.2 Status Port ..........................................................................................................................................92
7.4.3 Control Port.........................................................................................................................................93
7.4.4 EPP Address Port ...............................................................................................................................94
7.4.5 EPP Data Port 0..................................................................................................................................94
7.4.6 EPP Data Port 1..................................................................................................................................94
7.4.7 EPP Data Port 2..................................................................................................................................94
7.4.8 EPP Data Port 3..................................................................................................................................95
7.5 EPP 1.9 Operation .....................................................................................................................................95
7.5.1 Software Constraints...........................................................................................................................95
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 5 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.6 EPP 1.9 Write.............................................................................................................................................95
7.7 EPP 1.9 Read ............................................................................................................................................96
7.8 EPP 1.7 Operation .....................................................................................................................................96
7.8.1 Software Constraints...........................................................................................................................96
7.9 EPP 1.7 Write.............................................................................................................................................97
7.10 EPP 1.7 Read.........................................................................................................................................97
7.10.1 Extended Capabilities Parallel Port .................................................................................................98
7.10.2 Vocabulary.......................................................................................................................................98
7.11 ECP Implementation Standard ...............................................................................................................99
7.11.1 Description.......................................................................................................................................99
7.12 Register Definitions...............................................................................................................................100
7.12.1 Data and ecpAFifo Port .................................................................................................................101
7.12.2 Device Status Register (dsr)..........................................................................................................102
7.12.3 Device Control Register (dcr) ........................................................................................................102
7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................103
7.12.5 ECPDFIFO (ECP Data FIFO)........................................................................................................103
7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................103
7.12.7 cnfgA (Configuration Register A) ...................................................................................................104
7.12.8 cnfgB (Configuration Register B) ...................................................................................................104
7.12.9 ecr (Extended Control Register) ....................................................................................................104
7.13 Operation..............................................................................................................................................107
7.13.1 Mode Switching/Software Control..................................................................................................107
7.14 ECP Operation .....................................................................................................................................107
7.15 Termination from ECP Mode ................................................................................................................108
7.16 Command/Data.....................................................................................................................................108
7.17 Data Compression................................................................................................................................108
7.18 Pin Definition ........................................................................................................................................108
7.19 LPC Connections..................................................................................................................................109
7.20 Interrupts ..............................................................................................................................................109
7.21 FIFO Operation.....................................................................................................................................109
7.21.1 DMA Transfers ..............................................................................................................................110
7.21.2 DMA Mode - Transfers from the FIFO to the Host......................................................................... 110
7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................110
7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................110
7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................111
7.22 Power Management..............................................................................................................................111
7.23 Serial IRQ.............................................................................................................................................111
7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................111
7.23.2 SER_IRQ Cycle Control ................................................................................................................112
7.23.3 SER_IRQ Data Frame...................................................................................................................113
7.23.4 Stop Cycle Control.........................................................................................................................113
7.23.5 Latency..........................................................................................................................................114
7.23.6 EOI/ISR Read Latency ..................................................................................................................114
7.23.7 AC/DC Specification Issue ............................................................................................................114
7.23.8 Reset and Initialization ..................................................................................................................114
7.24 Interrupt Generating Registers .............................................................................................................114
7.25 8042 Keyboard Controller Description..................................................................................................115
7.25.1 Keyboard Interface ........................................................................................................................115
7.25.2 Keyboard Data Write .....................................................................................................................116
7.25.3 Keyboard Data Read .....................................................................................................................116
7.25.4 Keyboard Command Write ............................................................................................................116
7.25.5 Keyboard Status Read ..................................................................................................................116
7.25.6 CPU-to-Host Communication ........................................................................................................116
7.25.7 Host-to-CPU Communication ........................................................................................................116
7.25.8 KIRQ..............................................................................................................................................116
7.25.9 MIRQ .............................................................................................................................................117
7.25.10 External Keyboard and Mouse Interface .......................................................................................117
7.25.11 Keyboard Power Management ......................................................................................................117
7.25.12 Soft Power Down Mode .................................................................................................................117
7.25.13 Hard Power Down Mode ...............................................................................................................117
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 6 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.25.14 Interrupts .......................................................................................................................................118
7.25.15 Memory Configurations .................................................................................................................118
7.25.16 Register Definitions .......................................................................................................................118
7.25.17 External Clock Signal ....................................................................................................................119
7.25.18 Default Reset Conditions ...............................................................................................................119
7.25.19 GateA20 and Keyboard Reset .......................................................................................................119
7.26 Port 92 Fast Gatea20 and Keyboard Reset..........................................................................................119
7.26.1 Port 92 Register.............................................................................................................................119
7.26.2 Keyboard and Mouse PME Generation .........................................................................................123
7.27 General Purpose I/O.............................................................................................................................124
7.27.1 GPIO Pins .....................................................................................................................................125
7.27.2 Description.....................................................................................................................................125
7.27.3 GPIO Control.................................................................................................................................126
7.27.4 GPIO Operation.............................................................................................................................127
7.27.5 GPIO PME Functionality................................................................................................................128
7.27.6 Either Edge Triggered Interrupts ...................................................................................................128
7.28 PME Support ........................................................................................................................................128
7.28.1 ‘Wake on Specific Key’ Option.......................................................................................................129
7.29 Fan Monitoring......................................................................................................................................130
7.29.1 Fan Tachometer Inputs .................................................................................................................131
7.29.2 Detection of a Stalled Fan .............................................................................................................131
7.30 Hard Drive and Power LED Logic.........................................................................................................132
7.30.1 Hard Drive Front Panel LED (Red) ................................................................................................132
7.30.2 Yellow and Green Power LED Pins ...............................................................................................133
7.31 Power Generation (5V).........................................................................................................................134
7.31.1 Reference Pins ..............................................................................................................................134
7.31.2 5V Main Reference Generation .....................................................................................................135
7.31.3 5V Standby Reference Generation................................................................................................135
7.31.4 Reference Timings ........................................................................................................................136
7.32 IDE Reset Output Pin ...........................................................................................................................136
7.33 PCI Reset Output Pins..........................................................................................................................136
7.34 Voltage Translation Circuit....................................................................................................................137
7.35 SMBus Isolation Circuitry......................................................................................................................139
7.36 PS_ON Logic........................................................................................................................................141
7.37 PWRGD_3V Logic................................................................................................................................141
7.38 SCK_BJT_GATE Output ......................................................................................................................143
7.39 Backfeed Cut and Latched Backfeed Cut Circuitry...............................................................................144
7.40 Resume Reset Logic ............................................................................................................................149
7.41 CNR Logic ............................................................................................................................................149
Chapter 8 Power Control Runtime Registers...................................................................................... 151
Chapter 9 GPIO Runtime Registers.................................................................................................... 158
Chapter 10 Runtime Register Block Runtime Registers ....................................................................... 162
Chapter 11 Configuration ......................................................................................................................173
11.1 System Elements..................................................................................................................................173
11.1.1 Primary Configuration Address Decoder .......................................................................................173
11.1.2 Entering the Configuration State....................................................................................................173
11.1.3 Exiting the Configuration State ......................................................................................................173
11.1.4 Configuration Sequence ................................................................................................................174
11.1.5 Enter Configuration Mode..............................................................................................................174
11.1.6 Configuration Mode .......................................................................................................................174
11.1.7 Exit Configuration Mode ................................................................................................................174
11.1.8 Programming Example ..................................................................................................................175
11.2 Chip Level (Global) Control/Configuration Registers[0x00-0x2F] .........................................................180
11.3 Logical Device Configuration/Control Registers [0x30-0xFF] ...............................................................183
11.4 Logical Device I/O Address ..................................................................................................................187
11.5 Logical Device Configuration Registers................................................................................................190
Chapter 12 Electrical Characteristics ....................................................................................................196
12.1 Maximum Guaranteed Ratings .............................................................................................................196
12.2 Operational DC Characteristics ............................................................................................................196
12.3 Standby Power Requirements ..............................................................................................................201
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 7 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
12.4 Capacitance Values for Pins.................................................................................................................202
Chapter 13 Timing Diagrams ................................................................................................................203
13.1 ECP Parallel Port Timing......................................................................................................................212
13.1.1 Parallel Port FIFO (Mode 101).......................................................................................................212
13.1.2 ECP Parallel Port Timing...............................................................................................................212
13.1.3 Forward-Idle ..................................................................................................................................212
13.1.4 Forward Data Transfer Phase .......................................................................................................212
13.1.5 Reverse-Idle Phase .......................................................................................................................212
13.1.6 Reverse Data Transfer Phase .......................................................................................................212
13.1.7 Output Drivers ...............................................................................................................................213
Chapter 14 Package Outline .................................................................................................................224
Chapter 15 Board Test Mode................................................................................................................225
Chapter 16 Reference Documents........................................................................................................ 227
List Of Figures
Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................13
Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................29
Figure 7.1 - NKBDRST Circuit....................................................................................................................................121
Figure 7.2 - Keyboard Latch.......................................................................................................................................122
Figure 7.3 - Mouse Latch ...........................................................................................................................................122
Figure 7.4 - GPIO Function Illustration.......................................................................................................................127
Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................131
Figure 7.6 - NHD_LED Circuit....................................................................................................................................133
Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................134
Figure 7.8 - REF5V Circuit .........................................................................................................................................135
Figure 7.9 - REF5V_STBY.........................................................................................................................................136
Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................139
Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................140
Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................142
Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................142
Figure 7.14 - NFPRST Timing....................................................................................................................................143
Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................144
Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................145
Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................146
Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................146
Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................147
Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................148
Figure 7.21 - CNR Circuit...........................................................................................................................................150
Figure 13.1 - Power-Up Timing ..................................................................................................................................204
Figure 13.2 - Input Clock Timing ................................................................................................................................205
Figure 13.3 - PCI Clock Timing ..................................................................................................................................205
Figure 13.4 - Reset Timing.........................................................................................................................................205
Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................206
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................206
Figure 13.7 - I/O Write................................................................................................................................................206
Figure 13.8 - I/O Read ...............................................................................................................................................207
Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................207
Figure 13.10 - DMA Write (First Byte) ........................................................................................................................207
Figure 13.11 - DMA Read (First Byte)........................................................................................................................207
Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................208
Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................209
Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................210
Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................211
Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................211
Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................213
Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................214
Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................215
Figure 13.20 - Setup and Hold Time ..........................................................................................................................216
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Datasheet
Figure 13.21 - Serial Port Data...................................................................................................................................216
Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................217
Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................218
Figure 13.24 - Power Led Output Timing ...................................................................................................................218
Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY ...............219
Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR ...............219
Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY...........220
Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR...........220
Figure 13.29 - Rise, Fall and Propagation Timings ....................................................................................................221
Figure 13.30 - Reseme Reset Sequence ...................................................................................................................223
Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................224
Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................225
List Of Tables
Table 3.1 - LPC47M172 Pin Description ......................................................................................................................15
Table 3.2 - Pins with Internal Resistors........................................................................................................................24
Table 3.3 - Pins that Require External Resistors..........................................................................................................24
Table 3.4 - Default State of Pins ..................................................................................................................................26
Table 6.1 - Super I/O Block Logical Device Number and Addresses ...........................................................................33
Table 6.2 - Status, Data and Control Registers............................................................................................................38
Table 6.3 - Internal 2 Drive Decode - Normal...............................................................................................................42
Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................43
Table 6.5 - Tape Select Bits .........................................................................................................................................43
Table 6.6 - Drive Type ID .............................................................................................................................................44
Table 6.7 - Precompensation Delays ...........................................................................................................................45
Table 6.8 - Data Rates .................................................................................................................................................45
Table 6.9 - DRVDEN Mapping .....................................................................................................................................46
Table 6.10 - Default Precompensation Delays .............................................................................................................46
Table 6.11 - FIFO Service Delay..................................................................................................................................47
Table 6.12 - Status Register 0 .....................................................................................................................................50
Table 6.13 - Status Register 1 .....................................................................................................................................50
Table 6.14 - Status Register 2 .....................................................................................................................................51
Table 6.15 - Status Register 3 .....................................................................................................................................51
Table 6.16 - Description of Command Symbols...........................................................................................................55
Table 6.17 - Instruction Set ..........................................................................................................................................57
Table 6.18 - Sector Sizes.............................................................................................................................................63
Table 6.19 - Effects of MT and N Bits ..........................................................................................................................64
Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................64
Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................65
Table 6.22 - Result Phase Table..................................................................................................................................65
Table 6.23 - Verify Command Result Phase Table ......................................................................................................67
Table 6.24 - Typical Values for Formatting ..................................................................................................................68
Table 6.25 - Interrupt Identification...............................................................................................................................70
Table 6.26 - Drive Control Delays (ms) ........................................................................................................................71
Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................74
Table 6.28 - Addressing the Serial Port .......................................................................................................................75
Table 6.29 - Interrupt Control Table .............................................................................................................................78
Table 6.30 - Baud Rates ..............................................................................................................................................85
Table 6.31 - Reset Function Table ...............................................................................................................................86
Table 32 - Register Summary for an Individual UART Channel ...................................................................................87
Table 7.1 - Parallel Port Connector ..............................................................................................................................92
Table 7.2 - EPP Pin Descriptions .................................................................................................................................97
Table 7.3 - ECP Pin Descriptions...............................................................................................................................100
Table 7.4 - ECP Register Definitions..........................................................................................................................101
Table 7.5 - Mode Descriptions ...................................................................................................................................101
Table 7.6 - Extended Control Register .......................................................................................................................106
Table 7.7 - Programming for Configuration Register B (Bits 5:3) ...............................................................................106
Table 7.8 - Programming for Configuration Register B (Bits 2:0) ...............................................................................106
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Datasheet
Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................108
Table 7.10 - I/O Address Map ....................................................................................................................................115
Table 7.11 - Host Interface Flags ...............................................................................................................................116
Table 7.12 - Status Register ......................................................................................................................................118
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................119
Table 7.14 - Keyboard Port 92 Register.....................................................................................................................120
Table 7.15 - nA20M Truth Table ................................................................................................................................121
Table 7.16 - GPIO Summary......................................................................................................................................125
Table 7.17 - General Purpose I/O Port Assignments .................................................................................................126
Table 7.18 - GPIO Configuration Summary ...............................................................................................................126
Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................127
Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................132
Table 7.21 - nHD_LED Truth Table............................................................................................................................132
Table 7.22 - LED Pins ................................................................................................................................................133
Table 7.23 - LED Truth Table.....................................................................................................................................133
Table 7.24 - Reference Generation Pins....................................................................................................................134
Table 7.25 - REF5V ...................................................................................................................................................135
Table 7.26 - REF5V_STBY ........................................................................................................................................135
Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................136
Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................136
Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................137
Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................137
Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................137
Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................138
Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................138
Table 7.34 - SMBus Isolation Pins .............................................................................................................................139
Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................140
Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................140
Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................141
Table 7.38 - nPS_ON Truth Table..............................................................................................................................141
Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................141
Table 7.40 - PWRGD_3V Truth Table........................................................................................................................142
Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................143
Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................143
Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................144
Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................144
Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................145
Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................146
Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................147
Table 7.48 - nRSMRST Pin........................................................................................................................................149
Table 7.49 - CNR Pins ...............................................................................................................................................149
Table 7.50 - CNR Logic Truth Table ..........................................................................................................................150
Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................151
Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................152
Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................158
Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................159
Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................162
Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................163
Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................176
Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................178
Table 11.3 - Chip Level Registers ..............................................................................................................................180
Table 11.4 - Logical Device Registers........................................................................................................................183
Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................185
Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................185
Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0........................................................................................187
Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................188
Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................190
Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................191
Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................192
Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................193
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 11.13 - Keyboard Logical Device Configuration Registers ...............................................................................194
Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers .................................194
Table 12.1 - Operational DC Characteristics..............................................................................................................196
Table 12.2 - S3-S5 Standby Current ..........................................................................................................................201
Table 13.1 - nIDE_RSTDRV Timing...........................................................................................................................221
Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing ........................................................................................221
Table 13.3 - PS_ON Timing .......................................................................................................................................221
Table 13.4 - SCK_BJT_GATE Timing........................................................................................................................222
Table 13.5 - PWRGD_3V Timing ...............................................................................................................................222
Table 13.6 - CNR CODEC Down Enable Timing .......................................................................................................222
Table 13.7 - Resume Reset Timing............................................................................................................................223
Table 14.1 - 128 Pin MQFP Package Parameters .....................................................................................................224
Table 15.1 - XOR Test Pattern Example....................................................................................................................226
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 11 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 1 General Description
The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop
PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well
as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard
resulting in lower cost. The LPC47M172 also provides 13 general purpose pins, which offer flexibility to
the system designer, and two Fan Tachometer Inputs. The LPC47M172’s LPC interface supports LPC I/O
and DMA cycles.
The LPC47M172 includes complete legacy I/O: a keyboard interface with AMI
CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs;
one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core
provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data
overflow and underflow protection. The SMSC’s patented advanced digital data separator allows for ease
of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP
and ECP. The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes
support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low
power-down modes. The LPC47M172 is ACPI 1.0b/2.0 compatible.
The Motherboard GLUE logic includes various power management logic; including generation of
nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three
LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V
signals. Also included is SMBus main power well to resume power well isolation circuitry.
The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address,
DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through
the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location
options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers
enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.
The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and
is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is
register compatible with SMSC’s proprietary 82077AA core.
This device utilizes two selectable (see Chapter 2) register sets; (1) standard SMSC and (2) tailored for
Intel reference designs. These register sets are detailed in Chapter 6 (Section 6.1).
TM
BIOS; SMSC's true
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 12 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 2 Pin Layout
IRTX2
IRRX2
nDCD2
nDTR2
nCTS2
VCC
nRTS2
nDSR2
TXD2
RXD2
nRI2
NC/VTR (Note)
DDCSDA_5V/GP20
DDCSDA_3V/GP22
DDCSCL_5V/GP21
DDCSCL_3V/GP23
GP17/FAN_TACH2
GP16/FAN_TACH1
VSS
GP15
GP14
VTR
GP13
GP12
GP11
GP10
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
MCLK
MDAT
KCLK
KDAT
GA20M
VCC
nKBDRST
VSS
nDSKCHG
nHDSEL
nRDATA
nWRTPRT
nTRK0
nWGATE
nWDATA
nSTEP
nDIR
nDS0
nMTR0
nINDEX
DRVDEN1
DRVDEN0
nDCD
nDSR
RXD
nRTS
TXD
nCTS
VSS
nDTR (XOR)
VCC
nRI
SLCT
PE
BUSY
nACK
PD7
PD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
LPC47M172
128 PIN QFP
103
64
102
nCDC_DWN_RST
101
nCDC_DWN_ENAB/GP24
100
nAUD_LINK_RST
99
nIO_PME
98
TEST_EN
97
F_CAP
96
VSS
95
YLW_LED
94
GRN_LED
93
VTR
92
nRSMRST
91
CLOCKI32
90
SMB_DAT_R
89
SMB_DAT_M
88
SMB_CLK_R
87
SMB_CLK_M
86
nSLP_S5
85
nSLP_S3
84
PWRGD_3V
83
nCPU_PRESENT
82
PWRGD_PS
81
nPS_ON
80
SCK_BJT_GATE
79
LATCHED_BF_CUT
78
VSS
77
nBACKFEED_CUT
76
VTR
75
nFPRST
74
nPCIRST_OUT2
73
nPCIRST_OUT
72
REF5V_STBY
71
V_5P0_STBY
70
REF5V
69
nSCSI
68
nSECONDARY_HD
67
nPRIMARY_HD
66
nHD_LED
65
CLOCKI
PD5
PD4
PD3
PD2
PD1
PD0
nERROR
VSS
VCC
nALF
nSLCTIN
nINITP
nLDRQ
nLPCPD
SER_IRQ
nSTROBE
VSS
VCC
LAD3
LAD2
LAD1
LAD0
PCI_CLK
nLFRAME
nPCI_RESET
nIDE_RSTDRV
Figure 2.1 - LPC47M172 Pin Layout
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 13 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the
TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the
LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin functions
as follows:
The pin has an internal pull-down resistor that selects the non-standard SMSC (Intel Compatible) mode. To
select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to ‘0’ and the
associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=0.
Connecting this pin to VTR will select the standard SMSC mode of the logical device numbering. This
configuration sets the LD_NUM bit to ‘1’ and the associated functionality corresponds to the existing functionality
in the part when the LD_NUM bit=1.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 14 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 3 Description of Pin Functions
Table 3.1 - LPC47M172 Pin Description
PIN#
6,31,
NAME
(NOTE 1)
DESCRIPTION
POWER AND GROUND PINS (20)
BUFFER
(NOTE 2)
See Note 11
NAME
VCC +3.3 Volt Main Supply Voltage (5) PWR
PWR
WELL
(NOTE 3)
49,60,
123
76,93,
107,
117
See Note
VTR +3.3 Volt Standby Supply Voltage (4)
Note
See
PWR 11
71 V_5P0_STBY +5 Volt Standby Supply Voltage. PWR
8,29,
VSS Ground (7) PWR
46,58,
78,96,
110
70 REF5V
5V Reference Output. Requires external
AO VCC
pull-up to VCC5V.
72 REF5V_STBY
Highest System Standby Voltage.
AO VTR
Requires external pull-up to
V_5P0_STBY.
97 F_CAP
Internal Regulator Filter Capacitor. This
pin is a no connect. A filter capacitor can
be placed on this pin if it is required by
system board layout.
CLOCKS (2)
65 CLOCKI 14.318Mhz Clock Input IS VCC
91 CLOCKI32 32.768kHz Clock Input IS VTR 4
PROCESSOR/HOST LPC INTERFACE (11)
52 nLPCPD
Active low input Power Down signal
PCI_I VCC 5
indicates that the LPC47M172 should
prepare for power to be shut-off on the
LPC interface.
53 SER_IRQ
Serial IRQ pin used with the PCI_CLK pin
PCI_IO VCC
to transfer LPC47M172 interrupts to the
host.
54 nLDRQ
Active low output used for encoded
PCI_O VCC
DMA/Bus Master request for the LPC
interface.
55 PCI_CLK 33.33 MHz PCI Clock input. PCI_ICLK VCC
56 nLFRAME
Active low input indicates start of new
PCI_I VCC
cycle and termination of broken cycle.
57,59,
61,62
LAD[3:0]
Active high LPC I/O used for multiplexed
command, address and data bus.
PCI_IO VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 15 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
63 nPCI_RESET
NAME
(NOTE 1)
Active low input used as LPC Interface
Reset. 3.3V and 5V buffered copy of PCI
Reset signal is available on
nPCIRST_OUT and nIDE_RSTDRV.
These pins are listed under GLUE PINS.
99 nIO_PME
Power Management Event Output. This
active low Power Management Event
signal allows to request wakeup. This pin
can be configured as Push-Pull Output.
9 nDSKCHG
This input senses that the drive door is
open or that the diskette has possibly
been changed since the last drive
selection. This input is inverted and read
via bit 7 of I/O address 3F7H. The
nDSKCHG bit also depends upon the
state of the Force Disk Change bits in the
Force Disk Change register (see Chapter
11 Configuration).
10 nHDSEL
Head Select Output. This high current
output selects the floppy disk side for
reading or writing. A logic “1” on this pin
means side 0 will be accessed, while a
logic “0” means side 1 will be accessed.
Can be configured as an Open-Drain
Output.
11 nRDATA
Raw serial bit stream from the disk drive,
low active. Each falling edge represents
a flux transition of the encoded data.
12 nWRTPRT
This active low Schmitt Trigger input
senses from the disk drive that a disk is
write protected. Any write command is
ignored. The nWRPRT bit also depends
upon the state of the Force Write Protect
bit in the FDD Option register (see the
Configuration Registers section).
13 nTRK0
This active low Schmitt Trigger input
senses from the disk drive that the head
is positioned over the outermost track.
14 nWGATE
Write Gate Output. This active low high
current driver allows current to flow
through the write head. It becomes active
just prior to writing to the diskette. Can be
configured as an Open-Drain Output.
15 nWDATA
Write Disk Data Output. This active low
high current driver provides the encoded
data to the disk drive. Each falling edge
causes a flux transition on the media.
Can be configured as an Open-Drain
Output.
DESCRIPTION
FDD INTERFACE (14)
BUFFER
NAME
(NOTE 2)
PWR
WELL
(NOTE 3)
NOTES
PCI_I VCC
OD8 VTR
IS VCC
O12 VCC
IS VCC
IS VCC
IS VCC
O12 VCC
O12 VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 16 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
16 nSTEP
DESCRIPTION
Step Pulse Output. This active low high
BUFFER
NAME
(NOTE 2)
O12 VCC
PWR
WELL
(NOTE 3)
current driver issues a low pulse for each
track-to-track movement of the head.
Can be configured as an Open-Drain
Output.
17 nDIR
Step Direction Output. This high current
O12 VCC
low active output determines the direction
of the head movement. A logic “1” on this
pin means outward motion, while a logic
“0” means inward motion. Can be
configured as an Open-Drain Output.
18 nDS0
Drive Select 0 Output. Can be configured
O12 VCC
as an Open-Drain Output.
19 nMTR0
Motor On 0 Output. Can be configured as
O12 VCC
an Open-Drain Output.
20 nINDEX
This active low Schmitt Trigger input
IS VCC
senses from the disk drive that the head
is positioned over the beginning of a
track, as marked by an index hole.
21 DRVDEN1
Drive Density Select 1 Output. Indicates
O12 VCC
the drive and media selected. Can be
configured as Open-Drain Output.
22 DRVDEN0
Drive Density Select 0 Output. Indicates
O12 VCC
the drive and media selected. Can be
configured as Open-Drain Output.
SERIAL PORT 1 INTERFACE (8)
23 nDCD1
Active low Data Carrier Detect input for
I VCC
the serial port. Handshake signal that
notifies the UART that carrier signal is
detected by the modem. The CPU can
monitor the status of nDCD signal by
reading bit 7 of Modem Status Register
(MSR). A nDCD signal state change from
low to high after the last MSR read will set
MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of
nDCD.
24 nDSR1
Active low Data Set Ready input for the
I VCC
serial port. Handshake signal that notifies
the UART that the modem is ready to
establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR). A nDSR signal state
change from low to high after the last
MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the
interrupt is generated when nDSR
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
25 RXD1 Receiver serial data input. IS VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 17 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
26 nRTS1
DESCRIPTION
Active low Request to Send output for the
BUFFER
NAME
(NOTE 2)
O8 VCC
PWR
WELL
(NOTE 3)
Serial Port. Handshake output signal
notifies modem that the UART is ready to
transmit data. This signal can be
programmed by writing to bit 1 of the
Modem Control Register (MCR). The
hardware reset will reset the nRTS signal
to inactive mode (high). nRTS is forced
inactive during loop mode operation.
27 TXD1 Transmit serial data output. O12 VCC
28 nCTS1
Active low Clear to Send input for the
I VCC
serial port. Handshake signal that notifies
the UART that the modem is ready to
receive data. The CPU can monitor the
status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS
signal state change from low to high after
the last MSR read will set MSR bit 0 to a
1. If bit 3 of the Interrupt Enable Register
is set, the interrupt is generated when
nCTS changes state. The nCTS signal
has no effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
30 nDTR1
(XOR)
32 nRI1
Active low Data Terminal Ready output
for the serial port. Handshake output
signal notifies modem that the UART is
ready to establish data communication
link. This signal can be programmed by
writing to bit 0 of Modem Control Register
(MCR). The hardware reset will reset the
nDTR signal to inactive mode (high).
nDTR is forced inactive during loop mode
operation.
XOR Chain Output.
Active low Ring Indicator input for the
O8 VCC
I VTR 6
serial port. Handshake signal that notifies
the UART that the telephone ring signal is
detected by the modem. The CPU can
monitor the status of nRI signal by
reading bit 6 of Modem Status Register
(MSR). A nRI signal state change from
low to high after the last MSR read will set
MSR bit 2 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nRI changes state.
Note: Bit 6 of MSR is the complement of
nRI.
SERIAL PORT 2 INTERFACE (8)
118 nRI2
Active low Ring Indicator input for serial
IPD VTR 6, 10
port 2. See description for nRI1.
119 RXD2 Receiver serial data input. ISPD_400 VCC
120 TXD2 Transmit serial data output. O12 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 18 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
121 nDSR2
DESCRIPTION
Active low Data Set Ready input for serial
BUFFER
NAME
(NOTE 2)
IPD VCC 10
PWR
WELL
(NOTE 3)
port 2. See description for nDSR1.
122 nRTS2
Active low Request to Send output for
O8 VCC
Serial Port 2. See description for nRTS1.
124 nCTS2
Active low Clear to Send input for serial
IPD VCC 10
port 2. See description for nCTS1.
125 nDTR2
Active low Data Terminal Ready output
O8 VCC
for serial port 2. See description for
nDTR1.
126 nDCD2
Active low Data Carrier Detect input for
IPD VCC 10
serial port 2. See description for nDCD1.
INFRARED INTERFACE (2)
127 IRRX2 Infrared receive input. ISPD_400 VCC 10
128 IRTX2 Infrared transmit output. O12 VCC 9
PARALLEL PORT INTERFACE (17)
33 SLCT
This high active input from the printer
I VCC
indicates that it has power on. Bit 4 of the
Printer Status Register reads the SLCT
input. Refer to Parallel Port description
for use of this pin in ECP and EPP mode.
34 PE
Another status input from the printer, a
I VCC
high indicating that the printer is out of
paper. Bit 5 of the Printer Status Register
reads the PE input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
35 BUSY
This is a status input from the printer, a
I VCC
high indicating that the printer is not ready
to receive new data. Bit 7 of the Printer
Status Register is the complement of the
BUSY input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
36 nACK
A low active input from the printer
I VCC
indicating that it has received the data
and is ready to accept new data. Bit 6 of
the Printer Status Register reads the
nACK input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
37 PD7 Port Data 7 I/O IOP14 VCC
38 PD6 Port Data 6 I/O IOP14 VCC
39 PD5 Port Data 5 I/O IOP14 VCC
40 PD4 Port Data 4 I/O IOP14 VCC
41 PD3 Port Data 3 I/O IOP14 VCC
42 PD2 Port Data 2 I/O IOP14 VCC
43 PD1 Port Data 1 I/O IOP14 VCC
44 PD0 Port Data 0 I/O IOP14 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 19 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
45 nERROR
DESCRIPTION
A low on this input from the printer
BUFFER
NAME
(NOTE 2)
I VCC
PWR
WELL
(NOTE 3)
indicates that there is an error condition at
the printer. Bit 3 of the Printer Status
register reads the nERR input. Refer to
Parallel Port description for use of this pin
in ECP and EPP mode.
47 nSLCTIN
This active low output selects the printer.
OP14 VCC
This is the complement of bit 3 of the
Printer Control Register. Refer to Parallel
Port description for use of this pin in ECP
and EPP mode.
Can be Configured as an Open-Drain
Output.
48 nINITP
This output is bit 2 of the printer control
OP14 VCC
register. This is used to initiate the printer
when low. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode. Can be configured as an
Open-Drain Output.
50 nALF
This output goes low to cause the printer
OP14 VCC
to automatically feed one line after each
line is printed. The nALF output is the
complement of bit 1 of the Printer Control
Register. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
Can be configured as an Open-Drain
Output.
51 nSTROBE
An active low pulse on this output is used
OP14 VCC
to strobe the printer data into the printer.
The nSTROBE output is the complement
of bit 0 of the Printer Control Register.
Refer to Parallel Port description for use
of this pin in ECP and EPP mode.
Can be configured as an Open-Drain
Output.
KEYBOARD/MOUSE INTERFACE (6)
1 MCLK Mouse Clock I/O IOD24 VCC
2 MDAT Mouse Data I/O IOD24 VCC 6
3 KCLK Keyboard Clock I/O IOD24 VCC
4 KDAT Keyboard Data I/O IOD24 VCC 6
5 GA20M Gate A20 Open-Drain Output OD8 VCC 7
7 nKBDRST Keyboard Reset Open-Drain Output OD8 VCC 7
GLUE PINS (29)
64 nIDE_RSTDRV IDE Reset Output OD8 VCC 3
66 nHD_LED
Hard Drive Front Panel LED Open-Drain
OD12 VCC 3
Output
67
nPRIMARY_
IDE Primary Drive Active Input ISPU_400 VCC
HD
68
nSECONDARY
IDE Secondary Drive Active Input ISPU_400 VCC
_HD
69 nSCSI SCSI Drive Active Input ISPU_400 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 20 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
DESCRIPTION
BUFFER
NAME
(NOTE 2)
PWR
WELL
(NOTE 3)
NOTES
73 nPCIRST_OUT Buffered PCI Reset Output OP14 VTR
74
nPCIRST_OUT
Second Buffered PCI Reset Output OP14 VTR
2
75 nFPRST Reset Input from Front Panel ISPU_400 VTR
77
nBACKFEED_
Open-Drain Output used for STR Circuitry OD8 VTR 3
CUT
79
LATCHED_BF_
CUT
80
SCK_BJT_
GATE
81 nPS_ON
Latched Backfeed Cut Output for STR
Circuitry
Open-Drain Gate Output for the SCK_BJT
in Suspend-to-RAM
Power Supply Turn-ON Open Drain
OP14 VTR
OD8 VTR 3
OD8 VTR 3
Output
82 PWRGD_PS Power Good Input from Power Supply ISPU_400 VTR
83
nCPU_PRESENT
CPU Present Input from Processor ISPU_400 VTR
84 PWRGD_3V Power Good Output O8 VTR
85 nSLP_S3 S3 Power State Input from South Bridge IS_400 VTR
86 nSLP_S5
Input from South Bridge for Transitioning
IS_400 VTR
to the S5 Power State
87 SMB_CLK_M SMBus Clock Main IO_SW VTR
88 SMB_CLK_R SMBus Clock Resume IO_SW VTR
89 SMB_DAT_M SMBus Data Main IO_SW VTR
90 SMB_DAT_R SMBus Data Resume IO_SW VTR
92 nRSMRST Resume Reset Output O8 VTR
100
nAUD_LINK_
AC97 Link Reset Input I VTR
RST
101
nCDC_DWN_
ENAB/GP24
AC97 Codec Down Enable Input.
General Purpose I/O. GPIO can be
IO12 VTR 6
configured as an open-drain output.
102
nCDC_DWN_
AC97 Codec Down Reset Output. O12 VTR
RST
113 DDCSCL_3V/
GP23
3.3V DDC Clock
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
114 DDCSCL_5V/
GP21
5V DDC Clock
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
115 DDCSDA_3V/
GP22
3.3V DDC Data
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
116 DDCSDA_5V/
GP20
5V DDC Data
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
POWER LEDS (2)
94 GRN_LED Green Power LED Open-Drain Output OD24 VTR
95 YLW_LED Yellow Power LED Open-Drain Output OD24 VTR
GENERAL PURPOSE I/O (8)
103105
GP10-GP12
General Purpose I/O. GPIO can be
configured as an open-drain output.
ISO8 VTR 6
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 21 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
106,
108,
NAME
(NOTE 1)
GP13-GP15
DESCRIPTION
General Purpose I/O. GPIO can be
configured as an open-drain output.
BUFFER
NAME
(NOTE 2)
IO8 VTR 6
PWR
WELL
(NOTE 3)
NOTES
109
111 GP16/
FAN_TACH1
112 GP17/
FAN_TACH2
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 1 Input
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 2 Input
IO8 VTR 6
IO8 VTR 6
TEST (1)
98 TEST_EN
Test Enable Input for XOR-Chain test –
IPD VTR
the external pull-up or internal pull-down
sets the strap value. The XOR output is
the nDTR1 pin.
NO CONNECT (1)
See Note11
117 NC No Connect IPD - 11
Note 1: The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low”
signal. The primary and secondary functions on the pins are separated by “/”.
Note 2: The buffer names are described in the “Buffer Name Descriptions” section.
Note 3: Open-drain pins should be pulled-up externally to supply shown in the power well column. The
nIDE_RSTDRV, nHD_LED, DDCSDA_5V and DDCSCL_5V open-drain pins require external pull-ups to
VCC5V. The nBACKFEED_CUT, SCK_BJT_GATE and nPS_ON open-drain pins require external pullups to V_5P0_STBY. Inputs with internal pull-ups are pulled internally to the supply shown in the power
well column. All other pins are driven under the power well shown. See the “Pins With Internal Resistors”,
“Pins That Require External Resistors” and “Default State of Pins” sections.
Note 4: The 32.768 kHz input clock must not be driven high when VTR = 0V. CLOCKI32 is clock source to various
logic in the part, including LED, “wake on specific key” and nFPRST debounce circuitry. The 32 KHz input
clock must always be connected. There is a bit in the configuration register at 0xF0 in Logical Device A
that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the
logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).
Note 5: The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal
follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.
However, if nLPCPD is tied high, the keyboard wakeup isolation logic will be affected.
Note 6: These pins (except DDC and FAN_TACH functions) are also inputs to VTR powered logic internal to the
part. If DDC and FAN_TACH functions are selected on GPIOs, the pins will tri-state when VCC power is
removed.
Note 7: External pullups must be placed on the nKBDRST and GA20M pins. If the nKBDRST and GA20M
functions are to be used, the system must ensure that these pins are high. See the “That Require External
Resistors” section.
Note 8: When DDC functions are selected on GP20-GP23, the pins become IO_SW type and require external pull-
ups to the appropriate voltages. See the “That Require External Resistors” section. When the GPIO
functions are selected, the pins are IS0D8.
Note 9: The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC
POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 22 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
time the pin will reflect the state of the transmit output of the Serial Port 2 block. This is a VCC powered
pin.
Note 10: These pins are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial Port 2 is
enabled, the pull-downs are removed until VTR POR.
Note 11: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the
TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the
LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin has an
internal pull-down resistor that selects the non-SMSC (Intel Compatible) mode. To select this mode, the
pin should be left unconnected. Connecting this pin to VTR will select the SMSC mode of the logical
device numbering.
3.1 Buffer Name Descriptions
Note: Refer to the “Electrical Characteristics” section.
PWR Power and Ground
I Input TTL Compatible.
IPU Input with 30uA Integrated Pull-Up
IPD Input with 30uA Integrated Pull-Down
IS Input with 250mV Schmitt Trigger.
IS_400 Input with 400mV Schmitt Trigger.
ISPU_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up.
ISPD_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Down.
O8 Output, 8mA sink, 4mA source.
OD8 Output (Open Drain), 8mA sink.
O12 Output, 12mA sink, 6mA source.
OD12 Output (Open Drain), 12mA sink.
OP14 Output, 14mA sink, 14mA source.
OD24 Output (Open Drain), 24mA sink.
AO Output – Analog with 5V Level
IO8 Input/Output, 8mA sink, 4mA source.
ISO8 Input with 250mV Schmitt Trigger /Output, 8mA sink, 4mA source.
ISOD8 Input with 250mV Schmitt Trigger, Low Leakage/Output (Open-Drain), 8mA sink.
IO12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source.
IOP14 Input/Output, 14mA sink, 14mA source.
IOD24 Input/Output (Open Drain), 24mA sink.
IO_SW Input/Output, special type. Pins of this type are connected in pairs through a switch. The switch
provides a 25 ohm (max) resistance to ground when closed.
PCI_IO Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_O Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_I Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_ICLK Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2)
Note 1: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
Note 2: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 23 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
3.2 Pins With Internal Resistors
The following pins have internal resistors:
Table 3.2 - Pins with Internal Resistors
SIGNAL NAME RESISTOR VALUE NOTES
nCPU_PRESENT 30uA Pull-up to VTR
nFPRST 30uA Pull-up to VTR
nPRIMARY_HD 30uA Pull-up to VCC
PWRGD_PS 30uA Pull-up to VTR
nSCSI 30uA Pull-up to VCC
nSECONDARY_HD 30uA Pull-up to VCC
TEST_EN 30uA Pull-down to VSS
3.3 Pins That Require External Resistors
The following pins require external resistors:
Table 3.3 - Pins that Require External Resistors
SIGNAL NAME RESISTOR VALUE NOTES
SER_IRQ 10 kohm Pull-up to VCC
nLDRQ 100 kohm Pull-up to VCC
LAD[3:0] 100 kohm Pull-up to VCC
MCLK
MDAT
KCLK
KDAT
GA20M 10 kohm Pull-up to VCC
KBDRST 10 kohm Pull-up to VCC
nIO_PME 10 kohm Pull-up to VTR
nHDSEL 10 kohm
nWGATE 10 kohm
nWDATA 10 kohm
nSTEP 10 kohm
nDIR 10 kohm
nDS0 10 kohm
nMTR0 10 kohm
DRVDEN1 10 kohm
DRVDEN0 10 kohm
nDSKCHG 1 kohm Pull-up to VCC
nRDATA 1 kohm Pull-up to VCC
nWRTPRT 1 kohm Pull-up to VCC
nTRK0 1 kohm Pull-up to VCC
nINDEX 10 kohm Pull-up to VCC
REF5V 1 kohm Pull-up to VCC5V
REF5V_STBY 1 kohm Pull-up to V_5P0_STBY
2.7 kohm
Pull-up to VREG_PS2. The
VREG_PS2 is the voltage
regulator for the PS/2 ports.
Pull-up required if used as
Open-Drain Output.
Pull-up to VCC.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 24 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME RESISTOR VALUE NOTES
nIDE_RSTDRV 1 kohm Pull-up to VCC5V
nPS_ON 1 kohm Pull-up to V_5P0_STBY
nBACKFEED_CUT 1 kohm Pull-up to V_5P0_STBY
SCK_BJT_GATE 1 kohm Pull-up to V_5P0_STBY
nCDC_DWN_ENAB 10 kohm Pull-down to VSS
YLW_LED 220 ohm Pull-up to VTR
nHD_LED 330 ohm Pull-up to VCC
DDCSDA_3V 4.7 kohm Pull-up to VCC
DDCSCL_3V 4.7 kohm Pull-up to VCC
DDCSDA_5V 2.2 kohm Pull-up to VCC5V
DDCSCL_5V 2.2 kohm Pull-up to VCC5V
SMB_CLK_M 2.7 kohm Pull-up to VCC
SMB_CLK_R 2.7 kohm Pull-up to VTR
SMB_DAT_M 2.7 kohm Pull-up to VCC
SMB_DAT_R 2.7 kohm Pull-up to VTR
GRN_LED 220 ohm Pull-up to VTR
GPIOs
design-dependant
Pull-up to appropriate voltage
(not to exceed 5V)
3.4 Default State of Pins
The following table shows the default state of pins.
Notes:
Off
The pin is not powered by suspend supply and is valid under main power only.
Hi-Z
The pin is powered, but tri-stated either because the pin is open-drain or VCC function is selected on VTR
powered pin. The pin requires external pull-up when tri-stated.
Active
The pin is powered and active high.
Running
The input clock is powered and running.
Input
The pin is powered and driven by external circuitry to high or low level.
Out
The pin is powered and driven to high or low level by the part.
The input or output configuration state of the pin is retained and is not affected by PCI Reset or VCC POR.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 25 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 3.4 - Default State of Pins
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
REF5V_STBY VTR - - Active
REF5V VCC Active Active Off
This pin requires external pullup to V_5P0_STBY
This pin requires external pull-
up to VCC5V
CLOCKI VCC Running Running Off
CLOCKI32 VTR Running Running Running
nIO_PME VTR - - Hi-Z
PCI_CLK VCC Input Input Off
nLPCPD VCC Input Input Off
nPCI_RESET VCC Input Input Off
SER_IRQ VCC Input Input Off
nLDRQ VCC Input Input Off
nLFRAME VCC Input Input Off
LAD[0:3] VCC Input Input Off
nDSKCHG VCC Input Input Off
nHDSEL VCC Out – low Out – low Off
nRDATA VCC Input Input Off
nWRTPRT VCC Input Input Off
nTRK0 VCC Input Input Off
nWGATE VCC Hi-Z Hi-Z Off
nWDATA VCC Hi-Z Hi-Z Off
nSTEP VCC Out – low Out – low Off
nDIR VCC Out – low Out – low Off
nDS0 VCC Hi-Z Hi-Z Off
nMTR0 VCC Hi-Z Hi-Z Off
nINDEX VCC Input Input Off
DRVDEN0 VCC Out – high Out – high Off
DRVDEN1 VCC Out – high Out – high Off
nDCD1 VCC Input Input Off
nDSR1 VCC Input Input Off
RXD1 VCC Input Input Off
nRTS1 VCC Out – high Out – high Off
TXD1 VCC Out – low Out – low Off
nCTS1 VCC Input Input Off
nDTR1 (XOR) VCC Out – high Out – high Off
nRI1 VTR - - Input
This pin is internally pulled
nDCD2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
nDSR2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
RXD2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
nRTS2 VCC Out – high Out – high Off
TXD2 VCC Out – low Out – low Off
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 26 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
This pin is internally pulled
nCTS2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
nDTR2 VCC Out – high Out – high Off
This pin is internally pulled
nRI2 VTR - - Input
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
IRRX2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
IRTX2 VCC Out – low Out – low Off
SLCT VCC Input Input Off
PE VCC Input Input Off
BUSY VCC Input Input Off
nACK VCC Input Input Off
PD[7:0] VCC Input Input Off
ERROR VCC Input Input Off
nSLCTIN VCC Out – High Out – High Off
nINITP VCC Out – High Out – High Off
nALF VCC Out – High Out – High Off
nSTROBE VCC Out – High Out – High Off
MCLK VCC Hi-Z Hi-Z Off
MDAT VCC - - Input
KCLK VCC Hi-Z Hi-Z Off
KDAT VCC - - Input
GA20M VCC Hi-Z Hi-Z Off
nKBDRST VCC Hi-Z Hi-Z Off
nAUD_LINK_RST VTR - - Input
nCDC_DWN_ENAB/
GP24
VTR - - Input
nCDC_DWN_RST VTR - - Out – low
nFPRST VTR - - Input This pin is pulled up internally
nBACKFEED_CUT VTR - - Hi-Z
This pin requires external pull-
up to V_5P0_STBY.
LATCHED_BF_CUT VTR - - Out – low
SCK_BJT_GATE VTR - - Hi-Z
This pin requires external pull-
up to V_5P0_STBY.
nSCSI VCC Input Input Off This pin is pulled up internally
GRN_LED VTR - - Out – low
YLW_LED VTR - - Out – low
nHD_LED VCC Hi-Z Hi-Z Off
nSECONDARY_HD VCC Input Input Off This pin is pulled up internally
nPRIMARY_HD VCC Input Input Off This pin is pulled up internally
nIDE_RSTDRV VCC Out – low Out – low Off
Requires external pull-up to
VCC5V
PWRGD_PS VTR - - Input
nPS_ON VTR - - Hi-Z
Requires external pull-up to
V_5P0_STBY
nCPU_PRESENT VTR - - Input This pin is pulled up internally
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 27 SMSC LPC47M172
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
nSLP_S3 VTR - - Input
nSLP_S5 VTR - - Input
nRSMRST VTR - - Out – low
PWRGD_3V VTR - - Out – low
nPCIRST_OUT VTR Out – low Out – low Out – low
nPCIRST_OUT2 VTR Out – low Out – low Out – low
VTR
VTR
- - Input
The GPIO and FAN_TACH
Hi-Z Hi-Z Hi-Z
functions are multiplexed on
the same pin with GPIO as the
Hi-Z Hi-Z Hi-Z
default function.
GP10-GP15 VTR
GP16 - - Input
FAN_TACH1
GP17 - - Input
FAN_TACH2
SMB_CLK_M VTR Hi-Z Hi-Z Hi-Z
SMB_CLK_R VTR - - Hi-Z
SMB_DAT_M VTR Hi-Z Hi-Z Hi-Z
SMB_DAT_R VTR - - Hi-Z
DDCSDA_5V Hi-Z Hi-Z Hi-Z
VTR
GP20
- - Hi-Z
DDCSCL_5V Hi-Z Hi-Z Hi-Z
VTR
GP21
- - Hi-Z
DDCSDA_3V Hi-Z Hi-Z Hi-Z
VTR
GP22
DDCSCL_3V Hi-Z Hi-Z Hi-Z
VTR
GP23
- - Hi-Z
- - Hi-Z
TEST_EN VTR - - Input
The DDC and GPIO functions
are multiplexed on the same
pin with DDC as the default
function. DDC function
requires external pull-up to
VCC5V.
The DDC and GPIO functions
are multiplexed on the same
pin with DDC as the default
function. DDC function
requires external pull-up to
VCC.
Test Mode pin. This pin has
internally pull-down to VSS.
External pull-up required to
enable the test mode.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 28 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 4 Block Diagram
SER_IRQ
PCI_CLK
LAD[3:0]
nLFRAME
nLDRQ
nPCI_RESET
nLPCPD
nIO_PME
GP10-GP15, GP16*, GP17*
(GP20-GP23)*
GP24*
F_CAP
V_5P0_STBY
nRSMRST
REF5V
REF5V_STBY
nAUD_LINK_RST
nCDC_DWN_ENAB*
nCDC_DWN_RST
nPCI_RST_OUT
nPCI_RST_OUT2
nIDE_RSTDRV
nPRIMARY_HD
nSECONDARY_HD
LATCHED_BF_CUT
nSCSI
nHD_LED
nFPRST
nBACKFEED_CUT
SCK_BJT_GATE
nPS_ON
PWRGD_PS
SERIAL IRQ /
Interrupt
Generating
Registers
LPC
Bus Interface
PME /
Power Contro l
GPIOs
Resume Reset
Generation
5V Reference
Generation
CNR Logic
Buffered
PCI Reset
Hard Drive
Front Panel
LED
Power
Sequencing
CLOCKI32
CLOCK
nPCI_RESET
SMBus
Isolatio n
CLOCKI
GEN
Configuration
Registers
Translation
GRN_LED
Power LED
nSLP_S5
(Data, Address, and Control lines)
VCC (3.3V) VT R (3.3V)
VGA
Voltage
YLW_LED
Internal Bus
LPC47M172
(128 QFP)
V_5P0_STBY
SMSC PROPRIETARY
82077 COMPATIBLE
VERTICAL FLOPPYDISK
CONTROLLER CORE
FAN_TACH2*
FAN_TACH1*
FAN
Monitoring
WDATA
WCLOCK
RCLOCK
RDATA
TEST_EN
XOR*
XOR-Chain
Multi-Mod e
Parallel Port with
Keyboard/Mouse
8042 Controller
ChiProtect
High-Speed
16550A UART
PORT
High-Speed
16550A UART
PORT 2
W/ Infrared
DIGITAL DATA
SEPARATOR
WITH WRITE
PRECOM-
PENSATION
TM
PD[7:0]
BUSY, SLCT , PE,
nERROR, nACK
nSTROBE, nINITP,
nSLCTIN, nALF
RXD
TXD
nCTS
nRTS
nDSR
nDTR*
nDCD
nRI
RXD2
TXD2
nCTS2
nRTS2
nDSR2
nDTR2
nDCD2
nRI2
IRRX2
IRTX2
KDAT, MDAT
KCLK, MCLK
GA20M
nKBDRST
Note 1: This diagram shows the
various functions available on the chip
nRDATA
nSLP_S3
nSLP_S5
PWRGD_3V
nCPU_PRESENT
SMB_CLK_R
SMB_DAT_R
SMB_DAT_M
SMB_CLK_M
DDCSCL_3V*
DDCSCL_5V*
DDCSDA_3V*
DDCSDA_5V*
nDIR, nSTEP,
nDS0, nMTR0
nWGATE, nHDSEL
nTRK0, nDSKCHG,
DRVDEN0, DRVDEN1
nINDEX, nWRT PRT
nWDATA
(not pin layout). The block diagram
should not be used for pin count.
Note 2: Func tions with asterisks (*)
are located on multifunctional pins.
Figure 4.1 - LPC47M172 Block Diagram
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Chapter 5 Power and Clock Functionality
The LPC47M172 has three power planes: VCC, VTR and V5P0_STBY.
5.1 3 Volt Operation / 5 Volt Tolerance
The LPC47M172 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V
tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive
protected (they do not impose a load on any external VCC powered circuitry).
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. The
nRSMRST pin is also 3.3V only.
The following lists the pins that are 3.3V only (not 5V tolerant):
LAD[3:0]
nLFRAME
nLDRQ
nLPCPD
nRSMRST
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following
pins:
nPCI_RESET
PCI_CLK
SER_IRQ
nIO_PME
5.2 VCC Power
The LPC47M172 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational
Description” Section and the “Maximum Current Values” subsection.
5.3 VTR Power
The LPC47M172 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up
events in the PME interface and other suspend state logic when VCC is removed. The VTR supply is 3.3
Volts (nominal). See the Operational Description Section. The maximum VTR current that is required
depends on the functions that are used in the part. See Trickle Power Functionality subsection and
Maximum Current Values subsection. If the LPC47M172 is not intended to provide wake-up and/or
suspend power capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a
VTR Power-on-Reset signal to initialize these components.
Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full
minimum potential at least 10 µs before VCC begins a power-on cycle. When VTR and VCC are fully
powered, the potential difference between the two supplies must not exceed 500mV.
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5.3.1 Trickle Power Functionality
When the LPC47M172 is running under VTR only (VCC removed), PME wakeup events are active and (if
enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:
UART1 and UART 2 Ring Indicator
Keyboard data
Mouse data
“Wake on Specific Key” Logic
GPIOs for wakeup. See below.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these
pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are
powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are
powered by VTR. This means, at a minimum, they will source their specified current from VTR even when
VCC is present.
The GPIOs that are used for PME wakeup as input are GP10-GP17 and GP20-GP23
Buffers are powered by VTR. These pins have input buffers into the wakeup logic that are powered by
VTR. GP24 does not have input buffer into the wakeup logic.
The output buffer of GP24 is by VTR but does this pin does not have an input buffer into wakeup logic
powered by VTR.
For blocks, registers and pins that are powered by VTR see Table 3.1 and Figure 4.1.
5.4 V5P0_STBY Power
The V5P0_STBY pin is used in nRSMRST generation circuit. The V5P0_STBY, however, does not power
the nRSMRST pad.
5.5 32.768 kHz Trickle Clock Input
The LPC47M172 utilizes a 32.768 kHz trickle input to supply a clock signal for the nFPRST debounce
circuitry, LED blink and wake on specific key function.
5.5.1 Indication of 32KHZ Clock
There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M172. This bit is
located at bit 0 of the CLOCKI32 configuration register at 0xF0 in Logical Device A (see Table 11.14).
This register is powered by VTR and reset on a VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0=32kHz clock is connected to the CLKI32 pin (default)
1=32kHz clock is not connected to the CLKI32 pin (pin is grounded).
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Bit 0 controls the source of the 32kHz (nominal) clock for the nFPRST debounce circuitry, the LED blink
logic and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the
source for the nFPRST debounce circuitry, LED and “wake on specific key” logic. When the external
32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the
“wake on specific key” logic. The nFPRST debounce circuitry and LED require the 32kHz clock be always
connected.
The “wake on specific key” function will not work under VTR power (VCC removed) if the external 32kHz
clock is not connected. It will work under VCC power even if the external 32 kHz clock is not connected.
5.6 14.318 MHz Clock Input
The LPC47M172 utilizes a 14.318 MHz clock input (CLOCKI). This clock is used to generate specific
clocks needed for various logic (including SIO functions, Fan Tachometer, etc.) in the LPC47M172. The
CLOCKI is powered by VCC and is not available in VTR power only (VCC=0).
5.7 Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the
host interface as VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V
(nominal), and the LPC47M172 host interface is active. When the internal PWRGOOD signal is “0”
(inactive), VCC <= 2.3V (nominal), and the LPC47M172 host interface is inactive; that is, LPC bus reads
and writes will not be decoded.
The LPC47M172 device pins nIO_PME, CLOCKI32, KDAT, MDAT, nRI1, nRI2, and most GPIOs (as input)
are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive,
provided VTR is powered. Other VTR powered pins listed in Table 3.1 also remain active when the
internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality
section.
5.8 Maximum Current Values
See the “Operational Description” section for the maximum current values.
The maximum VTR current, I
from/to 0V to/from 3.3V. The total maximum current for the part is the unloaded value PLUS the maximum
current sourced by the pin that is driven by VTR. The pins that are powered by VTR are listed in the Table
3.1. The push-pull capable outputs will source minimum current specified in Table 12.2 at 2.4V when
driving.
The maximum VCC current, I
from/to 0V to/from 3.3V.
, is given with all outputs open (not loaded), and all inputs transitioning
TR
, is given with all outputs open (not loaded) and all inputs transitioning
CC
5.9 Power Management Events (PME/SCI)
The LPC47M172 offers support for Power Management Events (PMEs), also referred to as System
Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document
to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal. See the
“PME Support” section.
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Chapter 6 Functional Description
The following sections describe the functional blocks located in the LPC47M172 (see Figure 4.1). The
various Super I/O components are described in the following sections and their registers are implemented
as typical Plug-and-Play components (see section Chapter 11 − Configuration on page 173).
6.1 Super I/O Registers
Table 6.1 shows the logical device number and addresses of FDC, Serial and Parallel ports,
Keyboard/Mouse, Power Control and GPIO Block, Runtime register block and configuration register block
of the Super I/O immediately after power up. The logical device numbering is controlled by the LD_NUM
bit in the TEST 7 configuration register (0x29). The state of LD_NUM is determined by pin 117 as
described in Chapter 2. The base addresses of the blocks can be programmed via the configuration
registers. Some addresses are used to access more than one register. Refer to the “Configuration”
section for configuration register description.
Table 6.1 - Super I/O Block Logical Device Number and Addresses
LD_NUM bit = 0 (default)
(Non-Standard SMSC Register Sets)
LD
NUMBER
00h
01h Parallel Port
02h Serial Port 2 Base+(0-7) 02h Serial Port 2 Base+(0-7)
03h Serial Port 1 Base+(0-7) 03h Parallel Port
04h Power Control Base+(0-31) 04h Serial Port 1 Base+(0-7)
05h Mouse 05h - 06h Keyboard 60, 64 06h - 07h GPIO Base+(0-31) 07h
08h - - 08h - 09h - - 09h - 0Ah - - 0Ah
- Configuration Base + (0-1) - Configuration Base + (0-1)
DEVICE NAME BLOCK ADDRESS
Floppy Disk
Controller
Base+(0-5) and +(7) 00h
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
NUMBER
01h - -
(Standard SMSC Register Sets)
LD
LD_NUM bit = 1
DEVICE
NAME
Floppy Disk
Controller
Keyboard/
Mouse
Runtime
Register Block
– contains
Power Control
and GPIO
Block registers
in this mode.
BLOCK ADDRESS
Base+(0-5) and +(7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
60, 64
Base+(0-63)
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6.2 Host Processor Interface (LPC)
The host processor communicates with the LPC47M172 through a series of read/write registers via the
LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is
accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
6.3 LPC Interface
The following sub-sections specify the implementation of the LPC bus.
6.3.1 LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
SIGNAL
NAME
LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data bus.
nLFRAME Input Frame signal. Indicates start of new cycle and termination of broken cycle
nPCI_RESET Input PCI Reset. Used as LPC Interface Reset.
nLDRQ Output Encoded DMA/Bus Master request for the LPC interface.
nIO_PME OD Power Mgt Event signal. Allows the LPC47M172 to request wakeup.
nLPCPD Input
SER_IRQ I/O Serial IRQ.
PCI_CLK Input PCI Clock.
Note: The CLKRUN# signal is not implemented in this part.
TYPE DESCRIPTION
Powerdown Signal. Indicates that the LPC47M172 should prepare for power to be shut
on the LPC interface.
6.3.2 LPC Cycles
The following cycle types are supported by the LPC protocol.
CYCLE TYPE TRANSFER SIZE
I/O Write 1 Byte
I/O Read 1 Byte
DMA Write 1 Byte
DMA Read 1 Byte
LPC47M172 ignores cycles that it does not support.
6.3.3 Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the
cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and
data information over the LPC bus between the host and the LPC47M172. See the Low Pin Count (LPC)
Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.
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6.3.4 NLFRAME Usage
nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort
or time-out condition. This signal is to be used by the LPC47M172 to know when to monitor the bus for a
cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start
or stop of a cycle, and that the LPC47M172 monitors the bus to determine whether the cycle is intended
for it. The use of nLFRAME allows the LPC47M172 to enter a lower power state internally. There is no
need for the LPC47M172 to monitor the bus when it is inactive, so it can decouple its state machines from
the bus, and internally gate its clocks.
When the LPC47M172 samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on
the next clock and monitor the bus for new cycle information.
The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision
1.0.
6.3.5 I/O Read and Write Cycles
The LPC47M172 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO
accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes
is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will
break it up into 8-bit transfers.
See the “Low Pin Count (LPC) Interface Specification” Reference, Section 5.2, for the sequence of cycles
for the I/O Read and Write cycles.
6.3.6 DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M172. DMA write
cycles involve the transfer of data from the LPC47M172 to the host (main memory). Data will be coming
from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M172 are 1, 2
or 4 bytes.
See the “Low Pin Count (LPC) Interface Specification” Reference, Section 6.4, for the field definitions and
the sequence of the DMA Read and Write cycles.
6.3.7 DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M172 and special
encodings on LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the “Low Pin Count (LPC) Interface Specification,”
Revision 1.0.
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6.3.8 Power Management
CLOCKRUN Protocol
The CLKRUN# pin is not implemented in the LPC47M172.
See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.1.
LPCPD Protocol
See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.2.
6.3.9 SYNC Protocol
See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 4.2.1.8 for a table of valid
SYNC values.
Typical Usage
The SYNC pattern is used to add wait states. For read cycles, the LPC47M172 immediately drives the
SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If
the LPC47M172 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is
ready, at which point it will drive 0000 or 1001. The LPC47M172 will choose to assert 0101 or 0110, but
not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is
intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The
LPC47M172 uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided
for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the
LPC47M172 uses a SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
SYNC Timeout
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC
pattern, it will abort the cycle.
The LPC47M172 does not assume any particular timeout. When the host is driving SYNC, it may have to
insert a very large number of wait states, depending on PCI latencies and retries.
SYNC Patterns and Maximum Number of SYNCS
If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M172 has
protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the
same timeout protection that is in EPP.
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SYNC Error Indication
The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding.
If the host was reading data from the LPC47M172, data will still be transferred in the next two nibbles.
This data may be invalid, but it will be transferred by the LPC47M172. If the host was writing data to the
LPC47M172, the data had already been transferred.
In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle.
Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first
byte, the other three bytes will not be transferred.
6.3.10 I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to
the removal of the reset signal, so that everything is stable. This is the same reset active time after clock
is stable that is used for the PCI bus.
When nPCI_RESET goes active (low):
the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ
signal.
the LPC47M172 ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive
(high).
6.3.11 LPC Transfers
Wait State Requirements
I/O Transfers
The LPC47M172 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A
SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would
normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of
0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of
10us).
DMA Transfers
The LPC47M172 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A
SYNC of 0101 is used for all DMA transfers.
See the example timing for the LPC cycles in the “Timing Diagrams” section.
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6.4 Floppy Disk Controller
The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy
disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write
Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B
core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow
protection.
The FDC is compatible to the 82077AA using SMSC’s proprietary floppy disk controller core.
6.4.1 FDC Configuration Registers
The FDC configuration registers are summarized Table 11.2 in the “Configuration” section. The FDC
logical device configuration registers (0xF0, 0xF1, 0xF2 and 0xF4) are defined in Table 11.9.
6.4.2 FDC Internal Registers
The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host
microprocessor and the disk drive. Table 6.2 shows the addresses required to access these registers.
Registers other than the ones shown are not supported. The rest of the description assumes that the
primary addresses have been selected.
Table 6.2 - Status, Data and Control Registers
(Shown with base addresses of 3F0 and 370)
PRIMARY
ADDRESS
3F0
3F1
3F2
3F3
3F4
3F4
3F5
3F6
3F7
3F7
SECONDARY
ADDRESS
370
371
372
373
374
374
375
376
377
377
R/W REGISTER
Status Register A (SRA)
R
Status Register B (SRB)
R
R/W
R/W
W
R/W
W
Digital Output Register (DOR)
Tape Drive Register (TDR)
Main Status Register (MSR)
R
Data Rate Select Register (DSR)
Data (FIFO)
Reserved
Digital Input Register (DIR)
R
Configuration Control Register (CCR)
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6.4.3 Status Register A (SRA)
Address 3F0 READ ONLY
This register is read-only and monitors the state of the internal interrupt signal and several disk interface
pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the
PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F0.
PS/2 Mode
7 6 5 4 3 2 1 0
RESET
COND.
BIT 0 DIRECTION
Active high status indicating the direction of head movement. A logic “1” indicates inward direction; a logic
“0” indicates outward direction.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk interface input. A logic “0” indicates that the disk is write
protected.
INT
PENDIN
G
0 1 0 N/A 0 N/A N/A 0
nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR
BIT 2 nINDEX
Active low status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side
0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk interface output pin.
BIT 6 nDRV2
This function is not supported. This bit is always read as “1”.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt output.
PS/2 Model 30 Mode
7 6 5 4 3 2 1 0
PENDING
RESET
COND.
BIT 0 DIRECTION
INT
0 0 0 N/A 1 N/A N/A 1
DRQ STEP
F/F
TRK0 nHDSEL INDEX WP nDIR
Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic
“1” indicates outward direction.
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BIT 1 WRITE PROTECT
Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write
protected.
BIT 2 INDEX
Active high status of the INDEX disk interface input.
BIT 3 HEAD SELECT
Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side
0.
BIT 4 TRACK 0
Active high status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output
going active, and is cleared with a read from the DIR register, or with a hardware or software reset.
BIT 6 DMA REQUEST
Active high status of the DMA request pending.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
6.4.4 Status Register B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30
modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins
D0 – D7 are held in a high impedance state for a read of address 3F1.
PS/2 Mode
7 6 5 4 3 2 1 0
1 1
RESET
COND.
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
1 1 0 0 0 0 0 0
DRIVE
SEL0
WDATA
TOGGLE
RDATA
TOGGLE
WGATE
MOT
EN1
MOT
EN0
BIT 2 WRITE GATE
Active high status of the WGATE disk interface output.
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BIT 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes this bit to change state.
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes this bit to change state.
BIT 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a
hardware reset and it is unaffected by a software reset.
BIT 6 RESERVED
Always read as a logic “1”.
BIT 7 RESERVED
Always read as a logic “1”
PS/2 Model 30 Mode
7 6 5 4 3 2 1 0
nDRV2 nDS1 nDS0 WDATA
F/F
RESET
N/A 1 1 0 0 0 1 1
RDATA
F/F
WGATE
F/F
nDS3 nDS2
COND.
BIT 0 nDRIVE SELECT 2
The DS2 disk interface is not supported.
BIT 1 nDRIVE SELECT 3
The DS3 disk interface is not supported.
BIT 2 WRITE GATE
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of
WGATE and is cleared by the read of the DIR register.
BIT 3 READ DATA
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of
RDATA and is cleared by the read of the DIR register.
BIT 4 WRITE DATA
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of
WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.
BIT 5 nDRIVE SELECT 0
Active low status of the DS0 disk interface output.
BIT 6 nDRIVE SELECT 1
Active low status of the DS1 disk interface output.
BIT 7 nDRV2
Active low status of the DRV2 disk interface input. Note: This function is not supported.
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6.4.5 Digital Output Register (DOR)
Address 3F2 READ/WRITE
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the
enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software
reset. The DOR can be written to at any time.
7 6 5 4 3 2 1 0
RESET
COND.
BIT 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at
one time.
BIT 2 nRESET
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1”
is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the
other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by
consecutive writes to this register is a valid method of issuing a software reset.
MOT
EN3
MOT
EN2
MOT
EN1
0 0 0 0 0 0 0 0
MOT
EN0
DMAEN nRESET
DRIVE
SEL1
DRIVE
SEL0
BIT 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable
the DMA and interrupt functions. This bit is a logic “0” after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will
be cleared to a logic “0”.
BIT 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active.
BIT 5 MOTOR ENABLE 1
This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active.
DIGITAL OUTPUT
REGISTER
Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0
X 1 0 0 1 0 nBIT 5 nBIT 4
1 X 0 1 0 1 nBIT 5 nBIT 4
0 0 X X 1 1 nBIT 5 nBIT 4
DRIVE DOR VALUE
0 1CH
1 2DH
Table 6.3 - Internal 2 Drive Decode - Normal
DRIVE SELECT OUTPUTS
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
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Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped
DIGITAL OUTPUT
REGISTER
Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0
X 1 0 0 0 1 nBIT 4 nBIT 5
1 X 0 1 1 0 nBIT 4 nBIT 5
0 0 X X 1 1 nBIT 4 nBIT 5
BIT 6 MOTOR ENABLE 2
The MTR2 disk interface output is not supported in the LPC47M172.
BIT 7 MOTOR ENABLE 3
The MTR3 disk interface output is not supported in the LPC47M172.
DRIVE SELECT OUTPUTS
6.4.6 Tape Drive Register (TDR)
Address 3F3 READ/WRITE
The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign
tape support to a particular drive during initialization. Any future references to that drive automatically
invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.5
illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape
support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is
unaffected by a software reset.
(ACTIVE LOW)
MOTOR ON OUTPUTS
(ACTIVE LOW)
Normal Floppy Mode
Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REG 3F3 0 0 0 0 0 0 tape sel1 tape sel0
Enhanced Floppy Mode 2 (OS2)
Register 3F3 for Enhanced Floppy Mode 2 operation.
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0
Table 6.5 - Tape Select Bits
TAPE SEL1
(TDR.1)
0
0
1
1
TAPE SEL0
(TDR.0)
0
1
0
1
DRIVE
SELECTED
None
1
2
3
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Table 6.6 - Drive Type ID
DIGITAL OUTPUT REGISTER REGISTER 3F3 – DRIVE TYPE ID
Bit 1 Bit 0 Bit 5 Bit 4
0 0 L0-CRF2 – B1 L0-CRF2 – B0
0 1 L0-CRF2 – B3 L0-CRF2 – B2
1 0 L0-CRF2 – B5 L0-CRF2 – B4
1 1 L0-CRF2 – B7 L0-CRF2 – B6
Note: L0-CRF2-Bx = FDC Logical Device, Configuration Register F2, Bit x.
6.4.7 Data Rate Select Register (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program the data rate, amount of write precompensation, power
down status, and software reset. The data rate is programmed using the Configuration Control Register
(CCR) not the DSR, for PC/AT and PS/2 Model 30.
7 6 5 4 3 2 1 0
RESET
COND.
S/W
RESET
POWER
DOWN
0 0 0 0 0 0 1 0
0
PRE-
COMP2
PRE-
COMP1
PRE-
COMP0
DRATE
SEL1
DRATE
SEL0
This register is write only. It is used to program the data rate, amount of write precompensation, power
down status, and software reset. The data rate is programmed using the Configuration Control Register
(CCR) not the DSR, for PC/AT and PS/2 Model 30.
Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most
recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will
set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output
signal. Table 6.7 shows the precompensation values for the combination of these bits settings. Track 0 is
the default starting track number to start precompensation. This starting track number can be changed by
the configure command.
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Table 6.7 - Precompensation Delays
BIT 5 UNDEFINED
Should be written as a logic “0”.
BIT 6 LOW POWER
A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy
controller clock and data separator circuits will be turned off. The controller will come out of manual low
power mode after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
PRECOMP
432
PRECOMPENSATION
DELAY (NSEC)
<2Mbps 2Mbps
111
001
010
011
100
101
110
000
0.00
41.67
83.34
125.00
166.67
208.33
250.00
Default
0
20.8
41.7
62.5
83.3
104.2
125
Default
Default: See Table 6.10
Separator circuits will be turned off. The controller will come out of manual low power.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the
Power Control/Runtime Register block.
Table 6.8 - Data Rates
DRIVE RATE DATA RATE DATA RATE DRATE(1)
DRT1 DRT0 SEL1 SEL0 MFM FM
DENSEL
1 0
0 0 1 1 1Meg --- 1 1 1
0 0 0 0 500 250 1 0 0
0 0 0 1 300 150 0 0 1
0 0 1 0 250 125 0 1 0
0 1 1 1 1Meg --- 1 1 1
0 1 0 0 500 250 1 0 0
0 1 0 1 500 250 0 0 1
0 1 1 0 250 125 0 1 0
1 0 1 1 1Meg --- 1 1 1
1 0 0 0 500 250 1 0 0
1 0 0 1 2Meg --- 0 0 1
1 0 1 0 250 125 0 1 0
Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.
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Table 6.9 - DRVDEN Mapping
DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE
0 0 DRATE0 DENSEL 4/2/1 MB 3.5”
1 0 DRATE0 DRATE1
0 1 DRATE0 nDENSEL PS/2
1 1 DRATE1 DRATE0
Table 6.10 - Default Precompensation Delays
2/1 MB 5.25” FDDS
2/1.6/1 MB 3.5” (3-MODE)
DATA RATE
6.4.8 Main Status Register
Address 3F4 READ ONLY
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main
Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive
data via the Data Register. It should be read before each byte transferring to or from the data register
except in DMA mode. No delay is required when reading the MSR after a data transfer.
7 6 5 4 3 2 1 0
RQM DIO
BIT 0 – 1 DRV x BUSY
These bits are set to 1s when a drive is in the seek portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
2 Mbps
1 Mbps
500 Kbps
300 Kbps
250 Kbps
NON
DMA
PRECOMPENSATION
CMD
BUSY
Reserved Reserved
DELAYS
20.8 ns
41.67 ns
125 ns
125 ns
125 ns
DRV1
BUSY
DRV0
BUSY
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has
been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek,
Recalibrate commands), this bit is returned to a 0 after the last command byte.
BIT 5 NON-DMA
Reserved, read ‘0’. This part does not support non-DMA mode.
BIT 6 DIO
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write
is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.
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6.4.9 Data Register (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data and result status are transferred between the host
processor and the floppy disk controller through the Data Register.
Data transfers are governed by the RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT
hardware compatibility. The default values can be changed through the Configure command (enable full
FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger
DMA latency without causing a disk error. Table 6.11 gives several examples of the delays with a FIFO.
The data is based upon the following formula:
Threshold # x 1
DATA
RATE
At the start of a command, the FIFO action is always disabled and command parameters must be sent
based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is
cleared of any data to ensure that invalid data is not transferred.
x 8 - 1.5 us = DELAY
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove
the remaining data so that the result phase may be entered.
Table 6.11 - FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
FIFO THRESHOLD
EXAMPLES
1 byte
2 bytes
8 bytes
15 bytes
MAXIMUM DELAY TO SERVICING AT
2 MBPS DATA RATE
1 x 4 us - 1.5 us = 2.5 us
2 x 4 us - 1.5 us = 6.5 us
8 x 4 us - 1.5 us = 30.5 us
15 x 4 us - 1.5 us = 58.5 us
MAXIMUM DELAY TO SERVICING AT
1 MBPS DATA RATE
1 x 8 us - 1.5 us = 6.5 us
2 x 8 us - 1.5 us = 14.5 us
8 x 8 us - 1.5 us = 62.5 us
15 x 8 us - 1.5 us = 118.5 us
MAXIMUM DELAY TO SERVICING AT
500 KBPS DATA RATE
1 x 16 us - 1.5 us = 14.5 us
2 x 16 us - 1.5 us = 30.5 us
8 x 16 us - 1.5 us = 126.5 us
15 x 16 us - 1.5 us = 238.5 us
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6.4.10 Digital Input Register (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7 6 5 4 3 2 1 0
RESET
COND.
BIT 0 – 6 UNDEFINED
The data bus outputs D0 – 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
PS/2 Mode
7 6 5 4 3 2 1 0
RESET
COND.
BIT 0 nHIGH DENS
DSK
CHG
N/A N/A N/A N/A N/A N/A N/A N/A
DSK
CHG
N/A N/A N/A N/A N/A N/A N/A 1
0 0 0 0 0 0 0
1 1 1 1
DRATE
SEL1
DRATE
SEL0
nHIGH
DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and
300 Kbps are selected.
BITS 1 – 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BITS 3 – 6 UNDEFINED
Always read as a logic “1”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
Model 30 Mode
7 6 5 4 3 2 1 0
DSK CHG 0 0 0 DMAEN NOPREC
RESET
N/A 0 0 0 0 0 1 0
DRATE
SEL1
DRATE
SEL0
COND.
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BITS 0 – 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps
after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 – 6 UNDEFINED
Always read as a logic “0”
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the
value programmed in the Force Disk Change Register (see Power Control/Runtime Register Block runtime
register at offset 0x18).
6.4.11 Configuration Control Register (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
7 6 5 4 3 2 1 0
0 0 0 0 0 0
RESET
COND.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 – 7 RESERVED
Should be set to a logical “0”
PS/2 Model 30 Mode
7 6 5 4 3 2 1 0
0 0 0 0 0 NOPREC
RESET
COND.
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 6.8 for the appropriate values.
BIT 2 NO PRECOMPENSATION
N/A N/A N/A N/A N/A N/A 1 0
N/A N/A N/A N/A N/A N/A 1 0
DRATE
SEL1
DRATE
SEL1
DRATE
SEL0
DRATE
SEL0
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in
Model 30 register mode. Unaffected by software reset.
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BIT 3 – 7 RESERVED
Should be set to a logical “0”
Table 6.9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is
unaffected by the DOR and the DSR resets.
6.4.12 Status Register Encoding
During the Result Phase of certain commands, the Data Register contains data bytes that give the status
of the command just executed.
Table 6.12 - Status Register 0
BIT NO. SYMBOL NAME DESCRIPTION
7,6 IC
5 SE Seek End
4 EC
3 Unused. This bit is always "0".
2 H
1,0 DS1,0 Drive Select The current selected drive.
Interrupt
Code
Equipment
Check
Head
Address
Table 6.13 - Status Register 1
00 - Normal termination of command. The specified
command was properly executed and completed
without error.
01 - Abnormal termination of command. Command
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command could
not be executed.
11 - Abnormal termination caused by Polling.
The FDC completed a Seek, Relative Seek or
Recalibrate command (used during a Sense Interrupt
Command).
The TRK0 pin failed to become a "1" after:
1. Step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to
step outward beyond Track 0.
The current head address.
BIT NO. SYMBOL NAME DESCRIPTION
7 EN
End of
Cylinder
The FDC tried to access a sector beyond the final
sector of the track (255D). Will be set if TC is not
issued after Read or Write Data command.
6 Unused. This bit is always "0".
5 DE Data Error
The FDC detected a CRC error in either the ID field or
the data field of a sector.
4 OR Overrun/
Underrun
Becomes set if the FDC does not receive CPU or DMA
service within the required time interval, resulting in
data overrun or underrun.
3 Unused. This bit is always "0".
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BIT NO. SYMBOL NAME DESCRIPTION
2 ND No Data Any one of the following:
1. Read Data, Read Deleted Data command - the
FDC did not find the specified sector.
2. Read ID command - the FDC cannot read the ID
field without an error.
3. Read A Track command - the FDC cannot find the
proper sector sequence.
1 NW Not Writeable
WP pin became a "1" while the FDC is executing a
Write Data, Write Deleted Data, or Format A Track
command.
0 MA
Missing
Address Mark
Any one of the following:
1. The FDC did not detect an ID address mark at the
specified track after encountering the index pulse
from the nINDEX pin twice.
2. The FDC cannot detect a data address mark or a
deleted data address mark on the specified track.
Table 6.14 - Status Register 2
BIT NO. SYMBOL NAME DESCRIPTION
7 Unused. This bit is always "0".
6 CM Control Mark Any one of the following:
Read Data command - the FDC encountered a deleted
data address mark.
Read Deleted Data command - the FDC encountered a
data address mark.
5 DD
Data Error in
The FDC detected a CRC error in the data field.
Data Field
4 WC
Wrong
Cylinder
The track address from the sector ID field is different
from the track address maintained inside the FDC.
3 Unused. This bit is always "0".
2 Unused. This bit is always "0".
1 BC Bad Cylinder
The track address from the sector ID field is different
from the track address maintained inside the FDC and
is equal to FF hex, which indicates a bad track with a
hard error according to the IBM soft-sectored format.
0 MD
Missing Data
Address Mark
The FDC cannot detect a data address mark or a
deleted data address mark.
Table 6.15 - Status Register 3
BIT NO. SYMBOL NAME DESCRIPTION
7 Unused. This bit is always "0".
6 WP
Write
Indicates the status of the WRTPRT pin.
Protected
5 Unused. This bit is always "1".
4 T0 Track 0 Indicates the status of the TRK0 pin.
3 Unused. This bit is always "1".
2 HD Head Address Indicates the status of the HDSEL pin.
1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins.
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RESET
There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset generated via a bit in
the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC.
All resets take the FDC out of the power down state.
All operations are terminated upon a nPCI_RESET, and the FDC enters an idle state. A reset while a disk
write is in progress will corrupt the data and CRC.
On exiting the reset state, various internal registers are cleared, including the Configure command
information, and the FDC waits for a new command. Drive polling will start unless disabled by a new
Configure command.
nPCI_RESET Pin (Hardware Reset)
The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify
command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both will reset the FDC core, which affects drive status
information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires
the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set
automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset
state.
6.5 Modes of Operation
The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are
determined by the state of the Interface Mode bits in FDC logical device -CRF0[3,2].
6.5.1 PC/AT Mode
The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt
and DMA functions), and DENSEL is an active high signal.
6.5.2 PS/2 Mode
This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR
becomes a “don’t care”. The DMA and interrupt functions are always enabled, and DENSEL is active low.
6.5.3 Model 30 Mode
This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR
becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.
6.6 DMA Transfers
DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA
request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer
modes: Single Transfer and Burst Transfer. Burst mode is enabled via FDC Logical Device -CRF0-Bit[1].
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6.7 Controller Phases
For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and
Result. Each phase is described in the following sections.
6.7.1 Command Phase
After a reset, the FDC enters the command phase and is ready to accept a command from the host. For
each of the commands, a defined set of command code bytes and parameter bytes has to be written to the
FDC before the command phase is complete. (Please refer to section 6.10 Command Set/Descriptions).
These bytes of data must be transferred in the order prescribed.
Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register.
RQM and DIO must be equal to “1” and “0” respectively before command bytes may be written. RQM is
set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM
again to request each parameter byte of the command unless an illegal command condition is detected.
After the last parameter byte is received, RQM remains “0” and the FDC automatically enters the next
phase as defined by the command definition.
The FIFO is disabled during the command phase to provide for the proper handling of the “Invalid
Command” condition.
6.7.2 Execution Phase
All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode
as indicated in the Specify command.
After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending
on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.
The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold>
is defined as the number of bytes available to the FDC when service is requested from the host and
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to
15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster
servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until
empty (full), then the transfer request goes inactive. The host must be very responsive to the service
request. This is the desired case for use with a “fast” system.
A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long latency period after a
service request, but results in more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to the Host
This part does not support non-DMA mode.
Non-DMA Mode - Transfers from the Host to the FIFO
This part does not support non-DMA mode.
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DMA Mode - Transfers from the FIFO to the Host
The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte
of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by
reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by
generating the proper sync for the data transfer.
DMA Mode - Transfers from the Host to the FIFO.
The FDC generates a DMA request cycle when entering the execution phase of the data transfer
commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains
active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold>
bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more
data is required.
6.8 Data Transfer Termination
The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun
and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector
to be transferred in a single or multi-sector transfer.
If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector,
and the FDC will continue to complete the sector as if a TC cycle was received. The only difference
between these implicit functions and TC cycle is that they return “abnormal termination” result status.
Such status indications can be ignored if they were expected.
Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete
when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the
transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The
host must tolerate this delay.
6.9 Result Phase
The generation of the interrupt determines the beginning of the result phase. For each of the commands,
a defined set of result bytes has to be read from the FDC before the result phase is complete. These
bytes of data must be read out for another command to start.
RQM and DIO must both equal “1” before the result bytes may be read. After all the result bytes have
been read, the RQM and DIO bits switch to “1” and “0” respectively, and the CB bit is cleared, indicating
that the FDC is ready to accept the next command.
6.10 Command Set/Descriptions
Commands can be written whenever the FDC is in the command phase. Each command has a unique set
of needed parameters and status results. The FDC checks to see that the first byte is a valid command
and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense
Interrupt Status command which returns an invalid command error. Refer to Table 6.16 for explanations of
the various symbols used. Table 6.17 lists the required parameters and the results associated with each
command that the FDC is capable of performing.
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Table 6.16 - Description of Command Symbols
SYMBOL NAME DESCRIPTION
C Cylinder Address The currently selected address; 0 to 255.
D Data Pattern The pattern to be written in each sector data field during formatting.
D0, D1 Drive Select 0-1
Designates which drives are perpendicular drives on the
Perpendicular Mode Command. A “1” indicates a perpendicular
drive.
DIR Direction Control
If this bit is 0, then the head will step out from the spindle during a
relative seek. If set to a 1, the head will step in toward the spindle.
DS0, DS1 Disk Drive Select DS1 DS0 DRIVE
0 0 Drive 0
0 1 Drive 1
DTL
Special Sector
Size
By setting N to zero (00), DTL may be used to control the number
of bytes transferred in disk read/write commands. The sector size
(N = 0) is set to 128. If the actual sector (on the diskette) is larger
than DTL, the remainder of the actual sector is read but is not
passed to the host during read commands; during write commands,
the remainder of the actual sector is written with all zero bytes. The
CRC check code is calculated with the actual sector. When N is
not zero, DTL has no meaning and should be set to FF HEX.
EC Enable Count
When this bit is “1” the “DTL” parameter of the Verify command
becomes SC (number of sectors per track).
EFIFO Enable FIFO
This active low bit when a 0, enables the FIFO. A “1” disables the
FIFO (default).
EIS
Enable Implied
Seek
When set, a seek operation will be performed before executing any
read or write command that requires the C parameter in the
command phase. A “0” disables the implied seek.
EOT End of Track The final sector number of the current track.
GAP Alters Gap 2 length when using Perpendicular Mode.
GPL Gap Length
The Gap 3 size. (Gap 3 is the space between sectors excluding
the VCO synchronization field).
H/HDS Head Address
Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID
field.
HLT Head Load Time
The time interval that FDC waits after loading the head and before
initializing a read or write operation. Refer to the Specify command
for actual delays.
HUT
Head Unload
Time
The time interval from the end of the execution phase (of a read or
write command) until the head is unloaded. Refer to the Specify
command for actual delays.
LOCK
Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters
of the CONFIGURE COMMAND can be reset to their default values
by a “software Reset”. (A reset caused by writing to the appropriate
bits of either the DSR or DOR)
MFM
MT
MFM/FM Mode
Selector
Multi-Track
Selector
A one selects the double density (MFM) mode. A zero selects
single density (FM) mode.
When set, this flag selects the multi-track operating mode. In this
mode, the FDC treats a complete cylinder under head 0 and 1 as a
single track. The FDC operates as this expanded track started at
the first sector under head 0 and ended at the last sector under
head 1. With this flag set, a multitrack read or write operation will
automatically continue to the first sector under head 1 when the
FDC finishes operating on the last sector under head 0.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 55 SMSC LPC47M172
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SYMBOL NAME DESCRIPTION
N Sector Size Code
NCN
New Cylinder
Number
ND
Non-DMA Mode
Flag
OW Overwrite
PCN
Present Cylinder
Number
POLL Polling Disable
PRETRK
Precompensation
Start Track
Number
R Sector Address
RCN
Relative Cylinder
Number
SC
Number of
Sectors Per Track
SK Skip Flag
SRT Step Rate Interval
ST0
ST1
ST2
ST3
Status 0
Status 1
Status 2
Status 3
WGATE Write Gate
This specifies the number of bytes in a sector. If this parameter is
"00", then the sector size is 128 bytes. The number of bytes
transferred is determined by the DTL parameter. Otherwise the
sector size is (2 raised to the "N'th" power) times 128. All values up
to "07" hex are allowable. "07"h would equal a sector size of 16k.
It is the user's responsibility to not select combinations that are not
possible with the drive.
N SECTOR SIZE
00 128 Bytes
01 256 Bytes
02 512 Bytes
03 1024 Bytes
… …
07 16K Bytes
The desired cylinder number.
Write ‘0’. This part does not support non-DMA mode.
The bits D0-D3 of the Perpendicular Mode Command can only be
modified if OW is set to 1. OW id defined in the Lock command.
The current position of the head at the completion of Sense
Interrupt Status command.
When set, the internal polling routine is disabled. When clear,
polling is enabled.
Programmable from track 00 to FFH.
The sector number to be read or written. In multi-sector transfers,
this parameter specifies the sector number of the first sector to be
read or written.
Relative cylinder offset from present cylinder as used by the
Relative Seek command.
The number of sectors per track to be initialized by the Format
command. The number of sectors per track to be verified during a
Verify command when EC is set.
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If
Read Deleted is executed, only sectors with a deleted address
mark will be accessed. When set to “0”, the sector is read or
written the same as the read and write commands.
The time interval between step pulses issued by the FDC.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at
the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Registers within the FDC which store status information after a
command has been executed. This status information is available
to the host during the result phase after command execution.
Alters timing of WE to allow for pre-erase loads in perpendicular
drives.
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6.10.1 Instruction Set
Table 6.17 - Instruction Set
READ DATA
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W MT MFM SK 0 0 1 1 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W C Sector ID information prior to
W H
W R
W N
W EOT
W GPL
W DTL
Execution Data transfer between the
Result R ST0 Status information after Com-
R ST1
R ST2
R C Sector ID information after
R H
R R
R N
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W MT MFM SK 0 1 1 0 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W C Sector ID information prior to
W H
W R
W N
W EOT
W GPL
W DTL
Execution Data transfer between the
Result R ST0 Status information after Com-
R ST1
R ST2
R C Sector ID information after
R H
R R
R N
DATA BUS
READ DELETED DATA
DATA BUS
Command execution.
FDD and system.
mand execution.
Command execution.
Command execution.
FDD and system.
mand execution.
Command execution.
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PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W MT MFM 0 0 0 1 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W C Sector ID information prior to
W H
W R
W N
W EOT
W GPL
W DTL
Execution Data transfer between the
Result R ST0 Status information after Com-
R ST1
R ST2
R C Sector ID information after
R H
R R
R N
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W MT MFM 0 0 1 0 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W C Sector ID information
W H
W R
W N
W EOT
W GPL
W DTL
Execution Data transfer between
Result R ST0 Status information after
R ST1
R ST2
R C Sector ID information
R H
R R
R N
WRITE DATA
DATA BUS
WRITE DELETED DATA
DATA BUS
Command execution.
FDD and system.
mand execution.
Command execution.
prior to Command
execution.
the FDD and system.
Command execution.
after Command
execution.
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READ A TRACK
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 MFM 0 0 0 0 1 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W C Sector ID information
prior to Command
execution.
W H
W R
W N
W EOT
W GPL
W DTL
Execution Data transfer between
the FDD and system.
FDC reads all of
cylinders’ contents from
index hole to EOT.
Result R ST0 Status information after
Command execution.
R ST1
R ST2
R C Sector ID information
after Command
execution.
R H
R R
R N
VERIFY
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W MT MFM SK 1 0 1 1 0 Command Codes
W EC 0 0 0 0 HDS DS1 DS0
W C Sector ID information
prior to Command
execution.
W H
W R
W N
W EOT
W GPL
W DTL/SC
Execution No data transfer takes
place.
Result R ST0 Status information after
Command execution.
R ST1
R ST2
R C Sector ID information
after Command
execution.
R H
R R
R N
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Datasheet
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 1 0 0 0 0 Command Code
Result R 1 0 0 1 0 0 0 0 Enhanced Controller
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 MFM 0 0 1 1 0 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W N Bytes/Sector
W SC Sectors/Cylinder
W GPL Gap 3
W D Filler Byte
Execution for
W C Input Sector Parameters
Each Sector
Repeat:
W H
W R
W N
FDC formats an entire
Result R ST0 Status information after
R ST1
R ST2
R Undefined
R Undefined
R Undefined
R Undefined
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 0 1 1 1 Command Codes
W 0 0 0 0 0 0 DS1 DS0
Execution Head retracted to Track 0
SENSE INTERRUPT STATUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 1 0 0 0 Command Codes
Result R ST0 Status information at the end
R PCN
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 0 0 1 1 Command Codes
W SRT HUT
W HLT ND
VERSION
DATA BUS
FORMAT A TRACK
DATA BUS
RECALIBRATE
DATA BUS
DATA BUS
SPECIFY
DATA BUS
cylinder
Command execution
Interrupt.
of each seek operation.
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SENSE DRIVE STATUS
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 0 1 0 0 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
Result R ST3 Status information about
FDD
SEEK
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 1 1 1 1 Command Codes
W 0 0 0 0 0 HDS DS1 DS0
W NCN
Execution Head positioned over
proper cylinder on
diskette.
CONFIGURE
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 1 0 0 1 1 Configure
Information
W 0 0 0 0 0 0 0 0
W 0 EIS EFIFO POLL FIFOTHR
Execution W PRETRK
RELATIVE SEEK
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 1 DIR 0 0 1 1 1 1
W 0 0 0 0 0 HDS DS1 DS0
W RCN
DUMPREG
DATA BUS
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 0 1 1 1 0 *Note:
Registers
placed in
FIFO
Execution
Result R PCN-Drive 0
R PCN-Drive 1
R PCN-Drive 2
R PCN-Drive 3
R SRT HUT
R HLT ND
R SC/EOT
R LOCK 0 D3 D2 D1 D0 GAP WGATE
R 0 EIS EFIFO POLL FIFOTHR
R PRETRK
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PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 MFM 0 0 1 0 1 0 Commands
W 0 0 0 0 0 HDS DS1 DS0
Execution The first correct ID
Result R ST0 Status information after
R ST1
R ST2
R C
R H
R R
R N
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W 0 0 0 1 0 0 1 0 Command Codes
OW 0 D3 D2 D1 D0 GAP WGATE
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W Invalid Codes Invalid Command Codes
Result R ST0 ST0 = 80H
PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS
Command W LOCK 0 0 1 0 1 0 0 Command Codes
Result R 0 0 0 LOCK 0 0 0 0
READ ID
DATA BUS
PERPENDICULAR MODE
DATA BUS
INVALID CODES
DATA BUS
LOCK
DATA BUS
information on the
Cylinder is stored in
Data Register
Command execution.
Disk status after the
Command has
completed
(NoOp – FDC goes into
Standby State)
SC is returned if the last command that was issued was the Format command. EOT is returned if the last
command was a Read or Write.
Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user’s
responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 62 SMSC LPC47M172
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Datasheet
6.11 Data Transfer Commands
All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the
same results information, the only difference being the coding of bits 0-4 in the first byte.
An implied seek will be executed if the feature was enabled by the Configure command. This seek is
completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status
Register during the seek portion of the command. If the seek portion fails, it is reflected in the results
status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error
code and C would contain the cylinder on which the seek failed.
6.11.1 Read Data
A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data
command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head
settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When
the sector address read off the diskette matches with the sector address specified in the command, the
FDC reads the sector’s data field and transfers the data to the FIFO.
After completion of the read operation from the current sector, the sector address is incremented by one
and the data from the next logical sector is read and output via the FIFO. This continuous read function is
called “Multi-Sector Read Operation”. Upon receipt of the TC cycle, or an implied TC (FIFO
overrun/underrun), the FDC stops sending data but will continue to read data from the current sector,
check the CRC bytes, and at the end of the sector, terminate the Read Data Command.
N determines the number of bytes per sector (see Table 6.18 below). If N is set to zero, the sector size is
set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the
FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N
is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred.
Table 6.18 - Sector Sizes
N SECTOR SIZE
00
01
02
03
..
07
The amount of data which can be handled with a single command to the FDC depends upon MT (multitrack) and N (number of bytes/sector).
The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular
cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same
track at Side 1.
128 bytes
256 bytes
512 bytes
1024 bytes
…
16 Kbytes
If the host terminates a read or write operation in the FDC, the ID information in the result phase is
dependent upon the state of the MT bit and EOT byte. Refer to Table 6.19.
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At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time
Interval (specified in the Specify command) has elapsed. If the host issues another command before the
head unloads, then the head settling time may be saved between subsequent reads.
If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the
diskette’s index hole passes through index detect logic in the drive twice), the FDC sets the IC code in
Status Register 0 to “01” indicating abnormal termination, sets the ND bit in Status Register 1 to “1”
indicating a sector not found, and terminates the Read Data Command.
After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs
in the ID or data field, the FDC sets the IC code in Status Register 0 to “01” indicating abnormal
termination, sets the DE bit flag in Status Register 1 to “1”, sets the DD bit in Status Register 2 to “1” if
CRC is incorrect in the ID field, and terminates the Read Data Command. Table 6.20 describes the effect
of the SK bit on the Read Data command execution and results. Except where noted in Table 6.20, the C
or R value of the sector address is automatically incremented (see Table 6.22).
Table 6.19 - Effects of MT and N Bits
MT N
0
1
0
1
0
1
SK BIT
VALUE
0
0
1
1
MAXIMUM TRANSFER
CAPACITY
256 x 26 = 6,656
1
256 x 52 = 13,312
1
512 x 15 = 7,680
2
512 x 30 = 15,360
2
1024 x 8 = 8,192
3
1024 x 16 = 16,384
3
Table 6.20 - Skip Bit vs Read Data Command
DATA ADDRESS
MARK TYPE
ENCOUNTERED
Normal Data
Deleted Data
Normal Data
Deleted Data
SECTOR
READ?
Yes
Yes
Yes
No
FINAL SECTOR READ
FROM DISK
26 at side 0 or 1
26 at side 1
15 at side 0 or 1
15 at side 1
8 at side 0 or 1
16 at side 1
RESULTS
CM BIT OF
ST2 SET?
No
Yes
No
Yes
DESCRIPTION
OF RESULTS
Normal
termination.
Address not
incremented. Next
sector not
searched for.
Normal
termination.
Normal
termination.
Sector not read
(“skipped”).
6.12 Read Deleted Data
This command is the same as the Read Data command, only it operates on sectors that contain a Deleted
Data Address Mark at the beginning of a Data Field.
Table 6.21 describes the effect of the SK bit on the Read Deleted Data command execution and results.
Except where noted in Table 6.21, the C or R value of the sector address is automatically incremented
(see Table 6.22).
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Table 6.21 - Skip Bit vs. Read Deleted Data Command
SK BIT
VALUE
0
0
1
1
DATA ADDRESS
ENCOUNTERED
6.13 Read A Track
This command is similar to the Read Data command except that the entire data field is read continuously
from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC
starts to read all data fields on the track as continuous blocks of data without regard to logical sector
numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the
track and sets the appropriate error bits at the end of the command. The FDC compares the ID
information read from each sector with the specified value in the command and sets the ND flag of Status
Register 1 to a “1” if there no comparison. Multi-track or skip operations are not allowed with this
command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be
set to “0”.
MARK TYPE
Normal Data
Deleted Data
Normal Data
Deleted Data
SECTOR
READ?
Yes
Yes
No
Yes
RESULTS
CM BIT OF
ST2 SET?
Yes
No
Yes
No
DESCRIPTION
OF RESULTS
Address not
incremented. Next
sector not
searched for.
Normal
termination.
Normal
termination.
Sector not read
(“skipped”).
Normal
termination.
This command terminates when the EOT specified number of sectors has not been read. If the FDC does
not find an ID Address Mark on the diskette after the second occurrence of a pulse on the nINDEX pin,
then it sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status
Register 1 to “1”, and terminates the command.
Table 6.22 - Result Phase Table
MT
0 0 Less than EOT NC NC R + 1 NC
Equal to EOT C + 1 NC 01 NC
1 Less than EOT NC NC R + 1 NC
Equal to EOT C + 1 NC 01 NC
1 0 Less than EOT NC NC R + 1 NC
Equal to EOT NC LSB 01 NC
1 Less than EOT NC NC R + 1 NC
Equal to EOT C + 1 LSB 01 NC
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
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HEAD
FINAL SECTOR
TRANSFERRED TO
HOST C H R N
ID INFORMATION AT RESULT PHASE
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6.14 Write Data
After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state),
waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID
fields. When the sector address read from the diskette matches the sector address specified in the
command, the FDC reads the data from the host via the FIFO and writes it to the sector’s data field.
After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field
at the end of the sector transfer. The Sector Number stored in “R” is incremented by one, and the FDC
continues writing to the next data field. The FDC continues this “Multi-Sector Write Operation”. Upon
receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then
the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks
the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to
“01” (abnormal termination), sets the DE bit of Status Register 1 to “1”, and terminates the Write Data
command.
The Write Data command operates in much the same manner as the Read Data command. The following
items are the same. Please refer to the Read Data Command for details:
Transfer Capacity
EN (End of Cylinder) bit
ND (No Data) bit
Head Load, Unload Time Interval
ID information when the host terminates the command
Definition of DTL when N = 0 and when N does not = 0
6.15 Write Deleted Data
This command is almost the same as the Write Data command except that a Deleted Data Address Mark
is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is
typically used to mark a bad sector containing an error on the floppy disk.
6.16 Verify
The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read
Data command except that no data is transferred to the host. Data is read from the disk and CRC is
computed and checked against the previously-stored value.
Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By
setting the EC bit to “1”, an implicit TC will be issued to the FDC. This implicit TC will occur when the
SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be
terminated by setting the EC bit to “0” and the EOT value equal to the final sector to be checked. If EC is
set to “0”, DTL/SC should be programmed to 0FFH. Refer to Table 6.22 and Table 6.23 for information
concerning the values of MT and EC versus SC and EOT value.
Definitions:
# Sectors Per Side = Number of formatted sectors per each side of the disk.
# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the
disk if MT is set to “1”.
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Table 6.23 - Verify Command Result Phase Table
MT EC SC/EOT VALUE TERMINATION RESULT
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: If MT is set to “1” and the SC value is greater than the number of remaining formatted sectors on Side 0,
verifying will continue on Side 1 of the disk.
SC = DTL
EOT <= # Sectors Per Side
SC = DTL
EOT > # Sectors Per Side
SC <= # Sectors Remaining AND
EOT <= # Sectors Per Side
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
SC = DTL
EOT <= # Sectors Per Side
SC = DTL
EOT > # Sectors Per Side
SC <= # Sectors Remaining AND
EOT <= # Sectors Per Side
SC > # Sectors Remaining OR
EOT > # Sectors Per Side
Success Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
Successful Termination
Result Phase Valid
Unsuccessful Termination
Result Phase Invalid
6.17 Format A Track
The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is
detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields
per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written
to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are
specified by the host during the command phase. The data field of the sector is filled with the data byte
specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are
needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively).
After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next
sector on the track. The R value (sector number) is the only value that must be changed by the host after
each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses
(interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a
pulse on the nINDEX pin again and it terminates the command.
Table 6.24 contains typical values for gap fields that are dependent upon the size of the sector and the
number of sectors on each track. Actual values can vary due to drive electronics.
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SYSTEM 34 (DOUBLE DENSITY) FORMAT
GAP4a
SYNC
80x
4E
3x
IAM GAP1
12x
00
C2
50x
FC 3xA1FE 3xA1FBF8
4E
SYNC
12x
00
SYSTEM 3740 (SINGLE DENSITY) FORMAT
GAP4a
SYNC
40x
FF
FC FE FB or
GAP4a
SYNC
80x
4E
3x
6x
00
12x
00
IAM GAP1
26x
IAM GAP1
50x
FC 3xA1FE 3xA1FBF8
C2
FF
4E
SYNC
6x
00
SYNC
12x
00
Table 6.24 - Typical Values for Formatting
FORMAT FIELDS
IDAM C
IDAM C
H
S
N
C
GAP2
Y
D
E
O
R
22x
L
C
C
4E
GAP2
C
S
N
H
11x
R
E
Y
L
O
D
C
C
FF
PERPENDICULAR FORMAT
IDAM C
H
S
N
C
GAP2
Y
D
E
O
R
41x
L
C
C
4E
SYNC
12x
00
SYNC
6x
00
SYNC
12x
00
DATA
AM
DATA
AM
F8
DATA
AM
C
DATA
R
GAP3
GAP 4b
C
C
GAP 4b
GAP3
R
DATA
C
C
DATA
R
GAP3
GAP 4b
C
5.25” Drives
3.5” Drives
FORMAT SECTOR SIZE N SC GPL1 GPL2
FM
MFM
FM
MFM
128
128
512
1024
2048
4096
...
256
256
512*
1024
2048
4096
...
128
256
512
256
512**
1024
00
00
02
03
04
05
...
01
01
02
03
04
05
...
0
1
2
1
2
3
12
10
08
04
02
01
12
10
09
04
02
01
0F
09
05
0F
09
05
07
10
18
46
C8
C8
0A
20
2A
80
C8
C8
07
0F
1B
0E
1B
35
09
19
30
87
FF
FF
0C
32
50
F0
FF
FF
1B
2A
3A
36
54
74
GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and
ID field of contiguous sections.
GPL2 = suggested GPL value in Format A Track command.
*PC/AT values (typical)
**PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.
Note: All values except sector size are in hex.
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6.18 Control Commands
Control commands differ from the other commands in that no data transfer takes place. Three commands
generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do
not generate an interrupt.
6.18.1 Read ID
The Read ID command is used to find the present position of the recording heads. The FDC stores the
values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark
on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in
Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates
the command.
The following commands will generate an interrupt upon completion. They do not return any result bytes.
It is highly recommended that control commands be followed by the Sense Interrupt Status command.
Otherwise, valuable interrupt status information will be lost.
6.18.2 Recalibrate
This command causes the read/write head within the FDC to retract to the track 0 position. The FDC
clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as
the nTRK0 pin is low, the DIR signal remains 0 and step pulses are issued. When the nTRK0 pin goes
high, the SE bit in Status Register 0 is set to “1” and the command is terminated. If the nTRK0 pin is still
low after 255 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to
“1” and terminates the command. Disks capable of handling more than 256 tracks per side may require
more than one Recalibrate command to return the head back to physical Track 0.
The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be
issued after the Recalibrate command to effectively terminate it and to provide verification of the head
position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but
during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be
issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon
power up, the software must issue a Recalibrate command to properly initialize all drives and the
controller.
6.18.3 Seek
The read/write head within the drive is moved from track to track under the control of the Seek command.
The FDC compares the PCN, which is the current head position, with the NCN and performs the following
operation if there is a difference:
PCN < NCN: Direction signal to drive set to “1” (step in) and issues step pulses.
PCN > NCN: Direction signal to drive set to “0” (step out) and issues step pulses.
The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify
command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE
bit in Status Register 0 is set to “1” and the command is terminated. During the command phase of the
seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the
NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner,
parallel seek operations may be done on up to four drives at once.
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Note that if implied seek is not enabled, the read and write commands should be preceded by:
1. Seek command - Step to the proper track
2. Sense Interrupt Status command - Terminate the Seek command
3. Read ID - Verify head is on proper track
4. Issue Read/Write command.
The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense
Interrupt Status command is issued after the Seek command to terminate it and to provide verification of
the head position (PCN). The H bit (Head Address) in ST0 will always return to a “0”. When exiting
POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing
the POWERDOWN command, it is highly recommended that the user service all pending interrupts
through the Sense Interrupt Status command.
6.19 Sense Interrupt Status
An interrupt signal is generated by the FDC for one of the following reasons:
1. Upon entering the Result Phase of:
a. Read Data command
b. Read A Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format A Track command
g. Write Deleted Data command
h. Verify command
2. End of Seek, Relative Seek, or Recalibrate command
The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status
Register 0, identifies the cause of the interrupt.
Table 6.25 - Interrupt Identification
SE IC INTERRUPT DUE TO
Polling
0
1
1
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status
command must be issued immediately after these commands to terminate them and to provide verification
of the head position (PCN). The H (Head Address) bit in ST0 will always return a “0”. If a Sense Interrupt
Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 70 SMSC LPC47M172
11
00
Normal termination of Seek
or Recalibrate command
Abnormal termination of
Seek or Recalibrate
01
command
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6.20 Sense Drive Status
Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the
result phase from the command phase. Status Register 3 contains the drive status information.
6.21 Specify
The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload
Time) defines the time from the end of the execution phase of one of the read/write commands to the head
unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that
the spacing between the first and second step pulses may be shorter than the remaining step pulses. The
HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write
operation starts. The values change with the data rate speed selection and are documented in Table 6.26.
The values are the same for MFM and FM.
DMA operation is selected by the ND bit. When ND is “0”, the DMA mode is selected. This part does not
support non-DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles.
6.22 Configure
The Configure command is issued to select the special features of the FDC. A Configure command need
not be issued if the default values of the FDC meet the system requirements.
Table 6.26 - Drive Control Delays (ms)
2M 1M 500K 300K 250K 2M 1M 500K 300K 250K
128
64
0
4
1
..
..
56
E
60
F
00
01
02
..
7F
7F
8
..
112
120
2M 1M 500K 300K 250K
64
0.5
1
..
63
63.5
HUT
256
16
..
224
240
128
1
2
..
126
127
6.22.1 Configure Default Values
426
26.7
..
373
400
512
32
..
448
480
256
252
254
2
4
..
4
3.75
..
0.5
0.25
HLT
8
7.5
..
1
0.5
426
3.3
6.7
..
420
423
16
15
..
2
1
SRT
26.7
25
..
3.33
1.67
32
30
..
4
2
512
4
8
.
504
508
EIS - No Implied Seeks
EFIFO - FIFO Disabled
POLL - Polling Enabled
FIFOTHR - FIFO Threshold Set to 1 Byte
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PRETRK - Pre-Compensation Set to Track 0
EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a
read or write command. Defaults to no implied seek.
EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte
basis. Defaults to "1", FIFO disabled. The threshold defaults to "1".
POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is
generated after a reset. No polling is performed while the drive head is loaded and the head unload delay
has not expired.
FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable
from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.
PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track
0. A "00" selects track 0; "FF" selects track 255.
6.23 Version
The Version command checks to see if the controller is an enhanced type or the older type (765A). A
value of 90 H is returned as the result byte.
6.24 Relative Seek
The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit.
DIR Head Step Direction Control
RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the
current track number.
The Relative Seek command differs from the Seek command in that it steps the head the absolute number
of tracks specified in the command instead of making a comparison against an internal register. The Seek
command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped
with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be
overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek
attempts to step outward beyond Track 0.
As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and
the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a
Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless
of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the
maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial
track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is
255 (D).
DIR ACTION
0
1
Step Head Out
Step Head In
The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D).
The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0
again as the track number goes above 255 (D). It is the user’s responsibility to compensate FDC functions
(precompensation track number) when accessing tracks greater than 255. The FDC does not keep track
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that it is working in an “extended track area” (greater than 255). Any command issued will use the current
PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will
return an error if the head is farther than 255 due to its limitation of issuing a maximum of 256 step pulses.
The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks
will function correctly within the 44 (D) track (299-255) area of the “extended track area”. It is the user’s
responsibility not to issue a new track position that will exceed the maximum track that is present in the
extended area.
To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the
track 255 boundary.
A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the
difference between the current head location and the new (target) head location. This may require the
host to issue a Read ID command to ensure that the head is physically on the track that software assumes
it to be. Different FDC commands will return different cylinder results which may be difficult to keep track
of with software without the Read ID command.
6.25 Perpendicular Mode
The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that
access a disk drive with perpendicular recording capability. With this command, the length of the Gap2
field and VCO enable timing can be altered to accommodate the unique requirements of these drives.
Table 6.27 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command.
Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0).
Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate
selected in the Data Rate Select Register. The user must ensure that these two data rates remain
consistent.
The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design
of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head
by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density.
Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the
same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the
first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To
accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41
bytes. The Format Fields table illustrates the change in the Gap2 field size for the perpendicular format.
On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field.
For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the
start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1,
GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both
cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the
purposes of avoiding write splices in the presence of motor speed variation.
For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the
conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC.
With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to
insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1),
38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes
will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0).
It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal
program flow. The information provided here is just for background purposes and is not needed for normal
operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user
standpoint is unchanged.
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The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular
recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives
without having to issue Perpendicular mode commands between the accesses of the different drive types,
nor having to change write pre-compensation values.
When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to
“0” (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to “1” for that
drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also
apply:
1. The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed
data rate.
2. The write pre-compensation given to a perpendicular mode drive will be 0ns.
3. For D0-D3 programmed to “0” for conventional mode drives any data written will be at the currently
programmed write pre-compensation.
Note: Bits D0-D3 can only be overwritten when OW is programmed as a “1”.If either GAP or WGATE is a “1”
then D0-D3 are ignored.
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:
“Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3
are unaffected and retain their previous value.
“Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e all conventional mode.
Table 6.27 - Effects of WGATE and GAP Bits
6.26 Lock
In order to protect systems with long DMA latencies against older application software that can disable the
FIFO the LOCK Command has been added. This command should only be used by the FDC routines,
and application software should refrain from using it. If an application calls for the FIFO to be disabled
then the CONFIGURE command should be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic
“1” all subsequent “software RESETS by the DOR and DSR registers will not change the previously set
parameters to their default values. All “hardware” RESET from the nPCI_RESET pin will set the LOCK bit
to logic “0” and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is
returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by
the command byte.
WGATE GAP MODE
Conventional
0
0
1
1
0
Perpendicular
1
(500 Kbps)
Reserved
0
(Conventional)
Perpendicular
1
(1 Mbps)
LENGTH OF
GAP2 FORMAT
FIELD
22 Bytes
22 Bytes
22 Bytes
41 Bytes
PORTION OF
GAP 2
WRITTEN BY
WRITE DATA
OPERATION
0 Bytes
19 Bytes
0 Bytes
38 Bytes
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6.27 Enhanced DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software
development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR
MODE command the eighth byte of the DUMPREG command has been modified to contain the additional
data from these two commands.
6.27.1 Compatibility
The LPC47M172 was designed with software compatibility in mind. It is a fully backwards- compatible
solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for
compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a
hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2
Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the
system BIOS.
6.28 Serial Port (UART)
The LPC47M172 incorporates two full function UARTs. They are compatible with the 16450, the 16450
ACE registers and the 16C550A. The UARTs perform serial-to-parallel conversion on received characters
and parallel-to-serial conversion on transmit characters. The data rates are independently programmable
from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop
bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs contain a programmable baud
rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The
UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for
information on disabling, power down and changing the base address of the UARTs. The interrupt from a
UART is enabled by programming OUT2 of that UART to a logic “1”. OUT2 being a logic “0” disables that
UART’s interrupt. The second UART also supports IrDA, HP-SIR, and ASK-IR infrared modes of
operation.
Note: Input pins of Serial Port 2 are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial
Port 2 is enabled, the pull-downs are removed until VTR POR.
6.28.1 Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
port is defined by the configuration registers (see “Configuration” section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses (see Table 6.28).
Table 6.28 - Addressing the Serial Port
DLAB* A2 A1 A0 REGISTER NAME
0 0 0 0 Receive Buffer (read)
0 0 0 0 Transmit Buffer (write)
0 0 0 1 Interrupt Enable (read/write)
X 0 1 0 Interrupt Identification (read)
X 0 1 0 FIFO Control (write)
X 0 1 1 Line Control (read/write)
X 1 0 0 Modem Control (read/write)
X 1 0 1 Line Status (read/write)
X 1 1 0 Modem Status (read/write)
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DLAB* A2 A1 A0 REGISTER NAME
X 1 1 1 Scratchpad (read/write)
1 0 0 0 Divisor LSB (read/write)
1 0 0 1 Divisor MSB (read/write
*Note: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
6.28.2 Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted
and received first. Received data is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register.
The shift register is not accessible.
6.28.3 Transmit Buffer Register (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an
additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register
is loaded from the Transmit Buffer when the transmission of the previous byte is complete.
6.28.4 Interrupt Enable Register (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port
interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register.
Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled.
Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port
interrupt out of the LPC47M172. All other system functions operate in their normal manner, including the
Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described
below.
Bit 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set
to logic “1”.
Bit 1
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
Bit 2
This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the
interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the
source.
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Bit 3
This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the
Modem Status Register bits changes state.
Bits 4 through 7
These bits are always logic “0”.
6.28.5 FIFO Control Register (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear the
FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART is shadowed in the
UART1 FIFO Control Shadow Register (Power Control/Runtime Register at offset 0x1A).
Bit 0
Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0”
disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO
Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when
other bits in this register are written to or they will not be properly programmed.
Bit 1
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift
register is not cleared. This bit is self-clearing.
Bit 2
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift
register is not cleared. This bit is self-clearing.
Bit 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not
available on this chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the trigger level for the RCVR FIFO interrupt.
6.28.6 Interrupt Identification Register (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four
levels of priority interrupt exist. They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
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Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the
Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the
Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this
CPU access, even if the Serial Port records new interrupts, the current indication does not change until
access is completed. The contents of the IIR are described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt
is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a
pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table.
Bit 3
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic “0”.
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
FIFO
MODE
ONLY
BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 1 - None None -
0 1 1 0 Highest
0 1 0 0 Second
Bit 7 Bit 6
RCVR FIFO
Trigger Level (BYTES)
0 0 1
0 1 4
1 0 8
1 1 14
Table 6.29 - Interrupt Control Table
INTERRUPT
IDENTIFICATION
REGISTER
PRIORIT
Y LEVEL
INTERRUPT SET AND RESET FUNCTIONS
INTERRUPT
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET
CONTROL
Overrun Error,
Receiver Line
Status
Parity Error,
Framing Error or
Reading the Line
Status Register
Break Interrupt
Read Receiver
Received Data
Available
Receiver Data
Available
Buffer or the FIFO
drops below the
trigger level.
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FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
No Characters
Have Been
Removed From or
Input to the
RCVR FIFO
during the last 4
Char times and
Reading the
Receiver Buffer
Register
1 1 0 0 Second
Character
Timeout
Indication
there is at least 1
char in it during
this time
Reading the IIR
Register (if
Source of
Interrupt) or
Writing the
Transmitter
0 0 1 0 Third
Transmitter
Holding
Register
Empty
Transmitter
Holding Register
Empty
Holding Register
Clear to Send or
0 0 0 0 Fourth
MODEM
Status
Data Set Ready
or Ring Indicator
or Data Carrier
Reading the
MODEM Status
Register
Detect
6.28.7 Line Control Register (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
Start LSB Data 5-8 bits MSB Parity Stop
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of
bits 0 and 1 is as follows:
The Start, Stop and Parity bits are not included in the word length.
BIT 1 BIT 0 WORD LENGTH
0
0
1
1
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following
table summarizes the information.
Serial Data
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
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BIT 2 WORD LENGTH
NUMBER OF
STOP BITS
0 -- 1
1 5 bits 1.5
1 6 bits 2
1 7 bits 2
1 8 bits 2
Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to
generate an even or odd number of 1s when the data word bits and the parity bit are summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is
transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic
“1” an even number of bits is transmitted and checked.
Bit 5
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or
Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space
Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark
Parity). If bit 5 is 0 Stick Parity is disabled.
Bit 6
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or
logic “0” state and remains there (until reset by a low level bit 6) regardless of other transmitter activity.
This feature enables the Serial Port to alert a terminal in a communications system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set high (logic “1”) to access the Divisor Latches of the Baud
Rate Generator during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer
Register, the Transmitter Holding Register, or the Interrupt Enable Register.
6.28.8 Modem Control Register (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The
contents of the MODEM control register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output
is forced to a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”.
Bit 1
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical
to that described above for bit 0.
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Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or
written by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port
interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port
interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic
“1”, the following occur:
1. The TXD is set to the Marking State(logic “1”).
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is “looped back” into the Receiver Shift Register input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI, DCD).
6. The Modem Control output pins are forced inactive high.
7. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the
diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control
Interrupts are also operational but the interrupts’ sources are now the lower four bits of the MODEM
Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt
Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
6.28.9 Line Status Register (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic “1” whenever a complete incoming character has been received and
transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic “0” by reading all of the
data in the Receive Buffer Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next
character was transferred into the register, thereby destroying the previous character. In FIFO mode, an
overrun error will occur only when the FIFO is full and the next character has been completely received in
the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE
indicator is set to a logic “1” immediately upon detection of an overrun condition, and reset whenever the
Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd
parity, as selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error
and is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is
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associated with the particular character in the FIFO it applies to. This error is indicated when the
associated character is at the top of the FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to
a logic “1” whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing
level). The FE is reset to a logic “0” whenever the Line Status Register is read. In the FIFO mode this
error is associated with the particular character in the FIFO it applies to. This error is indicated when the
associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing
error. To do this, it assumes that the framing error was due to the next start bit, so it samples this ‘start’ bit
twice and then takes in the ‘data’.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic “1” whenever the received data input is held in the Spacing state
(logic “0”) for longer than a full word transmission time (that is, the total time of the start bit + data bits +
parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the
FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO. When break occurs only one zero
character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be
logic “1” for at least ½ bit time.
Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new
character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the
Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic “1” when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is
reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is
set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a
read only bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR)
and Transmitter Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR or
TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the
THR and TSR are both empty,
Bit 7
This bit is permanently set to logic “0” in the 450 mode. In the FIFO mode, this bit is set to a logic “1” when
there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the
LSR is read if there are no subsequent errors in the FIFO.
6.28.10 Modem Status Register (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE
This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In
addition to this current state information, four bits of the MODEM Status Register (MSR) provide change
information. These bits are set to logic “1” whenever a control input from the MODEM changes state. They
are reset to logic “0” whenever the MODEM Status Register is read.
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Bit 0
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the
last time the MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time
the MSR was read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic “0” to logic
“1”.
Bit 3
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to a logic “1”, a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic “1”, this bit
is equivalent to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic “1”, this
bit is equivalent to DTR in the MCR.
Bit 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic “1”, this bit is
equivalent to OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic “1”,
this bit is equivalent to OUT2 in the MCR.
6.28.11 Scratchpad Register (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a
scratchpad register to be used by the programmer to hold data temporarily.
6.29 Programmable Baud Rate Generator (And Divisor Latches DLH,
DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL
clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz
frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for
230.4k and a 7.3728MHz frequency for 460.8k. This output frequency of the Baud Rate Generator is 16x
the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be
loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading
either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on
initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is
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loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal
with a 50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of
the count. The input clock to the BRG is a 1.8462 MHz clock. Table 6.30 shows the baud rates possible.
6.29.1 Effect Of The Reset on Register File
The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port.
6.29.2 FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR
interrupts occur as follows:
A. The receive data available interrupt will be issued when the FIFO has reached its programmed trigger
level; it is cleared as soon as the FIFO drops below its programmed trigger level.
B. The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is
cleared when the FIFO drops below the trigger level.
C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available
(IIR=04H) interrupt.
D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the
RCVR FIFO. It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:
A. A FIFO timeout interrupt occurs if all the following conditions exist:
At least one character is in the FIFO.
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop
bits are programmed, the second one is included in this time delay).
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a
12 bit character.
B. Character times are calculated by using the RCLK input for a clock signal (this makes the delay
proportional to the baud rate).
C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one
character from the RCVR FIFO.
D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received
or after the CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT
interrupts occur as follows:
A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as
soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT
FIFO while servicing this interrupt) or the IIR is read.
B. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time
in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be
immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received
data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register
empty interrupt.
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6.29.3 FIFO Polled Mode Operation
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of
operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the
polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the
LSR. LSR definitions for the FIFO Polled Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way
as when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
Table 6.30 - Baud Rates
DESIRED
BAUD RATE
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50 2304 0.001 X
75 1536 - X
110 1047 - X
134.5 857 0.004 X
150 768 - X
300 384 - X
600 192 - X
1200 96 - X
1800 64 - X
2000 58 0.005 X
2400 48 - X
3600 32 - X
4800 24 - X
7200 16 - X
9600 12 - X
19200 6 - X
38400 3 0.030 X
57600 2 0.16 X
115200 1 0.16 X
230400 32770 0.16 1
460800 32769 0.16 1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
2
Note
: The High Speed bit is located in the Device Configuration Space.
1
SPEED BIT
HIGH
2
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Table 6.31 - Reset Function Table
REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt Enable Register RESET All bits low
Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 - 7 low
FIFO Control RESET All bits low
Line Control Reg. RESET All bits low
MODEM Control Reg. RESET All bits low
Line Status Reg. RESET All bits low except 5, 6 high
MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input
TXD1, TXD2 RESET High
INTRPT (RCVR errs) RESET/Read LSR Low
INTRPT (RCVR Data Ready) RESET/Read RBR Low
INTRPT (THRE) RESET/ReadIIR/Write THR Low
OUT2B RESET High
RTSB RESET High
DTRB RESET High
OUT1B RESET High
RCVR FIFO RESET/
XMIT FIFO RESET/
All Bits Low
FCR1*FCR0/_FCR0
All Bits Low
FCR1*FCR0/_FCR0
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Table 32 - Register Summary for an Individual UART Channel
REGISTER
ADDRESS
(Note 1)
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2 Interrupt Ident. Register (Read Only) IIR “0” if Interrupt
ADDR = 2 FIFO Control Register (Write Only) FCR (Note 8) FIFO Enable RCVR FIFO
ADDR = 3 Line Control Register LCR Word Length
ADDR = 4 MODEM Control Register MCR Data Terminal
ADDR = 5 Line Status Register LSR Data Ready
ADDR = 6 MODEM Status Register MSR Delta Clear to
ADDR = 7 Scratch Register (Note 5) SCR Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Receive Buffer Register (Read Only) RBR Data Bit 0
Transmitter Holding Register (Write Only) THR Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Interrupt Enable Register IER Enable
Divisor Latch (LS) DDL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Divisor Latch (MS) DLM Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
REGISTER NAME
REGISTER
SYMBOL
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
(Note 2)
Received
Data
Available
Interrupt
(ERDAI)
Pending
Select Bit 0
(WLS0)
Ready (DTR)
(DR)
Send (DCTS)
Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(DDSR)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt ID
Bit
XMIT FIFO
Reset
Number of
Stop Bits
(STB)
OUT1
(Note 4)
Parity Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Enable
MODEM
Status
Interrupt
(EMSI)
Interrupt ID
(Note 6)
Bit
DMA Mode
Select
(Note 7)
Parity
Enable
(PEN)
OUT2
(Note 4)
Framing
Error (FE)
Delta Data
Carrier
Detect
(DDCD)
0 0 0 0
0 0 FIFOs
Reserved Reserved RCVR Trigger
Even Parity
Select
(EPS)
Loop 0 0 0
Break
Interrupt
(BI)
Clear to
Send (CTS)
Stick Parity Set Break Divisor
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Enabled
(Note 6)
LSB
Transmitter
Empty
(TEMT)
(Note 3)
Ring Indicator
(RI)
FIFOs
Enabled
(Note 6)
RCVR
Trigger
MSB
Latch
Access Bit
(DLAB)
Error in
RCVR
FIFO
(Note 6)
Data
Carrier
Detect
(DCD)
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Note 1 DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 2 Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 3 When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Note 4 This bit no longer has a pin associated with it.
Note 5 When operating in the XT mode, this register is not available.
Note 6 These bits are always zero in the non-FIFO mode.
Note 7 Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 8 The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
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Chapter 7 Notes On Serial Port Operation
7.1 FIFO Mode Operation:
7.1.1 General
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
7.1.2 TX and RX FIFO Operation
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx
FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the
Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These
capabilities account for the largely autonomous operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt
whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume
that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO
empty interrupt will transition from active to inactive. Depending on the execution speed of the service
routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the
CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART’s
interrupt line would transition to the active state. This could cause a system with an interrupt control unit to
record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore,
after the first byte has been loaded into the FIFO the UART will wait one serial character
transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt
delay will remain active until at least two bytes have been loaded into the FIFO, concurrently.
When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one
character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx
FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that
time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue
to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data
entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the
programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level
in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level.
No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the
software from having to check for this situation the chip incorporates a timeout interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor
the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout
interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful given
the higher baud rate capability (256 kbaud).
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7.2 Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission
medium. Several IR implementations have been provided for the second UART in this chip, IrDA, HP-SIR
and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or
optional IRTX2 and IRRX2 pins. These can be selected through the configuration registers.
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning
with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit
time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the
parameters of these pulses and the IrDA waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud.
Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz
waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit
time. Please refer to the AC timing for the parameters of the ASK-IR waveform.
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed.
This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the
timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is
restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is
being received, the transmission will not start until the time-out expires after the last receive bit has been
received. If the start bit of another character is received during this time-out, the timer is restarted after the
new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This
register allows the time-out to be programmed to any value between 0 and 10msec in 100usec
increments.
IR Transmit Pins
The following description pertains to the TXD2 and IRTX2 pins of the LPC47M172.
Following a VCC POR, the TXD2 and IRTX2 pins will be output and low. They will remain low until one of
the following conditions are met:
IRTX2 Pin
1. This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit,
at which time the pin will reflect the state of the IR transmit output of the IRCC block.
TXD2 Pin
1. This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit,
at which time the pin will reflect the state of the IR transmit output of the IRCC block (if IR is enabled
through the IR Option Register for Serial Port 2).
2. This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit,
at which time the pin will reflect the state of the transmit output of serial port 2.
7.3 Parallel Port
The LPC47M172 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2
type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities
Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power
down, changing the base address of the parallel port, and selecting the mode of operation.
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The Parallel Port configuration registers are summarized in Table 11.2 in the “Configuration” section. The
Parallel Port logical device configuration registers (0xF0 and 0xF1) are defined in Table 11.11.
The parallel port also incorporates SMSC’s ChiProtect circuitry, which prevents possible damage to the
parallel port due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their
associated registers and control gating. The control and data port are read/write by the CPU, the status
port is read/write in the EPP mode. The address map of the Parallel Port is shown below:
DATA PORT BASE ADDRESS + 00H EPP DATA PORT 0 BASE ADDRESS + 04H
STATUS PORT BASE ADDRESS + 01H EPP DATA PORT 1 BASE ADDRESS + 05H
CONTROL PORT BASE ADDRESS + 02H EPP DATA PORT 2 BASE ADDRESS + 06H
EPP ADDR PORT BASE ADDRESS + 03H EPP DATA PORT 3 BASE ADDRESS + 07H
The bit map of these registers is:
D0 D1 D2 D3 D4 D5 D6 D7 NOTE
DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1
STATUS
TMOUT 0 0 nERR SLCT PE nACK nBUSY 1
PORT
CONTROL
STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1
PORT
EPP ADDR
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2
PORT
EPP DATA
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2
PORT 0
EPP DATA
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2
PORT 1
EPP DATA
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2
PORT 2
EPP DATA
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2
PORT 3
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
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Table 7.1 - Parallel Port Connector
HOST
CONNECTOR
1 nSTROBE nWrite nStrobe
2-9 PD<0:7> PData<0:7> PData<0:7>
10 nACK Intr nAck
11 BUSY nWait Busy, PeriphAck(3)
12 PE (User Defined) PError,
13 SLCT (User Defined) Select
14 nALF nDatastb nAutoFd,
15 nERROR (User Defined) nFault (1)
16 nINITP nRESET nInit(1)
17
(1) = Compatible Mode
(3) = High Speed Mode
Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This
document is available from Microsoft.
SMSC
PIN NUMBER
See Chapter 3
Description of Pin
Functions.
nSLCTIN nAddrstrb nSelectIn(1,3)
STANDARD
EPP
ECP
nAckReverse (3)
HostAck(3)
nPeriphRequest (3)
nReverseRqst(3)
7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes
7.4.1 Data Port
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
7.4.2 Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode
Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘0’, writing a one to this bit clears
the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the
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Parallel Port Mode Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘1’, the
TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2
Are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
BIT 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0
means an error has been detected; a logic 1 means no error has been detected.
BIT 4 SLT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means
the printer is on line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a
paper end; a logic 0 indicates the presence of paper.
BIT 6 nACK - ACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means
that the printer has received a character and can now accept another. A logic 1 means that it is still
processing the last character or has not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register.
A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that
it is ready to accept the next character.
7.4.3 Control Port
ADDRESS OFFSET = 02H
The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized
by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed
after each line is printed. A logic 0 means no autofeed.
BIT 2 nINIT - INITIATE OUTPUT
This bit is output onto the nINITP output without inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0
means the printer is not selected.
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BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the
Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK
input. When the IRQE bit is programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out
regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port
is in output mode (write); a logic 1 means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
7.4.4 EPP Address Port
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is
cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an
EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP
write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP
ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of
ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP
mode.
7.4.5 EPP Data Port 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are
buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP
DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write
cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ
cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the
PData for the duration of the read cycle. This register is only available in EPP mode.
7.4.6 EPP Data Port 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
7.4.7 EPP Data Port 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
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7.4.8 EPP Data Port 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT 0
for a description of operation. This register is only available in EPP mode.
7.5 EPP 1.9 Operation
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are
also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the
standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP
Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is
required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of
the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is
aborted and the time-out condition is indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always
be in a write mode and the nWRITE signal to always be asserted.
7.5.1 Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic “0”
(i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic “1”, and
attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic “1”) and
will appear to perform an EPP read on the parallel bus, no error is indicated.
7.6 EPP 1.9 Write
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address
cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write
cycle can complete. The write cycle can complete under the following circumstances:
1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then
the write can complete when nWAIT goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is
determined inactive.
Write Sequence of Operation
1. The host initiates an I/O write cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the
WRITE signal is valid.
5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip
may begin the termination phase of the cycle.
6. a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase.
If it has not already done so, the peripheral should latch the information byte now.
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b) The chip latches the data from the internal data bus for the PData bus and drives the sync that
indicates that no more wait states are required followed by the TAR to complete the write cycle.
7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
8. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
7.7 EPP 1.9 Read
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts
wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The
read cycle can complete under the following circumstances:
1. If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can
complete when nWAIT goes inactive high.
2. If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before
changing the state of nWRITE or before nDATASTB goes active. The read can complete once
nWAIT is determined inactive.
Read Sequence of Operation
1. The host initiates an I/O read cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
3. The chip tri-states the PData bus and deasserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
5. Peripheral drives PData bus valid.
6. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase
of the cycle.
7. a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB
or nADDRSTRB. This marks the beginning of the termination phase.
b) The chip drives the sync that indicates that no more wait states are required and drives valid data
onto the LAD[3:0] signals, followed by the TAR to complete the read cycle.
8. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tristated.
9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
7.8 EPP 1.7 Operation
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes
are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in
the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is
required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of
the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the timeout condition is indicated in Status bit 0.
7.8.1 Software Constraints
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3
are set to zero. Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
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7.9 EPP 1.7 Write
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or
Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is
inactive high.
Write Sequence of Operation
1. The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
2. The host initiates an I/O write cycle to the selected EPP register.
3. The chip places address or data on PData bus.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and
the WRITE signal is valid.
5. If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts
nWAIT or a time-out occurs.
6. The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the
internal data bus for the PData bus.
7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
7.10 EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip
inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1. The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the
PData bus.
2. The host initiates an I/O read cycle to the selected EPP register.
3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
4. If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts
nWAIT or a time-out occurs.
5. The Peripheral drives PData bus valid.
6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination
phase of the cycle.
7. The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
Table 7.2 - EPP Pin Descriptions
EPP
SIGNAL
nWRITE nWrite O This signal is active low. It denotes a write operation.
PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus.
INTR Interrupt I
EPP NAME TYPE
EPP DESCRIPTION
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
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EPP
SIGNAL
nWAIT nWait I
nDATASTB nData Strobe O
nRESET nReset O
nADDRSTB
PE Paper End I Same as SPP mode.
SLCT
nERR Error I Same as SPP mode.
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For
correct EPP read cycles, PCD is required to be a low.
EPP NAME TYPE
Address
Strobe
Printer
Selected
Status
O
EPP DESCRIPTION
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device
is ready for the next transfer.
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
I Same as SPP mode.
7.10.1 Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the
use of adaptive signal timing Peer-to-peer capability.
7.10.2 Vocabulary
The following terms are used in this document:
assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
forward: Host to Peripheral communication.
reverse: Peripheral to Host communication
Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is
always 8 bits.
1 A high level.
0 A low level.
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
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nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard
1.14, July 14, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
ecpAFifo Addr/RLE Address or RLE field 2
dsr nBusy nAck PError Select nFault 0 0 0 1
dcr 0 0 Direction ackIntEn
cFifo Parallel Port Data FIFO 2
ecpDFifo ECP Data FIFO 2
tFifo Test FIFO 2
cnfgA 0 0 0 1 0 0 0 0
cnfgB compress intrValue Parallel Port IRQ Parallel Port DMA
ecr MODE
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration
Registers.
D7 D6 D5 D4 D3 D2 D1 D0 NOTE
nInit autofd strobe 1
nErrIntrE
n
SelectI
n
dmaEn serviceIntr full empty
, Rev
7.11 ECP Implementation Standard
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC
devices supporting ECP must meet the requirements contained in this section or the port will not be
supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended
Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
7.11.1 Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a
standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of
gates to implement. It does not do any “protocol” negotiation, rather it provides an automatic high
burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the
maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic
handshake for the standard parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is
accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the
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next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte
the specified number of times. Hardware support for compression is optional.
NAME TYPE DESCRIPTION
nStrobe O
PData 7:0 I/O Contains address or data or RLE data.
nAck I
PeriphAck (Busy) I
PError
(nAckReverse)
Select I Indicates printer on line.
nAutoFd
(HostAck)
nFault
(nPeriphRequest)
nInit O
nSelectIn O Always deasserted in ECP mode.
During write operations nStrobe registers data or address into the slave
on the asserting edge (handshakes with Busy).
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept data. This
signal handshakes with nStrobe in the forward direction. In the reverse
direction this signal indicates whether the data lines contain ECP
command information or data. The peripheral uses this signal to flow
control in the forward direction. It is an “interlocked” handshake with
nStrobe. PeriphAck also provides command information in the reverse
direction.
I
Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an “interlocked” handshake with
nReverseRequest. The host relies upon nAckReverse to determine when
it is permitted to drive the data bus.
O
Requests a byte of data from the peripheral when asserted, handshaking
with nAck in the reverse direction. In the forward direction this signal
indicates whether the data lines contain ECP address or data. The host
drives this signal to flow control in the reverse direction. It is an
“interlocked” handshake with nAck. HostAck also provides command
information in the forward phase.
I
Generates an error interrupt when asserted. This signal provides a
mechanism for peer-to-peer communication. This signal is valid only in
the forward direction. During ECP Mode the peripheral is permitted (but
not required) to drive this pin low to request a reverse transfer. The
request is merely a “hint” to the host; the host has ultimate control over
the transfer direction. This signal would be typically used to generate an
interrupt to the host CPU.
Sets the transfer direction (asserted = reverse, deasserted = forward).
This pin is driven low to place the channel in the reverse direction. The
peripheral is only allowed to drive the bi-directional data bus while in
ECP Mode and HostAck is low and nSelectIn is high.
Table 7.3 - ECP Pin Descriptions
7.12 Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports
are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to
avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may
be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below
lists these dependencies. Operation of the devices in modes other that those specified is undefined.
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