SMSC LPC47M172 Technical data
LPC47M172
Advanced I/O Controller
with Motherboard GLUE
Logic
Datasheet
Product Features
3.3V Operation (5V tolerant)
LPC Interface
− Multiplexed Command, Address and Data Bus
− Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
ACPI 1.0b/2.0 Compliant
Programmable Wake-up Event Interface
PC99a/PC2001 Compliant
General Purpose Input/Output Pins (13)
Fan Tachometer Inputs (2)
Green and Yellow Power LEDs
ISA Plug-and-Play Compatible Register Set
Motherboard GLUE Logic
− 5V Reference Generation
− 5V Standby Reference Generation
− IDE Reset/Buffered PCI Reset Outputs
− Power OK Signal Generation
− Power Sequencing
− Power Supply Turn On Circuitry
− Resume Reset Signal Generation
− Hard Drive Front Panel LED
− Voltage Translation for DDC to VGA Monitor
− SMBus Isolation Circuitry
− CNR Dynamic Down Control
2.88MB Super I/O Floppy Disk Controller
− Licensed CMOS 765B Floppy Disk Controller
− Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
− Supports One Floppy Drive
− Configurable Open Drain/Push-Pull Output Drivers
− Supports Vertical Recording Format
16-Byte Data FIFO
− 100% IBM Compatibility
− Detects All Overrun and Underrun Conditions
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
− DMA Enable Logic
− Data Rate and Drive Control Registers
480 Address, Up to Eight IRQ and Three DMA
Options
Enhanced Digital Data Separator
− 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
Data Rates
− Programmable Precompensation Modes
Keyboard Controller
− 8042 Software Compatible
− 8 Bit Microcomputer
− 2k Bytes of Program ROM
− 256 Bytes of Data RAM
− Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
− Asynchronous Access to Two Data Registers and
One Status Register
− Supports Interrupt and Polling Access
− 8 Bit Counter Timer
− Port 92 Support
− Fast Gate A20 and KRESET Outputs
Serial Ports
− Two Full Function Serial Ports
− High Speed 16C550A Compatible UART with
Send/Receive 16-Byte FIFOs
− Supports 230k and 460k Baud
− Programmable Baud Rate Generator
− Modem Control Circuitry
− 480 Address and 15 IRQ Options
Infrared Port
− Multiprotocol Infrared Interface
− 32-Byte Data FIFO
− IrDA 1.0 Compliant
− SHARP ASK IR
− HP-SIR
− 480 Address, Up to 15 IRQ and Three DMA Options
Multi-Mode Parallel Port with ChiProtect
− Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bi-directional Parallel Port
− Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
− IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
− ChiProtect Circuitry for Protection
− 960 Address, Up to 15 IRQ and Three DMA Options
Interrupt Generating Registers
− Registers Generate IRQ1 – IRQ15 on Serial IRQ
Interface.
XOR-Chain Board Test
128 Pin MQFP Package, 3.2 mm Footprint
SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
ORDERING INFORMATION
Order Number(s):
LPC47M172-NR for 128 MQFP (3.2mm footprint) package
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
80 Arkay Drive
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 2 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
LPC47M172 Datasheet Revision History
REVISION LEVEL
AND DATE
Rev. 02-27-04
Rev. 02-27-04 Ordering Information Added.
Rev. 02-27-04
Rev. 02-26-04 Chapter 1 - General Description, page 12
Rev. 02-23-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04 Chapter 2 - Pin Layout, page 13 Note for pin 117
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Rev. 02-20-04
Table 12.2 - S3-S5 Standby Current, page
201
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Chapter 12 - Electrical Characteristics,
page 196
Section 3.1 - Buffer Name Descriptions,
page 23
Table 3.1 - LPC47M172 Pin Description,
page 15
Table 6.1 - Super I/O Block Logical Device
Number and Addresses, page 33
Table 7.31 - Voltage Translation DDC Pins,
page 137
Figure 7.10 - VGA DDC Voltage
Translation Circuit, page 139
Table 7.34 - SMBus Isolation Pins, page
139
Figure 7.11 - SMBUS Isolation Circuit,
page 140
Table 12.1 - Operational DC
Characteristics, page 196
Table 7.7 - Programming for Configuration
Register B (Bits 5:3), page 106; Table 7.8 Programming for Configuration Register B
(Bits 2:0), page 106
Table 11.2 - LPC47M172 Configuration
Register Summary, page 178
Table 11.3 - Chip Level Registers, page
180
Table 3.1 - LPC47M172 Pin Description,
page 15
Chapter 8 Power Control Runtime
Registers, page 151
Chapter 9 GPIO Runtime Registers, page
158
Chapter 10 Runtime Register Block
Runtime Registers, page 162
Table 11.3 - Chip Level Registers, page
180
SECTION/FIGURE/ENTRY CORRECTION
Added note above table.
Revised heading to include “standard
SMSC” and “non-standard SMSC” register
sets.
Revised General Description adding AMITM
BIOS to keyboard interface.
Lead Temperature Range, lead and leadfree; reference to spec name J-STD-020B.
Added I0_SW.
Buffer names revised for pins 87 – 90,
113 – 116.
Note 8 under table revised.
Added table.
Replaced buffer IOD8 with IO_SW.
Revised figure.
Replaced buffer IOD8 with IO_SW.
First paragraph under table revised.
Revised figure.
Added IO_SW buffer and description;
updated parameters for Icc and Itr.
Titles added to tables.
Value of TEST 7 reg for LD_NUM=1
changed to 0x01.
Definition of TEST 7 value:
Default = 0x00 (when pin 117 is NC), 0x01
(when pin 117 is connected to VTR) on
VCC POR, VTR POR, and HARD RESET
No Connect Pin 117,
Pin 117 described in Note 11.
Table added.
Table added.
Added paragraph describing runtime
registers tables.
Register 0x29
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 3 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
LPC47M172 Datasheet Revision History .................................................................................................3
Chapter 1 General Description.............................................................................................................. 12
Chapter 2 Pin Layout ............................................................................................................................13
Chapter 3 Description of Pin Functions ................................................................................................15
3.1 Buffer Name Descriptions ..........................................................................................................................23
3.2 Pins With Internal Resistors .......................................................................................................................24
3.3 Pins That Require External Resistors.........................................................................................................24
3.4 Default State of Pins...................................................................................................................................25
Chapter 4 Block Diagram ......................................................................................................................29
Chapter 5 Power and Clock Functionality............................................................................................. 30
5.1 3 Volt Operation / 5 Volt Tolerance ............................................................................................................30
5.2 VCC Power ................................................................................................................................................30
5.3 VTR Power.................................................................................................................................................30
5.3.1 Trickle Power Functionality .................................................................................................................31
5.4 V5P0_STBY Power....................................................................................................................................31
5.5 32.768 kHz Trickle Clock Input...................................................................................................................31
5.5.1 Indication of 32KHZ Clock...................................................................................................................31
5.6 14.318 MHz Clock Input .............................................................................................................................32
5.7 Internal PWRGOOD...................................................................................................................................32
5.8 Maximum Current Values...........................................................................................................................32
5.9 Power Management Events (PME/SCI) .....................................................................................................32
Chapter 6 Functional Description..........................................................................................................33
6.1 Super I/O Registers....................................................................................................................................33
6.2 Host Processor Interface (LPC) .................................................................................................................34
6.3 LPC Interface .............................................................................................................................................34
6.3.1 LPC Interface Signal Definition ...........................................................................................................34
6.3.2 LPC Cycles .........................................................................................................................................34
6.3.3 Field Definitions...................................................................................................................................34
6.3.4 NLFRAME Usage................................................................................................................................35
6.3.5 I/O Read and Write Cycles..................................................................................................................35
6.3.6 DMA Read and Write Cycles ..............................................................................................................35
6.3.7 DMA Protocol ......................................................................................................................................35
6.3.8 Power Management ............................................................................................................................36
6.3.9 SYNC Protocol ....................................................................................................................................36
6.3.10 I/O and DMA START Fields.............................................................................................................37
6.3.11 LPC Transfers .................................................................................................................................37
6.4 Floppy Disk Controller ................................................................................................................................38
6.4.1 FDC Configuration Registers ..............................................................................................................38
6.4.2 FDC Internal Registers........................................................................................................................38
6.4.3 Status Register A (SRA) .....................................................................................................................39
6.4.4 Status Register B (SRB) .....................................................................................................................40
6.4.5 Digital Output Register (DOR).............................................................................................................42
6.4.6 Tape Drive Register (TDR) .................................................................................................................43
6.4.7 Data Rate Select Register (DSR)........................................................................................................44
6.4.8 Main Status Register...........................................................................................................................46
6.4.9 Data Register (FIFO)...........................................................................................................................47
6.4.10 Digital Input Register (DIR)..............................................................................................................48
6.4.11 Configuration Control Register (CCR) .............................................................................................49
6.4.12 Status Register Encoding ................................................................................................................50
6.5 Modes of Operation....................................................................................................................................52
6.5.1 PC/AT Mode .......................................................................................................................................52
6.5.2 PS/2 Mode ..........................................................................................................................................52
6.5.3 Model 30 Mode ...................................................................................................................................52
6.6 DMA Transfers ...........................................................................................................................................52
6.7 Controller Phases.......................................................................................................................................53
6.7.1 Command Phase ................................................................................................................................53
6.7.2 Execution Phase .................................................................................................................................53
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 4 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
6.8 Data Transfer Termination .........................................................................................................................54
6.9 Result Phase..............................................................................................................................................54
6.10 Command Set/Descriptions....................................................................................................................54
6.10.1 Instruction Set..................................................................................................................................57
6.11 Data Transfer Commands ......................................................................................................................63
6.11.1 Read Data .......................................................................................................................................63
6.12 Read Deleted Data .................................................................................................................................64
6.13 Read A Track..........................................................................................................................................65
6.14 Write Data...............................................................................................................................................66
6.15 Write Deleted Data .................................................................................................................................66
6.16 Verify ......................................................................................................................................................66
6.17 Format A Track.......................................................................................................................................67
6.18 Control Commands.................................................................................................................................69
6.18.1 Read ID ...........................................................................................................................................69
6.18.2 Recalibrate ......................................................................................................................................69
6.18.3 Seek ................................................................................................................................................69
6.19 Sense Interrupt Status............................................................................................................................70
6.20 Sense Drive Status.................................................................................................................................71
6.21 Specify....................................................................................................................................................71
6.22 Configure................................................................................................................................................71
6.22.1 Configure Default Values.................................................................................................................71
6.23 Version ...................................................................................................................................................72
6.24 Relative Seek .........................................................................................................................................72
6.25 Perpendicular Mode................................................................................................................................73
6.26 Lock........................................................................................................................................................74
6.27 Enhanced DUMPREG ............................................................................................................................75
6.27.1 Compatibility....................................................................................................................................75
6.28 Serial Port (UART)..................................................................................................................................75
6.28.1 Register Description ........................................................................................................................75
6.28.2 Receive Buffer Register (RB) ..........................................................................................................76
6.28.3 Transmit Buffer Register (TB)..........................................................................................................76
6.28.4 Interrupt Enable Register (IER) .......................................................................................................76
6.28.5 FIFO Control Register (FCR)...........................................................................................................77
6.28.6 Interrupt Identification Register (IIR)................................................................................................77
6.28.7 Line Control Register (LCR) ............................................................................................................79
6.28.8 Modem Control Register (MCR) ......................................................................................................80
6.28.9 Line Status Register (LSR)..............................................................................................................81
6.28.10 Modem Status Register (MSR) ........................................................................................................82
6.28.11 Scratchpad Register (SCR) .............................................................................................................83
6.29 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL) .................................................83
6.29.1 Effect Of The Reset on Register File ...............................................................................................84
6.29.2 FIFO Interrupt Mode Operation .......................................................................................................84
6.29.3 FIFO Polled Mode Operation...........................................................................................................85
Chapter 7 Notes On Serial Port Operation ...........................................................................................89
7.1 FIFO Mode Operation: ...............................................................................................................................89
7.1.1 General ...............................................................................................................................................89
7.1.2 TX and RX FIFO Operation.................................................................................................................89
7.2 Infrared Interface........................................................................................................................................90
7.3 Parallel Port................................................................................................................................................90
7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................92
7.4.1 Data Port.............................................................................................................................................92
7.4.2 Status Port ..........................................................................................................................................92
7.4.3 Control Port.........................................................................................................................................93
7.4.4 EPP Address Port ...............................................................................................................................94
7.4.5 EPP Data Port 0..................................................................................................................................94
7.4.6 EPP Data Port 1..................................................................................................................................94
7.4.7 EPP Data Port 2..................................................................................................................................94
7.4.8 EPP Data Port 3..................................................................................................................................95
7.5 EPP 1.9 Operation .....................................................................................................................................95
7.5.1 Software Constraints...........................................................................................................................95
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 5 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.6 EPP 1.9 Write.............................................................................................................................................95
7.7 EPP 1.9 Read ............................................................................................................................................96
7.8 EPP 1.7 Operation .....................................................................................................................................96
7.8.1 Software Constraints...........................................................................................................................96
7.9 EPP 1.7 Write.............................................................................................................................................97
7.10 EPP 1.7 Read.........................................................................................................................................97
7.10.1 Extended Capabilities Parallel Port .................................................................................................98
7.10.2 Vocabulary.......................................................................................................................................98
7.11 ECP Implementation Standard ...............................................................................................................99
7.11.1 Description.......................................................................................................................................99
7.12 Register Definitions...............................................................................................................................100
7.12.1 Data and ecpAFifo Port .................................................................................................................101
7.12.2 Device Status Register (dsr)..........................................................................................................102
7.12.3 Device Control Register (dcr) ........................................................................................................102
7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................103
7.12.5 ECPDFIFO (ECP Data FIFO)........................................................................................................103
7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................103
7.12.7 cnfgA (Configuration Register A) ...................................................................................................104
7.12.8 cnfgB (Configuration Register B) ...................................................................................................104
7.12.9 ecr (Extended Control Register) ....................................................................................................104
7.13 Operation..............................................................................................................................................107
7.13.1 Mode Switching/Software Control..................................................................................................107
7.14 ECP Operation .....................................................................................................................................107
7.15 Termination from ECP Mode ................................................................................................................108
7.16 Command/Data.....................................................................................................................................108
7.17 Data Compression................................................................................................................................108
7.18 Pin Definition ........................................................................................................................................108
7.19 LPC Connections..................................................................................................................................109
7.20 Interrupts ..............................................................................................................................................109
7.21 FIFO Operation.....................................................................................................................................109
7.21.1 DMA Transfers ..............................................................................................................................110
7.21.2 DMA Mode - Transfers from the FIFO to the Host......................................................................... 110
7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................110
7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................110
7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................111
7.22 Power Management..............................................................................................................................111
7.23 Serial IRQ.............................................................................................................................................111
7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................111
7.23.2 SER_IRQ Cycle Control ................................................................................................................112
7.23.3 SER_IRQ Data Frame...................................................................................................................113
7.23.4 Stop Cycle Control.........................................................................................................................113
7.23.5 Latency..........................................................................................................................................114
7.23.6 EOI/ISR Read Latency ..................................................................................................................114
7.23.7 AC/DC Specification Issue ............................................................................................................114
7.23.8 Reset and Initialization ..................................................................................................................114
7.24 Interrupt Generating Registers .............................................................................................................114
7.25 8042 Keyboard Controller Description..................................................................................................115
7.25.1 Keyboard Interface ........................................................................................................................115
7.25.2 Keyboard Data Write .....................................................................................................................116
7.25.3 Keyboard Data Read .....................................................................................................................116
7.25.4 Keyboard Command Write ............................................................................................................116
7.25.5 Keyboard Status Read ..................................................................................................................116
7.25.6 CPU-to-Host Communication ........................................................................................................116
7.25.7 Host-to-CPU Communication ........................................................................................................116
7.25.8 KIRQ..............................................................................................................................................116
7.25.9 MIRQ .............................................................................................................................................117
7.25.10 External Keyboard and Mouse Interface .......................................................................................117
7.25.11 Keyboard Power Management ......................................................................................................117
7.25.12 Soft Power Down Mode .................................................................................................................117
7.25.13 Hard Power Down Mode ...............................................................................................................117
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 6 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.25.14 Interrupts .......................................................................................................................................118
7.25.15 Memory Configurations .................................................................................................................118
7.25.16 Register Definitions .......................................................................................................................118
7.25.17 External Clock Signal ....................................................................................................................119
7.25.18 Default Reset Conditions ...............................................................................................................119
7.25.19 GateA20 and Keyboard Reset .......................................................................................................119
7.26 Port 92 Fast Gatea20 and Keyboard Reset..........................................................................................119
7.26.1 Port 92 Register.............................................................................................................................119
7.26.2 Keyboard and Mouse PME Generation .........................................................................................123
7.27 General Purpose I/O.............................................................................................................................124
7.27.1 GPIO Pins .....................................................................................................................................125
7.27.2 Description.....................................................................................................................................125
7.27.3 GPIO Control.................................................................................................................................126
7.27.4 GPIO Operation.............................................................................................................................127
7.27.5 GPIO PME Functionality................................................................................................................128
7.27.6 Either Edge Triggered Interrupts ...................................................................................................128
7.28 PME Support ........................................................................................................................................128
7.28.1 ‘Wake on Specific Key’ Option.......................................................................................................129
7.29 Fan Monitoring......................................................................................................................................130
7.29.1 Fan Tachometer Inputs .................................................................................................................131
7.29.2 Detection of a Stalled Fan .............................................................................................................131
7.30 Hard Drive and Power LED Logic.........................................................................................................132
7.30.1 Hard Drive Front Panel LED (Red) ................................................................................................132
7.30.2 Yellow and Green Power LED Pins ...............................................................................................133
7.31 Power Generation (5V).........................................................................................................................134
7.31.1 Reference Pins ..............................................................................................................................134
7.31.2 5V Main Reference Generation .....................................................................................................135
7.31.3 5V Standby Reference Generation................................................................................................135
7.31.4 Reference Timings ........................................................................................................................136
7.32 IDE Reset Output Pin ...........................................................................................................................136
7.33 PCI Reset Output Pins..........................................................................................................................136
7.34 Voltage Translation Circuit....................................................................................................................137
7.35 SMBus Isolation Circuitry......................................................................................................................139
7.36 PS_ON Logic........................................................................................................................................141
7.37 PWRGD_3V Logic................................................................................................................................141
7.38 SCK_BJT_GATE Output ......................................................................................................................143
7.39 Backfeed Cut and Latched Backfeed Cut Circuitry...............................................................................144
7.40 Resume Reset Logic ............................................................................................................................149
7.41 CNR Logic ............................................................................................................................................149
Chapter 8 Power Control Runtime Registers...................................................................................... 151
Chapter 9 GPIO Runtime Registers.................................................................................................... 158
Chapter 10 Runtime Register Block Runtime Registers ....................................................................... 162
Chapter 11 Configuration ......................................................................................................................173
11.1 System Elements..................................................................................................................................173
11.1.1 Primary Configuration Address Decoder .......................................................................................173
11.1.2 Entering the Configuration State....................................................................................................173
11.1.3 Exiting the Configuration State ......................................................................................................173
11.1.4 Configuration Sequence ................................................................................................................174
11.1.5 Enter Configuration Mode..............................................................................................................174
11.1.6 Configuration Mode .......................................................................................................................174
11.1.7 Exit Configuration Mode ................................................................................................................174
11.1.8 Programming Example ..................................................................................................................175
11.2 Chip Level (Global) Control/Configuration Registers[0x00-0x2F] .........................................................180
11.3 Logical Device Configuration/Control Registers [0x30-0xFF] ...............................................................183
11.4 Logical Device I/O Address ..................................................................................................................187
11.5 Logical Device Configuration Registers................................................................................................190
Chapter 12 Electrical Characteristics ....................................................................................................196
12.1 Maximum Guaranteed Ratings .............................................................................................................196
12.2 Operational DC Characteristics ............................................................................................................196
12.3 Standby Power Requirements ..............................................................................................................201
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 7 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
12.4 Capacitance Values for Pins.................................................................................................................202
Chapter 13 Timing Diagrams ................................................................................................................203
13.1 ECP Parallel Port Timing......................................................................................................................212
13.1.1 Parallel Port FIFO (Mode 101).......................................................................................................212
13.1.2 ECP Parallel Port Timing...............................................................................................................212
13.1.3 Forward-Idle ..................................................................................................................................212
13.1.4 Forward Data Transfer Phase .......................................................................................................212
13.1.5 Reverse-Idle Phase .......................................................................................................................212
13.1.6 Reverse Data Transfer Phase .......................................................................................................212
13.1.7 Output Drivers ...............................................................................................................................213
Chapter 14 Package Outline .................................................................................................................224
Chapter 15 Board Test Mode................................................................................................................225
Chapter 16 Reference Documents........................................................................................................ 227
List Of Figures
Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................13
Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................29
Figure 7.1 - NKBDRST Circuit....................................................................................................................................121
Figure 7.2 - Keyboard Latch.......................................................................................................................................122
Figure 7.3 - Mouse Latch ...........................................................................................................................................122
Figure 7.4 - GPIO Function Illustration.......................................................................................................................127
Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................131
Figure 7.6 - NHD_LED Circuit....................................................................................................................................133
Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................134
Figure 7.8 - REF5V Circuit .........................................................................................................................................135
Figure 7.9 - REF5V_STBY.........................................................................................................................................136
Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................139
Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................140
Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................142
Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................142
Figure 7.14 - NFPRST Timing....................................................................................................................................143
Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................144
Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................145
Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................146
Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................146
Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................147
Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................148
Figure 7.21 - CNR Circuit...........................................................................................................................................150
Figure 13.1 - Power-Up Timing ..................................................................................................................................204
Figure 13.2 - Input Clock Timing ................................................................................................................................205
Figure 13.3 - PCI Clock Timing ..................................................................................................................................205
Figure 13.4 - Reset Timing.........................................................................................................................................205
Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................206
Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................206
Figure 13.7 - I/O Write................................................................................................................................................206
Figure 13.8 - I/O Read ...............................................................................................................................................207
Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................207
Figure 13.10 - DMA Write (First Byte) ........................................................................................................................207
Figure 13.11 - DMA Read (First Byte)........................................................................................................................207
Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................208
Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................209
Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................210
Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................211
Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................211
Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................213
Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................214
Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................215
Figure 13.20 - Setup and Hold Time ..........................................................................................................................216
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 8 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Figure 13.21 - Serial Port Data...................................................................................................................................216
Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................217
Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................218
Figure 13.24 - Power Led Output Timing ...................................................................................................................218
Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY ...............219
Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR ...............219
Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY...........220
Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR...........220
Figure 13.29 - Rise, Fall and Propagation Timings ....................................................................................................221
Figure 13.30 - Reseme Reset Sequence ...................................................................................................................223
Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................224
Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................225
List Of Tables
Table 3.1 - LPC47M172 Pin Description ......................................................................................................................15
Table 3.2 - Pins with Internal Resistors........................................................................................................................24
Table 3.3 - Pins that Require External Resistors..........................................................................................................24
Table 3.4 - Default State of Pins ..................................................................................................................................26
Table 6.1 - Super I/O Block Logical Device Number and Addresses ...........................................................................33
Table 6.2 - Status, Data and Control Registers............................................................................................................38
Table 6.3 - Internal 2 Drive Decode - Normal...............................................................................................................42
Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................43
Table 6.5 - Tape Select Bits .........................................................................................................................................43
Table 6.6 - Drive Type ID .............................................................................................................................................44
Table 6.7 - Precompensation Delays ...........................................................................................................................45
Table 6.8 - Data Rates .................................................................................................................................................45
Table 6.9 - DRVDEN Mapping .....................................................................................................................................46
Table 6.10 - Default Precompensation Delays .............................................................................................................46
Table 6.11 - FIFO Service Delay..................................................................................................................................47
Table 6.12 - Status Register 0 .....................................................................................................................................50
Table 6.13 - Status Register 1 .....................................................................................................................................50
Table 6.14 - Status Register 2 .....................................................................................................................................51
Table 6.15 - Status Register 3 .....................................................................................................................................51
Table 6.16 - Description of Command Symbols...........................................................................................................55
Table 6.17 - Instruction Set ..........................................................................................................................................57
Table 6.18 - Sector Sizes.............................................................................................................................................63
Table 6.19 - Effects of MT and N Bits ..........................................................................................................................64
Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................64
Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................65
Table 6.22 - Result Phase Table..................................................................................................................................65
Table 6.23 - Verify Command Result Phase Table ......................................................................................................67
Table 6.24 - Typical Values for Formatting ..................................................................................................................68
Table 6.25 - Interrupt Identification...............................................................................................................................70
Table 6.26 - Drive Control Delays (ms) ........................................................................................................................71
Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................74
Table 6.28 - Addressing the Serial Port .......................................................................................................................75
Table 6.29 - Interrupt Control Table .............................................................................................................................78
Table 6.30 - Baud Rates ..............................................................................................................................................85
Table 6.31 - Reset Function Table ...............................................................................................................................86
Table 32 - Register Summary for an Individual UART Channel ...................................................................................87
Table 7.1 - Parallel Port Connector ..............................................................................................................................92
Table 7.2 - EPP Pin Descriptions .................................................................................................................................97
Table 7.3 - ECP Pin Descriptions...............................................................................................................................100
Table 7.4 - ECP Register Definitions..........................................................................................................................101
Table 7.5 - Mode Descriptions ...................................................................................................................................101
Table 7.6 - Extended Control Register .......................................................................................................................106
Table 7.7 - Programming for Configuration Register B (Bits 5:3) ...............................................................................106
Table 7.8 - Programming for Configuration Register B (Bits 2:0) ...............................................................................106
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 9 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................108
Table 7.10 - I/O Address Map ....................................................................................................................................115
Table 7.11 - Host Interface Flags ...............................................................................................................................116
Table 7.12 - Status Register ......................................................................................................................................118
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................119
Table 7.14 - Keyboard Port 92 Register.....................................................................................................................120
Table 7.15 - nA20M Truth Table ................................................................................................................................121
Table 7.16 - GPIO Summary......................................................................................................................................125
Table 7.17 - General Purpose I/O Port Assignments .................................................................................................126
Table 7.18 - GPIO Configuration Summary ...............................................................................................................126
Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................127
Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................132
Table 7.21 - nHD_LED Truth Table............................................................................................................................132
Table 7.22 - LED Pins ................................................................................................................................................133
Table 7.23 - LED Truth Table.....................................................................................................................................133
Table 7.24 - Reference Generation Pins....................................................................................................................134
Table 7.25 - REF5V ...................................................................................................................................................135
Table 7.26 - REF5V_STBY ........................................................................................................................................135
Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................136
Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................136
Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................137
Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................137
Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................137
Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................138
Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................138
Table 7.34 - SMBus Isolation Pins .............................................................................................................................139
Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................140
Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................140
Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................141
Table 7.38 - nPS_ON Truth Table..............................................................................................................................141
Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................141
Table 7.40 - PWRGD_3V Truth Table........................................................................................................................142
Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................143
Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................143
Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................144
Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................144
Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................145
Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................146
Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................147
Table 7.48 - nRSMRST Pin........................................................................................................................................149
Table 7.49 - CNR Pins ...............................................................................................................................................149
Table 7.50 - CNR Logic Truth Table ..........................................................................................................................150
Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................151
Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................152
Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................158
Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................159
Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................162
Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................163
Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................176
Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................178
Table 11.3 - Chip Level Registers ..............................................................................................................................180
Table 11.4 - Logical Device Registers........................................................................................................................183
Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................185
Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................185
Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0........................................................................................187
Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................188
Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................190
Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................191
Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................192
Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................193
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 10 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 11.13 - Keyboard Logical Device Configuration Registers ...............................................................................194
Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers .................................194
Table 12.1 - Operational DC Characteristics..............................................................................................................196
Table 12.2 - S3-S5 Standby Current ..........................................................................................................................201
Table 13.1 - nIDE_RSTDRV Timing...........................................................................................................................221
Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing ........................................................................................221
Table 13.3 - PS_ON Timing .......................................................................................................................................221
Table 13.4 - SCK_BJT_GATE Timing........................................................................................................................222
Table 13.5 - PWRGD_3V Timing ...............................................................................................................................222
Table 13.6 - CNR CODEC Down Enable Timing .......................................................................................................222
Table 13.7 - Resume Reset Timing............................................................................................................................223
Table 14.1 - 128 Pin MQFP Package Parameters .....................................................................................................224
Table 15.1 - XOR Test Pattern Example....................................................................................................................226
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 11 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 1 General Description
The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop
PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well
as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard
resulting in lower cost. The LPC47M172 also provides 13 general purpose pins, which offer flexibility to
the system designer, and two Fan Tachometer Inputs. The LPC47M172’s LPC interface supports LPC I/O
and DMA cycles.
The LPC47M172 includes complete legacy I/O: a keyboard interface with AMI
CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs;
one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core
provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data
overflow and underflow protection. The SMSC’s patented advanced digital data separator allows for ease
of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP
and ECP. The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes
support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low
power-down modes. The LPC47M172 is ACPI 1.0b/2.0 compatible.
The Motherboard GLUE logic includes various power management logic; including generation of
nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three
LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V
signals. Also included is SMBus main power well to resume power well isolation circuitry.
The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address,
DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through
the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location
options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers
enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.
The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and
is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is
register compatible with SMSC’s proprietary 82077AA core.
This device utilizes two selectable (see Chapter 2) register sets; (1) standard SMSC and (2) tailored for
Intel reference designs. These register sets are detailed in Chapter 6 (Section 6.1).
TM
BIOS; SMSC's true
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 12 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 2 Pin Layout
IRTX2
IRRX2
nDCD2
nDTR2
nCTS2
VCC
nRTS2
nDSR2
TXD2
RXD2
nRI2
NC/VTR (Note)
DDCSDA_5V/GP20
DDCSDA_3V/GP22
DDCSCL_5V/GP21
DDCSCL_3V/GP23
GP17/FAN_TACH2
GP16/FAN_TACH1
VSS
GP15
GP14
VTR
GP13
GP12
GP11
GP10
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
MCLK
MDAT
KCLK
KDAT
GA20M
VCC
nKBDRST
VSS
nDSKCHG
nHDSEL
nRDATA
nWRTPRT
nTRK0
nWGATE
nWDATA
nSTEP
nDIR
nDS0
nMTR0
nINDEX
DRVDEN1
DRVDEN0
nDCD
nDSR
RXD
nRTS
TXD
nCTS
VSS
nDTR (XOR)
VCC
nRI
SLCT
PE
BUSY
nACK
PD7
PD6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39404142434445464748495051525354555657585960616263
LPC47M172
128 PIN QFP
103
64
102
nCDC_DWN_RST
101
nCDC_DWN_ENAB/GP24
100
nAUD_LINK_RST
99
nIO_PME
98
TEST_EN
97
F_CAP
96
VSS
95
YLW_LED
94
GRN_LED
93
VTR
92
nRSMRST
91
CLOCKI32
90
SMB_DAT_R
89
SMB_DAT_M
88
SMB_CLK_R
87
SMB_CLK_M
86
nSLP_S5
85
nSLP_S3
84
PWRGD_3V
83
nCPU_PRESENT
82
PWRGD_PS
81
nPS_ON
80
SCK_BJT_GATE
79
LATCHED_BF_CUT
78
VSS
77
nBACKFEED_CUT
76
VTR
75
nFPRST
74
nPCIRST_OUT2
73
nPCIRST_OUT
72
REF5V_STBY
71
V_5P0_STBY
70
REF5V
69
nSCSI
68
nSECONDARY_HD
67
nPRIMARY_HD
66
nHD_LED
65
CLOCKI
PD5
PD4
PD3
PD2
PD1
PD0
nERROR
VSS
VCC
nALF
nSLCTIN
nINITP
nLDRQ
nLPCPD
SER_IRQ
nSTROBE
VSS
VCC
LAD3
LAD2
LAD1
LAD0
PCI_CLK
nLFRAME
nPCI_RESET
nIDE_RSTDRV
Figure 2.1 - LPC47M172 Pin Layout
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 13 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Note: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the
TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the
LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin functions
as follows:
The pin has an internal pull-down resistor that selects the non-standard SMSC (Intel Compatible) mode. To
select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to ‘0’ and the
associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=0.
Connecting this pin to VTR will select the standard SMSC mode of the logical device numbering. This
configuration sets the LD_NUM bit to ‘1’ and the associated functionality corresponds to the existing functionality
in the part when the LD_NUM bit=1.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 14 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 3 Description of Pin Functions
Table 3.1 - LPC47M172 Pin Description
PIN#
6,31,
NAME
(NOTE 1)
DESCRIPTION
POWER AND GROUND PINS (20)
BUFFER
(NOTE 2)
See Note 11
NAME
VCC +3.3 Volt Main Supply Voltage (5) PWR
PWR
WELL
(NOTE 3)
49,60,
123
76,93,
107,
117
See Note
VTR +3.3 Volt Standby Supply Voltage (4)
Note
See
PWR 11
71 V_5P0_STBY +5 Volt Standby Supply Voltage. PWR
8,29,
VSS Ground (7) PWR
46,58,
78,96,
110
70 REF5V
5V Reference Output. Requires external
AO VCC
pull-up to VCC5V.
72 REF5V_STBY
Highest System Standby Voltage.
AO VTR
Requires external pull-up to
V_5P0_STBY.
97 F_CAP
Internal Regulator Filter Capacitor. This
pin is a no connect. A filter capacitor can
be placed on this pin if it is required by
system board layout.
CLOCKS (2)
65 CLOCKI 14.318Mhz Clock Input IS VCC
91 CLOCKI32 32.768kHz Clock Input IS VTR 4
PROCESSOR/HOST LPC INTERFACE (11)
52 nLPCPD
Active low input Power Down signal
PCI_I VCC 5
indicates that the LPC47M172 should
prepare for power to be shut-off on the
LPC interface.
53 SER_IRQ
Serial IRQ pin used with the PCI_CLK pin
PCI_IO VCC
to transfer LPC47M172 interrupts to the
host.
54 nLDRQ
Active low output used for encoded
PCI_O VCC
DMA/Bus Master request for the LPC
interface.
55 PCI_CLK 33.33 MHz PCI Clock input. PCI_ICLK VCC
56 nLFRAME
Active low input indicates start of new
PCI_I VCC
cycle and termination of broken cycle.
57,59,
61,62
LAD[3:0]
Active high LPC I/O used for multiplexed
command, address and data bus.
PCI_IO VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 15 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
63 nPCI_RESET
NAME
(NOTE 1)
Active low input used as LPC Interface
Reset. 3.3V and 5V buffered copy of PCI
Reset signal is available on
nPCIRST_OUT and nIDE_RSTDRV.
These pins are listed under GLUE PINS.
99 nIO_PME
Power Management Event Output. This
active low Power Management Event
signal allows to request wakeup. This pin
can be configured as Push-Pull Output.
9 nDSKCHG
This input senses that the drive door is
open or that the diskette has possibly
been changed since the last drive
selection. This input is inverted and read
via bit 7 of I/O address 3F7H. The
nDSKCHG bit also depends upon the
state of the Force Disk Change bits in the
Force Disk Change register (see Chapter
11 Configuration).
10 nHDSEL
Head Select Output. This high current
output selects the floppy disk side for
reading or writing. A logic “1” on this pin
means side 0 will be accessed, while a
logic “0” means side 1 will be accessed.
Can be configured as an Open-Drain
Output.
11 nRDATA
Raw serial bit stream from the disk drive,
low active. Each falling edge represents
a flux transition of the encoded data.
12 nWRTPRT
This active low Schmitt Trigger input
senses from the disk drive that a disk is
write protected. Any write command is
ignored. The nWRPRT bit also depends
upon the state of the Force Write Protect
bit in the FDD Option register (see the
Configuration Registers section).
13 nTRK0
This active low Schmitt Trigger input
senses from the disk drive that the head
is positioned over the outermost track.
14 nWGATE
Write Gate Output. This active low high
current driver allows current to flow
through the write head. It becomes active
just prior to writing to the diskette. Can be
configured as an Open-Drain Output.
15 nWDATA
Write Disk Data Output. This active low
high current driver provides the encoded
data to the disk drive. Each falling edge
causes a flux transition on the media.
Can be configured as an Open-Drain
Output.
DESCRIPTION
FDD INTERFACE (14)
BUFFER
NAME
(NOTE 2)
PWR
WELL
(NOTE 3)
NOTES
PCI_I VCC
OD8 VTR
IS VCC
O12 VCC
IS VCC
IS VCC
IS VCC
O12 VCC
O12 VCC
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 16 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
16 nSTEP
DESCRIPTION
Step Pulse Output. This active low high
BUFFER
NAME
(NOTE 2)
O12 VCC
PWR
WELL
(NOTE 3)
current driver issues a low pulse for each
track-to-track movement of the head.
Can be configured as an Open-Drain
Output.
17 nDIR
Step Direction Output. This high current
O12 VCC
low active output determines the direction
of the head movement. A logic “1” on this
pin means outward motion, while a logic
“0” means inward motion. Can be
configured as an Open-Drain Output.
18 nDS0
Drive Select 0 Output. Can be configured
O12 VCC
as an Open-Drain Output.
19 nMTR0
Motor On 0 Output. Can be configured as
O12 VCC
an Open-Drain Output.
20 nINDEX
This active low Schmitt Trigger input
IS VCC
senses from the disk drive that the head
is positioned over the beginning of a
track, as marked by an index hole.
21 DRVDEN1
Drive Density Select 1 Output. Indicates
O12 VCC
the drive and media selected. Can be
configured as Open-Drain Output.
22 DRVDEN0
Drive Density Select 0 Output. Indicates
O12 VCC
the drive and media selected. Can be
configured as Open-Drain Output.
SERIAL PORT 1 INTERFACE (8)
23 nDCD1
Active low Data Carrier Detect input for
I VCC
the serial port. Handshake signal that
notifies the UART that carrier signal is
detected by the modem. The CPU can
monitor the status of nDCD signal by
reading bit 7 of Modem Status Register
(MSR). A nDCD signal state change from
low to high after the last MSR read will set
MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of
nDCD.
24 nDSR1
Active low Data Set Ready input for the
I VCC
serial port. Handshake signal that notifies
the UART that the modem is ready to
establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR). A nDSR signal state
change from low to high after the last
MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the
interrupt is generated when nDSR
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
25 RXD1 Receiver serial data input. IS VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 17 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
26 nRTS1
DESCRIPTION
Active low Request to Send output for the
BUFFER
NAME
(NOTE 2)
O8 VCC
PWR
WELL
(NOTE 3)
Serial Port. Handshake output signal
notifies modem that the UART is ready to
transmit data. This signal can be
programmed by writing to bit 1 of the
Modem Control Register (MCR). The
hardware reset will reset the nRTS signal
to inactive mode (high). nRTS is forced
inactive during loop mode operation.
27 TXD1 Transmit serial data output. O12 VCC
28 nCTS1
Active low Clear to Send input for the
I VCC
serial port. Handshake signal that notifies
the UART that the modem is ready to
receive data. The CPU can monitor the
status of nCTS signal by reading bit 4 of
Modem Status Register (MSR). A nCTS
signal state change from low to high after
the last MSR read will set MSR bit 0 to a
1. If bit 3 of the Interrupt Enable Register
is set, the interrupt is generated when
nCTS changes state. The nCTS signal
has no effect on the transmitter.
Note: Bit 4 of MSR is the complement of
nCTS.
30 nDTR1
(XOR)
32 nRI1
Active low Data Terminal Ready output
for the serial port. Handshake output
signal notifies modem that the UART is
ready to establish data communication
link. This signal can be programmed by
writing to bit 0 of Modem Control Register
(MCR). The hardware reset will reset the
nDTR signal to inactive mode (high).
nDTR is forced inactive during loop mode
operation.
XOR Chain Output.
Active low Ring Indicator input for the
O8 VCC
I VTR 6
serial port. Handshake signal that notifies
the UART that the telephone ring signal is
detected by the modem. The CPU can
monitor the status of nRI signal by
reading bit 6 of Modem Status Register
(MSR). A nRI signal state change from
low to high after the last MSR read will set
MSR bit 2 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nRI changes state.
Note: Bit 6 of MSR is the complement of
nRI.
SERIAL PORT 2 INTERFACE (8)
118 nRI2
Active low Ring Indicator input for serial
IPD VTR 6, 10
port 2. See description for nRI1.
119 RXD2 Receiver serial data input. ISPD_400 VCC
120 TXD2 Transmit serial data output. O12 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 18 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
121 nDSR2
DESCRIPTION
Active low Data Set Ready input for serial
BUFFER
NAME
(NOTE 2)
IPD VCC 10
PWR
WELL
(NOTE 3)
port 2. See description for nDSR1.
122 nRTS2
Active low Request to Send output for
O8 VCC
Serial Port 2. See description for nRTS1.
124 nCTS2
Active low Clear to Send input for serial
IPD VCC 10
port 2. See description for nCTS1.
125 nDTR2
Active low Data Terminal Ready output
O8 VCC
for serial port 2. See description for
nDTR1.
126 nDCD2
Active low Data Carrier Detect input for
IPD VCC 10
serial port 2. See description for nDCD1.
INFRARED INTERFACE (2)
127 IRRX2 Infrared receive input. ISPD_400 VCC 10
128 IRTX2 Infrared transmit output. O12 VCC 9
PARALLEL PORT INTERFACE (17)
33 SLCT
This high active input from the printer
I VCC
indicates that it has power on. Bit 4 of the
Printer Status Register reads the SLCT
input. Refer to Parallel Port description
for use of this pin in ECP and EPP mode.
34 PE
Another status input from the printer, a
I VCC
high indicating that the printer is out of
paper. Bit 5 of the Printer Status Register
reads the PE input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
35 BUSY
This is a status input from the printer, a
I VCC
high indicating that the printer is not ready
to receive new data. Bit 7 of the Printer
Status Register is the complement of the
BUSY input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
36 nACK
A low active input from the printer
I VCC
indicating that it has received the data
and is ready to accept new data. Bit 6 of
the Printer Status Register reads the
nACK input. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
37 PD7 Port Data 7 I/O IOP14 VCC
38 PD6 Port Data 6 I/O IOP14 VCC
39 PD5 Port Data 5 I/O IOP14 VCC
40 PD4 Port Data 4 I/O IOP14 VCC
41 PD3 Port Data 3 I/O IOP14 VCC
42 PD2 Port Data 2 I/O IOP14 VCC
43 PD1 Port Data 1 I/O IOP14 VCC
44 PD0 Port Data 0 I/O IOP14 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 19 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
45 nERROR
DESCRIPTION
A low on this input from the printer
BUFFER
NAME
(NOTE 2)
I VCC
PWR
WELL
(NOTE 3)
indicates that there is an error condition at
the printer. Bit 3 of the Printer Status
register reads the nERR input. Refer to
Parallel Port description for use of this pin
in ECP and EPP mode.
47 nSLCTIN
This active low output selects the printer.
OP14 VCC
This is the complement of bit 3 of the
Printer Control Register. Refer to Parallel
Port description for use of this pin in ECP
and EPP mode.
Can be Configured as an Open-Drain
Output.
48 nINITP
This output is bit 2 of the printer control
OP14 VCC
register. This is used to initiate the printer
when low. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode. Can be configured as an
Open-Drain Output.
50 nALF
This output goes low to cause the printer
OP14 VCC
to automatically feed one line after each
line is printed. The nALF output is the
complement of bit 1 of the Printer Control
Register. Refer to Parallel Port
description for use of this pin in ECP and
EPP mode.
Can be configured as an Open-Drain
Output.
51 nSTROBE
An active low pulse on this output is used
OP14 VCC
to strobe the printer data into the printer.
The nSTROBE output is the complement
of bit 0 of the Printer Control Register.
Refer to Parallel Port description for use
of this pin in ECP and EPP mode.
Can be configured as an Open-Drain
Output.
KEYBOARD/MOUSE INTERFACE (6)
1 MCLK Mouse Clock I/O IOD24 VCC
2 MDAT Mouse Data I/O IOD24 VCC 6
3 KCLK Keyboard Clock I/O IOD24 VCC
4 KDAT Keyboard Data I/O IOD24 VCC 6
5 GA20M Gate A20 Open-Drain Output OD8 VCC 7
7 nKBDRST Keyboard Reset Open-Drain Output OD8 VCC 7
GLUE PINS (29)
64 nIDE_RSTDRV IDE Reset Output OD8 VCC 3
66 nHD_LED
Hard Drive Front Panel LED Open-Drain
OD12 VCC 3
Output
67
nPRIMARY_
IDE Primary Drive Active Input ISPU_400 VCC
HD
68
nSECONDARY
IDE Secondary Drive Active Input ISPU_400 VCC
_HD
69 nSCSI SCSI Drive Active Input ISPU_400 VCC
NOTES
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 20 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
NAME
(NOTE 1)
DESCRIPTION
BUFFER
NAME
(NOTE 2)
PWR
WELL
(NOTE 3)
NOTES
73 nPCIRST_OUT Buffered PCI Reset Output OP14 VTR
74
nPCIRST_OUT
Second Buffered PCI Reset Output OP14 VTR
2
75 nFPRST Reset Input from Front Panel ISPU_400 VTR
77
nBACKFEED_
Open-Drain Output used for STR Circuitry OD8 VTR 3
CUT
79
LATCHED_BF_
CUT
80
SCK_BJT_
GATE
81 nPS_ON
Latched Backfeed Cut Output for STR
Circuitry
Open-Drain Gate Output for the SCK_BJT
in Suspend-to-RAM
Power Supply Turn-ON Open Drain
OP14 VTR
OD8 VTR 3
OD8 VTR 3
Output
82 PWRGD_PS Power Good Input from Power Supply ISPU_400 VTR
83
nCPU_PRESENT
CPU Present Input from Processor ISPU_400 VTR
84 PWRGD_3V Power Good Output O8 VTR
85 nSLP_S3 S3 Power State Input from South Bridge IS_400 VTR
86 nSLP_S5
Input from South Bridge for Transitioning
IS_400 VTR
to the S5 Power State
87 SMB_CLK_M SMBus Clock Main IO_SW VTR
88 SMB_CLK_R SMBus Clock Resume IO_SW VTR
89 SMB_DAT_M SMBus Data Main IO_SW VTR
90 SMB_DAT_R SMBus Data Resume IO_SW VTR
92 nRSMRST Resume Reset Output O8 VTR
100
nAUD_LINK_
AC97 Link Reset Input I VTR
RST
101
nCDC_DWN_
ENAB/GP24
AC97 Codec Down Enable Input.
General Purpose I/O. GPIO can be
IO12 VTR 6
configured as an open-drain output.
102
nCDC_DWN_
AC97 Codec Down Reset Output. O12 VTR
RST
113 DDCSCL_3V/
GP23
3.3V DDC Clock
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
114 DDCSCL_5V/
GP21
5V DDC Clock
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
115 DDCSDA_3V/
GP22
3.3V DDC Data
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
116 DDCSDA_5V/
GP20
5V DDC Data
General Purpose I/O. GPIO can be
IO_SW/IS
OD8
VTR 3, 6, 8
configured as an open-drain output.
POWER LEDS (2)
94 GRN_LED Green Power LED Open-Drain Output OD24 VTR
95 YLW_LED Yellow Power LED Open-Drain Output OD24 VTR
GENERAL PURPOSE I/O (8)
103105
GP10-GP12
General Purpose I/O. GPIO can be
configured as an open-drain output.
ISO8 VTR 6
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 21 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
PIN#
106,
108,
NAME
(NOTE 1)
GP13-GP15
DESCRIPTION
General Purpose I/O. GPIO can be
configured as an open-drain output.
BUFFER
NAME
(NOTE 2)
IO8 VTR 6
PWR
WELL
(NOTE 3)
NOTES
109
111 GP16/
FAN_TACH1
112 GP17/
FAN_TACH2
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 1 Input
General Purpose I/O. GPIO can be
configured as an open-drain output.
Fan Tachometer 2 Input
IO8 VTR 6
IO8 VTR 6
TEST (1)
98 TEST_EN
Test Enable Input for XOR-Chain test –
IPD VTR
the external pull-up or internal pull-down
sets the strap value. The XOR output is
the nDTR1 pin.
NO CONNECT (1)
See Note11
117 NC No Connect IPD - 11
Note 1: The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low”
signal. The primary and secondary functions on the pins are separated by “/”.
Note 2: The buffer names are described in the “Buffer Name Descriptions” section.
Note 3: Open-drain pins should be pulled-up externally to supply shown in the power well column. The
nIDE_RSTDRV, nHD_LED, DDCSDA_5V and DDCSCL_5V open-drain pins require external pull-ups to
VCC5V. The nBACKFEED_CUT, SCK_BJT_GATE and nPS_ON open-drain pins require external pullups to V_5P0_STBY. Inputs with internal pull-ups are pulled internally to the supply shown in the power
well column. All other pins are driven under the power well shown. See the “Pins With Internal Resistors”,
“Pins That Require External Resistors” and “Default State of Pins” sections.
Note 4: The 32.768 kHz input clock must not be driven high when VTR = 0V. CLOCKI32 is clock source to various
logic in the part, including LED, “wake on specific key” and nFPRST debounce circuitry. The 32 KHz input
clock must always be connected. There is a bit in the configuration register at 0xF0 in Logical Device A
that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the
logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).
Note 5: The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal
follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”.
However, if nLPCPD is tied high, the keyboard wakeup isolation logic will be affected.
Note 6: These pins (except DDC and FAN_TACH functions) are also inputs to VTR powered logic internal to the
part. If DDC and FAN_TACH functions are selected on GPIOs, the pins will tri-state when VCC power is
removed.
Note 7: External pullups must be placed on the nKBDRST and GA20M pins. If the nKBDRST and GA20M
functions are to be used, the system must ensure that these pins are high. See the “That Require External
Resistors” section.
Note 8: When DDC functions are selected on GP20-GP23, the pins become IO_SW type and require external pull-
ups to the appropriate voltages. See the “That Require External Resistors” section. When the GPIO
functions are selected, the pins are IS0D8.
Note 9: The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC
POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 22 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
time the pin will reflect the state of the transmit output of the Serial Port 2 block. This is a VCC powered
pin.
Note 10: These pins are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial Port 2 is
enabled, the pull-downs are removed until VTR POR.
Note 11: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the
TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the
LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin has an
internal pull-down resistor that selects the non-SMSC (Intel Compatible) mode. To select this mode, the
pin should be left unconnected. Connecting this pin to VTR will select the SMSC mode of the logical
device numbering.
3.1 Buffer Name Descriptions
Note: Refer to the “Electrical Characteristics” section.
PWR Power and Ground
I Input TTL Compatible.
IPU Input with 30uA Integrated Pull-Up
IPD Input with 30uA Integrated Pull-Down
IS Input with 250mV Schmitt Trigger.
IS_400 Input with 400mV Schmitt Trigger.
ISPU_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up.
ISPD_400 Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Down.
O8 Output, 8mA sink, 4mA source.
OD8 Output (Open Drain), 8mA sink.
O12 Output, 12mA sink, 6mA source.
OD12 Output (Open Drain), 12mA sink.
OP14 Output, 14mA sink, 14mA source.
OD24 Output (Open Drain), 24mA sink.
AO Output – Analog with 5V Level
IO8 Input/Output, 8mA sink, 4mA source.
ISO8 Input with 250mV Schmitt Trigger /Output, 8mA sink, 4mA source.
ISOD8 Input with 250mV Schmitt Trigger, Low Leakage/Output (Open-Drain), 8mA sink.
IO12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source.
IOP14 Input/Output, 14mA sink, 14mA source.
IOD24 Input/Output (Open Drain), 24mA sink.
IO_SW Input/Output, special type. Pins of this type are connected in pairs through a switch. The switch
provides a 25 ohm (max) resistance to ground when closed.
PCI_IO Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_O Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_I Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1)
PCI_ICLK Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2)
Note 1: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
Note 2: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 23 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
3.2 Pins With Internal Resistors
The following pins have internal resistors:
Table 3.2 - Pins with Internal Resistors
SIGNAL NAME RESISTOR VALUE NOTES
nCPU_PRESENT 30uA Pull-up to VTR
nFPRST 30uA Pull-up to VTR
nPRIMARY_HD 30uA Pull-up to VCC
PWRGD_PS 30uA Pull-up to VTR
nSCSI 30uA Pull-up to VCC
nSECONDARY_HD 30uA Pull-up to VCC
TEST_EN 30uA Pull-down to VSS
3.3 Pins That Require External Resistors
The following pins require external resistors:
Table 3.3 - Pins that Require External Resistors
SIGNAL NAME RESISTOR VALUE NOTES
SER_IRQ 10 kohm Pull-up to VCC
nLDRQ 100 kohm Pull-up to VCC
LAD[3:0] 100 kohm Pull-up to VCC
MCLK
MDAT
KCLK
KDAT
GA20M 10 kohm Pull-up to VCC
KBDRST 10 kohm Pull-up to VCC
nIO_PME 10 kohm Pull-up to VTR
nHDSEL 10 kohm
nWGATE 10 kohm
nWDATA 10 kohm
nSTEP 10 kohm
nDIR 10 kohm
nDS0 10 kohm
nMTR0 10 kohm
DRVDEN1 10 kohm
DRVDEN0 10 kohm
nDSKCHG 1 kohm Pull-up to VCC
nRDATA 1 kohm Pull-up to VCC
nWRTPRT 1 kohm Pull-up to VCC
nTRK0 1 kohm Pull-up to VCC
nINDEX 10 kohm Pull-up to VCC
REF5V 1 kohm Pull-up to VCC5V
REF5V_STBY 1 kohm Pull-up to V_5P0_STBY
2.7 kohm
Pull-up to VREG_PS2. The
VREG_PS2 is the voltage
regulator for the PS/2 ports.
Pull-up required if used as
Open-Drain Output.
Pull-up to VCC.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 24 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME RESISTOR VALUE NOTES
nIDE_RSTDRV 1 kohm Pull-up to VCC5V
nPS_ON 1 kohm Pull-up to V_5P0_STBY
nBACKFEED_CUT 1 kohm Pull-up to V_5P0_STBY
SCK_BJT_GATE 1 kohm Pull-up to V_5P0_STBY
nCDC_DWN_ENAB 10 kohm Pull-down to VSS
YLW_LED 220 ohm Pull-up to VTR
nHD_LED 330 ohm Pull-up to VCC
DDCSDA_3V 4.7 kohm Pull-up to VCC
DDCSCL_3V 4.7 kohm Pull-up to VCC
DDCSDA_5V 2.2 kohm Pull-up to VCC5V
DDCSCL_5V 2.2 kohm Pull-up to VCC5V
SMB_CLK_M 2.7 kohm Pull-up to VCC
SMB_CLK_R 2.7 kohm Pull-up to VTR
SMB_DAT_M 2.7 kohm Pull-up to VCC
SMB_DAT_R 2.7 kohm Pull-up to VTR
GRN_LED 220 ohm Pull-up to VTR
GPIOs
design-dependant
Pull-up to appropriate voltage
(not to exceed 5V)
3.4 Default State of Pins
The following table shows the default state of pins.
Notes:
Off
The pin is not powered by suspend supply and is valid under main power only.
Hi-Z
The pin is powered, but tri-stated either because the pin is open-drain or VCC function is selected on VTR
powered pin. The pin requires external pull-up when tri-stated.
Active
The pin is powered and active high.
Running
The input clock is powered and running.
Input
The pin is powered and driven by external circuitry to high or low level.
Out
The pin is powered and driven to high or low level by the part.
The input or output configuration state of the pin is retained and is not affected by PCI Reset or VCC POR.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 25 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 3.4 - Default State of Pins
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
REF5V_STBY VTR - - Active
REF5V VCC Active Active Off
This pin requires external pullup to V_5P0_STBY
This pin requires external pull-
up to VCC5V
CLOCKI VCC Running Running Off
CLOCKI32 VTR Running Running Running
nIO_PME VTR - - Hi-Z
PCI_CLK VCC Input Input Off
nLPCPD VCC Input Input Off
nPCI_RESET VCC Input Input Off
SER_IRQ VCC Input Input Off
nLDRQ VCC Input Input Off
nLFRAME VCC Input Input Off
LAD[0:3] VCC Input Input Off
nDSKCHG VCC Input Input Off
nHDSEL VCC Out – low Out – low Off
nRDATA VCC Input Input Off
nWRTPRT VCC Input Input Off
nTRK0 VCC Input Input Off
nWGATE VCC Hi-Z Hi-Z Off
nWDATA VCC Hi-Z Hi-Z Off
nSTEP VCC Out – low Out – low Off
nDIR VCC Out – low Out – low Off
nDS0 VCC Hi-Z Hi-Z Off
nMTR0 VCC Hi-Z Hi-Z Off
nINDEX VCC Input Input Off
DRVDEN0 VCC Out – high Out – high Off
DRVDEN1 VCC Out – high Out – high Off
nDCD1 VCC Input Input Off
nDSR1 VCC Input Input Off
RXD1 VCC Input Input Off
nRTS1 VCC Out – high Out – high Off
TXD1 VCC Out – low Out – low Off
nCTS1 VCC Input Input Off
nDTR1 (XOR) VCC Out – high Out – high Off
nRI1 VTR - - Input
This pin is internally pulled
nDCD2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
nDSR2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
RXD2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
nRTS2 VCC Out – high Out – high Off
TXD2 VCC Out – low Out – low Off
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 26 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
This pin is internally pulled
nCTS2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
nDTR2 VCC Out – high Out – high Off
This pin is internally pulled
nRI2 VTR - - Input
down to VSS until Serial Port 2
is enabled.
This pin is internally pulled
IRRX2 VCC Input Input Off
down to VSS until Serial Port 2
is enabled.
IRTX2 VCC Out – low Out – low Off
SLCT VCC Input Input Off
PE VCC Input Input Off
BUSY VCC Input Input Off
nACK VCC Input Input Off
PD[7:0] VCC Input Input Off
ERROR VCC Input Input Off
nSLCTIN VCC Out – High Out – High Off
nINITP VCC Out – High Out – High Off
nALF VCC Out – High Out – High Off
nSTROBE VCC Out – High Out – High Off
MCLK VCC Hi-Z Hi-Z Off
MDAT VCC - - Input
KCLK VCC Hi-Z Hi-Z Off
KDAT VCC - - Input
GA20M VCC Hi-Z Hi-Z Off
nKBDRST VCC Hi-Z Hi-Z Off
nAUD_LINK_RST VTR - - Input
nCDC_DWN_ENAB/
GP24
VTR - - Input
nCDC_DWN_RST VTR - - Out – low
nFPRST VTR - - Input This pin is pulled up internally
nBACKFEED_CUT VTR - - Hi-Z
This pin requires external pull-
up to V_5P0_STBY.
LATCHED_BF_CUT VTR - - Out – low
SCK_BJT_GATE VTR - - Hi-Z
This pin requires external pull-
up to V_5P0_STBY.
nSCSI VCC Input Input Off This pin is pulled up internally
GRN_LED VTR - - Out – low
YLW_LED VTR - - Out – low
nHD_LED VCC Hi-Z Hi-Z Off
nSECONDARY_HD VCC Input Input Off This pin is pulled up internally
nPRIMARY_HD VCC Input Input Off This pin is pulled up internally
nIDE_RSTDRV VCC Out – low Out – low Off
Requires external pull-up to
VCC5V
PWRGD_PS VTR - - Input
nPS_ON VTR - - Hi-Z
Requires external pull-up to
V_5P0_STBY
nCPU_PRESENT VTR - - Input This pin is pulled up internally
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 27 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
SIGNAL NAME PWR WELL PCI RESET VCC POR VTR POR NOTES
nSLP_S3 VTR - - Input
nSLP_S5 VTR - - Input
nRSMRST VTR - - Out – low
PWRGD_3V VTR - - Out – low
nPCIRST_OUT VTR Out – low Out – low Out – low
nPCIRST_OUT2 VTR Out – low Out – low Out – low
VTR
VTR
- - Input
The GPIO and FAN_TACH
Hi-Z Hi-Z Hi-Z
functions are multiplexed on
the same pin with GPIO as the
Hi-Z Hi-Z Hi-Z
default function.
GP10-GP15 VTR
GP16 - - Input
FAN_TACH1
GP17 - - Input
FAN_TACH2
SMB_CLK_M VTR Hi-Z Hi-Z Hi-Z
SMB_CLK_R VTR - - Hi-Z
SMB_DAT_M VTR Hi-Z Hi-Z Hi-Z
SMB_DAT_R VTR - - Hi-Z
DDCSDA_5V Hi-Z Hi-Z Hi-Z
VTR
GP20
- - Hi-Z
DDCSCL_5V Hi-Z Hi-Z Hi-Z
VTR
GP21
- - Hi-Z
DDCSDA_3V Hi-Z Hi-Z Hi-Z
VTR
GP22
DDCSCL_3V Hi-Z Hi-Z Hi-Z
VTR
GP23
- - Hi-Z
- - Hi-Z
TEST_EN VTR - - Input
The DDC and GPIO functions
are multiplexed on the same
pin with DDC as the default
function. DDC function
requires external pull-up to
VCC5V.
The DDC and GPIO functions
are multiplexed on the same
pin with DDC as the default
function. DDC function
requires external pull-up to
VCC.
Test Mode pin. This pin has
internally pull-down to VSS.
External pull-up required to
enable the test mode.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 28 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 4 Block Diagram
SER_IRQ
PCI_CLK
LAD[3:0]
nLFRAME
nLDRQ
nPCI_RESET
nLPCPD
nIO_PME
GP10-GP15, GP16*, GP17*
(GP20-GP23)*
GP24*
F_CAP
V_5P0_STBY
nRSMRST
REF5V
REF5V_STBY
nAUD_LINK_RST
nCDC_DWN_ENAB*
nCDC_DWN_RST
nPCI_RST_OUT
nPCI_RST_OUT2
nIDE_RSTDRV
nPRIMARY_HD
nSECONDARY_HD
LATCHED_BF_CUT
nSCSI
nHD_LED
nFPRST
nBACKFEED_CUT
SCK_BJT_GATE
nPS_ON
PWRGD_PS
SERIAL IRQ /
Interrupt
Generating
Registers
LPC
Bus Interface
PME /
Power Contro l
GPIOs
Resume Reset
Generation
5V Reference
Generation
CNR Logic
Buffered
PCI Reset
Hard Drive
Front Panel
LED
Power
Sequencing
CLOCKI32
CLOCK
nPCI_RESET
SMBus
Isolatio n
CLOCKI
GEN
Configuration
Registers
Translation
GRN_LED
Power LED
nSLP_S5
(Data, Address, and Control lines)
VCC (3.3V) VT R (3.3V)
VGA
Voltage
YLW_LED
Internal Bus
LPC47M172
(128 QFP)
V_5P0_STBY
SMSC PROPRIETARY
82077 COMPATIBLE
VERTICAL FLOPPYDISK
CONTROLLER CORE
FAN_TACH2*
FAN_TACH1*
FAN
Monitoring
WDATA
WCLOCK
RCLOCK
RDATA
TEST_EN
XOR*
XOR-Chain
Multi-Mod e
Parallel Port with
Keyboard/Mouse
8042 Controller
ChiProtect
High-Speed
16550A UART
PORT
High-Speed
16550A UART
PORT 2
W/ Infrared
DIGITAL DATA
SEPARATOR
WITH WRITE
PRECOM-
PENSATION
TM
PD[7:0]
BUSY, SLCT , PE,
nERROR, nACK
nSTROBE, nINITP,
nSLCTIN, nALF
RXD
TXD
nCTS
nRTS
nDSR
nDTR*
nDCD
nRI
RXD2
TXD2
nCTS2
nRTS2
nDSR2
nDTR2
nDCD2
nRI2
IRRX2
IRTX2
KDAT, MDAT
KCLK, MCLK
GA20M
nKBDRST
Note 1: This diagram shows the
various functions available on the chip
nRDATA
nSLP_S3
nSLP_S5
PWRGD_3V
nCPU_PRESENT
SMB_CLK_R
SMB_DAT_R
SMB_DAT_M
SMB_CLK_M
DDCSCL_3V*
DDCSCL_5V*
DDCSDA_3V*
DDCSDA_5V*
nDIR, nSTEP,
nDS0, nMTR0
nWGATE, nHDSEL
nTRK0, nDSKCHG,
DRVDEN0, DRVDEN1
nINDEX, nWRT PRT
nWDATA
(not pin layout). The block diagram
should not be used for pin count.
Note 2: Func tions with asterisks (*)
are located on multifunctional pins.
Figure 4.1 - LPC47M172 Block Diagram
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 29 SMSC LPC47M172
DATASHEET
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Chapter 5 Power and Clock Functionality
The LPC47M172 has three power planes: VCC, VTR and V5P0_STBY.
5.1 3 Volt Operation / 5 Volt Tolerance
The LPC47M172 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V
tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive
protected (they do not impose a load on any external VCC powered circuitry).
The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. The
nRSMRST pin is also 3.3V only.
The following lists the pins that are 3.3V only (not 5V tolerant):
LAD[3:0]
nLFRAME
nLDRQ
nLPCPD
nRSMRST
The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following
pins:
nPCI_RESET
PCI_CLK
SER_IRQ
nIO_PME
5.2 VCC Power
The LPC47M172 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational
Description” Section and the “Maximum Current Values” subsection.
5.3 VTR Power
The LPC47M172 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up
events in the PME interface and other suspend state logic when VCC is removed. The VTR supply is 3.3
Volts (nominal). See the Operational Description Section. The maximum VTR current that is required
depends on the functions that are used in the part. See Trickle Power Functionality subsection and
Maximum Current Values subsection. If the LPC47M172 is not intended to provide wake-up and/or
suspend power capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a
VTR Power-on-Reset signal to initialize these components.
Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full
minimum potential at least 10 µs before VCC begins a power-on cycle. When VTR and VCC are fully
powered, the potential difference between the two supplies must not exceed 500mV.
SMSC/Non-SMSC Register Sets (Rev. 02-27-04) Page 30 SMSC LPC47M172
DATASHEET
Loading...