SMSC LPC47M14x Technical data

128 Pin Enhanced Super I/O Controller

with an LPC Interface and USB Hub

 3.3 Volt Operation (5 Volt Tolerant)  LPC Interface  ACPI 1.0 Compliant  Fan Control

- Fan Speed Control Outputs

- Fan Tachometer Inputs

 Programmable Wake-up Event Interface  PC98, PC99 Compliant  Dual Game Port Interface  MPU-401 MIDI Support  General Purpose Input/Output Pins  ISA Plug-and-Play Compatible Register Set  Intelligent Auto Power Management  System Management Interrupt  2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core

- Supports Two Floppy Drives

- Configurable Open Drain/Push-Pull Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM Compatibility

- Detects All Overrun and Underrun Conditions

- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, Up to Eight IRQ and Four DMA Options

 Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

- Programmable Precompensation Modes

FEATURES

 Keyboard Controller

 Serial Ports

 Infrared Port

 Multi-Mode Parallel Port with ChiProtect

LPC47M14x

PRELIMINAR

- 8042 Software Compatible

- 8 Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface

- Asynchronous Access to Two Data Registers and One Status Register

- Supports Interrupt and Polling Access

- 8 Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- Two Full Function Serial Ports

- High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs

- Supports 230k and 460k Baud

Programmable Baud Rate Generator Modem Control Circuitry

- 480 Address and 15 IRQ Options

- Multiprotocol Infrared Interface

- IrDA 1.0 Compliant

- SHARP ASK IR

- 480 Addresses, Up to 15 IRQ

- Standard Mode IBM PC/XT, PS/2 Compatible Bi-directional Parallel Port

- Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

- ChiProtect Circuitry for Protection

- 960 Address, Up to 15 IRQ and Four DMA Options

PC/AT, and

SMSC DS – LPC47M14X Rev. 03/19/2001

 USB Hub

- 1 Upstream and up to 4 Downstream Ports

- Compliant with USB Spec. version 1.1

- Programmable USB Manufacturer ID, Product ID and Device Rev. Number

- Number of active ports programmable or selectable via jumpers

- Powered by Vtr for Downstream Port Wakeup

 LPC Interface

- Multiplexed Command, Address and Data Bus

- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems

- PME Interface

 Interrupt Generating Registers

- Registers Generate IRQ1 – 15 on Serial IRQ Interface

ORDERING INFORMATION

Order Number: LPC47M14x – NC

128 Pin QFP Packa

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

80 Arkay Drive

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

SMSC DS – LPC47M14X Page 2 Rev. 03/19/2001

GENERAL DESCRIPTION

The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller with an LPC interface and a standalone USB hub. It is designed to be compatible with a family of Super I/O Controllers (LPC47M13x, LPC47M14x, and LPC47M15x). To the interested reader, the LPC47M15x offers hardware monitoring capabilities. The first one hundred pins of all these packages are completely pin compatible and offer the designer added flexibility in their board designs. In addition, any board designed to support the LPC47M14x will automatically offer the dual capability of supporting the LPC47M13x, as well.

The LPC47M14x implements the LPC interface, a pin reduced ISA bus interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. This interface makes use of the PCI clock, which runs at 33MHz instead of the traditional 8MHz for the ISA bus, that eases some complications found in synchronous designs. In addition, all legacy drivers used for Super I/O components are still supported making this new interface transparent to the supporting software. The LPC bus also supports power management, such as wake-up and sleep modes, in the same way as the PCI bus.

The LPC47M14X incorporates a standalone USB Hub, implementing one upstream port and up to four (4) downstream ports, with an internal data path connection for programming the USB Vendor ID, Product ID and Device Revision Number. The number of active downstream ports is also programmable or selectable with external jumpers. This programming is done by BIOS accessing the hub control registers.

The LPC47M14x has incorporated the following Super I/O components: a parallel port that is compatible with IBM PC/AT architecture, as well as the IEEE 1284 EPP and ECP; two serial ports that are 16C550A UART compatible; a keyboard/mouse controller that uses an 8042 microcontroller; two floppy controllers, which use SMSC's true CMOS 765B core; two infrared ports that are IrDA 1.0 compliant; a MIDI interface, which is a MPU-401-compatible; and 37 General Purpose I/O control functions, which offer flexibility to the system designer. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with the 82077AA. This chip also controls two LED’s, a dual game port interface, and the speed of two fans with fan tachometer inputs through the use of a pulse width modulation scheme.

The LPC47M14x is ACPI 1.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events.

The LPC47M14X supports the ISA Plug-and-Play Standard (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M14X may be reprogrammed through the internal configuration registers. There are 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and four DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.

The LPC47M14X does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area.

* The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip.

SMSC DS – LPC47M14X Page 3 Rev. 03/19/2001

TABLE OF CONTENTS

1 PIN LAYOUT ..........................................................................................................................................................8

2 PIN CONFIGURATION...........................................................................................................................................9

3 DESCRIPTION OF PIN FUNCTIONS...................................................................................................................10

3.1 B

3.2 P

4 BLOCK DIAGRAM ............................................................................................................................................... 16

5 POWER FUNCTIONALITY...................................................................................................................................17

5.1 VCC POWER..................................................................................................................................................17

5.2 USB POWER.................................................................................................................................................. 17

5.3 VTR S

5.4 VREF P

5.5 I

5.6 32.768

5.7 T

5.8 M

5.9 P

6 FUNCTIONAL DESCRIPTION .............................................................................................................................20

6.1 S

6.2 H

6.3 LPC I

6.4 USB H

6.5 FLOPPY DISK CONTROLLER .................................................................................................................... 26

6.6 SERIAL PORT (UART) ................................................................................................................................60

6.7 INFRARED INTERFACE..............................................................................................................................72

6.8 MPU-401 MIDI UART................................................................................................................................... 73

6.9 PARALLEL PORT ........................................................................................................................................78

6.10 POWER MANAGEMENT............................................................................................................................. 94

6.11 SERIAL IRQ ................................................................................................................................................. 98

6.12 INTERRUPT GENERATING REGISTERS..............................................................................................................101

6.13 8042 KEYBOARD CONTROLLER DESCRIPTION ...................................................................................102

UFFER TYPE DESCRIPTIONS........................................................................................................................... 14

INS THAT REQUIRE EXTERNAL PULLUP RESISTORS ..........................................................................................15

5.1.1 3 Volt Operation / 5 Volt Tolerance......................................................................................................... 17

UPPORT ............................................................................................................................................... 17

IN .....................................................................................................................................................17

NTERNAL PWRGOOD ...................................................................................................................................18

KHZ TRICKLE CLOCK INPUT ..................................................................................................................18

RICKLE POWER FUNCTIONALITY...................................................................................................................... 18

AXIMUM CURRENT VALUES............................................................................................................................19

OWER MANAGEMENT EVENTS (PME/SCI) ......................................................................................................19

UPER I/O REGISTERS....................................................................................................................................20

OST PROCESSOR INTERFACE (LPC) ............................................................................................................... 20

NTERFACE .............................................................................................................................................21

6.3.1 LPC Interface Signal Definition...............................................................................................................21

6.3.2 LPC Cycles.............................................................................................................................................21

6.3.3 Field Definitions ......................................................................................................................................21

6.3.4 LFRAME# Usage.................................................................................................................................... 21

6.3.5 I/O Read and Write Cycles .....................................................................................................................22

6.3.6 DMA Read and Write Cycles ..................................................................................................................22

6.3.7 DMA Protocol .........................................................................................................................................22

6.3.8 Power Management................................................................................................................................22

6.3.9 SYNC Protocol .......................................................................................................................................22

6.3.10 LPC Transfer ..........................................................................................................................................23

UB FUNCTIONAL DESCRIPTION ...............................................................................................................24

6.4.1 USB Downstream Port Selection............................................................................................................25

6.5.1 FDC Internal Registers ...........................................................................................................................27

6.5.2 STATUS REGISTER ENCODING..........................................................................................................37

6.5.3 Instruction Set......................................................................................................................................... 43

6.5.4 DATA TRANSFER COMMANDS............................................................................................................50

6.8.1 Overview.................................................................................................................................................73

6.8.2 Host Interface .........................................................................................................................................73

6.8.3 MIDI Data Port........................................................................................................................................74

6.8.4 Status Port..............................................................................................................................................74

6.8.5 MPU-401 Command Controller ..............................................................................................................76

6.8.6 MIDI UART .............................................................................................................................................77

6.8.7 MPU-401 Configuration Registers ..........................................................................................................77

6.9.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes ......................................................................... 79

6.9.2 Extended Capabilities Parallel Port.........................................................................................................84

6.13.1 Keyboard Interface ...............................................................................................................................103

6.13.2 External Keyboard and Mouse Interface...............................................................................................104

6.13.3 Keyboard Power Management ............................................................................................................. 104

6.13.4 Interrupts ..............................................................................................................................................104

6.13.5 Memory Configurations.........................................................................................................................104

6.13.6 Register Definitions...............................................................................................................................105

SMSC DS – LPC47M14X Page 4 Rev. 03/19/2001

6.13.7 External Clock Signal............................................................................................................................105

6.13.8 Default Reset Conditions ...................................................................................................................... 105

6.13.9 Latches On Keyboard and Mouse IRQs ...............................................................................................108

6.13.10 Keyboard and Mouse PME Generation ................................................................................................ 109

6.14 GENERAL PURPOSE I/O..........................................................................................................................110

6.14.1 GPIO Pins.............................................................................................................................................110

6.14.2 Description............................................................................................................................................111

6.14.3 GPIO Control ........................................................................................................................................ 112

6.14.4 GPIO Operation....................................................................................................................................112

6.14.5 GPIO PME and SMI Functionality......................................................................................................... 113

6.14.6 Either Edge Triggered Interrupts...........................................................................................................114

6.14.7 LED Functionality..................................................................................................................................115

6.15 SYSTEM MANAGEMENT INTERRUPT (SMI)...........................................................................................115

6.15.1 SMI Registers .......................................................................................................................................115

6.16 PME SUPPORT.........................................................................................................................................116

6.16.1 ‘Wake on Specific Key’ Option..............................................................................................................117

6.17 FAN SPEED CONTROL AND MONITORING............................................................................................118

6.17.1 Fan Speed Control................................................................................................................................118

6.17.2 Fan Tachometer Inputs.........................................................................................................................119

6.18 SECURITY FEATURE ...............................................................................................................................122

6.18.1 GPIO Device Disable Register Control ................................................................................................. 122

6.18.2 Device Disable Register .......................................................................................................................122

6.19 GAME PORT LOGIC..................................................................................................................................122

6.19.1 Power Control Register.........................................................................................................................124

6.19.2 VREF Pin..............................................................................................................................................124

7 RUNTIME REGISTERS......................................................................................................................................125

8 CONFIGURATION..............................................................................................................................................152

9 OPERATIONAL DESCRIPTION ........................................................................................................................172

9.1 M

9.2 DC E

AXIMUM GUARANTEED RATINGS...................................................................................................................172

LECTRICAL CHARACTERISTICS................................................................................................................ 172

10 TIMING DIAGRAMS........................................................................................................................................... 177

11 PACKAGE OUTLINE .........................................................................................................................................200

12 APPENDIX - TEST MODE..................................................................................................................................201

12.1 B

OARD TEST MODE.......................................................................................................................................201

12.1.1 XNOR-Chain Test Mode.......................................................................................................................201

13 REFERENCE DOCUMENTS..............................................................................................................................204

14 LPC47M14X REVISIONS...................................................................................................................................205

TABLES

Table 1 – Super I/O Block Addresses ........................................................................................................................20

Table 2 – Hub Descriptor to be Modified....................................................................................................................25

Table 3 – Status, Data and Control Registers............................................................................................................27

Table 4 – Tape Select Bits .........................................................................................................................................30

Table 5 – Internal 2 Drive Decode - Normal ...............................................................................................................30

Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................31

Table 7 – Drive Type ID .............................................................................................................................................31

Table 8 – Precompensation Delays ...........................................................................................................................32

Table 9 – Data Rates .................................................................................................................................................33

Table 10 – DRVDEN Mapping ...................................................................................................................................33

Table 11 – Default Precompensation Delays .............................................................................................................33

Table 12 – FIFO Service Delay..................................................................................................................................35

Table 13 – Status Register 0......................................................................................................................................37

Table 14 – Status Register 1......................................................................................................................................38

Table 15 – Status Register 2......................................................................................................................................38

Table 16 – Status Register 3......................................................................................................................................39

Table 17 – Description of Command Symbols ...........................................................................................................41

Table 18 – Instruction Set ..........................................................................................................................................43

Table 19 – Sector Sizes .............................................................................................................................................50

Table 20 – Effects of MT and N Bits...........................................................................................................................51

Table 21 – Skip Bit vs Read Data Command.............................................................................................................51

SMSC DS – LPC47M14X Page 5 Rev. 03/19/2001

Table 22 – Skip Bit vs. Read Deleted Data Command...............................................................................................51

Table 23 – Result Phase Table ..................................................................................................................................52

Table 24 – Verify Command Result Phase Table ......................................................................................................53

Table 25 – Typical Values for Formatting...................................................................................................................55

Table 26 – Interrupt Identification...............................................................................................................................56

Table 27 – Drive Control Delays (ms) ........................................................................................................................57

Table 28 – Effects of WGATE and GAP Bits..............................................................................................................59

Table 29 – Addressing the Serial Port........................................................................................................................60

Table 30 – Interrupt Control Table .............................................................................................................................63

Table 31 – Baud Rates ..............................................................................................................................................68

Table 32 – Reset Function Table ...............................................................................................................................69

Table 33 – Register Summary for an Individual UART Channel ................................................................................69

Table 34 – MPU-401 HOST INTERFACE REGISTERS ............................................................................................74

Table 35 – MIDI DATA PORT ....................................................................................................................................74

Table 36 – MPU-401 STATUS PORT ........................................................................................................................74

Table 37 – MIDI RECEIVE BUFFER EMPTY STATUS BIT.......................................................................................75

Table 38 – MIDI TRANSMIT BUSY STATUS BIT ......................................................................................................75

Table 39 – MPU-401 COMMAND PORT ...................................................................................................................75

Table 40 – Parallel Port Connector ............................................................................................................................79

Table 41 – EPP Pin Descriptions ...............................................................................................................................83

Table 42 – ECP Pin Descriptions ...............................................................................................................................85

Table 43 – ECP Register Definitions..........................................................................................................................86

Table 44 – Mode Descriptions....................................................................................................................................86

Table 45a – Extended Control Register .....................................................................................................................90

Table 46 – Channel/Data Commands supported in ECP mode .................................................................................92

Table 47 – PC/AT and PS/2 Available Registers .......................................................................................................95

Table 48 – State of System Pins in Auto Powerdown ................................................................................................96

Table 49 – State of Floppy Disk Drive Interface Pins in Powerdown..........................................................................96

Table 50 – I/O Address Map ....................................................................................................................................103

Table 51 – Host Interface Flags ...............................................................................................................................103

Table 52 – Status Register.......................................................................................................................................105

Table 53 – Resets ....................................................................................................................................................105

Table 54 – General Purpose I/O Port Assignments .................................................................................................111

Table 55 – GPIO Configuration Summary................................................................................................................112

Table 56 – GPIO Read/Write Behavior ....................................................................................................................113

Table 57 – Different Modes for Fan..........................................................................................................................118

Table 58 – Runtime Register Block Summary..........................................................................................................125

Table 59 – PME, SMI, GPIO, FAN Register Description..........................................................................................127

Table 60 – Game Port..............................................................................................................................................151

Table 61 – LPC47M14x Configuration Registers Summary.....................................................................................154

Table 62 – Chip Level Registers ..............................................................................................................................156

Table 63 – Logical Device Registers........................................................................................................................159

Table 64 – Logical Device Registers........................................................................................................................160

Table 65 – I/O Base Address Configuration Register Description............................................................................161

Table 66 – Interrupt Select Configuration Register Description ...............................................................................162

Table 67 – DMA Channel Select Configuration Register Description.......................................................................163

Table 68 – Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] ............................................164

Table 69 – Parallel Port, Logical Device 3 [Logical Device Number = 0x03]............................................................165

Table 70 – Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]............................................................166

Table 71 – Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]............................................................166

Table 72 – KYBD, Logical Device 7 [Logical Device Number = 0x07] .....................................................................168

Table 73 – PME, Logical Device A [Logical Device Number = 0x0A].......................................................................168

Table 74 – MPU-401 [Logical Device Number = 0x0B] ............................................................................................169

Table 75 – USB Hub, Logical Device C [Logical Device Number = 0x0C] ...............................................................169

Table 76 – HubControl_1 Register Definition ...........................................................................................................171

Table 77 – Electrical Source Characteristics............................................................................................................178

SMSC DS – LPC47M14X Page 6 Rev. 03/19/2001

FIGURES

FIGURE 1 – LPC47M14X BLOCK DIAGRAM...........................................................................................................16

FIGURE 2 – LPC47M14X CLOCK GENERATOR .....................................................................................................24

FIGURE 3 – MPU-401 MIDI INTERFACE..................................................................................................................73

FIGURE 4 – MPU-401 INTERRUPT ..........................................................................................................................76

FIGURE 5 - MIDI DATA BYTE EXAMPLE ...................................................................................................................77

FIGURE 6 – KEYBOARD LATCH............................................................................................................................108

FIGURE 7 – MOUSE LATCH...................................................................................................................................108

FIGURE 8 – GPIO FUNCTION ILLUSTRATION......................................................................................................112

FIGURE 9 – POWER-UP TIMING ...........................................................................................................................178

FIGURE 10 – DATA SIGNAL RISE AND FALL TIME..............................................................................................180

FIGURE 11 – FULL SPEED LOAD ..........................................................................................................................180

FIGURE 12 – LOW-SPEED PORT LOADS .............................................................................................................180

FIGURE 13 – CABLE DELAY ..................................................................................................................................180

FIGURE 14 – DIFFERENTIAL DATA JITTER..........................................................................................................181

FIGURE 15 – DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH...................................................181

FIGURE 16 – RECEIVER JITTER TOLERANCE ....................................................................................................181

FIGURE 17 – INPUT CLOCK TIMING .....................................................................................................................182

FIGURE 18 – PCI CLOCK TIMING..........................................................................................................................182

FIGURE 19 – RESET TIMING .................................................................................................................................182

FIGURE 20 – OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.................................................183

FIGURE 21 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.....................................................183

FIGURE 22 – I/O WRITE .........................................................................................................................................184

FIGURE 23 – I/O READ...........................................................................................................................................184

FIGURE 24 – DMA REQUEST ASSERTION THROUGH LDRQ#...........................................................................185

FIGURE 25 – DMA WRITE (FIRST BYTE) ..............................................................................................................185

FIGURE 26 – DMA READ (FIRST BYTE)................................................................................................................185

FIGURE 27 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) ...........................................................................186

FIGURE 28 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE.................................................................................187

FIGURE 29 – EPP 1.9 DATA OR ADDRESS READ CYCLE ..................................................................................188

FIGURE 30 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE.................................................................................189

FIGURE 31 – EPP 1.7 DATA OR ADDRESS READ CYCLE ..................................................................................189

FIGURE 32 – PARALLEL PORT FIFO TIMING.......................................................................................................191

FIGURE 33 – ECP PARALLEL PORT FORWARD TIMING ....................................................................................191

FIGURE 34 – ECP PARALLEL PORT REVERSE TIMING......................................................................................192

FIGURE 35 – IRDA RECEIVE TIMING....................................................................................................................193

FIGURE 36 – IRDA TRANSMIT TIMING .................................................................................................................194

FIGURE 37 – AMPLITUDE SHIFT KEYED IR RECEIVE TIMING...........................................................................195

FIGURE 38 – AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ........................................................................196

FIGURE 39 – SETUP AND HOLD TIME..................................................................................................................197

FIGURE 40 – SERIAL PORT DATA ........................................................................................................................197

FIGURE 41 – JOYSTICK POSITION SIGNAL.........................................................................................................197

FIGURE 42 – JOYSTICK BUTTON SIGNAL ...........................................................................................................197

FIGURE 43 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .....................................................................198

FIGURE 44 – MIDI DATA BYTE ..............................................................................................................................198

FIGURE 45 – FAN OUTPUT TIMING ......................................................................................................................199

FIGURE 46 – FAN TACHOMETER INTPUT TIMING ..............................................................................................199

FIGURE 47 – LED OUTPUT TIMING ......................................................................................................................199

FIGURE 48 – 128 PIN QFP PACKAGE OUTLINE...................................................................................................200

FIGURE 49 – XNOR-CHAIN TEST STRUCTURE...................................................................................................201

SMSC DS – LPC47M14X Page 7 Rev. 03/19/2001

1 PIN LAYOUT

GP40/DRVDEN0 GP41/DRVDEN1

nMTR0

nDSKCHG

nDS0

CLKI32

VSS

nDIR

nSTEP nWDATA nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

GP42/nIO_PME

VTR

CLOCKI

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ#

PCI_RESET#

LPCPD#

GP43/DDRC

PCI_CLK

SER_IRQ

VSS GP10 /J1B1 GP11 /J1B2 GP12 /J2B1 GP13 /J2B2

GP14 /J1X GP15 /J1Y GP16 /J2X

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

VSS

nStrp1

nStrp0

VCC

OCLK

ICLK

VTR

nPWROK4

nPWROK3

nPWROK2

nPWROK1

nPWREN4

nPWREN3

nPWREN2

nPWREN1

VTR

PD4 -

PD4 +

PD3 -

PD3 +

PD2 -

PD2 +

PD1 -

PD1 +

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

LPC47M14x

128 PIN QFP

39404142434445464748495051525354555657585960616263

USB -

104

103

USB +

102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

VSS VSS GP57/nDTR2 GP56/nCTS2 GP55/nRTS2 GP54/nDSR2 GP53/TXD2 (IRTX) GP52/RXD2 (IRRX) GP51/nDCD2 VCC GP50/nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC

VCC

GP32/FAN2

GP33/FAN1

GP27/nIO_SMI

GP30/FAN_TACH2

GP31/FAN_TACH1

KDAT

GP20/P17

GP21/P16/nDS1

GP22/P12/nMTR1

VREF

GP24/SYSOPT

GP60/LED1

GP61/LED2

GP25/MIDI_IN

GP26/MIDI_OUT

AVSS

GP17 /J2Y

SMSC DS – LPC47M14X Page 8 Rev. 03/19/2001

KCLK

MDAT

VSS

MCLK

GP37/A20M

IRTX2/GP35

IRRX2/GP34

GP36/nKBDRST

2 PIN CONFIGURATION

PIN # NAME PIN # NAME PIN # NAME PIN # NAME

1 GP40/DRVDEN0 33 GP11 /J1B2 65 VCC 97 GP54/nDSR2 2 GP41/DRVDEN1 34 GP12 /J2B1 66 nINIT 98 GP55/nRTS2 3 nMTR0 35 GP13 /J2B2 67 nSLCTIN 99 GP56/nCTS2 4 nDSKCHG 36 GP14 /J1X 68 PD0 100 GP57/nDTR2 5 nDS0 37 GP15 /J1Y 69 PD1 101 VSS 6 CLKI32 38 GP16 /J2X 70 PD2 102 VSS 7 VSS 39 GP17 /J2Y 71 PD3 103 USB + 8 nDIR 40 AVSS 72 PD4 104 USB 9 nSTEP 41 GP20/P17 73 PD5 105 PD1 + 10 nWDATA 42 GP21/P16/nDS1 74 PD6 106 PD1 11 nWGATE 43 GP22/P12/nMTR1 75 PD7 107 PD2 + 12 nHDSEL 44 VREF 76 VSS 108 PD2 13 nINDEX 45 GP24/SYSOPT 77 SLCT 109 PD3 + 14 nTRK0 46 GP25/MIDI_IN 78 PE 110 PD3 15 nWRTPRT 47 GP26/MIDI_OUT 79 BUSY 111 PD4 + 16 nRDATA 48 GP60/LED1 80 nACK 112 PD4 - 17 GP42/nIO_PME 49 GP61/LED2 81 nERROR 113 VTR 18 VTR 50 GP27/nIO_SMI 82 nALF 114 nPWREN1 19 CLOCKI 51 GP30/FAN_TACH2 83 nSTROBE 115 nPWREN2 20 LAD0 52 GP31/FAN_TACH1 84 RXD1 116 nPWREN3 21 LAD1 53 VCC 85 TXD1 117 nPWREN4 22 LAD2 54 GP32/FAN2 86 nDSR1 118 nUSBOC1 23 LAD3 55 GP33/FAN1 87 nRTS1 119 nUSBOC2 24 LFRAME# 56 KDAT 88 nCTS1 120 nUSBOC3 25 LDRQ# 57 KCLK 89 nDTR1 121 nUSBOC4 26 PCI_RESET# 58 MDAT 90 nRI1 122 VTR 27 LPCPD# 59 MCLK 91 nDCD1 123 ICLK 28 GP43/DDRC 60 VSS 92 GP50/nRI2 124 OCLK 29 PCI_CLK 61 IRRX2/GP34 93 VCC 125 VCC 30 SER_IRQ 62 IRTX2/GP35 94 GP51/nDCD2 126 nStrp0 31 VSS 63 GP36/nKBDRST 95 GP52/RXD2

(IRRX)

32 GP10 /J1B1 64 GP37/A20M 96 GP53/TXD2

(IRTX)

Note: The chip is part of a family of LPC chips (LPC47M13x, LPC47M14x, and LPC47M15x). The first 100 pins of these chips are pin compatible, which adds more flexibility for the board designer. In addition, a board designed for the LPC47M14x can also support the LPC47M13x with little or no changes made to the board design.

127 nStrp1

128 VSS

SMSC DS – LPC47M14X Page 9 Rev. 03/19/2001

3 DESCRIPTION OF PIN FUNCTIONS

QFP

PIN #

23:20

24 Frame 1 LFRAME# PCI_I 25 Encoded DMA Request 1 LDRQ# PCI_O 26 PCI Reset 1 PCI_RESET# PCI_I

27 Power Down 1 LPCPD# PCI_I 29 PCI Clock 1 PCI_CLK PCI_ICLK 30 Serial IRQ 1 SER_IRQ PCI_IO

19 14.318MHz Clock Input 1 CLOCKI IS IS

123

124 24MHz Crystal (terminal 2) 1 OCLK IS IS 14

51 General Purpose I/O

52 General Purpose I/O

54 General Purpose I/O

55 General Purpose I/O

61 Infrared Rx

62 Infrared Tx

53,

65,93,1

7, 31,

60,76,

101, 102,

128

40 Analog Ground 1 AVSS

44 Reference Voltage 1 VREF

18,

113,

122

16 Read Disk Data 1 nRDATA IS 11 Write Gate 1 nWGATE O12 (O12/OD12) 10 Write Disk Data 1 nWDATA O12 (O12/OD12)

Multiplexed Command, Address, Data [3:0]

32.768KHz Trickle Clock Input

24MHz Crystal (terminal 1) / 48MHz Clock Input

/Fan Tachometer 2

/Fan Tachometer 1

/Fan Speed Control 2

/Fan Speed Control 1

/General Purpose I/O

Power 4 VCC

Ground 7 VSS

Trickle Voltage 3 VTR 7

NAME

PROCESSOR/HOST LPC INTERFACE (10)

TOTAL SYMBOL

4 LAD[3:0] PCI_IO PCI_IO

CLOCKS (4)

1 CLOCKI32 IS

1 ICLK IS IS

FAN CONTROL (4)

GP30/ FAN_TACH2

GP31/ FAN_TACH1

1 GP32/FAN2 IO12

1 GP33/FAN1 IO12

INFRARED INTERFACE (2)

1 IRRX2/GP34 IS/O8

1 IRTX2/GP35 IO12

POWER PINS (16)

FDD INTERFACE (14)

BUFFER

TYPE

IO8

BUFFER TYPE

PER FUNCTION

(NOTE 1)

PCI_I PCI_O PCI_I

PCI_I 2 PCI_ICLK PCI_IO

IS 3

(I/O8/OD8)/I

(I/O12/OD12)/ (O12/OD12)

IS/(IS/O8/OD8)

O12/(I/O12/OD12) 5, 6

NOTES

11, 14

SMSC DS – LPC47M14X Page 10 Rev. 03/19/2001

QFP

PIN #

NAME

TOTAL SYMBOL

BUFFER

TYPE

BUFFER TYPE

PER FUNCTION

(NOTE 1)

NOTES

12 Head Select 1 nHDSEL O12 (O12/OD12)

8 Step Direction 1 nDIR O12 (O12/OD12)

9 Step Pulse 1 nSTEP O12 (O12/OD12) 4 Disk Change 1 nDSKCHG IS

5 Drive Select 0 1 nDS0 O12 (O12/OD12)

3 Motor On 0 1 nMTR0 O12 (O12/OD12) 15 Write Protected 1 nWRTPRT IS 14 Track 0 1 nTRKO IS

13 Index Pulse Input 1 nINDEX IS

General Purpose I/O/Drive Density Select 0

General Purpose I/O/Drive Density Select 1

GP40/ DRVDEN0

GP41/ DRVDEN1

IO12

IS IS

IS (I/O12/OD12)/

(O12/OD12)

(I/O12/OD12)/ (O12/OD12)

SERIAL PORT 1 INTERFACE (8)

84 Receive Serial Data 1 1 RXD1 IS IS

85 Transmit Serial Data 1 1 TXD1 O12 O12 87 Request to Send 1 1 nRTS1 O8 O8 88 Clear to Send 1 1 nCTS1 I I

89 Data Terminal Ready 1 1 nDTR1 O6 O6 86 Data Set Ready 1 1 nDSR1 I I 91 Data Carrier Detect 1 1 nDCD1 I I

90 Ring Indicator 1 1 nRI1 I I

SERIAL PORT 2 INTERFACE (8)

95 General Purpose I/O

/Receive Serial Data 2

GP52/RXD2 (IRRX)

IS/O8

(IS/O8/OD8)/IS

/Infrared Rx

96 General Purpose I/O

/Transmit Serial Data 2

GP53/TXD2 (IRTX)

IO12

(I/O12/OD12)/O12 5

/Infrared Tx

98 General Purpose I/O

1 GP55/nRTS2 IO8

(I/O8/OD8)/O8

/Request to Send 2

99 General Purpose I/O

1 GP56/nCTS2 IO8

(I/O8/OD8)/I

/Clear to Send 2

100 General Purpose I/O

1 GP57/nDTR2 IO8

(I/O8/OD8)/O8

/Data Terminal Ready

97 General Purpose I/O

1 GP54/nDSR2 IO8

(I/O8/OD8)/I

/Data Set Ready 2

General Purpose I/O/Data

1 GP51/nDCD2 IO8 (I/O8/OD8)/I

Carrier Detect 2

General Purpose I/O/Ring

1 GP50/nRI2 IO8 (I/O8/OD8)/I

Indicator 2

PARALLEL PORT INTERFACE (17) 66 Initiate Output 67 Printer Select Input

68 Port Data 0 69 Port Data 1 70 Port Data 2

71 Port Data 3 72 Port Data 4 73 Port Data 5

Port Data 6

nINIT OP14 (OD14/OP14)

nSLCTIN OP14 (OD14/OP14)

PD0 IOP14 IOP14

PD1 IOP14 IOP14

PD2 IOP14 IOP14

PD3 IOP14 IOP14

PD4 IOP14 IOP14

PD5 IOP14 IOP14

PD6 IOP14 IOP14

SMSC DS – LPC47M14X Page 11 Rev. 03/19/2001

QFP

PIN #

NAME

75 Port Data 7 77 Printer Selected Status

78 Paper End 79 Busy 80 Acknowledge

81 Error 82 Autofeed Output 83 Strobe Output

TOTAL SYMBOL

PD7 IOP14 IOP14

SLCT I I

PE I I

BUSY I I

nACK I I

nERROR I I

nALF OP14 (OD14/OP14)

nSTROBE OP14 (OD14/OP14)

BUFFER

TYPE

KEYBOARD/MOUSE INTERFACE (6)

56 Keyboard Data 1 KDAT IOD16 57 Keyboard Clock 1 KCLK IOD16 58 Mouse Data 1 MDAT IOD16

59 Mouse Clock 1 MCLK IOD16 63 General Purpose I/O

/Keyboard Reset

64 General Purpose I/O

GP36/

IO8

nKBDRST

1 GP37/A20M IO8

/Gate A20

USB HUB(18)

103

Serial Port Upstream Data

USB+ IOUSB IOUSB

104

Serial Port Upstream Data

USB- IOUSB IOUSB

105

Serial Port Downstream

PD1+ IOUSB IOUSB

Data +

106

Serial Port Downstream

PD 1- IOUSB IOUSB

Data -

107

Serial Port Downstream

PD 2+ IOUSB IOUSB

Data +

108

Serial Port Downstream

PD 2- IOUSB IOUSB

Data -

109

Serial Port Downstream

PD 3+ IOUSB IOUSB

Data +

110

Serial Port Downstream

PD 3- IOUSB IOUSB

Data -

111

Serial Port Downstream

PD 4+ IOUSB IOUSB

Data +

112

Serial Port Downstream

PD 4- IOUSB IOUSB

Data -

nUSBOC1 nPWREN1 nUSBOC2

nPWREN2 nUSBOC3 nPWREN3

nUSBOC4 nPWREN4 nStrp0

IPU O24 IPU

O24 IPU O24

IPU O24 IPU

118 USB Over-Current sense 1 114 USB Power Enable 1 119 USB Over-Current sense 1

115 USB Power Enable 1 120 USB Over-Current sense 1 116 USB Power Enable 1

121 USB Over-Current sense 1 117 USB Power Enable 1 126

Number of Down Stream Ports select

127

Number of Down Stream

nStrp1

IPU

Ports select

BUFFER TYPE

PER FUNCTION

NOTES

(NOTE 1)

IOD16 IOD16 IOD16

IOD16 (I/O8/OD8)/O8 9

(I/O8/OD8)/O8 9

IPU 13 O24 13 IPU 13

O24 13 IPU 13 O24 13

IPU 13 O24 13 IPU Input with

30ua Pull

IPU Input with

30ua Pull

SMSC DS – LPC47M14X Page 12 Rev. 03/19/2001

QFP

PIN #

NAME

TOTAL SYMBOL

BUFFER

TYPE

BUFFER TYPE

PER FUNCTION

(NOTE 1)

NOTES

GENERAL PURPOSE I/O (19)

General Purpose I/O

GP10 /J1B1 IS/O8 (IS/O8/OD8)/IS

/Joystick 1 Button 1

General Purpose I/O

GP11 /J1B2 IS/O8 (IS/O8/OD8)/IS

/Joystick 1 Button 2

General Purpose I/O

GP12 /J2B1 IS/O8 (IS/O8/OD8)/IS

/Joystick 2 Button 1

General Purpose I/O

GP13 /J2B2 IS/O8 (IS/O8/OD8)/IS

/Joystick 2 Button 2

General Purpose I/O

GP14 /J1X IO12 (I/O12/OD12)/ IO12

/Joystick 1 X-Axis

General Purpose I/O

GP15 /J1Y IO12 (I/O12/OD12)/ IO12

/Joystick 1 Y-Axis

General Purpose I/O

GP16 /J2X IO12 (I/O12/OD12)/ IO12

/Joystick 2 X-Axis

General Purpose I/O

GP17 /J2Y IO12 (I/O12/OD12)/ IO12

/Joystick 2 Y-Axis

41 42

General Purpose I/O / P17 General Purpose I/O / P16

/nDS1

General Purpose I/O / P12 /nMTR1

General Purpose I/O / System Option

General Purpose I/O /MIDI_IN

General Purpose I/O /MIDI_OUT

50 General Purpose I/O

/SMI Output

General Purpose I/O /

GP20 /P17 IO8 (I/O8/OD8)/IO8

GP21 /P16/

nDS1 GP22 /P12/

nMTR1 GP24

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8 (I/O8/OD8) 8 /SYSOPT GP25

IO8 (I/O8/OD8)/I /MIDI_IN GP26

IO12 (I/O12/OD12)/O12 /MIDI_OUT

GP27

IO12 (I/O12/OD12)/ OD12 /nIO_SMI

GP60 /LED1 IO12 (I/O12/OD12)/O12 10

LED

General Purpose I/O /

GP61 /LED2 IO12 (I/O12/OD12)/O12 10

LED

General Purpose I/O / Power Management Event

28 General Purpose I/O

GP42 /nIO_PME

GP43/DDRC IO8 (I/O8/OD8)/I

IO12 (I/O12/OD12)/ OD12

/Device Disable Reg. Control

Note: The "n" as the first letter of a signal name or the “#” as the suffix of a signal name indicates an "Active Low"

signal.

Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis

represent multiple buffer types for a single pin function.

Note 2: The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal

follows the protocol defined for the LRESET# signal in the “Low Pin Count Interface Specification”.

Note 3: For USB Hub functionality, the 32 KHz input clock must always be connected. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).

Note 4: The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.

These pins revert to their non-inverting GPIO input function when VCC is removed from the part.

Note 5: The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR

(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.

Note 6: The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO. Note 7: VTR must not be connected to VCC. The 32 KHz input clock must not be driven high whenVTR = 0v.

SMSC DS – LPC47M14X Page 13 Rev. 03/19/2001

Note 8: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration

at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.

Note 9: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs

after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used the system must ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”.

Note 10: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. Note 11: The 48MHz clock input must not be driven high when VTR = 0V. Note 12: VTR is used to power the USB cable transceivers. VTR must not be connected to VCC. Note 13: When the specified USB Down Stream Ports are disabled via the Strp0/Strp1 bit or nStrp1/nStrp0 Pins, the

associated Over-current sense pins (nUSBOC[x]) and Power Enable (nPWREN[4:1]) pins are also disabled. The USB Down Stream Port nUSBOC[x] input pin can be a NC (No Connect) pin for existing designs or tied High (1). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1). The Power Enable (nPWREN[x]) pin will be forced low (0).

Note 14: When a 24MHz crystal oscillator is used, these pins need off-balance capacitive loading. It is suggested to

use a 22pf capacitor on ICLK and a 10pf capacitor on OCLK.

3.1 BUFFER TYPE DESCRIPTIONS

Note: The buffer type values are specified at VCC=3.3V

IO12 Input/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD8 Open Drain Output, 8mA sink. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Back-drive protected. IOD16 Input/Output (Open Drain), 16mA sink. IO8 Input/Output, 8mA sink, 4mA source. O24 Output, 24mA sink, 12mA source. I Input TTL Compatible. IPU Input TTL Compatible. With 30ua internal Pull Up IS Input with Schmitt Trigger. PCI_IO Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_O Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_I Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_ICLK Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2) IOUSB Buffer Type for the USB differential data lines. Defined in the “Operational Description” section according to the USB specification; V1.1

Note 1: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2. Note 2: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.

SMSC DS – LPC47M14X Page 14 Rev. 03/19/2001

3.2 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS

The following pins require external pullup resistors:

 KDAT  KCLK  MDAT  MCLK  GP36/KBDRST if KBDRST function is used  GP37/A20M if A20M function is used  GP20/P17 If P17 function is used  GP21/P16 if P16 function is used  GP22/P12 if P12 function is used  GP27/nIO_SMI if nIO_SMI function is used as Open Collector output.  GP42/nIO_PME if nIO_PME function is used as Open Collector output.  SER_IRQ  GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector.  GP41/DRVDEN1 if DRVDEN1 function is used as Open Collector.  nMTR0 if used as Open Collector Output  nDS0 if used as Open Collector Output  nDIR if used as Open Collector Output  nSTEP if used as Open Collector Output  nWDATA if used as Open Collector Output  nWGATE if used as Open Collector Output  nHDSEL if used as Open Collector Output  nINDEX  nTRK0  nWRTPRT  nRDATA  nDSKCHG

SMSC DS – LPC47M14X Page 15 Rev. 03/19/2001

4 BLOCK DIAGRAM

SER_IRQ PCI_CLK

LAD[3:0]

PCI_RESET

IO_PME*

IO_SMI*

GP1[0:7]*

GP2[0:2,4:7]* GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]*

Oscillator

(24MHz)

Crystal

PWROK[3,0]

PWREN[3,0]

CLK32

CLOCKI

LFrame

LDRQ

LPCPD

ICLK

OCLK

PD1+

PD1-

PD2+

PD2-

PD3+

PD3-

PD4+

PD4-

CLOCK GEN

SERIAL

IRQ

LPC

Bus Interface

Power Mgmt

General

Purpose

I/O

CLOCK GEN

USB HUB

IRTX2*

IRRX2*

(Data, Address, and Control lines)

SMC PROPRIETARY 82077 COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER CORE

J1X, J1Y*

J2B1, J2B2*

J1B1, J1B2*

J2X, J2Y*

Game Port Fan Control2nd Infrared Port

Internal Bus

LPC47M14x

(128 QFP)

WDATA

WCLOCK

RCLOCK

RDATA

FAN2*

FAN1*

DIGITAL DATA

SEPARATOR WITH WRITE

PRECOM-

PENSATION

FAN_TACH2*

FAN_TACH1*

LED2*

LED1*

LEDs

Multi-Mode

Parallel Port

with

ChiProtect

(see LPC47B27x)

Keyboard/Mouse

MUX

High-Speed

16550A

UART

PORT 1

High-Speed

16550A

UART

PORT 2

MPU-401

Serial Port

8042

controller

/FDC

PD[7,0]

Busy, Slct, PE, ERROR, ACK

STROBE, INIT, SLCTIN, ALF

TXD1, RXD1

CTS1, RTS1

DSR1, DTR1

DCD1, RI1

TXD2 (IRTX)*, RXD2 (IRRX)*

CTS2*, RTS2 *

DSR2*, DTR2*

DCD2*, RI2*

MIDI_IN*

MIDI_OUT*

KCLK, MCLK

KDATA, MDATA

GateA20*

KRESET*

P12*, P16*, P17*

DIR, STEP,

USB-

USB+

DSKCHG, DS0, DS1*

DRVDEN0*, DRVDEN1*

MTR0, MTR1*,TRK0,

INDEX, WRTPRT

WGATE, HDSEL

RDATA, WDATA

Note 1:

This diagram does not show power and ground

connections.

Note 2:

Functions with " *" are located on multifunctional pins. This diagram is designed to show the various functions available on the chip (not pin layout).

FIGURE 1 – LPC47M14X BLOCK DIAGRAM

SMSC DS – LPC47M14X Page 16 Rev. 03/19/2001

5 POWER FUNCTIONALITY

The LPC47M14x has three power planes: VCC, VTR, and VREF.

5.1 VCC POWER

The LPC47M14x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational Description” Section and the “Maximum Current Values” subsection.

5.1.1 3 Volt Operation / 5 Volt Tolerance

The LPC47M14x is a 3.3 Volt part. It is intended solely for 3.3V applications. All signal pins are 5V tolerant except those that pertain to the LPC Bus and USB Hub interfaces; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

 LAD[3:0]  LFRAME#  LDRQ#  LPCPD#

The USB interface pins are 3.3V tolerant. The maximum input voltage tolerated on the downstream port pins is 3.6V (See “Operational Description” for the IOUSB buffers). These pins are labeled:

 PD+[1:4]  PD-[1:4]

The input voltage for all other pins is 5.5V max including the following pins:

 PCI_RESET#  PCI_CLK  SER_IRQ  nIO_PME  nUSBOC[1:4]  nPWREN[1:4]

5.2 USB POWER

The LPC47M14x requires that the USB Hub maintain power for wake-up events in the absence of VCC power. To meet these requirements, the Hub Block and the transceiver pins are powered by VTR. CLKI32, which is also powered by VTR, is used to monitor changes in the signaling on the USB ports. This will enable the Hub Block to resume from a suspend state by receiving a signal on either its downstream ports or its upstream port.

5.3 VTR SUPPORT

The LPC47M14x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when V

is removed. The VTR pin is connected to the VTR (standby) power supply, which is 3.3

Volts (nominal). See the “Operational Description” Section. The maximum VTR current that is required depends on the functions that are used in the part. See “Trickle Power Functionality” subsection and “Maximum Current Values” subsection. This voltage source is also used to power the USB Hub interface, the IR interface, the PME configuration registers, and the PME interface. The V

pin generates a VTR Power-on-Reset signal to initialize these components.

Note: If V minimum potential at least 10 µs before V

is to be used for programmable wake-up events when VCC is removed, VTR must be at its full

begins a power-on cycle. When VTR and Vcc are fully

powered, the potential difference between the two supplies must not exceed 500mV.

5.4 VREF PIN

The LPC47M14x has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply. It is used for the game port. See the “GAME PORT LOGIC” section.

SMSC DS – LPC47M14X Page 17 Rev. 03/19/2001

5.5 INTERNAL PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface

cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the

as V

LPC47M14x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V

≤ 2.3V (nominal), and

the LPC47M14x host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47M14x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2, USB+, USB-, PD[4:1]+, PD[4:1]- and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, since V

must always be powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and

GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive. See “Trickle Power Functionality” section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.

5.6 32.768 KHZ TRICKLE CLOCK INPUT

The LPC47M14x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink, wake on specific key function, and to the USB Hub to support suspend and resume signaling.

5.7 TRICKLE POWER FUNCTIONALITY

When the LPC47M14x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:

 UART 1 Ring Indicator  UART 2 Ring Indicator  Keyboard data  Mouse data  “Wake on Specific Key” Logic  Fan Tachometers (Note)  GPIOs for wakeup. See below.  Event on USB Downstream/Upstream ports

Note: The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant:

 I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may

only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

 I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by

VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, and GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 - see below):

 Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load

on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.

All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin which comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output buffer type is retained.

The other GPIOs function as follows: GP36, GP37 and GP40:

 Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input

buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.

SMSC DS – LPC47M14X Page 18 Rev. 03/19/2001

GP35, GP42, GP53, GP60 and GP61:

 Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are

powered by VTR so that the pins are always forced low when not used. GP42 is the nIO_PME pin, which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR.

The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are powered by VTR so that they are driven low when VCC = 0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.

The following list summarizes the blocks, registers and pins that are powered by VTR.

 USB Hub  PME interface block  PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)  “Wake on Specific Key” logic  LED control logic  Fan Tachometers  Pins for PME Wakeup:

◊ GP42/nIO_PME (output, buffer powered by VTR) ◊ nRI1 (input) ◊ GP50/nRI2 (input) ◊ GP52/RXD2(IRRX) (input) ◊ KDAT (input) ◊ MDAT (input) ◊ GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, and

GP61) – all input-only except GP53, GP60, and GP61. See below.

 Other Pins

◊ IRTX2/GP35 (output, buffer powered by VTR) ◊ GP53/TXD2(IRTX) (output, buffer powered by VTR) ◊ GP60/LED1 (output, buffer powered by VTR) ◊ GP61/LED2 (output, buffer powered by VTR)

5.8 MAXIMUM CURRENT VALUES

See the “Operational Description” section for the maximum current values.

The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or

3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1, GP61/LED2, and CLKI32. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.

 The maximum VCC current, ICC, is given with all outputs open (not loaded) , and all inputs in a fixed state

(i.e., 0V or 3.3V).

 The maximum VREF current, I

, is given with all outputs open (not loaded) , and all inputs in a fixed state

REF

(i.e., 0V or 3.3V).

5.9 POWER MANAGEMENT EVENTS (PME/SCI)

The LPC47M14x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.

SMSC DS – LPC47M14X Page 19 Rev. 03/19/2001

6 FUNCTIONAL DESCRIPTION

6.1 SUPER I/O REGISTERS

The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.

6.2 HOST PROCESSOR INTERFACE (LPC)

The host processor communicates with the LPC47M14x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

Table 1 – Super I/O Block Addresses

ADDRESS BLOCK NAME

Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base1+(0-7) Base2+(0-7)

Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 KYBD 7 Base + 0 Game Port 9 Base + (0-5F) Runtime Registers A 2 Base + (0-1) MPU-401 B Base + (0-1) Configuration n/a USB Hub C 1

Note: Refer to the configuration register descriptions for setting the base address. Note 1: No Addressable Registers in the Hub Block. Note 2: Logical Device A is referred to as the Runtime Register block or PME Block and may be

used interchangeably throughout this document.

Serial Port Com 2 5

Parallel Port

SPP EPP ECP

ECP+EPP+SPP

LOGICAL

DEVICE

NOTES

SMSC DS – LPC47M14X Page 20 Rev. 03/19/2001

6.3 LPC INTERFACE

The following sub-sections specify the implementation of the LPC bus.

6.3.1 LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics.

SIGNAL

NAME

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data bus.

LFRAME# Input Frame signal. Indicates start of new cycle and termination of broken cycle

PCI_RESET# Input PCI Reset. Used as LPC Interface Reset.

LDRQ# Output Encoded DMA/Bus Master request for the LPC interface.

nIO_PME OD Power Mgt Event signal. Allows the LPC47M14x to request wakeup.

LPCPD# Input

SER_IRQ I/O Serial IRQ.

PCI_CLK Input PCI Clock.

Note: The CLKRUN# signal is not implemented in this part.

6.3.2 LPC Cycles

The following cycle types are supported by the LPC protocol.

The LPC47M14x ignores cycles that it does not support.

6.3.3 Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M14x. See the “Low Pin Count (LPC) Interface Specification”, Revision

1.0, Section 4.2 for definition of these fields.

6.3.4 LFRAME# Usage

LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47M14x to know when to monitor the bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M14x monitors the bus to determine whether the cycle is intended for it. The use of LFRAME# allows the LPC47M14x to enter a lower power state internally. There is no need for the LPC47M14x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.

When the LPC47M14x samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information.

The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.

TYPE DESCRIPTION

Powerdown Signal. Indicates that the LPC47M14x should prepare for power to be shut on the LPC interface.

CYCLE TYPE TRANSFER SIZE

I/O Write 1 Byte

I/O Read 1 Byte DMA Write 1 byte DMA Read 1 byte

SMSC DS – LPC47M14X Page 21 Rev. 03/19/2001

6.3.5 I/O Read and Write Cycles

The LPC47M14x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers.

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.

6.3.6 DMA Read and Write Cycles

DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M14x. DMA write cycles involve the transfer of data from the LPC47M14x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47B10x are 1, 2 or 4 bytes.

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.

6.3.7 DMA Protocol

DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47M14x and special encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the “Low Pin Count (LPC) Interface Specification,” Revision

1.0.

6.3.8 Power Management

CLOCKRUN Protocol

The CLKRUN# pin is not implemented in the LPC47M14x. See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.1.

LPCPD Protocol

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.2.

6.3.9 SYNC Protocol

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 4.2.1.8 for a table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47M14x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M14x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or

1001. The LPC47M14x will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M14x uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M14x uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle.

The LPC47M14x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.

SMSC DS – LPC47M14X Page 22 Rev. 03/19/2001

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M14x has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP.

SYNC Error Indication

The LPC47M14x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47M14x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M14x. If the host was writing data to the LPC47M14x, the data had already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

 When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the

removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus.

 When PCI_RESET# goes active (low):

 The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.

 The LPC47M14x must ignore LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).

6.3.10 LPC Transfer

Wait State Requirements

I/O Transfers

The LPC47M14x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47M14x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers.

See the example timing for the LPC cycles in the “Timing Diagrams” section.

SMSC DS – LPC47M14X Page 23 Rev. 03/19/2001

6.4 USB HUB FUNCTIONAL DESCRIPTION

The USB Hub Block implements one upstream port and up to four downstream ports. The internal address/data/control connection is provided for programming by BIOS the USB Vendor ID, Product ID, Device Revision Number and number of down stream ports by accessing the Hub Control register. USB cable data is not transmitted or received via the internal connection.

The USB Hub Block implements the requirements defined in the USB Hub Device Class Specification Version 1.1 (USB Specification 1.1, Chapter 11), including Status Change Endpoint, Hub class specific descriptors and Hub class specific requests. The USB Hub Block supports Suspend and Resume both as a USB device and in terms of propagating Suspend and Resume signaling. It also supports remote wakeup by a device on downstream ports.

For wakeup requirements, the Hub Block is powered from VTR. VTR also powers the 24MHz OSC/PLL, 32 KHz clock input buffer, 48MHz CLK/OSC MUX and all Logical Device and Global Configuration Registers as well as programmable wakeup events in the PME interface.

The Hub Block clock requirements are derived from separate CLK/OSC pins (ICLK, OCLK). Clock pins ICLK and OCLK provide implementation flexibility for the system designer (see FIGURE 2). When a 48MHz clock signal is available, it may be connected directly to the ICLK pin. To reduce overall system EMI, a local 24MHz oscillator may alternately be connected between the ICLK and OCLK pins. The OSC_CLK control bit in the Logical Device C Configuration Register at 0xF0, selects between clock sources. The 32 KHz clock source is used to time certain port change events. This will ensure the USB Hub will respond to port change events while the hub is in Suspend.

Clocks for IO

Blocks

To Hub Block

and SIO

PLL

Buffer

CLOCKI

14.318 MHz. Clock

CLKI32

32.768 KHz.

ICLK

Clock

FIGURE 2 – LPC47M14X CLOCK GENERATOR

For power conservation the USB Hub Block turns off internal hub clocks during Suspend, as follows:

 The Hub Block responds to two types of Suspend. Selective (or Port) Suspend and Global Suspend.

Segments of the bus can be selectively suspended by sending the command SetPortFeature (PORT_SUSPEND) to the hub port to which that segment is attached. The suspended port will block activity to the suspended bus segment. Because other ports on the hub remain active, internal clocks are not turned off.

 Global Suspend is used when no communication is desired anywhere on the bus and the entire bus is

placed in the Suspend state. The host signals the start of global suspend by ceasing all its transmissions (including the SOF token). As the hub block, and each device on the bus, recognizes that the bus is in the idle state for the appropriate length of time, it goes into the Suspend state. Because all bus segments attached to the hub are in the Suspend state, the hub will turn off the internal 24MHz driven PLL. In addition, 48MHz is stopped in the Hub Block. The 48MHz clock signal at the ICLK pin, if enabled, is not stopped. Control logic external to the LPC47M14X should stop this clock, if desired.

 The Hub Block will Resume from a Suspend state by receiving any non-idle signaling by a remote wakeup

enabled device on its downstream ports or Resume signaling on its upstream port. If the Hub has been enabled as a remote wakeup source, it will also Resume from connects and disconnects on downstream

CLK/OSC

OSC/PLL

48 MHz.

Clock

48 Mhz. (to Hub Block)

MUX

OCLK

24 MHz.

Crystal

OSC_CLK (from config. registers)

PLL_EN (control from hub)

SMSC DS – LPC47M14X Page 24 Rev. 03/19/2001

ports. The internal 24MHz driven PLL (and the 48MHz in the Hub Block) will be started to complete the Resume.

6.4.1 USB Downstream Port Selection

The LPC47M14x USB Hub has the ability to program, via BIOS, control register access or through external PIN strapping options, the number of Down Stream Ports that are available to the User. There is also a “Pin Strapping” option that will allow the board designer the ability to define the number of down stream ports that will be active via during USB_PWR POR.

The LPC47M120 USB Hub block will make the following changes to its external signals and device class response parameters:

1) All related input and output signals such as the associated Over-current sense pins (nUSBOC[x]) and Power Enable (nPWREN[x]) pin are also disabled.

2) The USB Down Stream Port nUSBOC[x] input pin can be a NC (No Connect) pin or tied High (1). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

3) The Power Enable (nPWREN[x]) pin will be forced low (0). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

4) The associated PDx+ and PDx- pins will not be active can be a NC (No Connect) pin). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

5) All Hub Device Class return descriptor must respond with the appropriate information relating to the number of ports that are currently selected by the Strap Pins or control bits in the register described in Table 76 – HubControl_1 Register Definition, shown on page 171, below, describes what fields now need to be programmed bas on the number of enabled ports.

Table 2 – Hub Descriptor to be Modified

OFFSET FIELD PROGRAMMABLE SIZE DESCRIPTION

0 bDescLength 1 Number of bytes in this descriptor, including

1 bDescriptorType 1 Descriptor Type

2 bNbrPorts X 1 Number of downstream ports that this hub

3 wHubCharacteristics 2 D1..D0: Power Switching Mode

this byte.

supports. Selected by the “Strp0 and nStrp1” input pins or the HubControl_1 register defined in Table 76 – HubControl_1 Register Definition, shown on page 171, below.

00 - Ganged power switching (all ports’ power at once)

01 - Individual port power switching 1X - No power switching (ports always powered

on when hub is on and off when hub is off).

D2:Identifies a Compound Device 0 - Hub is not part of a compound device 1 - Hub is part of a compound device

D4..D3: Over-current Protection Mode 00 - Global Over-current Protection. The hub

reports over-current as a summation of all ports’ current draw, without a breakdown of individual port over-current status.

01 - Individual Port Over-current protection. The hub reports over-current on a per-port basis. Each port has an over-current indicator.

1X -No Over-Current Protection. This option is only allowed for bus-powered hubs that do not implement over-current protection.

D15..D5: Reserved

SMSC DS – LPC47M14X Page 25 Rev. 03/19/2001

OFFSET FIELD PROGRAMMABLE SIZE DESCRIPTION

5 bPwrOn2PwrGood 1 Time (in 2 ms intervals) from the time power on

6 bHubContrCurrent 1 Maximum current requirements of the hub

7 DeviceRemovable X Variable

depending on number of ports on

hub

Variable PortPwrCtrlMask X Variable

depending on number of ports on

hub

sequence begins on a port until power is good on that port. System software uses this value to determine how long to wait before accessing a powered-on port.

controller electronics in mA.

Indicates if a port has a removable device attached. If a non-removable device is attached to a port, that port will never receive an insertion change notification. This field is reported on byte-granularity. Within a byte, if no port exists for a given location, the field representing the port characteristics returns “0”.

Bit definition: 0 - Device is removable 1 - Device is not removable (permanently

attached) This is a bitmap corresponding to the individual

ports on the hub: Bit 0: Reserved for future use Bit 1: Port 1 Bit 2: Port 2 Etc. Bit n: Port n (implementation dependent, up to

a maximum of 255 ports).

Indicates if a port is not affected by a gangmode power control request. Ports that have this field set always require a manual SetPortFeature(PORT_POWER) request to control the port’s power state.

Bit definition: 0 - Port does not mask the gang-mode power

control capability. 1 - Port is not affected by gang-mode power

commands. Manual commands must be sent to this port to turn power on and off. This is a bitmap corresponding to the individual ports on the hub:

Bit 0: Reserved for future use. Bit 1: Port 1 Bit 2: Port 2 Etc. Bit n: Port n (implementation dependent, up to

a maximum of 255 ports).

6.5 FLOPPY DISK CONTROLLER

The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

SMSC DS – LPC47M14X Page 26 Rev. 03/19/2001

6.5.1 FDC Internal Registers

The Floppy Disk Controller contains eight internal registers, which facilitate the interfacing between the host microprocessor and the disk drive. Table 3 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

Table 3 – Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

SECONDARY

ADDRESS

370 371 372 373 374 374 375 376 377 377

R/W REGISTER

R R/W R/W

R/W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TSR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

INT

7 6 5 4 3 2 1 0

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDIN

RESET

0 1 0 N/A 0 N/A N/A 0

COND.

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

This function is not supported. This bit is always read as “1”.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

SMSC DS – LPC47M14X Page 27 Rev. 03/19/2001

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

INT

PENDING

RESET

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

COND.

BIT 0 DIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0

1 1 DRIVE

SEL0

RESET

1 1 0 0 0 0 0 0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

COND.

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

SMSC DS – LPC47M14X Page 28 Rev. 03/19/2001

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

nDRV2 nDS1 nDS0 WDATA

F/F

RESET

N/A 1 1 0 0 0 1 1

RDATA

F/F

WGATE

F/F

nDS3 nDS2

COND.

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

RESET

7 6 5 4 3 2 1 0

MOT

EN3

MOT

EN2

MOT

EN1

MOT

EN0

DMAEN nRESET DRIVE

SEL1

DRIVE

SEL0

0 0 0 0 0 0 0 0

COND.

SMSC DS – LPC47M14X Page 29 Rev. 03/19/2001

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

DRIVE DOR VALUE

0 1CH 1 2DH

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the LPC47M14x.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the LPC47M14x.

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 4 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

Table 4 – Tape Select Bits

TAPE SEL1

(TDR.1)

0 0 1 1

TAPE SEL0

(TDR.0)

0 1 0 1

DRIVE

SELECTED

None

1 2 3

Table 5 – Internal 2 Drive Decode - Normal

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 1 0 nBIT 5 nBIT 4

X X 1 X 0 1 0 1 nBIT 5 nBIT 4 X 1 X X 1 0 1 1 nBIT 5 nBIT 4 1 X X X 1 1 1 1 nBIT 5 nBIT 4

0 0 0 0 X X 1 1 nBIT 5 nBIT 4

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Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 0 1 nBIT 4 nBIT 5

X X 1 X 0 1 1 0 nBIT 4 nBIT 5 X 1 X X 1 0 1 1 nBIT 4 nBIT 5 1 X X X 1 1 1 1 nBIT 4 nBIT 5

0 0 0 0 X X 1 1 nBIT 4 nBIT 5

Normal Floppy Mode

Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are ‘0’.

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 0 0 0 0 0 0 tape sel1 tape sel0

Enhanced Floppy Mode 2 (OS2)

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REG 3F3 Reserved Reserved Drive Type ID Floppy Boot Drive tape sel1 tape sel0

Table 7 – Drive Type ID

DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID

Bit 1 Bit 0 Bit 5 Bit 4

0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2

1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6

Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x.

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DATA RATE SELECT REGISTER (DSR)

Address 3F4 WRITE ONLY

This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30.

7 6 5 4 3 2 1 0

S/W

RESET

POWER

DOWN

0 PRE-

COMP2

PRE-

COMP1

PRE-

COMP0

DRATE

SEL1

DRATE

SEL0

0 0 0 0 0 0 1 0

COND.

Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.

BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 8 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command.

Table 8 – Precompensation Delays

PRECOMP

432

PRECOMPENSATION

DELAY (nsec)

<2Mbps 2Mbps

111 001 010 011 100 101 110 000

0.00

41.67

83.34

125.00

166.67

208.33

250.00 Default

20.8

41.7

62.5

83.3

104.2 125

Default

Default: See Table 11

BIT 5 UNDEFINED Should be written as a logic "0".

BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register.

BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing.

Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block Separator circuits will be turned off. The controller will come out of manual low power.

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Table 9 – Data Rates

DRIVE RATE DATA RATE DATA RATE DRATE(1)

DRT1 DRT0 SEL1 SEL0 MFM FM

DENSEL

1 0

0 0 1 1 1Meg --- 1 1 1

0 0 0 0 500 250 1 0 0

0 0 0 1 300 150 0 0 1

0 0 1 0 250 125 0 1 0

0 1 1 1 1Meg --- 1 1 1

0 1 0 0 500 250 1 0 0

0 1 0 1 500 250 0 0 1

0 1 1 0 250 125 0 1 0

1 0 1 1 1Meg --- 1 1 1

1 0 0 0 500 250 1 0 0

1 0 0 1 2Meg --- 0 0 1

1 0 1 0 250 125 0 1 0

Drive Rate Table (Recommended) 00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 01 = 3-Mode Drive 10 = 2 Meg Tape

Note 1: The DRATE and DENSEL values are mapped onto the DRVDEN pins.

Table 10 – DRVDEN Mapping

DT1 DT0 DRVDEN1 (1) DRVDEN0 (1) DRIVE TYPE

0 0 DRATE0 DENSEL 4/2/1 MB 3.5"

2/1 MB 5.25" FDDS 2/1.6/1 MB 3.5" (3-MODE)

1 0 DRATE0 DRATE1

0 1 DRATE0 nDENSEL PS/2

1 1 DRATE1 DRATE0

Table 11 – Default Precompensation Delays

DATA RATE

2 Mbps

1 Mbps 500 Kbps 300 Kbps 250 Kbps

PRECOMPENSATION

DELAYS

20.8 ns

41.67 ns 125 ns 125 ns 125 ns

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MAIN STATUS REGISTER

Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before each byte transferring to or from the data register except in DMA mode. No delay is required when reading the MSR after a data transfer.

7 6 5 4 3 2 1 0

RQM

DIO

NON DMA

CMD

BUSY

Reserved Reserved

DRV1

BUSY

DRV0

BUSY

BIT 0 - 1 DRV x BUSY These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates.

BIT 4 COMMAND BUSY This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a 0 after the last command byte.

BIT 5 NON-DMA Reserved, read ‘0’. This part does not support non-DMA mode.

BIT 6 DIO Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.

BIT 7 RQM Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register.

Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 12 gives several examples of the delays with a FIFO.

The data is based upon the following formula:

Threshold # x 1

DATA RATE

x 8

- 1.5 µs = DELAY

At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred.

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An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

Table 12 – FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

FIFO THRESHOLD

EXAMPLES

1 byte 2 bytes 8 bytes

15 bytes

DIGITAL INPUT REGISTER (DIR)

Address 3F7 READ ONLY This register is read-only in all modes.

PC-AT Mode

7 6 5 4 3 2 1 0

DSK

CHG

RESET

N/A N/A N/A N/A N/A N/A N/A N/A

COND.

MAXIMUM DELAY TO SERVICING AT

2 Mbps DATA RATE

1 x 4 µs - 1.5 µs = 2.5 µs 2 x 4 µs - 1.5 µs = 6.5 µs 8 x 4 µs - 1.5 µs = 30.5 µs 15 x 4 µs - 1.5 µs = 58.5 µs

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 x 8 µs - 1.5 µs = 6.5 µs 2 x 8 µs - 1.5 µs = 14.5 µs 8 x 8 µs - 1.5 µs = 62.5 µs 15 x 8 µs - 1.5 µs = 118.5 µs

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 x 16 µs - 1.5 µs = 14.5 µs 2 x 16 µs - 1.5 µs = 30.5 µs 8 x 16 µs - 1.5 µs = 126.5 µs 15 x 16 µs - 1.5 µs = 238.5 µs

0 0 0 0 0 0 0

BIT 0 - 6 UNDEFINED The data bus outputs D0 - 6 are read as ‘0’.

BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).

PS/2 Mode

7 6 5 4 3 2 1 0

DSK

CHG

RESET

N/A N/A N/A N/A N/A N/A N/A 1

1 1 1 1 DRATE

SEL1

DRATE

SEL0

nHIGH

DENS

COND.

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BIT 0 nHIGH DENS This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected.

BITS 1 - 2 DATA RATE SELECT

These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.

BITS 3 - 6 UNDEFINED Always read as a logic "1"

Model 30 Mode

7 6 5 4 3 2 1 0 DSK

CHG

RESET

N/A 0 0 0 0 0 1 0

0 0 0 DMAEN NOPREC DRATE

SEL1

DRATE

SEL0

COND.

BITS 0 - 1 DATA RATE SELECT

BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register.

BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3.

BITS 4 - 6 UNDEFINED Always read as a logic "0"

BIT 7 DSKCHG

This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).

CONFIGURATION CONTROL REGISTER (CCR)

Address 3F7 WRITE ONLY PC/AT and PS/2 Modes

7 6 5 4 3 2 1 0

RESET

N/A N/A N/A N/A N/A N/A 1 0

DRATE

SEL1

DRATE

SEL0

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1

These bits determine the data rate of the floppy controller. See Table 9 for the appropriate values.

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BIT 2 - 7 RESERVED Should be set to a logical "0"

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

NOPRECDRATE

SEL1

RESET

N/A N/A N/A N/A N/A N/A 1 0

DRATE

SEL0

COND.

BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 9 for the appropriate values.

BIT 2 NO PRECOMPENSATION This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset.

BIT 3 - 7 RESERVED Should be set to a logical "0"

Table 10 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets.

6.5.2 STATUS REGISTER ENCODING

During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed.

Table 13 – Status Register 0

BIT NO. SYMBOL NAME DESCRIPTION

7,6 IC Interrupt Code

00 - Normal termination of command. The specified command was properly executed and completed without error.

01 - Abnormal termination of command. Command execution was started, but was not successfully completed.

10 - Invalid command. The requested command could not be executed.

11 - Abnormal termination caused by Polling.

5 SE Seek End

The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command).

4 EC

Equipment

Check

The TRK0 pin failed to become a "1" after:

1. 80 step pulses in the Recalibrate command.

2. The Relative Seek command caused the FDC to step outward beyond Track 0.

3 Unused. This bit is always "0". 2 H Head Address The current head address.

1,0 DS1,0 Drive Select The current selected drive.

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Table 14 – Status Register 1

BIT NO. SYMBOL NAME DESCRIPTION

7 EN

End of

Cylinder

The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after

Read or Write Data command. 6 Unused. This bit is always "0". 5 DE Data Error

The FDC detected a CRC error in either the ID field or

the data field of a sector. 4 OR Overrun/

Underrun

Becomes set if the FDC does not receive CPU or DMA

service within the required time interval, resulting in data

overrun or underrun. 3 Unused. This bit is always "0". 2 ND No Data Any one of the following:

1. Read Data, Read Deleted Data command - the FDC did not find the specified sector.

2. Read ID command - the FDC cannot read the ID field without an error.

3. Read A Track command - the FDC cannot find the proper sector sequence.

1 NW Not Writeable

WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command.

0 MA

Missing

Address Mark

Any one of the following:

1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the nINDEX pin twice.

2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track.

Table 15 – Status Register 2

BIT NO. SYMBOL NAME DESCRIPTION

7 Unused. This bit is always "0". 6 CM Control Mark Any one of the following:

Read Data command - the FDC encountered a deleted

data address mark.

Read Deleted Data command - the FDC encountered a

data address mark.

5 DD

Data Error in

The FDC detected a CRC error in the data field.

Data Field

4 WC

Wrong

Cylinder

The track address from the sector ID field is different

from the track address maintained inside the FDC. 3 Unused. This bit is always "0". 2 Unused. This bit is always "0".

1 BC Bad Cylinder

The track address from the sector ID field is different

from the track address maintained inside the FDC and is

equal to FF hex, which indicates a bad track with a hard

error according to the IBM soft-sectored format. 0 MD

Missing Data

Address Mark

The FDC cannot detect a data address mark or a

deleted data address mark.

SMSC DS – LPC47M14X Page 38 Rev. 03/19/2001

Table 16 – Status Register 3

BIT NO. SYMBOL NAME DESCRIPTION

7 Unused. This bit is always "0". 6 WP

Write

Indicates the status of the WP pin.

Protected 5 Unused. This bit is always "1". 4 T0 Track 0 Indicates the status of the TRK0 pin.

3 Unused. This bit is always "1". 2 HD Head Address Indicates the status of the HDSEL pin.

1,0 DS1,0 Drive Select Indicates the status of the DS1, DS0 pins.

RESET There are three sources of system reset on the FDC: the PCI_RESET# pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state.

All operations are terminated upon a PCI_RESET#, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC.

On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command.

PCI_RESET# Pin (Hardware Reset) The PCI_RESET# pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state.

DOR Reset vs. DSR Reset (Software Reset) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state.

MODES OF OPERATION The FDC has three modes of operation, PC/AT mode, PS/2 mode and Model 30 mode. These are determined by the state of the Interface Mode bits in LD0-CRF0[3,2].

PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal.

PS/2 mode This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care". The DMA and interrupt functions are always enabled, and DENSEL is active low.

Model 30 mode This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is active low.

DMA TRANSFERS DMA transfers are enabled with the Specify command and are initiated by the FDC by activating a DMA request cycle. DMA read, write and verify cycles are supported. The FDC supports two DMA transfer modes: Single Transfer and Burst Transfer. Burst mode is enabled via Logical Device 0-CRF0-Bit[1] (LD0-CRF0[1]).

CONTROLLER PHASES For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections.

Command Phase

After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the

SMSC DS – LPC47M14X Page 39 Rev. 03/19/2001

command phase is complete. (Please refer to Table 17 for the command set descriptions). These bytes of data must be transferred in the order prescribed.

Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition.

The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition.

Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA mode as indicated in the Specify command.

After a reset, the FIFO is disabled. Each data byte is transferred by a read/write or DMA cycle depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system.

A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.

Non-DMA Mode - Transfers from the FIFO to the Host

This part does not support non-DMA mode.

Non-DMA Mode - Transfers from the Host to the FIFO

This part does not support non-DMA mode.

DMA Mode - Transfers from the FIFO to the Host

The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DMA request when the FIFO becomes empty by generating the proper sync for the data transfer.

DMA Mode - Transfers from the Host to the FIFO

The FDC generates a DMA request cycle when entering the execution phase of the data transfer commands. The DMA controller must respond by placing data in the FIFO. The DMA request remains active until the FIFO becomes full. The DMA request cycle is reasserted when the FIFO has <threshold> bytes remaining in the FIFO. The FDC will terminate the DMA cycle after a TC, indicating that no more data is required.

Data Transfer Termination

The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-oftrack (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer.

If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a TC cycle was received. The only difference between these implicit functions and TC cycle is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected.

Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay.

Result Phase The generation of the interrupt determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start.

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RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command.

Command Set/Descriptions

Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command, which returns an invalid command error. Refer to Table 17 for explanations of the various symbols used. Table 18 lists the required parameters and the results associated with each command that the FDC is capable of performing.

Table 17 – Description of Command Symbols

SYMBOL NAME DESCRIPTION

C Cylinder Address The currently selected address; 0 to 255. D Data Pattern The pattern to be written in each sector data field during formatting.

D0, D1 Drive Select 0-1

DIR Direction Control

DS0, DS1 Disk Drive Select DS1 DS0 DRIVE

DTL

EC Enable Count

EFIFO Enable FIFO

EIS

EOT End of Track The final sector number of the current track. GAP Alters Gap 2 length when using Perpendicular Mode.

GPL Gap Length

H/HDS Head Address

HLT Head Load Time

HUT

LOCK

MFM

Special Sector

Size

Enable Implied

Seek

Head Unload

Time

MFM/FM Mode

Selector

Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive.

If this bit is 0, then the head will step out from the spindle during a relative seek. If set to a 1, the head will step in toward the spindle.

0 0 Drive 0 0 1 Drive 1

By setting N to zero (00), DTL may be used to control the number of bytes transferred in disk read/write commands. The sector size (N =

0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX.

When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track).

This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default).

When set, a seek operation will be performed before executing any read or write command that requires the C parameter in the command phase. A "0" disables the implied seek.

The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field).

Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field.

The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays.

The time interval from the end of the execution phase (of a read or write command) until the head is unloaded. Refer to the Specify command for actual delays.

Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset". (A reset caused by writing to the appropriate bits of either the DSR or DOR)

A one selects the double density (MFM) mode. A zero selects single density (FM) mode.

SMSC DS – LPC47M14X Page 41 Rev. 03/19/2001

Table 17 – Description of Command Symbols

SYMBOL NAME DESCRIPTION

Multi-Track

Selector

When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0.

N Sector Size Code

This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "Nth" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive.

N SECTOR SIZE 128 Bytes 256 Bytes 512 Bytes 1024 Bytes … … 07 16K Bytes

NCN

New Cylinder

The desired cylinder number.

Number

Non-DMA Mode

Write ‘0’. This part does not support non-DMA mode.

Flag

OW Overwrite

The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to 1. OW id defined in the Lock command.

PCN

POLL Polling Disable

Present Cylinder

Number

The current position of the head at the completion of Sense Interrupt Status command.

When set, the internal polling routine is disabled. When clear, polling is enabled.

PRETRK

Precompensation

Programmable from track 00 to FFH.

Start Track

Number

R Sector Address

The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written.

RCN

Relative Cylinder

Number

Number of

Sectors Per Track

Relative cylinder offset from present cylinder as used by the Relative Seek command.

The number of sectors per track to be initialized by the Format command. The number of sectors per track to be verified during a Verify command when EC is set.

SK Skip Flag

When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to "0", the sector is read or written the same as the read and write commands.

SRT Step Rate Interval

The time interval between step pulses issued by the FDC. Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 Mbit data rate. Refer to the SPECIFY command for actual

delays. ST0 ST1 ST2 ST3

Status 0 Status 1 Status 2 Status 3

Registers within the FDC that store status information after a

command has been executed. This status information is available to

the host during the result phase after command execution.

SMSC DS – LPC47M14X Page 42 Rev. 03/19/2001

Table 17 – Description of Command Symbols

SYMBOL NAME DESCRIPTION

WGATE Write Gate

Alters timing of WE to allow for pre-erase loads in perpendicular

drives.

6.5.3 Instruction Set

Table 18 – Instruction Set

READ DATA

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W C

W H W R W N W EOT W GPL W DTL

Execution

Result R ST0

R ST1 R ST2 R C

R H R R R N

DATA BUS

Sector ID information prior to Command execution.

Data transfer between the FDD and system.

Status information after Command execution.

Sector ID information after Command execution.

SMSC DS – LPC47M14X Page 43 Rev. 03/19/2001

READ DELETED DATA

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W C

W H W R W N W EOT W GPL W DTL

Execution

Result R ST0

R ST1 R ST2 R C

R H R R R N

WRITE DATA

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W C

W H W R W N W EOT W GPL W DTL

Execution

Result R ST0

R ST1 R ST2 R C

R H R R R N

Sector ID information prior to Command execution.

Data transfer between the FDD and system.

Status information after Command execution.

Sector ID information after Command execution.

Sector ID information prior to Command execution.

Data transfer between the FDD and system.

Status information after Command execution.

Sector ID information after Command execution.

SMSC DS – LPC47M14X Page 44 Rev. 03/19/2001

WRITE DELETED DATA

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W C

W H W R W N W EOT W GPL W DTL

Execution

Result R ST0

R ST1 R ST2 R C

R H R R R N

READ A TRACK

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W C

W H W R W N W EOT W GPL W DTL

Execution

Result R ST0

R ST1 R ST2 R C

R H R R R N

Sector ID information prior to Command execution.

Data transfer between the FDD and system.

Status information after Command execution.

Sector ID information after Command execution.

Sector ID information prior to Command execution.

Data transfer between the FDD and system. FDC reads all of cylinders' contents from index hole to EOT.

Status information after Command execution.

Sector ID information after Command execution.

SMSC DS – LPC47M14X Page 45 Rev. 03/19/2001

VERIFY

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 1 0 1 1 0 Command Codes

W EC 0 0 0 0 HDS DS1 DS0 W C

Sector ID information prior to Command

execution. W H W R W N W EOT W GPL W DTL/SC

Execution

No data transfer takes

place.

Result R ST0

Status information after

Command execution. R ST1 R ST2 R C

Sector ID information

after Command

execution. R H R R R N

VERSION

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command Code

Result R 1 0 0 1 0 0 0 0 Enhanced Controller

SMSC DS – LPC47M14X Page 46 Rev. 03/19/2001

FORMAT A TRACK

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W N Bytes/Sector W SC Sectors/Cylinder W GPL Gap 3 W D Filler Byte

Execution for

W C Input Sector Parameters

Each Sector

Repeat:

W H W R W N

FDC formats an entire

cylinder

Result R ST0

Status information after

Command execution R ST1 R ST2 R Undefined R Undefined R Undefined R Undefined

RECALIBRATE

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command Codes

W 0 0 0 0 0 0 DS1 DS0

Execution

Head retracted to Track 0 Interrupt.

SENSE INTERRUPT STATUS

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command Codes

Result R ST0

Status information at the end of each seek operation.

R PCN

SPECIFY

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command Codes

W SRT HUT W HLT ND

SMSC DS – LPC47M14X Page 47 Rev. 03/19/2001

SENSE DRIVE STATUS

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 0 0 Command Codes

W 0 0 0 0 0 HDS DS1 DS0

Result R ST3

Status information about FDD

SEEK

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command Codes

W 0 0 0 0 0 HDS DS1 DS0 W NCN

Execution

Head positioned over proper cylinder on diskette.

CONFIGURE

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 1

Configure

Information W 0 0 0 0 0 0 0 0 W 0 EIS EFIFO POLL FIFOTHR

Execution W PRETRK

RELATIVE SEEK

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 1 DIR 0 0 1 1 1 1

W 0 0 0 0 0 HDS DS1 DS0

W RCN

DUMPREG

PHASE R/W

DATA BUS

D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W 0 0 0 0 1 1 1 0 *Note:

Registers placed in FIFO

Execution

Result R PCN-Drive 0

R PCN-Drive 1

R PCN-Drive 2

R PCN-Drive 3

R SRT HUT

R HLT ND

R SC/EOT

R LOCK 0 D3 D2 D1 D0 GAP WGATE

R 0 EIS EFIFO POLL FIFOTHR

R PRETRK

SMSC DS – LPC47M14X Page 48 Rev. 03/19/2001

READ ID

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Commands

W 0 0 0 0 0 HDS DS1 DS0

Execution

The first correct ID information on the Cylinder is stored in Data Register

Result R ST0

Status information after Command execution.

Disk status after the Command has

completed R ST1 R ST2 R C R H R R R N

PERPENDICULAR MODE

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 0 Command Codes

OW 0 D3 D2 D1 D0 GAP WGATE

INVALID CODES

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W Invalid Codes

Invalid Command Codes (NoOp - FDC goes into Standby State)

Result R ST0 ST0 = 80H

LOCK

DATA BUS

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W LOCK 0 0 1 0 1 0 0 Command Codes

Result R 0 0 0 LOCK 0 0 0 0

SC is returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write.

Note: These bits are used internally only. They are not reflected in the Drive Select pins. It is the user's responsibility to maintain correspondence between these bits and the Drive Select pins (DOR).

SMSC DS – LPC47M14X Page 49 Rev. 03/19/2001

6.5.4 DATA TRANSFER COMMANDS

All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte.

An implied seek will be executed if the feature was enabled by the Configure command. This seek is completely transparent to the user. The Drive Busy bit for the drive will go active in the Main Status Register during the seek portion of the command. If the seek portion fails, it is reflected in the results status normally returned for a Read/Write Data command. Status Register 0 (ST0) would contain the error code and C would contain the cylinder on which the seek failed.

Read Data A set of nine (9) bytes is required to place the FDC in the Read Data Mode. After the Read Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the Specify command), and begins reading ID Address Marks and ID fields. When the sector address read off the diskette matches with the sector address specified in the command, the FDC reads the sector's data field and transfers the data to the FIFO.

After completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the FIFO. This continuous read function is called "Multi-Sector Read Operation". Upon receipt of the TC cycle, or an implied TC (FIFO overrun/underrun), the FDC stops sending data but will continue to read data from the current sector, check the CRC bytes, and at the end of the sector, terminate the Read Data Command.

N determines the number of bytes per sector (see Table 19 below). If N is set to zero, the sector size is set to 128. The DTL value determines the number of bytes to be transferred. If DTL is less than 128, the FDC transfers the specified number of bytes to the host. For reads, it continues to read the entire 128-byte sector and checks for CRC errors. For writes, it completes the 128-byte sector by filling in zeros. If N is not set to 00 Hex, DTL should be set to FF Hex and has no impact on the number of bytes transferred.

Table 19 – Sector Sizes

N SECTOR SIZE

00 01 02 03

128 bytes 256 bytes 512 bytes

1024 bytes

...

16 Kbytes

The amount of data, which can be handled with a single command to the FDC, depends upon MT (multi-track) and N (number of bytes/sector).

The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. For a particular cylinder, data will be transferred starting at Sector 1, Side 0 and completing the last sector of the same track at Side 1.

If the host terminates a read or write operation in the FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 20.

At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads.

If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the ND bit in Status Register 1 to "1" indicating a sector not found, and terminates the Read Data Command.

After reading the ID and Data Fields in each sector, the FDC checks the CRC bytes. If a CRC error occurs in the ID or data field, the FDC sets the IC code in Status Register 0 to "01" indicating abnormal termination, sets the DE bit flag in Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 21 describes the effect of the SK bit on the Read Data command execution and results. Except where noted in Table 21, the C or R value of the sector address is automatically incremented (see Table 23).

SMSC DS – LPC47M14X Page 50 Rev. 03/19/2001

Table 20 – Effects of MT and N Bits

MT N

0 1 0 1 0 1

MAXIMUM TRANSFER

CAPACITY

256 x 26 = 6,656

256 x 52 = 13,312

512 x 15 = 7,680

512 x 30 = 15,360

1024 x 8 = 8,192

1024 x 16 = 16,384

FINAL SECTOR READ

FROM DISK

26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1

Table 21 – Skip Bit vs Read Data Command

SK BIT

VALUE

DATA ADDRESS

MARK TYPE

ENCOUNTERED

Normal Data

Deleted Data

Normal Data

Deleted Data

SECTOR

READ?

Yes

CM BIT OF

ST2 SET?

RESULTS

Yes

DESCRIPTION OF

RESULTS

Normal termination.

Address not incremented. Next sector not searched for.

Normal termination.

Normal termination. Sector not read ("skipped").

Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field.

Table 22 describes the effect of the SK bit on the Read Deleted Data command execution and results. Except where noted in Table 22, the C or R value of the sector address is automatically incremented (see Table 23).

Table 22 – Skip Bit vs. Read Deleted Data Command

SK BIT VALUE

DATA ADDRESS

MARK TYPE

ENCOUNTERED

Normal Data

Deleted Data

Normal Data

Deleted Data

SECTOR

READ?

Yes

RESULTS

CM BIT OF

ST2 SET?

Yes

DESCRIPTION OF

RESULTS

Address not incremented. Next sector not searched for.

Normal termination.

Normal termination. Sector not read ("skipped").

Normal termination.

SMSC DS – LPC47M14X Page 51 Rev. 03/19/2001

Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. If the FDC finds an error in the ID or DATA CRC check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. The FDC compares the ID information read from each sector with the specified value in the command and sets the ND flag of Status Register 1 to a “1” if there no comparison. Multi-track or skip operations are not allowed with this command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be set to "0".

This command terminates when the EOT specified number of sectors has not been read. If the FDC does not find an ID Address Mark on the diskette after the second occurrence of a pulse on the INDEX pin, then it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.

Table 23 – Result Phase Table

HEAD

0 0

FINAL SECTOR

TRANSFERRED TO

ID INFORMATION AT RESULT PHASE

HOST C H R N

Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 NC 01 NC

Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 NC 01 NC

1 0

Less than EOT NC NC R + 1 NC

Equal to EOT NC LSB 01 NC

Less than EOT NC NC R + 1 NC

Equal to EOT C + 1 LSB 01 NC

NC: No Change, the same value as the one at the beginning of command execution. LSB: Least Significant Bit, the LSB of H is complemented.

Write Data

After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID fields. When the sector address read from the diskette matches the sector address specified in the command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field.

After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register 0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data command.

The Write Data command operates in much the same manner as the Read Data command. The following items are the same. Please refer to the Read Data Command for details:

 Transfer Capacity  EN (End of Cylinder) bit  ND (No Data) bit  Head Load, Unload Time Interval  ID information when the host terminates the command

Definition of DTL when N = 0 and when N does not = 0

Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is typically used to mark a bad sector containing an error on the floppy disk.

SMSC DS – LPC47M14X Page 52 Rev. 03/19/2001

Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is computed and checked against the previously-stored value.

Because data is not transferred to the host, the TC cycle cannot be used to terminate this command. By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC value of 0 will verify 256 sectors). This command can also be terminated by setting the EC bit to "0" and the EOT value equal to the final sector to be checked. If EC is set to "0", DTL/SC should be programmed to 0FFH. Refer to Table 23 and Table 24 for information concerning the values of MT and EC versus SC and EOT value.

Definitions:

# Sectors Per Side = Number of formatted sectors per each side of the disk.

# Sectors Remaining = Number of formatted sectors left which can be read, including side 1 of the disk if MT is set to "1".

Table 24 – Verify Command Result Phase Table

MT EC SC/EOT VALUE TERMINATION RESULT

0 0

0 1

1 0

1 1

SC = DTL EOT ≤ # Sectors Per Side SC = DTL EOT > # Sectors Per Side

SC ≤ # Sectors Remaining AND EOT ≤ # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side SC = DTL EOT ≤ # Sectors Per Side SC = DTL EOT > # Sectors Per Side

SC ≤ # Sectors Remaining AND EOT ≤ # Sectors Per Side SC > # Sectors Remaining OR EOT > # Sectors Per Side

Success Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid

Successful Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid

Successful Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid

Successful Termination Result Phase Valid

Unsuccessful Termination Result Phase Invalid

Note: If MT is set to "1" and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk.

SMSC DS – LPC47M14X Page 53 Rev. 05/02/2000

Format A Track The Format command allows an entire track to be formatted. After a pulse from the nINDEX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System 34 or 3740 format (MFM or FM respectively). The particular values that will be written to the gap and data field are controlled by the values programmed into N, SC, GPL, and D which are specified by the host during the command phase. The data field of the sector is filled with the data byte specified by D. The ID field for each sector is supplied by the host; that is, four data bytes per sector are needed by the FDC for C, H, R, and N (cylinder, head, sector number and sector size respectively).

After formatting each sector, the host must send new values for C, H, R and N to the FDC for the next sector on the track. The R value (sector number) is the only value that must be changed by the host after each sector is formatted. This allows the disk to be formatted with nonsequential sector addresses (interleaving). This incrementing and formatting continues for the whole track until the FDC encounters a pulse on the nINDEX pin again and it terminates the command.

Table 25 contains typical values for gap fields that are dependent upon the size of the sector and the number of sectors on each track. Actual values can vary due to drive electronics.

FORMAT FIELDS

SYSTEM 34 (DOUBLE DENSITY) FORMAT

GAP4a

SYNC

80x

12x

IAM

GAP1

50x

SYNC

12x

IDAM

3x A1

GAP2

22x

SYNC

12x

DATA

3xA1FB

DATA

R C

GAP3

GAP 4b

SYSTEM 3740 (SINGLE DENSITY) FORMAT

SYNC

GAP4a

40x

FC FE

6x 00

IAM

GAP1

26x

SYNC

6x 00

IDAM

Y L

E C

GAP2

11x

SYNC

6x 00

DATA

FB or

DATA

GAP3

R C

GAP 4b

PERPENDICULAR FORMAT

GAP4a

SYNC

80x

12x

IAM

GAP1

50x

SYNC

12x

IDAM

3x A1

GAP2

41x

SYNC

12x

DATA

3xA1FB

DATA

R C

GAP3

GAP 4b

SMSC DS – LPC47M14X Page 54 Rev. 05/02/2000

Table 25 – Typical Values for Formatting

5.25" Drives

3.5" Drives

FORMAT SECTOR SIZE N SC GPL1 GPL2

MFM

128 128

512 1024 2048 4096

...

256

256 512* 1024 2048 4096

...

128

256

512

256

512**

1024

00 00 02 03 04 05

...

01 01 02 03 04 05

...

0 1 2

1 2 3

12 10 08 04 02 01

12 10 09 04 02 01

0F 09 05

07 10 18 46 C8 C8

0A 20 2A 80 C8 C8

07 0F 1B

0E 1B 35

09 19 30

87 FF FF

F0 FF FF

GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A Track command. *PC/AT values (typical) **PS/2 values (typical). Applies with 1.0 MB and 2.0 MB drives.

Note: All values except sector size are in hex.

CONTROL COMMANDS

Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt.

Read ID The Read ID command is used to find the present position of the recording heads. The FDC stores the values from the first ID field it is able to read into its registers. If the FDC does not find an ID address mark on the diskette after the second occurrence of a pulse on the nINDEX pin, it then sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command.

The following commands will generate an interrupt upon completion. They do not return any result bytes. It is highly recommended that control commands be followed by the Sense Interrupt Status command. Otherwise, valuable interrupt status information will be lost.

Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTRK0 pin from the FDD. As long as the nTRK0 pin is low, the DIR pin remains 0 and step pulses are issued. When the nTRK0 pin goes high, the SE bit in Status Register 0 is set to "1" and the command is terminated. If the nTRK0 pin is still low after 79 step pulses have been issued, the FDC sets the SE and the EC bits of Status Register 0 to "1" and terminates the command. Disks capable of handling more than 80 tracks per side may require more than one Recalibrate command to return the head back to physical Track 0.

The Recalibrate command does not have a result phase. The Sense Interrupt Status command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the head position (PCN). During the command phase of the recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in a NON-BUSY state. At this time, another Recalibrate command may be issued, and in this manner parallel Recalibrate operations may be done on up to four drives at once. Upon power up, the software must issue a Recalibrate command to properly initialize all drives and the controller.

SMSC DS – LPC47M14X Page 55 Rev. 05/02/2000

Seek The read/write head within the drive is moved from track to track under the control of the Seek command. The FDC compares the PCN, which is the current head position, with the NCN and performs the following operation if there is a difference:

PCN < NCN: Direction signal to drive set to "1" (step in) and issues step pulses. PCN > NCN: Direction signal to drive set to "0" (step out) and issues step pulses.

The rate at which step pulses are issued is controlled by SRT (Stepping Rate Time) in the Specify command. After each step pulse is issued, NCN is compared against PCN, and when NCN = PCN the SE bit in Status Register 0 is set to "1" and the command is terminated. During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase it is in the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once.

Note that if implied seek is not enabled, the read and write commands should be preceded by:

1) Seek command - Step to the proper track

2) Sense Interrupt Status command - Terminate the Seek command

3) Read ID - Verify head is on proper track

4) Issue Read/Write command.

The Seek command does not have a result phase. Therefore, it is highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head position (PCN). The H bit (Head Address) in ST0 will always return to a "0". When exiting POWERDOWN mode, the FDC clears the PCN value and the status information to zero. Prior to issuing the POWERDOWN command, it is highly recommended that the user service all pending interrupts through the Sense Interrupt Status command.

Sense Interrupt Status An interrupt signal is generated by the FDC for one of the following reasons:

1) Upon entering the Result Phase of: a. Read Data command b. Read A Track command c. Read ID command d. Read Deleted Data command e. Write Data command f. Format A Track command g. Write Deleted Data command h. Verify command

2) End of Seek, Relative Seek, or Recalibrate command

The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt.

Table 26 – Interrupt Identification

SE IC INTERRUPT DUE TO

0 1

Polling

Normal termination of Seek or Recalibrate command Abnormal termination of

Seek or Recalibrate command

The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue to be BUSY and may affect the operation of the next command.

Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information.

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Specify

The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT (Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 27. The values are the same for MFM and FM.

A DMA operation is selected by the ND bit. When ND is "0", the DMA mode is selected. This part does not support non-

DMA mode. In DMA mode, data transfers are signaled by the DMA request cycles. Configure

The Configure command is issued to select the special features of the FDC. A Configure command need not be issued if the default values of the FDC meet the system requirements.

Table 27 – Drive Control Delays (ms)

256

.. 224 240

HUT

426

26.7 ..

373 400

512

.. 448 480

3.75 ..

0.5

0.25

7.5 .. 1

0.5

2M 1M 500K 300K 250K 2M 1M 500K 300K 250K

128

.. 112 120

E F

56 60

16 15

.. 2 1

SRT

26.7 25

3.33

1.67

32 30

.. 4 2

00 01 02

.. 7F 7F

2M 1M 500K 300K 250K

0.5 1 ..

63.5

128

1 2

.. 126 127

256

252 254

HLT

426 2 4 ..

3.3

6.7 ..

420 423

512

4 8

. 504 508

Configure Default Values:

 EIS - No Implied Seeks  EFIFO - FIFO Disabled  POLL - Polling Enabled  FIFOTHR - FIFO Threshold Set to 1 Byte  PRETRK - Pre-Compensation Set to Track 0

EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek.

EFIFO - A "1" disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to "1", FIFO disabled. The threshold defaults to "1".

POLL - Disable polling of the drives. Defaults to "0", polling enabled. When enabled, a single interrupt is generated after a reset. No polling is performed while the drive head is loaded and the head unload delay has not expired.

FIFOTHR - The FIFO threshold in the execution phase of read or write commands. This is programmable from 1 to 16 bytes. Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes.

PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255.

Version The Version command checks to see if the controller is an enhanced type or the older type (765A). A value of 90 H is returned as the result byte.

Relative Seek

The command is coded the same as for Seek, except for the MSB of the first byte and the DIR bit.

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DIR Head Step Direction Control RCN Relative Cylinder Number that determines how many tracks to step the head in or out from the current track

number.

DIR ACTION

0 1 Step Head Out

Step Head In

The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives that support a maximum of 256 tracks. Relative Seeks cannot be overlapped with other Relative Seeks. Only one Relative Seek can be active at a time. Relative Seeks may be overlapped with Seeks and Recalibrates. Bit 4 of Status Register 0 (EC) will be set if Relative Seek attempts to step outward beyond Track 0.

As an example, assume that a floppy drive has 300 useable tracks. The host needs to read track 300 and the head is on any track (0-255). If a Seek command is issued, the head will stop at track 255. If a Relative Seek command is issued, the FDC will move the head the specified number of tracks, regardless of the internal cylinder position register (but will increment the register). If the head was on track 40 (d), the maximum track that the FDC could position the head on using Relative Seek will be 295 (D), the initial track + 255 (D). The maximum count that the head can be moved with a single Relative Seek command is 255 (D).

The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the track number goes above 255 (D). It is the user's responsibility to compensate FDC functions (precompensation track number) when accessing tracks greater than 255. The FDC does not keep track that it is working in an "extended track area" (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. The user simply needs to issue a second Recalibrate command. The Seek command and implied seeks will function correctly within the 44 (D) track (299-255) area of the "extended track area". It is the user's responsibility not to issue a new track position that will exceed the maximum track that is present in the extended area.

To return to the standard floppy range (0-255) of tracks, a Relative Seek should be issued to cross the track 255 boundary.

A Relative Seek can be used instead of the normal Seek, but the host is required to calculate the difference between the current head location and the new (target) head location. This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results, which may be difficult to keep track of with software without the Read ID command.

Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. With this command, the length of the Gap2 field and VCO enable timing can be altered to accommodate the unique requirements of these drives. Table 28 describes the effects of the WGATE and GAP bits for the Perpendicular Mode command. Upon a reset, the FDC will default to the conventional mode (WGATE = 0, GAP = 0).

Selection of the 500 Kbps and 1 Mbps perpendicular modes is independent of the actual data rate selected in the Data Rate Select Register. The user must ensure that these two data rates remain consistent.

The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. This works out to about 38 bytes at a 1 Mbps recording density. Whenever the write head is enabled by the Write Gate signal, the pre-erase head is also activated at the same time. Thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. To accommodate this head activation and deactivation time, the Gap2 field is expanded to a length of 41 bytes. The format field shown on Page 58 illustrates the change in the Gap2 field size for the perpendicular format.

On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled (VCOEN) approximately 24 bytes from the start of the Gap2 field. But, when the controller operates in the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), VCOEN goes active after 43 bytes to accommodate the increased Gap2 field size. For both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation.

For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC. With the pre-erase head of the perpendicular drive, the write head must be activated in the Gap2 field to insure a proper write of the new sync field. For the 1 Mbps perpendicular mode (WGATE = 1, GAP = 1), 38 bytes will be written in the Gap2 space. Since the bit density is proportional to the data rate, 19 bytes will be written in the Gap2 field for the 500 Kbps perpendicular mode (WGATE = 1, GAP =0).

It should be noted that none of the alterations in Gap2 size, VCO timing, or Write Gate timing affect normal program flow. The information provided here is just for background purposes and is not needed for normal operation. Once the Perpendicular Mode command is invoked, FDC software behavior from the user standpoint is unchanged.

The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive types, nor having to change write precompensation values.

When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also apply:

1) The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed data rate.

2) The write pre-compensation given to a perpendicular mode drive will be 0ns.

3) For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation.

Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-

D3 are ignored.

Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:

1) "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected and retain their previous value.

2) "Hardware" resets will clear all bits (GAP, WGATE and D0-D3) to "0", i.e. all conventional mode.

Table 28 – Effects of WGATE and GAP Bits

WGATE

0 0

GAP

0 1

MODE

Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular

LENGTH OF

GAP2 FORMAT

FIELD

22 Bytes 22 Bytes

22 Bytes

41 Bytes

PORTION OF

GAP 2 WRITTEN BY WRITE DATA

OPERATION

0 Bytes

19 Bytes

0 Bytes

38 Bytes

(1 Mbps)

LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be used by the FDC routines, and application software should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should be used.

The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware" RESET from the PCI_RESET# pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte.

SMSC DS – LPC47M14X Page 59 Rev. 05/02/2000

ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth byte of the DUMPREG command has been modified to contain the additional data from these two commands.

COMPATIBILITY

The LPC47M14x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS.

6.6 SERIAL PORT (UART)

The LPC47M14x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-toserial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UARTs interrupt. The second UART also supports IrDA, HP-SIR and ASK-IR modes of operation.

Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for more information.

REGISTER DESCRIPTION Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are defined by the configuration registers (see “Configuration” section). The Serial Port registers are located at sequentially increasing addresses above these base addresses. The LPC47M14x contains two serial ports, each of which contain a register set as described below.

Table 29 – Addressing the Serial Port

DLAB* A2 A1 A0 REGISTER NAME

0 0 0 0 Receive Buffer (read)

0 0 0 0 Transmit Buffer (write)

0 0 0 1 Interrupt Enable (read/write)

X 0 1 0 Interrupt Identification (read)

X 0 1 0 FIFO Control (write)

X 0 1 1 Line Control (read/write)

X 1 0 0 Modem Control (read/write)

X 1 0 1 Line Status (read/write)

X 1 1 0 Modem Status (read/write)

X 1 1 1 Scratchpad (read/write)

1 0 0 0 Divisor LSB (read/write)

1 0 0 1 Divisor MSB (read/write

*Note: DLAB is Bit 7 of the Line Control Register

SMSC DS – LPC47M14X Page 60 Rev. 05/02/2000

The following section describes the operation of the registers.

RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY

This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.

TRANSMIT BUFFER REGISTER (TB) Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit Buffer when the transmission of the previous byte is complete.

INTERRUPT ENABLE REGISTER (IER) Address Offset = 1H, DLAB = 0, READ/WRITE

The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M14x. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below.

Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1".

Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1".

Bit 2 This bit enables the Received Line Status Interrupt when set to logic "1". The error sources causing the interrupt are Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.

Bit 3 This bit enables the MODEM Status Interrupt when set to logic "1". This is caused when one of the Modem Status Register bits changes state.

Bits 4 through 7 These bits are always logic "0".

FIFO CONTROL REGISTER (FCR) Address Offset = 2H, DLAB = X, WRITE

This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the RCVR FIFO trigger level. Note: DMA is not supported. The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).

Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic "0" disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to or they will not be properly programmed.

Bit 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing.

Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing.

Bit 3 Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip.

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Bit 4,5

Reserved

Bit 6,7 These bits are used to set the trigger level for the RCVR FIFO interrupt.

INTERRUPT IDENTIFICATION REGISTER (IIR) Address Offset = 2H, DLAB = X, READ

By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority interrupt exist. They are in descending order of priority:

1) Receiver Line Status (highest priority)

2) Received Data Ready

3) Transmitter Holding Register Empty

4) MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate internal service routine. When bit 0 is a logic "1", no interrupt is pending.

Bits 1 and 2 These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control Table.

Bit 3 In non-FIFO mode, this bit is a logic "0". In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.

Bits 4 and 5 These bits of the IIR are always logic "0".

Bits 6 and 7 These two bits are set when the FIFO CONTROL Register bit 0 equals 1.

Bit 7 Bit 6

RCVR FIFO

Trigger Level (BYTES)

0 0 1

0 1 4

1 0 8

1 1 14

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Table 30 – Interrupt Control Table

FIFO

MODE

ONLY

INTERRUPT

IDENTIFICATION

BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 - None None -

0 1 1 0 Highest

0 1 0 0 Second

1 1 0 0 Second

0 0 1 0 Third

0 0 0 0 Fourth

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

PRIORITY

LEVEL

INTERRUPT SET AND RESET FUNCTIONS

INTERRUPT

TYPE

INTERRUPT

SOURCE

INTERRUPT

CONTROL

Overrun Error,

Receiver Line

Status

Parity Error,

Framing Error or

Reading the Line

Status Register

Break Interrupt

Read Receiver

Received Data

Available

Receiver Data

Available

Buffer or the FIFO

drops below the

trigger level.

No Characters

Have Been

Removed From or

Character

Timeout

Indication

Input to the RCVR

FIFO during the

last 4 Char times

Reading the

Receiver Buffer

and there is at

least 1 char in it

during this time

Reading the IIR

Transmitter

Holding

Transmitter

Holding Register

Empty

of Interrupt) or

Writing the

Transmitter

Holding Register

Clear to Send or

MODEM

Status

Data Set Ready or

Ring Indicator or

Data Carrier

Reading the

MODEM Status

Detect

RESET

Start LSB Data 5-8 bits MSB Parity Stop

Serial Data

This register contains the format information of the serial line. The bit definitions are:

Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1 is as follows:

The Start, Stop and Parity bits are not included in the word length.

BIT 1 BIT 0 WORD LENGTH

0 0 1 1

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0 1 0 1

5 Bits 6 Bits 7 Bits 8 Bits

Bit 2 This bit specifies the number of stop bits in each transmitted or received serial character. The following table summarizes the information.

BIT 2 WORD LENGTH

NUMBER OF

STOP BITS

0 -- 1 1 5 bits 1.5 1 6 bits 2

1 7 bits 2 1 8 bits 2

Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.

Bit 3

Parity Enable bit. When bit 3 is a logic "1", a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed).

Bit 4 Even Parity Select bit. When bit 3 is a logic "1" and bit 4 is a logic "0", an odd number of logic "1"'s is transmitted or checked in the data word bits and the parity bit. When bit 3 is a logic "1" and bit 4 is a logic "1" an even number of bits is transmitted and checked.

Bit 5

This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.

Bit 6 Set Break Control bit. When bit 6 is a logic "1", the transmit data output (TXD) is forced to the Spacing or logic "0" state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system.

Bit 7 Divisor Latch Access bit (DLAB). It must be set high (logic "1") to access the Divisor Latches of the Baud Rate Generator during read or write operations. It must be set low (logic "0") to access the Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.

MODEM CONTROL REGISTER (MCR)

Address Offset = 4H, DLAB = X, READ/WRITE

This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below.

Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit 0 is a logic "0", the nDTR output is forced to a logic "1".

Bit 1 This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0.

Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU.

Bit 3 Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.

SMSC DS – LPC47M14X Page 64 Rev. 03/19/2001

Bit 4 This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic "1", the following occur:

1) The TXD is set to the Marking State(logic "1").

2) The receiver Serial Input (RXD) is disconnected.

3) The output of the Transmitter Shift Register is "looped back" into the Receiver Shift Register input.

4) All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.

5) The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI, DCD).

6) The Modem Control output pins are forced inactive high.

7) Data that is transmitted is immediately received.

This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register.

Bits 5 through 7 These bits are permanently set to logic zero.

LINE STATUS REGISTER (LSR) Address Offset = 5H, DLAB = X, READ/WRITE

Bit 0

Data Ready (DR). It is set to a logic "1" whenever a complete incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic "0" by reading all of the data in the Receive Buffer Register or the FIFO.

Bit 1 Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only when the FIFO is full and the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic "1" immediately upon detection of an overrun condition, and reset whenever the Line Status Register is read.

Bit 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. The PE is set to a logic "1" upon detection of a parity error and is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.

Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to a logic "0" whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this 'start' bit twice and then takes in the 'data'.

Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received, requires the serial data (RXD) to be logic "1" for at least 1/2 bit time.

Note: Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled.

Bit 5 Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register interrupt enable is set high. The THRE bit is set to a logic "1" when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic "0" whenever the CPU loads the Transmitter

SMSC DS – LPC47M14X Page 65 Rev. 03/19/2001

Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is a read only bit.

Bit 6 Transmitter Empty (TEMT). Bit 6 is set to a logic "1" whenever the Transmitter Holding Register (THR) and Transmitter Shift Register (TSR) are both empty. It is reset to logic "0" whenever either the THR or TSR contains a data character. Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty,

Bit 7 This bit is permanently set to logic "0" in the 450 mode. In the FIFO mode, this bit is set to a logic "1" when there is at least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are no subsequent errors in the FIFO.

MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB = X, READ/WRITE

This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits are set to logic "1" whenever a control input from the MODEM changes state. They are reset to logic "0" whenever the MODEM Status Register is read.

Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read.

Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read.

Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic "0" to logic "1".

Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.

Note: Whenever bit 0, 1, 2, or 3 is set to a logic "1", a MODEM Status Interrupt is generated.

Bit 4

This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to nRTS in the MCR.

Bit 5 This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to DTR in the MCR.

Bit 6 This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT1 in the MCR. Bit 7 This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic "1", this bit is equivalent to OUT2 in the MCR.

SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE

This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.

PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL) The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for

460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16 bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3. If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a

SMSC DS – LPC47M14X Page 66 Rev. 03/19/2001

50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input clock to the BRG is a 1.8462 MHz clock.

Table 31 shows the baud rates possible.

Effect Of The Reset on Register File

The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port.

FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows:

 The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is

cleared as soon as the FIFO drops below its programmed trigger level.

 The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when

the FIFO drops below the trigger level.

 The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H)

interrupt.

 The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR

FIFO. It is reset when the FIFO is empty.

When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:

1) A FIFO timeout interrupt occurs if all the following conditions exist:

 At least one character is in the FIFO.  The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits

are programmed, the second one is included in this time delay).

 The most recent CPU read of the FIFO was longer than 4 continuous character times ago.

This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12 bit character.

 Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional

to the baudrate).

 When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character

from the RCVR FIFO.

 When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after

the CPU reads the RCVR FIFO.

When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows:

 The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as

the transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this interrupt) or the IIR is read.

 The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever

the following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.

Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.

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FIFO POLLED MODE OPERATION With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows:

 Bit 0=1 as long as there is one byte in the RCVR FIFO.  Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when

in the interrupt mode, the IIR is not affected since EIR bit 2=0.

 Bit 5 indicates when the XMIT FIFO is empty.  Bit 6 indicates that both the XMIT FIFO and shift register are empty.  Bit 7 indicates whether there are any errors in the RCVR FIFO.

There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters.

Table 31 – Baud Rates

DESIRED

BAUD RATE

DIVISOR USED TO

GENERATE 16X CLOCK

PERCENT ERROR DIFFERENCE

BETWEEN DESIRED AND ACTUAL

50 2304 0.001 X 75 1536 - X 110 1047 - X

134.5 857 0.004 X 150 768 - X 300 384 - X 600 192 - X

1200 96 - X 1800 64 - X 2000 58 0.005 X 2400 48 - X 3600 32 - X 4800 24 - X 7200 16 - X

9600 12 - X 19200 6 - X 38400 3 0.030 X 57600 2 0.16 X

115200 1 0.16 X 230400 32770 0.16 1 460800 32769 0.16 1

: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.

Note

: The High Speed bit is located in the Device Configuration Space.

SPEED BIT

HIGH

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Table 32 – Reset Function Table

Interrupt Enable Register RESET All bits low

Interrupt Identification Reg. RESET Bit 0 is high; Bits 1 - 7 low

FIFO Control RESET All bits low

Line Control Reg. RESET All bits low

MODEM Control Reg. RESET All bits low

Line Status Reg. RESET All bits low except 5, 6 high

MODEM Status Reg. RESET Bits 0 - 3 low; Bits 4 - 7 input

TXD1, TXD2 RESET High

INTRPT (RCVR errs) RESET/Read LSR Low

INTRPT (RCVR Data Ready) RESET/Read RBR Low

INTRPT (THRE) RESET/ReadIIR/Write THR Low

OUT2B RESET High

RTSB RESET High

DTRB RESET High

OUT1B RESET High

RCVR FIFO

XMIT FIFO

RESET/ FCR1*FCR0/_FCR0

All Bits Low

Table 33 – Register Summary for an Individual UART Channel

ADDR = 0

Receive Buffer Register (Read Only) RBR Data Bit 0

SYMBOL

DLAB = 0

ADDR = 0 DLAB = 0

ADDR = 1

Transmitter Holding Register (Write

THR Data Bit 0 Data Bit 1

Only)

Interrupt Enable Register IER Enable

DLAB = 0

ADDR = 2

Interrupt Ident. Register (Read Only) IIR "0" if

ADDR = 2 FIFO Control Register (Write Only) FCR

(Note 7)

ADDR = 3

Line Control Register LCR Word

ADDR = 4

MODEM Control Register MCR Data

ADDR = 5

Line Status Register LSR

BIT 0

BIT 1

Data Bit 1

(Note 1)

Enable Received Data Available Interrupt (ERDAI)

Transmitter

Holding

Empty

Interrupt

(ETHREI)

Interrupt ID Interrupt

Bit Pending

FIFO Enable RCVR FIFO

Reset

Word Length Select Bit 0 (WLS0)

Length

Select Bit 1

(WLS1)

Request to Terminal

Send (RTS) Ready (DTR)

Data Ready (DR)

Overrun

Error (OE)

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ADDR = 6

ADDR = 7

ADDR = 0

MODEM Status Register MSR

Scratch Register (Note 4) SCR Bit 0 Bit 1

Divisor Latch (LS) DDL Bit 0 Bit 1

SYMBOL

BIT 0

Delta Clear to Send (DCTS)

BIT 1

Delta Data

Set Ready

(DDSR)

DLAB = 1

ADDR = 1

Divisor Latch (MS) DLM Bit 8 Bit 9

DLAB = 1

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.

Table 33 – Register Summary for an Individual UART Channel (continued)

BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7

Data Bit 2

Enable Receiver Line Status Interrupt (ELSI)

Interrupt ID Bit Interrupt ID Bit

XMIT FIFO Reset

Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7

Enable

0 0 0 MODEM Status Interrupt (EMSI)

0 0 FIFOs (Note 5)

DMA Mode

Reserved Reserved RCVR Trigger Select (Note

Enabled (Note 5)

LSB

FIFOs Enabled (Note 5)

RCVR Trigger MSB

Number of Stop Bits

Parity Enable (PEN)

(STB)

OUT1 (Note 3)

Parity Error (PE)

OUT2 (Note 3)

Framing Error (FE)

Even Parity

Stick Parity Set Break

Select (EPS)

Loop 0 0 0

Break

Interrupt (BI)

Transmitter Holding Register

Transmitter Empty (TEMT) (Note 2)

Divisor Latch Access Bit (DLAB)

Error in RCVR FIFO (Note 5)

(THRE)

Trailing Edge Ring Indicator (TERI)

Bit 2

Bit 10

Delta Data Carrier Detect

Clear to Send

(CTS)

Data Set Ready (DSR)

Ring Indicator (RI)

(DDCD)

Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Bit 11 Bit 12 Bit 13 Bit 14 Bit 15

Data Carrier Detect (DCD)

Note 3: This bit no longer has a pin associated with it. Note 4: When operating in the XT mode, this register is not available. Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime

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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION:

GENERAL

The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.

TX AND RX FIFO OPERATION

The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled

as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx.

The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inactive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UARTs interrupt line would transition to the active state. This could cause a system with an interrupt control unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore,

after the first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have the Tx FIFO empties after this condition, the Tx been loaded into the FIFO, concurrently. When interrupt will be activated without a one character delay.

Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.

One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO. This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation the chip incorporates a timeout interrupt.

The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it.

These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256 kbaud).

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6.7 INFRARED INTERFACE

The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins or optional IRTX2 and IRRX2 pins. These can be selected through the configuration registers.

IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA waveform.

The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR waveform.

If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. IR Transmit Pins

The following description pertains to the IRTX and IRTX2 pins of the LPC47M14x.

Following a VTR POR, the IRTX and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met:IRTX2/GP35 Pin. This pin defaults to the IRTX2 function.

1) This pin will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.

2) This pin will remain low following a VCC POR until the GPIO output function is selected for the pin, at which time the pin will reflect the state of the GPIO data bit if it is configured as an output.

GP53/TXD2(IRTX) Pin. This pin defaults to the GPIO output function.

 This pin will remain low following a VCC POR until the TXD2 function is selected for the pin AND serial port 2 is

enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of serial port 2. Following a VCC POR, setting the TXD2_MODE bit (bit 5 in Serial Port 2 Mode Register, 0xF0 in Logical Device 5 Configuration Registers) to ‘1’ will change the state of the TXD2 pin from low to tristate, regardless of the function selected on the pin (GPIO of TXD2), regardless of the state of the activate bit for serial port 2 and regardless of the state of VCC. When VCC is removed from the part while the TXD2_MODE bit is set to ‘1’, the TXD2 pin will remain tristate unless a VTR POR occurs, which will reset the TXD2_MODE bit.

 This pin will remain low following a VCC POR until the corresponding GPIO data bit (GP5 register bit 3) is set or

the polarity bit in the GP53 control register is set.

The TXD2_MODE bit is implemented for modems that do not assert the ring indicator pin when TXD2 is sensed low. If required, this bit should be used as follows:

 When the activate bit for serial port 2 is cleared prior to entering a sleep state, set the TXD2_MODE bit.  When the activate bit for serial port 2 is set, upon exiting a sleep state clear the TXD2_MODE bit.  The IRTX2 pin is not affected by the TXD2_MODE bit.

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6.8 MPU-401 MIDI UART

6.8.1 Overview

Serial Port 3 is used exclusively in the LPC47M14x as an MPU-401-compatible MIDI Interface. The LPC47M14x MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a compatible UART (FIGURE 3).

Each of these components are discussed in detail, below. Only the MPU-401 UART (pass-through) mode is included in this implementation. MPU-401 UART mode is supported on the Sound Blaster 16 Series-compatible MIDI hardware. The Sound Blaster 16 hardware is supported by Microsoft Windows Operating Systems.

In MPU-401 UART mode, data is transferred without modification between the host and the MIDI device (UART). Once UART mode is entered using the UART MODE command (3Fh), the only MPU-401 command that the interface recognizes is RESET (FFh).

MPU-401

COMMAND

CONTROLLER

SA[15:0]

SD[7:0]

HOST

INTERFACE

UART

MIDI_OUT

MIDI_IN

nIOW

nIO

IRQ

FIGURE 3 – MPU-401 MIDI INTERFACE

Note: This figure is for illustration purposes only and is not intended to suggest specific implementation

details.

6.8.2 Host Interface Overview

The Host Interface includes two contiguous 8-bit run-time registers (the Status/Command Port and the Data Port), and an interrupt. For illustration purposes, the Host Interface block shown in FIGURE 3 uses standard ISA signaling. Address decoding and interrupt selection for the Host Interface are determined by device configuration registers (see Section “MPU-401Configuration Registers”).

I/O Addresses

The Sound Blaster 16 MPU-401 UART mode MIDI interface requires two consecutive I/O addresses with possible base I/O addresses of 300h and 330h. The default is 330h. The LPC47M14x MPU-401 I/O base address is programmable on even-byte boundaries throughout the entire I/O address range (see Section “Activate and I/O Base address”).

CONFIGURATION

REGISTERS

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Registers (Ports)

The run-time registers in the MPU-401 Host Interface are shown below in Table 34.

Table 34 – MPU-401 Host Interface Registers

MIDI DATA MPU-401 I/O Base Address R/W Used for MIDI transmit data, MIDI

receive data, and MPU-401 command acknowledge.

STATUS MPU-401 I/O Base Address + 1 R Used to indicate the send/receive status

of the MIDI Data port.

COMMAND MPU-401 I/O Base Address + 1 W Used for MPU-401 Commands.

6.8.3 MIDI Data Port

The MIDI Data port exchanges MIDI transmit and MIDI receive data between the MPU-401 UART interface and the host. The MIDI Data port is read/write (Table 35). The MIDI Data port is also used to return the command acknowledge byte ‘FEh’ following host writes to the COMMAND port.

The MIDI Data port is full-duplex; i.e., the transmit and receive buffers can be used simultaneously. An interrupt is generated when either MIDI receive data or a command acknowledge is available to the host in the MIDI Data register. See Section “Bit 7 – MIDI Receive Buffer Empty” and “Interrupt”

Table 35 – MIDI Data Port

D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT TYPE R/W R/W R/W R/W R/W R/W R/W R/W NAME

MIDI DATA/COMMAND-ACKNOWLEDGE REGISTER

MPU-401 I/O BASE ADDRESS

n/a

6.8.4 Status Port

The Status port is used to indicate the state of the transmit and receive buffers in the MIDI Data port. The Status port is read-only (Table 36). Status port Bit 6 is MIDI Transmit Busy, Bit 7 is MIDI Receive Buffer Empty. The remaining bits in the Status port are RESERVED.

Table 36 – MPU-401 Status Port

D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT TYPE R R R R R R R R BIT NAME

MIDI RX

BUFFE

MIDI TX BUSY

MPU-401 I/O BASE ADDRESS+1

0x80

0 0 0 0 0 0

EMPTY

Bit 7 – MIDI Receive Buffer Empty

Bit 7 MIDI Receive Buffer Empty indicates the read state of the MIDI Data port (Table 37). If the MRBE bit is ‘0’, MIDI Read/Command Acknowledge data is available to the host. If the MRBE bit is ‘1’, MIDI Read/Command Acknowledge data is NOT available to the host.

The MPU-401 Interrupt output is active ‘1’ when the MIDI Receive Buffer Empty bit is ‘0’. The MPU-401 Interrupt output is inactive ‘0’ when the MIDI Receive Buffer Empty bit is ‘1’. See Section “Interrupt” for more information.

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Table 37 – MIDI Receive Buffer Empty Status Bit

STATUS PORT DESCRIPTION

0 MIDI Read/Command Acknowledge data is

available to the host.

1 MIDI Read/Command Acknowledge data is

NOT available to the host.

Bit 6 – MIDI Transmit Busy

Bit 6 MIDI Transmit Busy indicates the send (write) state of the MIDI Data port and Command port (Table 38)

There are no interrupts associated with MIDI transmit (write) data.

Table 38 – MIDI Transmit Busy Status Bit

STATUS PORT DESCRIPTION

0 The MPU-401 interface is ready to accept a

data/command byte from the host.

The MPU-401 interface is NOT ready to accept a data/command byte from the host.

Bits[5:0] RESERVED (Reserved bits cannot be written and return ‘0’ when read).

Command Port

The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is writeonly (Table 39). See Section “MPU-401 Command controller” below.

Table 39 – MPU-401 Command Port

D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT TYPE W W W W W W W W NAME

COMMAND REGISTER

MPU-401 I/O BASE ADDRESS+1

n/a

Interrupt

The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is available tot he host in the MIDI data register (FIGURE 4). the IRQ is deasserted (‘0’) when the host reads the MIDI Data port.

Note: If, following a host read, data is still available in the 16C550A Receive FIFO, the IRQ will remain asserted (‘1’).

The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is asserted ‘1’. If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section “MPU-401 Configuration Registers”).

The MPU-401 IRQ is not affected by MIDI write data, 16C550A transmit-related functions or Receiver Line Status interrupts.

The factory default Sound Blaster 16 MPU-401 IRQ is 5.

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OTE: IRQ remains asserted

until read FIFO is empty

MIDI RX DATA BYTE N MIDI RX DATA BYTE N+1MIDI_IN

IRQ

nREAD

MIDI RX CLOCK

DATA READY

FIGURE 4 – MPU-401 INTERRUPT

Note

DATA READY represents the Data Ready bit B0 in the 16C550A UART Line Status Register.

nREAD represents host read operations from the MIDI Data register.

Note

Threshold=1.

Note

IRQ is the MPU-401 Host Interface IRQ shown in FIGURE 3. The 16C550A UART Receive FIFO

MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs.

6.8.5 MPU-401 Command Controller Overview

Commands are written by the host to the MPU-401 MIDI Interface through the Command register (Table 34) and are immediately interpreted by the MPU-401 Command Controller shown in FIGURE 3. The MPU-401 Command Controller in this implementation only responds to the MPU-401 RESET (FFh) and UART MODE (3Fh) commands. All other commands are ignored.

Under certain conditions, the Command Controller acknowledges MPU-401 commands with a command acknowledge byte (FEh).

RESET Command

The RESET command is FFh. The RESET command resets the MPU-401 MIDI Interface. Reset disables the MPU401 UART MODE command, disables the 16C550A UART, clears the receive FIFO. The command controller places the command acknowledge byte ‘FEh’ in the MIDI Data port read buffer if the interface is not in the UART mode.

The RESET command is executed but not acknowledged when the command is received while the interface is in the UART mode.

When the MPU-401 is reset, receive data from the MIDI_IN port as well as data written by the host to the MIDI Data port is ignored.

The MPU-401 MIDI Interface is reset following the RESET command or POR.

UART MODE Command

The UART MODE command is 3Fh. The UART MODE command clears the 16C550A transmit and receive FIFOs, places the command acknowledge byte (FEh) in the MIDI Data port receive buffer, and enables the 16C550A UART for transmit and receive operations.

In UART mode, the MPU-401 Interface passes MIDI read and write data directly between the host (using the MIDI Data port) and the 16C550A UART Transmit and Receive buffers.

The MPU-401 Command Controller ignores the UART MODE command when the MPU-401 Interface is already in UART mode.

The MPU-401 RESET command is executed but not acknowledged by the MPU-401 Command Controller in UART MODE (see Section “RESET Command”, above).

Command Acknowledge Byte

Under certain conditions, the command controller acknowledges the RESET and UART MODE commands with a command acknowledge byte (FEh).

The command acknowledge byte appears as read-data in the MIDI Data port.

Note: The command acknowledge byte will appear as the next available data byte in the receive buffer of the MIDI Data port. For example if the receive FIFO is not empty when an MPU-401 RESET command is received, the

SMSC DS – LPC47M14X Page 76 Rev. 03/19/2001

command acknowledge will appear first, before any unread FIFO data. In the examples above, the receive FIFO is cleared before the command acknowledge byte is placed in the MIDI Data port read buffer.

6.8.6 MIDI UART Overview

The UART is used to transmit and receive MIDI protocol data from the MIDI Data port in the Host Interface (see Section “Host Interface”).

The MIDI protocol requires 31.25k Baud (±1%) and 10 bits total per frame: 1 start bit, 8 data bits, no parity, and 1 stop bit. For example, there are 320 microseconds per serial MIDI data byte. MIDI data is transferred LSB first (Figure 7).

The UART is configured in full-duplex mode for the MPU-401 MIDI Interface, with 16-byte send/receive FIFOs.

MIDI RX DATA BYTE (01H)

MIDI RX CLOCK

MIDI_IN

FIGURE 5 - MIDI DATA BYTE EXAMPLE

Note

: MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32µs.

6.8.7 MPU-401 Configuration Registers

The LPC47M14x configuration registers are in Logical Device B (see “Configuration” section). The configuration registers contain the MPU-401 Activate, Base Address and Interrupt select. The defaults for the Base Address and Interrupt Select configuration registers match the MPU-401 factory defaults.

Activate and I/O Base Address

When the Activate bit D0 is ‘0’, the MPU-401 I/O base address decoder is disabled, the IRQ is always deasserted, and the MPU-401 hardware is in a minimum power-consumption state. When the Activate bit is ‘1’, the MPU-401 I/O base address decoder and the IRQ are enabled, and the MPU-401 hardware is fully powered.

Register 0x60 is the MPU-401 I/O Base Address High Byte, register 0x61 is the MPU-401 I/O Base Address Low Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The valid MPU-401 I/O base address range is 0x0100 – 0x0FFE. See Section “Host Interface”.

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6.9 PARALLEL PORT

The LPC47M14x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation.

The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up.

The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below:

DATA PORT BASE ADDRESS + 00H STATUS PORT BASE ADDRESS + 01H CONTROL PORT BASE ADDRESS + 02H EPP ADDR PORT BASE ADDRESS + 03H

The bit map of these registers is:

DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1

STATUS PORT

CONTROL PORT

EPP ADDR PORT

EPP DATA PORT 0

EPP DATA PORT 1

EPP DATA PORT 2

EPP DATA PORT 3

Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode.

D0 D1 D2 D3 D4 D5 D6 D7 NOTE

TMOUT 0 0 nERR SLCT PE nACK nBUSY 1

STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2

EPP DATA PORT 0 BASE ADDRESS + 04H EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H

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Table 40 – Parallel Port Connector

HOST

CONNECTOR PIN NUMBER

STANDARD

EPP

ECP

1 83 nStrobe nWrite nStrobe

2-9 68-75 PData<0:7> PData<0:7> PData<0:7>

10 80 nAck Intr nAck

11 79 Busy nWait Busy, PeriphAck(3)

12 78 PE (User Defined) PError,

nAckReverse (3)

13 77 Select (User Defined) Select

14 82 nAutoFd nDatastb nAutoFd,

HostAck(3)

15 81 nError (User Defined) nFault (1)

nPeriphRequest (3)

16 66 nInit nRESET nInit(1)

nReverseRqst(3)

17 67 nSelectIn nAddrstrb nSelectIn(1,3)

(1) = Compatible Mode (3) = High Speed Mode

Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the

IEEE 1284 Extended Capabilities Port Protocol and ISA Standard

, Rev. 1.14, July 14, 1993. This document is

available from Microsoft.

6.9.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes

DATA PORT ADDRESS OFFSET = 00H

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.

STATUS PORT ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the duration of a read cycle. The bits of the Status Port are defined as follows:

BIT 0 TMOUT - TIME OUT This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is ‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.

BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.

BIT 3 nERR – nERROR

The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has been detected.

BIT 4 SLCT - PRINTER SELECTED STATUS The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on line; a logic 0 means it is not selected.

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BIT 5 PE - PAPER END The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a logic 0 indicates the presence of paper.

BIT 6 nACK - ACKNOWLEDGE The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer has received a character and can now accept another. A logic 1 means that it is still processing the last character or has not received the data.

BIT 7 nBUSY - nBUSY The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the next character.

CONTROL PORT ADDRESS OFFSET = 02H

The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.

BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.

BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINIT output without inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is programmed low the IRQ is disabled.

BIT 5 PCD - PARALLEL CONTROL DIRECTION Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read).

Bits 6 and 7 during a read are a low level, and cannot be written.

EPP ADDRESS PORT ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of '03H' from the base address. The address register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.

EPP DATA PORT 0 ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of '04H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.

SMSC DS – LPC47M14X Page 80 Rev. 03/19/2001

EPP DATA PORT 1 ADDRESS OFFSET = 05H

The EPP Data Port 1 is located at an offset of '05H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP DATA PORT 2 ADDRESS OFFSET = 06H

The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP DATA PORT 3 ADDRESS OFFSET = 07H

The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode.

EPP 1.9 OPERATION When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.

During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write mode and the nWRITE signal to always be asserted.

Software Constraints

Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic "0" (i.e., a 04H or 05H should be written to the Control port). If the user leaves PCD as a logic "1", and attempts to perform an EPP write, the chip is unable to perform the write (because PCD is a logic "1") and will appear to perform an EPP read on the parallel bus, no error is indicated.

EPP 1.9 Write

The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write cycle can complete under the following circumstances:

1) If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high.

2) If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.

Write Sequence of Operation

1) The host initiates an I/O write cycle to the selected EPP register.

2) If WAIT is not asserted, the chip must wait until WAIT is asserted.

3) The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.

4) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.

5) Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle.

6) a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it

has not already done so, the peripheral should latch the information byte now.

b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates

that no more wait states are required followed by the TAR to complete the write cycle.

7) Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle.

8) Chip may modify nWRITE and nPDATA in preparation for the next cycle.

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EPP 1.9 Read The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under the following circumstances:

1) If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when nWAIT goes inactive high.

2) If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.

Read Sequence of Operation

1) The host initiates an I/O read cycle to the selected EPP register.

2) If WAIT is not asserted, the chip must wait until WAIT is asserted.

3) The chip tri-states the PData bus and deasserts nWRITE.

4) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid.

5) Peripheral drives PData bus valid.

6) Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle.

7) a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nADDRSTRB. This marks the beginning of the termination phase.

b) The chip drives the sync that indicates that no more wait states are required and drives the valid data onto

the LAD[3:0] signals, followed by the TAR to complete the read cycle.

8) Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated.

9) Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.

EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bidirectional mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD of the Control port.

In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.

Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD) is a logic "0" for an EPP write or a logic "1" for and EPP read.

EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high.

Write Sequence of Operation

1) The host sets PDIR bit in the control register to a logic "0". This asserts nWRITE.

2) The host initiates an I/O write cycle to the selected EPP register.

3) The chip places address or data on PData bus.

4) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE signal is valid.

5) If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-out occurs.

6) The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data bus for the PData bus.

7) Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

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EPP 1.7 Read The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read cycle can complete when nWAIT is inactive high.

Read Sequence of Operation

1) The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the PData bus.

2) The host initiates an I/O read cycle to the selected EPP register.

3) Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE signal is valid.

4) If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a time-out occurs.

5) The Peripheral drives PData bus valid.

6) The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle.

7) The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.

8) Peripheral tri-states the PData bus.

9) Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.

Table 41 – EPP Pin Descriptions

EPP

SIGNAL EPP NAME TYPE

EPP DESCRIPTION

nWRITE nWrite O This signal is active low. It denotes a write operation.

PD<0:7> Address/Data I/O Bi-directional EPP byte wide address and data bus.

INTR Interrupt I This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP).

nWAIT nWait I This signal is active low. It is driven inactive as a positive

acknowledgement from the device that the transfer of data is completed. It is driven active as an indication that the device is ready for the next transfer.

nDATASTB nData Strobe O This signal is active low. It is used to denote data read or write

operation.

nRESET nReset O This signal is active low. When driven active, the EPP device

is reset to its initial operational mode.

nADDRSTB Address

Strobe

O This signal is active low. It is used to denote address read or

write operation.

PE Paper End I Same as SPP mode.

SLCT Printer

I Same as SPP mode. Selected Status

nERR Error I Same as SPP mode.

Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct

EPP read cycles, PCD is required to be a low.

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6.9.2 Extended Capabilities Parallel Port

ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section.

High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer capability.

Vocabulary The following terms are used in this document:

assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false"

state.

forward: Host to Peripheral communication. reverse: Peripheral to Host communication Pword: A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always

8 bits. 1 A high level. 0 A low level.

These terms may be considered synonymous:

 PeriphClk, nAck  HostAck, nAutoFd  PeriphAck, Busy  nPeriphRequest, nFault  nReverseRequest, nInit  nAckReverse, PError  Xflag, Select  ECPMode, nSelectln  HostClk, nStrobe

Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard

, Rev 1.14, July 14,

1993. This document is available from Microsoft.

The bit map of the Extended Parallel Port registers is:

D7 D6 D5 D4 D3 D2 D1 D0 NOTE

data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

ecpAFifo Addr/RLE Address or RLE field 2

dsr nBusy nAck PError Select nFault 0 0 0 1

dcr 0 0 Direction ackIntEn SelectI

nInit autofd strobe 1

cFifo Parallel Port Data FIFO 2

ecpDFifo ECP Data FIFO 2

tFifo Test FIFO 2

cnfgA 0 0 0 1 0 0 0 0

cnfgB compress intrValue Parallel Port IRQ Parallel Port DMA

ecr MODE nErrIntrEn dmaEn serviceIntr full empty

Note 1: These registers are available in all modes. Note 2: All FIFOs use one common 16 byte FIFO. Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration

Registers.

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ECP IMPLEMENTATION STANDARD This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.

Description The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional.

Table 42 – ECP Pin Descriptions

NAME TYPE DESCRIPTION

nStrobe O During write operations nStrobe registers data or address into the slave on

the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the peripheral when asserted. This signal

handshakes with nAutoFd in reverse. PeriphAck (Busy) I This signal deasserts to indicate that the peripheral can accept data. This

signal handshakes with nStrobe in the forward direction. In the reverse

direction this signal indicates whether the data lines contain ECP

command information or data. The peripheral uses this signal to flow

control in the forward direction. It is an "interlocked" handshake with

nStrobe. PeriphAck also provides command information in the reverse

direction. PError (nAckReverse)

I Used to acknowledge a change in the direction the transfer (asserted =

forward). The peripheral drives this signal low to acknowledge

nReverseRequest. It is an "interlocked" handshake with nReverseRequest.

The host relies upon nAckReverse to determine when it is permitted to

drive the data bus. Select I Indicates printer on line. nAutoFd (HostAck)

O Requests a byte of data from the peripheral when asserted, handshaking

with nAck in the reverse direction. In the forward direction this signal

indicates whether the data lines contain ECP address or data. The host

drives this signal to flow control in the reverse direction. It is an

"interlocked" handshake with nAck. HostAck also provides command

information in the forward phase. nFault (nPeriphRequest)

I Generates an error interrupt when asserted. This signal provides a

mechanism for peer-to-peer communication. This signal is valid only in the

forward direction. During ECP Mode the peripheral is permitted (but not

required) to drive this pin low to request a reverse transfer. The request is

merely a "hint" to the host; the host has ultimate control over the transfer

direction. This signal would be typically used to generate an interrupt to

the host CPU. nInit O Sets the transfer direction (asserted = reverse, deasserted = forward).

This pin is driven low to place the channel in the reverse direction. The

peripheral is only allowed to drive the bi-directional data bus while in ECP

Mode and HostAck is low and nSelectIn is high. nSelectIn O Always deasserted in ECP mode.

SMSC DS – LPC47M14X Page 85 Rev. 03/19/2001

Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on the mode field in the ecr. The table below lists these dependencies. Operation of the devices in modes other that those specified is undefined.

Table 43 – ECP Register Definitions

NAME ADDRESS (Note 1) ECP MODES FUNCTION

data +000h R/W 000-001 Data Register

ecpAFifo +000h R/W 011 ECP FIFO (Address)

dsr +001h R/W All Status Register

dcr +002h R/W All Control Register

cFifo +400h R/W 010 Parallel Port Data FIFO

ecpDFifo +400h R/W 011 ECP FIFO (DATA)

tFifo +400h R/W 110 Test FIFO

cnfgA +400h R 111 Configuration Register A

cnfgB +401h R/W 111 Configuration Register B

ecr +402h R/W All Extended Control Register

Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers. Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

Table 44 – Mode Descriptions

MODE DESCRIPTION*

000 SPP mode

001 PS/2 Parallel Port mode

010 Parallel Port Data FIFO mode

011 ECP Parallel Port mode

100 EPP mode (If this option is enabled in the configuration registers)

101 Reserved

110 Test mode

111 Configuration mode

*Refer to ECR Register Description

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DATA and ECPAFIFO PORT ADDRESS OFFSET = 00H

Modes 000 and 001 (Data Port)

The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read and output to the host CPU.

Mode 011 (ECP FIFO - Address/RLE)

A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet .

DEVICE STATUS REGISTER (DSR) ADDRESS OFFSET = 01H

The Status Port is located at an offset of '01H' from the base address. Bits 0 - 2 are not implemented as register bits, during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows:

BIT 3 nFault The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.

BIT 4 Select The level on the Select input is read by the CPU as bit 4 of the Device Status Register.

BIT 5 PError The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register.

BIT 6 nAck The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.

BIT 7 nBusy The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.

DEVICE CONTROL REGISTER (DCR) ADDRESS OFFSET = 02H

The Control Register is located at an offset of '02H' from the base address. The Control Register is initialized to zero by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.

BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each line is printed. A logic 0 means no autofeed.

BIT 2 nINIT - INITIATE OUTPUT This bit is output onto the nINIT output without inversion.

BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected.

BIT 4 ACKINTEN - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts.

BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read).

SMSC DS – LPC47M14X Page 87 Rev. 03/19/2001

BITS 6 and 7 during a read are a low level, and cannot be written.

CFIFO (Parallel Port Data FIFO) ADDRESS OFFSET = 400h

Mode = 010

Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward direction.

ECPDFIFO (ECP Data FIFO) ADDRESS OFFSET = 400H

Mode = 011

Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.

Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direction bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.

TFIFO (Test FIFO Mode) ADDRESS OFFSET = 400H

Mode = 110

Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be displayed on the parallel port data lines.

The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics.

The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and serviceIntr bits.

The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.

The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.

Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.

CNFGA (Configuration Register A) ADDRESS OFFSET = 400H

Mode = 111

This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte)

CNFGB (Configuration Register B) ADDRESS OFFSET = 401H

Mode = 111

BIT 7 Compress

This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression.

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BIT 6 intrValue Returns the value of the interrupt to determine possible conflicts.

BIT [5:3] Parallel Port IRQ (read-only)

to Table 45B

BITS [2:0] Parallel Port DMA (read-only)

to Table 45C

ECR (Extended Control Register) ADDRESS OFFSET = 402H

Mode = all

This register controls the extended ECP parallel port functions.

BITS 7,6,5

These bits are Read/Write and select the Mode.

BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is

asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr.

BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is 0). 0: Disables DMA unconditionally.

BIT 2 serviceIntr Read/Write 1: Disables DMA and all of the service interrupts. 0: Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr bit

shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not cause an interrupt.

case dmaEn=1: During DMA (this bit is set to a 1 when terminal count is reached).

case dmaEn=0 direction=0: This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.

case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.

BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte.

BIT 0 empty Read only 1: The FIFO is completely empty. 0: The FIFO contains at least 1 byte of data.

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Table 45a – Extended Control Register

R/W MODE

000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are

used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in this mode.

001: PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the

data lines and reading the data register returns the value on the data lines and not the value in the data register. All drivers have active pull-ups (push-pull).

010: Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the

FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull).

011: ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo

and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull).

100: Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in

configuration register L3-CRF0. All drivers have active pull-ups (push-pull).

101: Reserved

110: Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted

on the parallel port. All drivers have active pull-ups (push-pull).

111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and

0x401. All drivers have active pull-ups (push-pull).

Table 45B Table 45C

IRQ SELECTED

CONFIG REG B

BITS 5:3

CONFIG REG B

DMA

BITS 2:0

SELECTED

15 110

14 101

11 100

10 011

9 010

7 001

5 111

3 011

2 010

1 001

All Others 000

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OPERATION

Mode Switching/Software Control

Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (modes 011 or 010).

Setting the mode to 011 or 010 will cause the hardware to initiate data transfer.

If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. The direction can only be changed in mode 001.

Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake signals if the software meets the constraints above.

ECP Operation

Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000.

After negotiation, it is necessary to initialize some of the port bits. The following are required:

Set Direction = 0, enabling the drivers. Set strobe = 0, causing the nStrobe signal to default to the deasserted state. Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state. Set mode = 011 (ECP Mode)

ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively.

Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed in the forward direction.

The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty.

ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000.

Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.

Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 bit commands.

When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low.

The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address.

When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom used and may not be supported in hardware.

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Table 46 – Channel/Data Commands supported in ECP mode

Forward Channel Commands (HostAck Low)

Reverse Channel Commands (PeripAck Low)

D7 D[6:0]

0 Run-Length Count (0-127)

(mode 0011 0X00 only)

1 Channel Address (0-127)

Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.

Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.

Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes.

LPC Connections

The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide transfers are always possible with standard or PS/2 mode using program control of the control signals.

Interrupts The interrupts are enabled by serviceIntr in the ecr register.

serviceIntr = 1 Disables the DMA and all of the service interrupts.

serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is

generated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the number of bytes removed or added from/to the FIFO does not cross the threshold.

An interrupt is generated when:

1) For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.

2) For Programmed I/O: a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the

FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or more free bytes in the FIFO.

b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO.

Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO.

3) When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted.

4) When ackIntEn is 1 and the nAck signal transitions from a low to a high.

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FIFO Operation The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of DMA or Programmed I/O mode.

The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.

A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests.

DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received. (Note: The only way to properly terminate DMA transfers is with a TC cycle.)

DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.

DMA Mode - Transfers from the FIFO to the Host (Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.)

The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and serviceIntr has been re-enabled.

Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.

Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0.

The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.

Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.

Programmed I/O - Transfers from the FIFO to the Host

In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be read from the FIFO in a single burst.

readIntrThreshold =(16-<threshold>) data bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of

SMSC DS – LPC47M14X Page 93 Rev. 03/19/2001

the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16<threshold>) bytes may be read from the FIFO in a single burst.

Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.

writeIntrThreshold = (16-<threshold>) free bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO.

6.10 POWER MANAGEMENT

Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown.

FDC Power Management Direct power management is controlled by CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the following conditions have been met:

1) The motor enable pins of register 3F2H are inactive (zero).

2) The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts).

3) The head unload timer must have expired.

4) The Auto powerdown timer (10msec) must have timed out.

An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down when all the conditions are met.

Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown.

Note: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the internal microcontroller can prepare itself to accept commands.

DSR From Powerdown If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again become effective.

Wake Up From Auto Powerdown If the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers.

If a hardware or software reset is used then the part will go through the normal reset sequence. If the access is through the selected registers, then the FDC resumes operation as though it was never in powerdown. Besides activating the PCI_RESET# pin or one of the software reset bits in the DOR or DSR, the following register accesses will wake up the part:

1) Enabling any one of the motor enable bits in the DOR register (reading the DOR does not awaken the part).

2) A read from the MSR register.

3) A read or write to the Data register.

Once awake, the FDC will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied.

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Table 47 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 47 shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown state or exiting it.

Access to all other registers is possible without awakening the part. These registers can be accessed during powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in the register description in the FDC description. A write to the part will result in the part retaining the data and subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the power consumption by the part. The part will revert back to its low power mode when the access has been completed.

Pin Behavior The LPC47M14x is specifically designed for systems in which power conservation is a primary concern. This makes the behavior of the pins during powerdown very important.

The pins of the LPC47M14x can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system accesses that may wake up the part.

Table 47 – PC/AT and PS/2 Available Registers

AVAILABLE REGISTERS

BASE + ADDRESS PC-AT PS/2 (MODEL 30) ACCESS PERMITTED

Access to these registers DOES NOT wake up the part

00H ---- SRA R

01H ---- SRB R

02H DOR (1) DOR (1) R/W

03H --- --- ---

04H DSR (1) DSR (1) W

06H --- --- ---

07H DIR DIR R

07H CCR CCR W

Access to these registers wakes up the part

04H MSR MSR R

05H Data Data R/W

Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable bits or doing a

software reset (via DOR or DSR reset bits) will wake up the part.

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System Interface Pins

Table 48 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged.”

Table 48 – State of System Pins in Auto Powerdown

SYSTEM PINS STATE IN AUTO POWERDOWN

LAD[3:0] Unchanged

LDRQ# Unchanged

LPCPD# Unchanged

LFRAME# Unchanged

PCI_RESET# Unchanged

PCI_CLK Unchanged

SER_IRQ Unchanged

FDD Interface Pins

All pins in the FDD interface, which can be connected directly to the floppy disk drive itself, are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 49 depicts the state of the floppy disk drive interface pins in the powerdown state.

Table 49 – State of Floppy Disk Drive Interface Pins in Powerdown

FDD PINS STATE IN AUTO POWERDOWN

INPUT PINS

nRDATA Input

nWRTPRT Input

nTRK0 Input

nINDEX Input

nDSKCHG Input

OUTPUT PINS

nMTR0 Tristated

nDS0 Tristated

nDIR Active

nSTEP Active

nWDATA Tristated

nWGATE Tristated

nHDSEL Active

DRVDEN[0:1] Active

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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations:

1) The transmitter enters auto powerdown when the transmit buffer and shift register are empty.

2) The receiver enters powerdown when the following conditions are all met:

a) Receive FIFO is empty b) The receiver is waiting for a start bit.

Note: While in powerdown the Ring Indicator interrupt is still valid and transitions when the RI input changes.

Exit Auto Powerdown

The transmitter exits powerdown on a write to the XMIT buffer. The receiver exits auto powerdown when RXDx changes state.

Parallel Port Direct power management is controlled by CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used.

The EPP logic is in powerdown under any of the following conditions:

1) EPP is not enabled in the configuration registers.

2) EPP is not selected through ecr while in ECP mode.

The ECP logic is in powerdown under any of the following conditions:

1) ECP is not enabled in the configuration registers.

2) SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode.

Exit Auto Powerdown The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers.

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6.11 SERIAL IRQ

The LPC47M14x supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.

Timing Diagrams For SER_IRQ Cycle

A) Start Frame timing with source sampled a low pulse on IRQ1

START FRAME

RTSRT S

IRQ0 FRAME IRQ1 FRAME

IRQ2 FRAME

S RT

PCI_CLK

SER_IRQ

Drive Source

Note: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge

hierarchy in a synchronous bridge design.

B) Stop Frame Timing with Host using 17 SER_IRQ sampling period

IRQ1

START

IRQ14 IRQ15

FRAME

S RTS

Host Controller

None

IOCHCK#

FRAMEFRAME

S RT

STOP FRAME

IRQ1

None

NEXT CYCLE

PCI_CLK

SER_IRQ

Driver

Note: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle Note 1: The next SER_IRQ cycle’s Start Frame pulse may

of the Stop Frame.

Note 2: There may be none, one or more Idle states during the Stop Frame. Note 3: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.

None

or may not start immediately after the turn-around clock

STOP

Host ControllerIRQ15

START

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SER_IRQ Cycle Control

There are two modes of operation for the SER_IRQ Start Frame.

1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.

Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state. Any SER_IRQ Device (i.e., The LPC47M14x) which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle.

2) Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every Stop Frame.

An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to

Continuous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode.

SER_IRQ Data Frame

Once a Start Frame has been initiated, the LPC47M14x will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. During the Sample phase the LPC47M14x must drive the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SER_IRQ must be left tri-stated. During the Recovery phase the LPC47M14x must drive the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-around Phase the LPC47M14x must tri-state the SER_IRQ. The LPC47M14x will drive the SER_IRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initiated the Start Frame.

The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3) - 1 = 17th clock after the rising edge of the Start Pulse).

SER_IRQ Sampling Periods

SER_IRQ PERIOD SIGNAL SAMPLED # OF CLOCKS PAST START

1 Not Used 2 2 IRQ1 5 3 nIO_SMI/IRQ2 8 4 IRQ3 11 5 IRQ4 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23

9 IRQ8 26 10 IRQ9 29 11 IRQ10 32 12 IRQ11 35 13 IRQ12 38 14 IRQ13 41 15 IRQ14 44 16 IRQ15 47

SMSC DS – LPC47M14X Page 99 Rev. 03/19/2001

The SER_IRQ data frame will now support IRQ2 from a logical device, previously SER_IRQ Period 3 was reserved for use by the System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2.

SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 0 (FDC), 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), and 7 (KBD) shall have IRQ13 as a choice for their primary interrupt.

The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the SMI pin via bit 7 of the SMI Enable Register 2.

Stop Cycle Control

Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is the Continuos mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse.

Latency

Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84µS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.

EOI/ISR Read Latency

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of order.

AC/DC Specification Issue

All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained tri-state.

Reset and Initialization

The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller’s responsibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (IDLE) mode first. This is to guarantee SER_IRQ bus is in IDLE state before the system configuration changes.

SMSC DS – LPC47M14X Page 100 Rev. 03/19/2001

SMSC LPC47M14x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual