SMSC LPC47M14x Technical data

128 Pin Enhanced Super I/O Controller

with an LPC Interface and USB Hub

 3.3 Volt Operation (5 Volt Tolerant)  LPC Interface  ACPI 1.0 Compliant  Fan Control

- Fan Speed Control Outputs

- Fan Tachometer Inputs

 Programmable Wake-up Event Interface  PC98, PC99 Compliant  Dual Game Port Interface  MPU-401 MIDI Support  General Purpose Input/Output Pins  ISA Plug-and-Play Compatible Register Set  Intelligent Auto Power Management  System Management Interrupt  2.88MB Super I/O Floppy Disk Controller

- Licensed CMOS 765B Floppy Disk Controller

- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core

- Supports Two Floppy Drives

- Configurable Open Drain/Push-Pull Output Drivers

- Supports Vertical Recording Format

- 16-Byte Data FIFO

- 100% IBM Compatibility

- Detects All Overrun and Underrun Conditions

- Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption

- DMA Enable Logic

- Data Rate and Drive Control Registers

- 480 Address, Up to Eight IRQ and Four DMA Options

 Enhanced Digital Data Separator

- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates

- Programmable Precompensation Modes

FEATURES

 Keyboard Controller

 Serial Ports

 Infrared Port

 Multi-Mode Parallel Port with ChiProtect

LPC47M14x

PRELIMINAR

- 8042 Software Compatible

- 8 Bit Microcomputer

- 2k Bytes of Program ROM

- 256 Bytes of Data RAM

- Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface

- Asynchronous Access to Two Data Registers and One Status Register

- Supports Interrupt and Polling Access

- 8 Bit Counter Timer

- Port 92 Support

- Fast Gate A20 and KRESET Outputs

- Two Full Function Serial Ports

- High Speed NS16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs

- Supports 230k and 460k Baud

Programmable Baud Rate Generator Modem Control Circuitry

- 480 Address and 15 IRQ Options

- Multiprotocol Infrared Interface

- IrDA 1.0 Compliant

- SHARP ASK IR

- 480 Addresses, Up to 15 IRQ

- Standard Mode IBM PC/XT, PS/2 Compatible Bi-directional Parallel Port

- Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)

- IEEE 1284 Compliant Enhanced Capabilities Port (ECP)

- ChiProtect Circuitry for Protection

- 960 Address, Up to 15 IRQ and Four DMA Options

PC/AT, and

SMSC DS – LPC47M14X Rev. 03/19/2001

 USB Hub

- 1 Upstream and up to 4 Downstream Ports

- Compliant with USB Spec. version 1.1

- Programmable USB Manufacturer ID, Product ID and Device Rev. Number

- Number of active ports programmable or selectable via jumpers

- Powered by Vtr for Downstream Port Wakeup

 LPC Interface

- Multiplexed Command, Address and Data Bus

- Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems

- PME Interface

 Interrupt Generating Registers

- Registers Generate IRQ1 – 15 on Serial IRQ Interface

ORDERING INFORMATION

Order Number: LPC47M14x – NC

128 Pin QFP Packa

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

80 Arkay Drive

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

SMSC DS – LPC47M14X Page 2 Rev. 03/19/2001

GENERAL DESCRIPTION

The LPC47M14x* is a 3.3V (5V tolerant) PC99 compliant Super I/O controller with an LPC interface and a standalone USB hub. It is designed to be compatible with a family of Super I/O Controllers (LPC47M13x, LPC47M14x, and LPC47M15x). To the interested reader, the LPC47M15x offers hardware monitoring capabilities. The first one hundred pins of all these packages are completely pin compatible and offer the designer added flexibility in their board designs. In addition, any board designed to support the LPC47M14x will automatically offer the dual capability of supporting the LPC47M13x, as well.

The LPC47M14x implements the LPC interface, a pin reduced ISA bus interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. This interface makes use of the PCI clock, which runs at 33MHz instead of the traditional 8MHz for the ISA bus, that eases some complications found in synchronous designs. In addition, all legacy drivers used for Super I/O components are still supported making this new interface transparent to the supporting software. The LPC bus also supports power management, such as wake-up and sleep modes, in the same way as the PCI bus.

The LPC47M14X incorporates a standalone USB Hub, implementing one upstream port and up to four (4) downstream ports, with an internal data path connection for programming the USB Vendor ID, Product ID and Device Revision Number. The number of active downstream ports is also programmable or selectable with external jumpers. This programming is done by BIOS accessing the hub control registers.

The LPC47M14x has incorporated the following Super I/O components: a parallel port that is compatible with IBM PC/AT architecture, as well as the IEEE 1284 EPP and ECP; two serial ports that are 16C550A UART compatible; a keyboard/mouse controller that uses an 8042 microcontroller; two floppy controllers, which use SMSC's true CMOS 765B core; two infrared ports that are IrDA 1.0 compliant; a MIDI interface, which is a MPU-401-compatible; and 37 General Purpose I/O control functions, which offer flexibility to the system designer. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register compatible with the 82077AA. This chip also controls two LED’s, a dual game port interface, and the speed of two fans with fan tachometer inputs through the use of a pulse width modulation scheme.

The LPC47M14x is ACPI 1.0 compatible and therefore supports multiple low power-down modes. It incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events.

The LPC47M14X supports the ISA Plug-and-Play Standard (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M14X may be reprogrammed through the internal configuration registers. There are 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and four DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface.

The LPC47M14X does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area.

* The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip.

SMSC DS – LPC47M14X Page 3 Rev. 03/19/2001

TABLE OF CONTENTS

1 PIN LAYOUT ..........................................................................................................................................................8

2 PIN CONFIGURATION...........................................................................................................................................9

3 DESCRIPTION OF PIN FUNCTIONS...................................................................................................................10

3.1 B

3.2 P

4 BLOCK DIAGRAM ............................................................................................................................................... 16

5 POWER FUNCTIONALITY...................................................................................................................................17

5.1 VCC POWER..................................................................................................................................................17

5.2 USB POWER.................................................................................................................................................. 17

5.3 VTR S

5.4 VREF P

5.5 I

5.6 32.768

5.7 T

5.8 M

5.9 P

6 FUNCTIONAL DESCRIPTION .............................................................................................................................20

6.1 S

6.2 H

6.3 LPC I

6.4 USB H

6.5 FLOPPY DISK CONTROLLER .................................................................................................................... 26

6.6 SERIAL PORT (UART) ................................................................................................................................60

6.7 INFRARED INTERFACE..............................................................................................................................72

6.8 MPU-401 MIDI UART................................................................................................................................... 73

6.9 PARALLEL PORT ........................................................................................................................................78

6.10 POWER MANAGEMENT............................................................................................................................. 94

6.11 SERIAL IRQ ................................................................................................................................................. 98

6.12 INTERRUPT GENERATING REGISTERS..............................................................................................................101

6.13 8042 KEYBOARD CONTROLLER DESCRIPTION ...................................................................................102

UFFER TYPE DESCRIPTIONS........................................................................................................................... 14

INS THAT REQUIRE EXTERNAL PULLUP RESISTORS ..........................................................................................15

5.1.1 3 Volt Operation / 5 Volt Tolerance......................................................................................................... 17

UPPORT ............................................................................................................................................... 17

IN .....................................................................................................................................................17

NTERNAL PWRGOOD ...................................................................................................................................18

KHZ TRICKLE CLOCK INPUT ..................................................................................................................18

RICKLE POWER FUNCTIONALITY...................................................................................................................... 18

AXIMUM CURRENT VALUES............................................................................................................................19

OWER MANAGEMENT EVENTS (PME/SCI) ......................................................................................................19

UPER I/O REGISTERS....................................................................................................................................20

OST PROCESSOR INTERFACE (LPC) ............................................................................................................... 20

NTERFACE .............................................................................................................................................21

6.3.1 LPC Interface Signal Definition...............................................................................................................21

6.3.2 LPC Cycles.............................................................................................................................................21

6.3.3 Field Definitions ......................................................................................................................................21

6.3.4 LFRAME# Usage.................................................................................................................................... 21

6.3.5 I/O Read and Write Cycles .....................................................................................................................22

6.3.6 DMA Read and Write Cycles ..................................................................................................................22

6.3.7 DMA Protocol .........................................................................................................................................22

6.3.8 Power Management................................................................................................................................22

6.3.9 SYNC Protocol .......................................................................................................................................22

6.3.10 LPC Transfer ..........................................................................................................................................23

UB FUNCTIONAL DESCRIPTION ...............................................................................................................24

6.4.1 USB Downstream Port Selection............................................................................................................25

6.5.1 FDC Internal Registers ...........................................................................................................................27

6.5.2 STATUS REGISTER ENCODING..........................................................................................................37

6.5.3 Instruction Set......................................................................................................................................... 43

6.5.4 DATA TRANSFER COMMANDS............................................................................................................50

6.8.1 Overview.................................................................................................................................................73

6.8.2 Host Interface .........................................................................................................................................73

6.8.3 MIDI Data Port........................................................................................................................................74

6.8.4 Status Port..............................................................................................................................................74

6.8.5 MPU-401 Command Controller ..............................................................................................................76

6.8.6 MIDI UART .............................................................................................................................................77

6.8.7 MPU-401 Configuration Registers ..........................................................................................................77

6.9.1 IBM XT/AT Compatible, Bi-Directional and EPP Modes ......................................................................... 79

6.9.2 Extended Capabilities Parallel Port.........................................................................................................84

6.13.1 Keyboard Interface ...............................................................................................................................103

6.13.2 External Keyboard and Mouse Interface...............................................................................................104

6.13.3 Keyboard Power Management ............................................................................................................. 104

6.13.4 Interrupts ..............................................................................................................................................104

6.13.5 Memory Configurations.........................................................................................................................104

6.13.6 Register Definitions...............................................................................................................................105

SMSC DS – LPC47M14X Page 4 Rev. 03/19/2001

6.13.7 External Clock Signal............................................................................................................................105

6.13.8 Default Reset Conditions ...................................................................................................................... 105

6.13.9 Latches On Keyboard and Mouse IRQs ...............................................................................................108

6.13.10 Keyboard and Mouse PME Generation ................................................................................................ 109

6.14 GENERAL PURPOSE I/O..........................................................................................................................110

6.14.1 GPIO Pins.............................................................................................................................................110

6.14.2 Description............................................................................................................................................111

6.14.3 GPIO Control ........................................................................................................................................ 112

6.14.4 GPIO Operation....................................................................................................................................112

6.14.5 GPIO PME and SMI Functionality......................................................................................................... 113

6.14.6 Either Edge Triggered Interrupts...........................................................................................................114

6.14.7 LED Functionality..................................................................................................................................115

6.15 SYSTEM MANAGEMENT INTERRUPT (SMI)...........................................................................................115

6.15.1 SMI Registers .......................................................................................................................................115

6.16 PME SUPPORT.........................................................................................................................................116

6.16.1 ‘Wake on Specific Key’ Option..............................................................................................................117

6.17 FAN SPEED CONTROL AND MONITORING............................................................................................118

6.17.1 Fan Speed Control................................................................................................................................118

6.17.2 Fan Tachometer Inputs.........................................................................................................................119

6.18 SECURITY FEATURE ...............................................................................................................................122

6.18.1 GPIO Device Disable Register Control ................................................................................................. 122

6.18.2 Device Disable Register .......................................................................................................................122

6.19 GAME PORT LOGIC..................................................................................................................................122

6.19.1 Power Control Register.........................................................................................................................124

6.19.2 VREF Pin..............................................................................................................................................124

7 RUNTIME REGISTERS......................................................................................................................................125

8 CONFIGURATION..............................................................................................................................................152

9 OPERATIONAL DESCRIPTION ........................................................................................................................172

9.1 M

9.2 DC E

AXIMUM GUARANTEED RATINGS...................................................................................................................172

LECTRICAL CHARACTERISTICS................................................................................................................ 172

10 TIMING DIAGRAMS........................................................................................................................................... 177

11 PACKAGE OUTLINE .........................................................................................................................................200

12 APPENDIX - TEST MODE..................................................................................................................................201

12.1 B

OARD TEST MODE.......................................................................................................................................201

12.1.1 XNOR-Chain Test Mode.......................................................................................................................201

13 REFERENCE DOCUMENTS..............................................................................................................................204

14 LPC47M14X REVISIONS...................................................................................................................................205

TABLES

Table 1 – Super I/O Block Addresses ........................................................................................................................20

Table 2 – Hub Descriptor to be Modified....................................................................................................................25

Table 3 – Status, Data and Control Registers............................................................................................................27

Table 4 – Tape Select Bits .........................................................................................................................................30

Table 5 – Internal 2 Drive Decode - Normal ...............................................................................................................30

Table 6 – Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................31

Table 7 – Drive Type ID .............................................................................................................................................31

Table 8 – Precompensation Delays ...........................................................................................................................32

Table 9 – Data Rates .................................................................................................................................................33

Table 10 – DRVDEN Mapping ...................................................................................................................................33

Table 11 – Default Precompensation Delays .............................................................................................................33

Table 12 – FIFO Service Delay..................................................................................................................................35

Table 13 – Status Register 0......................................................................................................................................37

Table 14 – Status Register 1......................................................................................................................................38

Table 15 – Status Register 2......................................................................................................................................38

Table 16 – Status Register 3......................................................................................................................................39

Table 17 – Description of Command Symbols ...........................................................................................................41

Table 18 – Instruction Set ..........................................................................................................................................43

Table 19 – Sector Sizes .............................................................................................................................................50

Table 20 – Effects of MT and N Bits...........................................................................................................................51

Table 21 – Skip Bit vs Read Data Command.............................................................................................................51

SMSC DS – LPC47M14X Page 5 Rev. 03/19/2001

Table 22 – Skip Bit vs. Read Deleted Data Command...............................................................................................51

Table 23 – Result Phase Table ..................................................................................................................................52

Table 24 – Verify Command Result Phase Table ......................................................................................................53

Table 25 – Typical Values for Formatting...................................................................................................................55

Table 26 – Interrupt Identification...............................................................................................................................56

Table 27 – Drive Control Delays (ms) ........................................................................................................................57

Table 28 – Effects of WGATE and GAP Bits..............................................................................................................59

Table 29 – Addressing the Serial Port........................................................................................................................60

Table 30 – Interrupt Control Table .............................................................................................................................63

Table 31 – Baud Rates ..............................................................................................................................................68

Table 32 – Reset Function Table ...............................................................................................................................69

Table 33 – Register Summary for an Individual UART Channel ................................................................................69

Table 34 – MPU-401 HOST INTERFACE REGISTERS ............................................................................................74

Table 35 – MIDI DATA PORT ....................................................................................................................................74

Table 36 – MPU-401 STATUS PORT ........................................................................................................................74

Table 37 – MIDI RECEIVE BUFFER EMPTY STATUS BIT.......................................................................................75

Table 38 – MIDI TRANSMIT BUSY STATUS BIT ......................................................................................................75

Table 39 – MPU-401 COMMAND PORT ...................................................................................................................75

Table 40 – Parallel Port Connector ............................................................................................................................79

Table 41 – EPP Pin Descriptions ...............................................................................................................................83

Table 42 – ECP Pin Descriptions ...............................................................................................................................85

Table 43 – ECP Register Definitions..........................................................................................................................86

Table 44 – Mode Descriptions....................................................................................................................................86

Table 45a – Extended Control Register .....................................................................................................................90

Table 46 – Channel/Data Commands supported in ECP mode .................................................................................92

Table 47 – PC/AT and PS/2 Available Registers .......................................................................................................95

Table 48 – State of System Pins in Auto Powerdown ................................................................................................96

Table 49 – State of Floppy Disk Drive Interface Pins in Powerdown..........................................................................96

Table 50 – I/O Address Map ....................................................................................................................................103

Table 51 – Host Interface Flags ...............................................................................................................................103

Table 52 – Status Register.......................................................................................................................................105

Table 53 – Resets ....................................................................................................................................................105

Table 54 – General Purpose I/O Port Assignments .................................................................................................111

Table 55 – GPIO Configuration Summary................................................................................................................112

Table 56 – GPIO Read/Write Behavior ....................................................................................................................113

Table 57 – Different Modes for Fan..........................................................................................................................118

Table 58 – Runtime Register Block Summary..........................................................................................................125

Table 59 – PME, SMI, GPIO, FAN Register Description..........................................................................................127

Table 60 – Game Port..............................................................................................................................................151

Table 61 – LPC47M14x Configuration Registers Summary.....................................................................................154

Table 62 – Chip Level Registers ..............................................................................................................................156

Table 63 – Logical Device Registers........................................................................................................................159

Table 64 – Logical Device Registers........................................................................................................................160

Table 65 – I/O Base Address Configuration Register Description............................................................................161

Table 66 – Interrupt Select Configuration Register Description ...............................................................................162

Table 67 – DMA Channel Select Configuration Register Description.......................................................................163

Table 68 – Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] ............................................164

Table 69 – Parallel Port, Logical Device 3 [Logical Device Number = 0x03]............................................................165

Table 70 – Serial Port 1, Logical Device 4 [Logical Device Number = 0x04]............................................................166

Table 71 – Serial Port 2, Logical Device 5 [Logical Device Number = 0x05]............................................................166

Table 72 – KYBD, Logical Device 7 [Logical Device Number = 0x07] .....................................................................168

Table 73 – PME, Logical Device A [Logical Device Number = 0x0A].......................................................................168

Table 74 – MPU-401 [Logical Device Number = 0x0B] ............................................................................................169

Table 75 – USB Hub, Logical Device C [Logical Device Number = 0x0C] ...............................................................169

Table 76 – HubControl_1 Register Definition ...........................................................................................................171

Table 77 – Electrical Source Characteristics............................................................................................................178

SMSC DS – LPC47M14X Page 6 Rev. 03/19/2001

FIGURES

FIGURE 1 – LPC47M14X BLOCK DIAGRAM...........................................................................................................16

FIGURE 2 – LPC47M14X CLOCK GENERATOR .....................................................................................................24

FIGURE 3 – MPU-401 MIDI INTERFACE..................................................................................................................73

FIGURE 4 – MPU-401 INTERRUPT ..........................................................................................................................76

FIGURE 5 - MIDI DATA BYTE EXAMPLE ...................................................................................................................77

FIGURE 6 – KEYBOARD LATCH............................................................................................................................108

FIGURE 7 – MOUSE LATCH...................................................................................................................................108

FIGURE 8 – GPIO FUNCTION ILLUSTRATION......................................................................................................112

FIGURE 9 – POWER-UP TIMING ...........................................................................................................................178

FIGURE 10 – DATA SIGNAL RISE AND FALL TIME..............................................................................................180

FIGURE 11 – FULL SPEED LOAD ..........................................................................................................................180

FIGURE 12 – LOW-SPEED PORT LOADS .............................................................................................................180

FIGURE 13 – CABLE DELAY ..................................................................................................................................180

FIGURE 14 – DIFFERENTIAL DATA JITTER..........................................................................................................181

FIGURE 15 – DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH...................................................181

FIGURE 16 – RECEIVER JITTER TOLERANCE ....................................................................................................181

FIGURE 17 – INPUT CLOCK TIMING .....................................................................................................................182

FIGURE 18 – PCI CLOCK TIMING..........................................................................................................................182

FIGURE 19 – RESET TIMING .................................................................................................................................182

FIGURE 20 – OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.................................................183

FIGURE 21 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.....................................................183

FIGURE 22 – I/O WRITE .........................................................................................................................................184

FIGURE 23 – I/O READ...........................................................................................................................................184

FIGURE 24 – DMA REQUEST ASSERTION THROUGH LDRQ#...........................................................................185

FIGURE 25 – DMA WRITE (FIRST BYTE) ..............................................................................................................185

FIGURE 26 – DMA READ (FIRST BYTE)................................................................................................................185

FIGURE 27 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) ...........................................................................186

FIGURE 28 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE.................................................................................187

FIGURE 29 – EPP 1.9 DATA OR ADDRESS READ CYCLE ..................................................................................188

FIGURE 30 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE.................................................................................189

FIGURE 31 – EPP 1.7 DATA OR ADDRESS READ CYCLE ..................................................................................189

FIGURE 32 – PARALLEL PORT FIFO TIMING.......................................................................................................191

FIGURE 33 – ECP PARALLEL PORT FORWARD TIMING ....................................................................................191

FIGURE 34 – ECP PARALLEL PORT REVERSE TIMING......................................................................................192

FIGURE 35 – IRDA RECEIVE TIMING....................................................................................................................193

FIGURE 36 – IRDA TRANSMIT TIMING .................................................................................................................194

FIGURE 37 – AMPLITUDE SHIFT KEYED IR RECEIVE TIMING...........................................................................195

FIGURE 38 – AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ........................................................................196

FIGURE 39 – SETUP AND HOLD TIME..................................................................................................................197

FIGURE 40 – SERIAL PORT DATA ........................................................................................................................197

FIGURE 41 – JOYSTICK POSITION SIGNAL.........................................................................................................197

FIGURE 42 – JOYSTICK BUTTON SIGNAL ...........................................................................................................197

FIGURE 43 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .....................................................................198

FIGURE 44 – MIDI DATA BYTE ..............................................................................................................................198

FIGURE 45 – FAN OUTPUT TIMING ......................................................................................................................199

FIGURE 46 – FAN TACHOMETER INTPUT TIMING ..............................................................................................199

FIGURE 47 – LED OUTPUT TIMING ......................................................................................................................199

FIGURE 48 – 128 PIN QFP PACKAGE OUTLINE...................................................................................................200

FIGURE 49 – XNOR-CHAIN TEST STRUCTURE...................................................................................................201

SMSC DS – LPC47M14X Page 7 Rev. 03/19/2001

1 PIN LAYOUT

GP40/DRVDEN0 GP41/DRVDEN1

nMTR0

nDSKCHG

nDS0

CLKI32

VSS

nDIR

nSTEP nWDATA nWGATE

nHDSEL

nINDEX

nTRK0

nWRTPRT

nRDATA

GP42/nIO_PME

VTR

CLOCKI

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ#

PCI_RESET#

LPCPD#

GP43/DDRC

PCI_CLK

SER_IRQ

VSS GP10 /J1B1 GP11 /J1B2 GP12 /J2B1 GP13 /J2B2

GP14 /J1X GP15 /J1Y GP16 /J2X

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

VSS

nStrp1

nStrp0

VCC

OCLK

ICLK

VTR

nPWROK4

nPWROK3

nPWROK2

nPWROK1

nPWREN4

nPWREN3

nPWREN2

nPWREN1

VTR

PD4 -

PD4 +

PD3 -

PD3 +

PD2 -

PD2 +

PD1 -

PD1 +

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

LPC47M14x

128 PIN QFP

39404142434445464748495051525354555657585960616263

USB -

104

103

USB +

102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

VSS VSS GP57/nDTR2 GP56/nCTS2 GP55/nRTS2 GP54/nDSR2 GP53/TXD2 (IRTX) GP52/RXD2 (IRRX) GP51/nDCD2 VCC GP50/nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nALF nERROR nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC

VCC

GP32/FAN2

GP33/FAN1

GP27/nIO_SMI

GP30/FAN_TACH2

GP31/FAN_TACH1

KDAT

GP20/P17

GP21/P16/nDS1

GP22/P12/nMTR1

VREF

GP24/SYSOPT

GP60/LED1

GP61/LED2

GP25/MIDI_IN

GP26/MIDI_OUT

AVSS

GP17 /J2Y

SMSC DS – LPC47M14X Page 8 Rev. 03/19/2001

KCLK

MDAT

VSS

MCLK

GP37/A20M

IRTX2/GP35

IRRX2/GP34

GP36/nKBDRST

2 PIN CONFIGURATION

PIN # NAME PIN # NAME PIN # NAME PIN # NAME

1 GP40/DRVDEN0 33 GP11 /J1B2 65 VCC 97 GP54/nDSR2 2 GP41/DRVDEN1 34 GP12 /J2B1 66 nINIT 98 GP55/nRTS2 3 nMTR0 35 GP13 /J2B2 67 nSLCTIN 99 GP56/nCTS2 4 nDSKCHG 36 GP14 /J1X 68 PD0 100 GP57/nDTR2 5 nDS0 37 GP15 /J1Y 69 PD1 101 VSS 6 CLKI32 38 GP16 /J2X 70 PD2 102 VSS 7 VSS 39 GP17 /J2Y 71 PD3 103 USB + 8 nDIR 40 AVSS 72 PD4 104 USB 9 nSTEP 41 GP20/P17 73 PD5 105 PD1 + 10 nWDATA 42 GP21/P16/nDS1 74 PD6 106 PD1 11 nWGATE 43 GP22/P12/nMTR1 75 PD7 107 PD2 + 12 nHDSEL 44 VREF 76 VSS 108 PD2 13 nINDEX 45 GP24/SYSOPT 77 SLCT 109 PD3 + 14 nTRK0 46 GP25/MIDI_IN 78 PE 110 PD3 15 nWRTPRT 47 GP26/MIDI_OUT 79 BUSY 111 PD4 + 16 nRDATA 48 GP60/LED1 80 nACK 112 PD4 - 17 GP42/nIO_PME 49 GP61/LED2 81 nERROR 113 VTR 18 VTR 50 GP27/nIO_SMI 82 nALF 114 nPWREN1 19 CLOCKI 51 GP30/FAN_TACH2 83 nSTROBE 115 nPWREN2 20 LAD0 52 GP31/FAN_TACH1 84 RXD1 116 nPWREN3 21 LAD1 53 VCC 85 TXD1 117 nPWREN4 22 LAD2 54 GP32/FAN2 86 nDSR1 118 nUSBOC1 23 LAD3 55 GP33/FAN1 87 nRTS1 119 nUSBOC2 24 LFRAME# 56 KDAT 88 nCTS1 120 nUSBOC3 25 LDRQ# 57 KCLK 89 nDTR1 121 nUSBOC4 26 PCI_RESET# 58 MDAT 90 nRI1 122 VTR 27 LPCPD# 59 MCLK 91 nDCD1 123 ICLK 28 GP43/DDRC 60 VSS 92 GP50/nRI2 124 OCLK 29 PCI_CLK 61 IRRX2/GP34 93 VCC 125 VCC 30 SER_IRQ 62 IRTX2/GP35 94 GP51/nDCD2 126 nStrp0 31 VSS 63 GP36/nKBDRST 95 GP52/RXD2

(IRRX)

32 GP10 /J1B1 64 GP37/A20M 96 GP53/TXD2

(IRTX)

Note: The chip is part of a family of LPC chips (LPC47M13x, LPC47M14x, and LPC47M15x). The first 100 pins of these chips are pin compatible, which adds more flexibility for the board designer. In addition, a board designed for the LPC47M14x can also support the LPC47M13x with little or no changes made to the board design.

127 nStrp1

128 VSS

SMSC DS – LPC47M14X Page 9 Rev. 03/19/2001

3 DESCRIPTION OF PIN FUNCTIONS

QFP

PIN #

23:20

24 Frame 1 LFRAME# PCI_I 25 Encoded DMA Request 1 LDRQ# PCI_O 26 PCI Reset 1 PCI_RESET# PCI_I

27 Power Down 1 LPCPD# PCI_I 29 PCI Clock 1 PCI_CLK PCI_ICLK 30 Serial IRQ 1 SER_IRQ PCI_IO

19 14.318MHz Clock Input 1 CLOCKI IS IS

123

124 24MHz Crystal (terminal 2) 1 OCLK IS IS 14

51 General Purpose I/O

52 General Purpose I/O

54 General Purpose I/O

55 General Purpose I/O

61 Infrared Rx

62 Infrared Tx

53,

65,93,1

7, 31,

60,76,

101, 102,

128

40 Analog Ground 1 AVSS

44 Reference Voltage 1 VREF

18,

113,

122

16 Read Disk Data 1 nRDATA IS 11 Write Gate 1 nWGATE O12 (O12/OD12) 10 Write Disk Data 1 nWDATA O12 (O12/OD12)

Multiplexed Command, Address, Data [3:0]

32.768KHz Trickle Clock Input

24MHz Crystal (terminal 1) / 48MHz Clock Input

/Fan Tachometer 2

/Fan Tachometer 1

/Fan Speed Control 2

/Fan Speed Control 1

/General Purpose I/O

Power 4 VCC

Ground 7 VSS

Trickle Voltage 3 VTR 7

NAME

PROCESSOR/HOST LPC INTERFACE (10)

TOTAL SYMBOL

4 LAD[3:0] PCI_IO PCI_IO

CLOCKS (4)

1 CLOCKI32 IS

1 ICLK IS IS

FAN CONTROL (4)

GP30/ FAN_TACH2

GP31/ FAN_TACH1

1 GP32/FAN2 IO12

1 GP33/FAN1 IO12

INFRARED INTERFACE (2)

1 IRRX2/GP34 IS/O8

1 IRTX2/GP35 IO12

POWER PINS (16)

FDD INTERFACE (14)

BUFFER

TYPE

IO8

BUFFER TYPE

PER FUNCTION

(NOTE 1)

PCI_I PCI_O PCI_I

PCI_I 2 PCI_ICLK PCI_IO

IS 3

(I/O8/OD8)/I

(I/O12/OD12)/ (O12/OD12)

IS/(IS/O8/OD8)

O12/(I/O12/OD12) 5, 6

NOTES

11, 14

SMSC DS – LPC47M14X Page 10 Rev. 03/19/2001

QFP

PIN #

NAME

TOTAL SYMBOL

BUFFER

TYPE

BUFFER TYPE

PER FUNCTION

(NOTE 1)

NOTES

12 Head Select 1 nHDSEL O12 (O12/OD12)

8 Step Direction 1 nDIR O12 (O12/OD12)

9 Step Pulse 1 nSTEP O12 (O12/OD12) 4 Disk Change 1 nDSKCHG IS

5 Drive Select 0 1 nDS0 O12 (O12/OD12)

3 Motor On 0 1 nMTR0 O12 (O12/OD12) 15 Write Protected 1 nWRTPRT IS 14 Track 0 1 nTRKO IS

13 Index Pulse Input 1 nINDEX IS

General Purpose I/O/Drive Density Select 0

General Purpose I/O/Drive Density Select 1

GP40/ DRVDEN0

GP41/ DRVDEN1

IO12

IS IS

IS (I/O12/OD12)/

(O12/OD12)

(I/O12/OD12)/ (O12/OD12)

SERIAL PORT 1 INTERFACE (8)

84 Receive Serial Data 1 1 RXD1 IS IS

85 Transmit Serial Data 1 1 TXD1 O12 O12 87 Request to Send 1 1 nRTS1 O8 O8 88 Clear to Send 1 1 nCTS1 I I

89 Data Terminal Ready 1 1 nDTR1 O6 O6 86 Data Set Ready 1 1 nDSR1 I I 91 Data Carrier Detect 1 1 nDCD1 I I

90 Ring Indicator 1 1 nRI1 I I

SERIAL PORT 2 INTERFACE (8)

95 General Purpose I/O

/Receive Serial Data 2

GP52/RXD2 (IRRX)

IS/O8

(IS/O8/OD8)/IS

/Infrared Rx

96 General Purpose I/O

/Transmit Serial Data 2

GP53/TXD2 (IRTX)

IO12

(I/O12/OD12)/O12 5

/Infrared Tx

98 General Purpose I/O

1 GP55/nRTS2 IO8

(I/O8/OD8)/O8

/Request to Send 2

99 General Purpose I/O

1 GP56/nCTS2 IO8

(I/O8/OD8)/I

/Clear to Send 2

100 General Purpose I/O

1 GP57/nDTR2 IO8

(I/O8/OD8)/O8

/Data Terminal Ready

97 General Purpose I/O

1 GP54/nDSR2 IO8

(I/O8/OD8)/I

/Data Set Ready 2

General Purpose I/O/Data

1 GP51/nDCD2 IO8 (I/O8/OD8)/I

Carrier Detect 2

General Purpose I/O/Ring

1 GP50/nRI2 IO8 (I/O8/OD8)/I

Indicator 2

PARALLEL PORT INTERFACE (17) 66 Initiate Output 67 Printer Select Input

68 Port Data 0 69 Port Data 1 70 Port Data 2

71 Port Data 3 72 Port Data 4 73 Port Data 5

Port Data 6

nINIT OP14 (OD14/OP14)

nSLCTIN OP14 (OD14/OP14)

PD0 IOP14 IOP14

PD1 IOP14 IOP14

PD2 IOP14 IOP14

PD3 IOP14 IOP14

PD4 IOP14 IOP14

PD5 IOP14 IOP14

PD6 IOP14 IOP14

SMSC DS – LPC47M14X Page 11 Rev. 03/19/2001

QFP

PIN #

NAME

75 Port Data 7 77 Printer Selected Status

78 Paper End 79 Busy 80 Acknowledge

81 Error 82 Autofeed Output 83 Strobe Output

TOTAL SYMBOL

PD7 IOP14 IOP14

SLCT I I

PE I I

BUSY I I

nACK I I

nERROR I I

nALF OP14 (OD14/OP14)

nSTROBE OP14 (OD14/OP14)

BUFFER

TYPE

KEYBOARD/MOUSE INTERFACE (6)

56 Keyboard Data 1 KDAT IOD16 57 Keyboard Clock 1 KCLK IOD16 58 Mouse Data 1 MDAT IOD16

59 Mouse Clock 1 MCLK IOD16 63 General Purpose I/O

/Keyboard Reset

64 General Purpose I/O

GP36/

IO8

nKBDRST

1 GP37/A20M IO8

/Gate A20

USB HUB(18)

103

Serial Port Upstream Data

USB+ IOUSB IOUSB

104

Serial Port Upstream Data

USB- IOUSB IOUSB

105

Serial Port Downstream

PD1+ IOUSB IOUSB

Data +

106

Serial Port Downstream

PD 1- IOUSB IOUSB

Data -

107

Serial Port Downstream

PD 2+ IOUSB IOUSB

Data +

108

Serial Port Downstream

PD 2- IOUSB IOUSB

Data -

109

Serial Port Downstream

PD 3+ IOUSB IOUSB

Data +

110

Serial Port Downstream

PD 3- IOUSB IOUSB

Data -

111

Serial Port Downstream

PD 4+ IOUSB IOUSB

Data +

112

Serial Port Downstream

PD 4- IOUSB IOUSB

Data -

nUSBOC1 nPWREN1 nUSBOC2

nPWREN2 nUSBOC3 nPWREN3

nUSBOC4 nPWREN4 nStrp0

IPU O24 IPU

O24 IPU O24

IPU O24 IPU

118 USB Over-Current sense 1 114 USB Power Enable 1 119 USB Over-Current sense 1

115 USB Power Enable 1 120 USB Over-Current sense 1 116 USB Power Enable 1

121 USB Over-Current sense 1 117 USB Power Enable 1 126

Number of Down Stream Ports select

127

Number of Down Stream

nStrp1

IPU

Ports select

BUFFER TYPE

PER FUNCTION

NOTES

(NOTE 1)

IOD16 IOD16 IOD16

IOD16 (I/O8/OD8)/O8 9

(I/O8/OD8)/O8 9

IPU 13 O24 13 IPU 13

O24 13 IPU 13 O24 13

IPU 13 O24 13 IPU Input with

30ua Pull

IPU Input with

30ua Pull

SMSC DS – LPC47M14X Page 12 Rev. 03/19/2001

QFP

PIN #

NAME

TOTAL SYMBOL

BUFFER

TYPE

BUFFER TYPE

PER FUNCTION

(NOTE 1)

NOTES

GENERAL PURPOSE I/O (19)

General Purpose I/O

GP10 /J1B1 IS/O8 (IS/O8/OD8)/IS

/Joystick 1 Button 1

General Purpose I/O

GP11 /J1B2 IS/O8 (IS/O8/OD8)/IS

/Joystick 1 Button 2

General Purpose I/O

GP12 /J2B1 IS/O8 (IS/O8/OD8)/IS

/Joystick 2 Button 1

General Purpose I/O

GP13 /J2B2 IS/O8 (IS/O8/OD8)/IS

/Joystick 2 Button 2

General Purpose I/O

GP14 /J1X IO12 (I/O12/OD12)/ IO12

/Joystick 1 X-Axis

General Purpose I/O

GP15 /J1Y IO12 (I/O12/OD12)/ IO12

/Joystick 1 Y-Axis

General Purpose I/O

GP16 /J2X IO12 (I/O12/OD12)/ IO12

/Joystick 2 X-Axis

General Purpose I/O

GP17 /J2Y IO12 (I/O12/OD12)/ IO12

/Joystick 2 Y-Axis

41 42

General Purpose I/O / P17 General Purpose I/O / P16

/nDS1

General Purpose I/O / P12 /nMTR1

General Purpose I/O / System Option

General Purpose I/O /MIDI_IN

General Purpose I/O /MIDI_OUT

50 General Purpose I/O

/SMI Output

General Purpose I/O /

GP20 /P17 IO8 (I/O8/OD8)/IO8

GP21 /P16/

nDS1 GP22 /P12/

nMTR1 GP24

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO12 (I/O12/OD12)/

IO12/(O12/OD12)

IO8 (I/O8/OD8) 8 /SYSOPT GP25

IO8 (I/O8/OD8)/I /MIDI_IN GP26

IO12 (I/O12/OD12)/O12 /MIDI_OUT

GP27

IO12 (I/O12/OD12)/ OD12 /nIO_SMI

GP60 /LED1 IO12 (I/O12/OD12)/O12 10

LED

General Purpose I/O /

GP61 /LED2 IO12 (I/O12/OD12)/O12 10

LED

General Purpose I/O / Power Management Event

28 General Purpose I/O

GP42 /nIO_PME

GP43/DDRC IO8 (I/O8/OD8)/I

IO12 (I/O12/OD12)/ OD12

/Device Disable Reg. Control

Note: The "n" as the first letter of a signal name or the “#” as the suffix of a signal name indicates an "Active Low"

signal.

Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis

represent multiple buffer types for a single pin function.

Note 2: The LPCPD# pin may be tied high. The LPC interface will function properly if the PCI_RESET# signal

follows the protocol defined for the LRESET# signal in the “Low Pin Count Interface Specification”.

Note 3: For USB Hub functionality, the 32 KHz input clock must always be connected. There is a bit in the

configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’).

Note 4: The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset.

These pins revert to their non-inverting GPIO input function when VCC is removed from the part.

Note 5: The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR

(VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.

Note 6: The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO. Note 7: VTR must not be connected to VCC. The 32 KHz input clock must not be driven high whenVTR = 0v.

SMSC DS – LPC47M14X Page 13 Rev. 03/19/2001

Note 8: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration

at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.

Note 9: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs

after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used the system must ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”.

Note 10: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power. Note 11: The 48MHz clock input must not be driven high when VTR = 0V. Note 12: VTR is used to power the USB cable transceivers. VTR must not be connected to VCC. Note 13: When the specified USB Down Stream Ports are disabled via the Strp0/Strp1 bit or nStrp1/nStrp0 Pins, the

associated Over-current sense pins (nUSBOC[x]) and Power Enable (nPWREN[4:1]) pins are also disabled. The USB Down Stream Port nUSBOC[x] input pin can be a NC (No Connect) pin for existing designs or tied High (1). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1). The Power Enable (nPWREN[x]) pin will be forced low (0).

Note 14: When a 24MHz crystal oscillator is used, these pins need off-balance capacitive loading. It is suggested to

use a 22pf capacitor on ICLK and a 10pf capacitor on OCLK.

3.1 BUFFER TYPE DESCRIPTIONS

Note: The buffer type values are specified at VCC=3.3V

IO12 Input/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD8 Open Drain Output, 8mA sink. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Back-drive protected. IOD16 Input/Output (Open Drain), 16mA sink. IO8 Input/Output, 8mA sink, 4mA source. O24 Output, 24mA sink, 12mA source. I Input TTL Compatible. IPU Input TTL Compatible. With 30ua internal Pull Up IS Input with Schmitt Trigger. PCI_IO Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_O Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_I Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_ICLK Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2) IOUSB Buffer Type for the USB differential data lines. Defined in the “Operational Description” section according to the USB specification; V1.1

Note 1: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2. Note 2: See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.

SMSC DS – LPC47M14X Page 14 Rev. 03/19/2001

3.2 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS

The following pins require external pullup resistors:

 KDAT  KCLK  MDAT  MCLK  GP36/KBDRST if KBDRST function is used  GP37/A20M if A20M function is used  GP20/P17 If P17 function is used  GP21/P16 if P16 function is used  GP22/P12 if P12 function is used  GP27/nIO_SMI if nIO_SMI function is used as Open Collector output.  GP42/nIO_PME if nIO_PME function is used as Open Collector output.  SER_IRQ  GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector.  GP41/DRVDEN1 if DRVDEN1 function is used as Open Collector.  nMTR0 if used as Open Collector Output  nDS0 if used as Open Collector Output  nDIR if used as Open Collector Output  nSTEP if used as Open Collector Output  nWDATA if used as Open Collector Output  nWGATE if used as Open Collector Output  nHDSEL if used as Open Collector Output  nINDEX  nTRK0  nWRTPRT  nRDATA  nDSKCHG

SMSC DS – LPC47M14X Page 15 Rev. 03/19/2001

4 BLOCK DIAGRAM

SER_IRQ PCI_CLK

LAD[3:0]

PCI_RESET

IO_PME*

IO_SMI*

GP1[0:7]*

GP2[0:2,4:7]* GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]*

Oscillator

(24MHz)

Crystal

PWROK[3,0]

PWREN[3,0]

CLK32

CLOCKI

LFrame

LDRQ

LPCPD

ICLK

OCLK

PD1+

PD1-

PD2+

PD2-

PD3+

PD3-

PD4+

PD4-

CLOCK GEN

SERIAL

IRQ

LPC

Bus Interface

Power Mgmt

General

Purpose

I/O

CLOCK GEN

USB HUB

IRTX2*

IRRX2*

(Data, Address, and Control lines)

SMC PROPRIETARY 82077 COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER CORE

J1X, J1Y*

J2B1, J2B2*

J1B1, J1B2*

J2X, J2Y*

Game Port Fan Control2nd Infrared Port

Internal Bus

LPC47M14x

(128 QFP)

WDATA

WCLOCK

RCLOCK

RDATA

FAN2*

FAN1*

DIGITAL DATA

SEPARATOR WITH WRITE

PRECOM-

PENSATION

FAN_TACH2*

FAN_TACH1*

LED2*

LED1*

LEDs

Multi-Mode

Parallel Port

with

ChiProtect

(see LPC47B27x)

Keyboard/Mouse

MUX

High-Speed

16550A

UART

PORT 1

High-Speed

16550A

UART

PORT 2

MPU-401

Serial Port

8042

controller

/FDC

PD[7,0]

Busy, Slct, PE, ERROR, ACK

STROBE, INIT, SLCTIN, ALF

TXD1, RXD1

CTS1, RTS1

DSR1, DTR1

DCD1, RI1

TXD2 (IRTX)*, RXD2 (IRRX)*

CTS2*, RTS2 *

DSR2*, DTR2*

DCD2*, RI2*

MIDI_IN*

MIDI_OUT*

KCLK, MCLK

KDATA, MDATA

GateA20*

KRESET*

P12*, P16*, P17*

DIR, STEP,

USB-

USB+

DSKCHG, DS0, DS1*

DRVDEN0*, DRVDEN1*

MTR0, MTR1*,TRK0,

INDEX, WRTPRT

WGATE, HDSEL

RDATA, WDATA

Note 1:

This diagram does not show power and ground

connections.

Note 2:

Functions with " *" are located on multifunctional pins. This diagram is designed to show the various functions available on the chip (not pin layout).

FIGURE 1 – LPC47M14X BLOCK DIAGRAM

SMSC DS – LPC47M14X Page 16 Rev. 03/19/2001

5 POWER FUNCTIONALITY

The LPC47M14x has three power planes: VCC, VTR, and VREF.

5.1 VCC POWER

The LPC47M14x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the “Operational Description” Section and the “Maximum Current Values” subsection.

5.1.1 3 Volt Operation / 5 Volt Tolerance

The LPC47M14x is a 3.3 Volt part. It is intended solely for 3.3V applications. All signal pins are 5V tolerant except those that pertain to the LPC Bus and USB Hub interfaces; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

 LAD[3:0]  LFRAME#  LDRQ#  LPCPD#

The USB interface pins are 3.3V tolerant. The maximum input voltage tolerated on the downstream port pins is 3.6V (See “Operational Description” for the IOUSB buffers). These pins are labeled:

 PD+[1:4]  PD-[1:4]

The input voltage for all other pins is 5.5V max including the following pins:

 PCI_RESET#  PCI_CLK  SER_IRQ  nIO_PME  nUSBOC[1:4]  nPWREN[1:4]

5.2 USB POWER

The LPC47M14x requires that the USB Hub maintain power for wake-up events in the absence of VCC power. To meet these requirements, the Hub Block and the transceiver pins are powered by VTR. CLKI32, which is also powered by VTR, is used to monitor changes in the signaling on the USB ports. This will enable the Hub Block to resume from a suspend state by receiving a signal on either its downstream ports or its upstream port.

5.3 VTR SUPPORT

The LPC47M14x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when V

is removed. The VTR pin is connected to the VTR (standby) power supply, which is 3.3

Volts (nominal). See the “Operational Description” Section. The maximum VTR current that is required depends on the functions that are used in the part. See “Trickle Power Functionality” subsection and “Maximum Current Values” subsection. This voltage source is also used to power the USB Hub interface, the IR interface, the PME configuration registers, and the PME interface. The V

pin generates a VTR Power-on-Reset signal to initialize these components.

Note: If V minimum potential at least 10 µs before V

is to be used for programmable wake-up events when VCC is removed, VTR must be at its full

begins a power-on cycle. When VTR and Vcc are fully

powered, the potential difference between the two supplies must not exceed 500mV.

5.4 VREF PIN

The LPC47M14x has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply. It is used for the game port. See the “GAME PORT LOGIC” section.

SMSC DS – LPC47M14X Page 17 Rev. 03/19/2001

5.5 INTERNAL PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface

cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the

as V

LPC47M14x host interface is active. When the internal PWRGOOD signal is “0” (inactive), V

≤ 2.3V (nominal), and

the LPC47M14x host interface is inactive; that is, LPC bus reads and writes will not be decoded.

The LPC47M14x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2, USB+, USB-, PD[4:1]+, PD[4:1]- and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, since V

must always be powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and

GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive. See “Trickle Power Functionality” section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.

5.6 32.768 KHZ TRICKLE CLOCK INPUT

The LPC47M14x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink, wake on specific key function, and to the USB Hub to support suspend and resume signaling.

5.7 TRICKLE POWER FUNCTIONALITY

When the LPC47M14x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events:

 UART 1 Ring Indicator  UART 2 Ring Indicator  Keyboard data  Mouse data  “Wake on Specific Key” Logic  Fan Tachometers (Note)  GPIOs for wakeup. See below.  Event on USB Downstream/Upstream ports

Note: The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant:

 I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may

only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

 I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by

VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.

The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, and GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 - see below):

 Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load

on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR.

All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin which comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output buffer type is retained.

The other GPIOs function as follows: GP36, GP37 and GP40:

 Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input

buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.

SMSC DS – LPC47M14X Page 18 Rev. 03/19/2001

GP35, GP42, GP53, GP60 and GP61:

 Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are

powered by VTR so that the pins are always forced low when not used. GP42 is the nIO_PME pin, which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR.

The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are powered by VTR so that they are driven low when VCC = 0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.

The following list summarizes the blocks, registers and pins that are powered by VTR.

 USB Hub  PME interface block  PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)  “Wake on Specific Key” logic  LED control logic  Fan Tachometers  Pins for PME Wakeup:

◊ GP42/nIO_PME (output, buffer powered by VTR) ◊ nRI1 (input) ◊ GP50/nRI2 (input) ◊ GP52/RXD2(IRRX) (input) ◊ KDAT (input) ◊ MDAT (input) ◊ GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, and

GP61) – all input-only except GP53, GP60, and GP61. See below.

 Other Pins

◊ IRTX2/GP35 (output, buffer powered by VTR) ◊ GP53/TXD2(IRTX) (output, buffer powered by VTR) ◊ GP60/LED1 (output, buffer powered by VTR) ◊ GP61/LED2 (output, buffer powered by VTR)

5.8 MAXIMUM CURRENT VALUES

See the “Operational Description” section for the maximum current values.

The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or

3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The pins that are powered by VTR are as follows: GP42/nIO_PME, IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1, GP61/LED2, and CLKI32. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.

 The maximum VCC current, ICC, is given with all outputs open (not loaded) , and all inputs in a fixed state

(i.e., 0V or 3.3V).

 The maximum VREF current, I

, is given with all outputs open (not loaded) , and all inputs in a fixed state

REF

(i.e., 0V or 3.3V).

5.9 POWER MANAGEMENT EVENTS (PME/SCI)

The LPC47M14x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.

SMSC DS – LPC47M14X Page 19 Rev. 03/19/2001

6 FUNCTIONAL DESCRIPTION

6.1 SUPER I/O REGISTERS

The address map, shown below in Table 1 shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register.

6.2 HOST PROCESSOR INTERFACE (LPC)

The host processor communicates with the LPC47M14x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.

Table 1 – Super I/O Block Addresses

ADDRESS BLOCK NAME

Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base1+(0-7) Base2+(0-7)

Base+(0-3) Base+(0-7) Base+(0-3), +(400-402) Base+(0-7), +(400-402) 60, 64 KYBD 7 Base + 0 Game Port 9 Base + (0-5F) Runtime Registers A 2 Base + (0-1) MPU-401 B Base + (0-1) Configuration n/a USB Hub C 1

Note: Refer to the configuration register descriptions for setting the base address. Note 1: No Addressable Registers in the Hub Block. Note 2: Logical Device A is referred to as the Runtime Register block or PME Block and may be

used interchangeably throughout this document.

Serial Port Com 2 5

Parallel Port

SPP EPP ECP

ECP+EPP+SPP

LOGICAL

DEVICE

NOTES

SMSC DS – LPC47M14X Page 20 Rev. 03/19/2001

6.3 LPC INTERFACE

The following sub-sections specify the implementation of the LPC bus.

6.3.1 LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics.

SIGNAL

NAME

LAD[3:0] I/O LPC address/data bus. Multiplexed command, address and data bus.

LFRAME# Input Frame signal. Indicates start of new cycle and termination of broken cycle

PCI_RESET# Input PCI Reset. Used as LPC Interface Reset.

LDRQ# Output Encoded DMA/Bus Master request for the LPC interface.

nIO_PME OD Power Mgt Event signal. Allows the LPC47M14x to request wakeup.

LPCPD# Input

SER_IRQ I/O Serial IRQ.

PCI_CLK Input PCI Clock.

Note: The CLKRUN# signal is not implemented in this part.

6.3.2 LPC Cycles

The following cycle types are supported by the LPC protocol.

The LPC47M14x ignores cycles that it does not support.

6.3.3 Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M14x. See the “Low Pin Count (LPC) Interface Specification”, Revision

1.0, Section 4.2 for definition of these fields.

6.3.4 LFRAME# Usage

LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47M14x to know when to monitor the bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M14x monitors the bus to determine whether the cycle is intended for it. The use of LFRAME# allows the LPC47M14x to enter a lower power state internally. There is no need for the LPC47M14x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.

When the LPC47M14x samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information.

The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0.

TYPE DESCRIPTION

Powerdown Signal. Indicates that the LPC47M14x should prepare for power to be shut on the LPC interface.

CYCLE TYPE TRANSFER SIZE

I/O Write 1 Byte

I/O Read 1 Byte DMA Write 1 byte DMA Read 1 byte

SMSC DS – LPC47M14X Page 21 Rev. 03/19/2001

6.3.5 I/O Read and Write Cycles

The LPC47M14x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers.

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles.

6.3.6 DMA Read and Write Cycles

DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M14x. DMA write cycles involve the transfer of data from the LPC47M14x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47B10x are 1, 2 or 4 bytes.

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles.

6.3.7 DMA Protocol

DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47M14x and special encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the “Low Pin Count (LPC) Interface Specification,” Revision

1.0.

6.3.8 Power Management

CLOCKRUN Protocol

The CLKRUN# pin is not implemented in the LPC47M14x. See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.1.

LPCPD Protocol

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.2.

6.3.9 SYNC Protocol

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 4.2.1.8 for a table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47M14x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M14x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or

1001. The LPC47M14x will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M14x uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M14x uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle.

The LPC47M14x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries.

SMSC DS – LPC47M14X Page 22 Rev. 03/19/2001

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M14x has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP.

SYNC Error Indication

The LPC47M14x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47M14x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M14x. If the host was writing data to the LPC47M14x, the data had already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred.

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

 When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the

removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus.

 When PCI_RESET# goes active (low):

 The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.

 The LPC47M14x must ignore LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).

6.3.10 LPC Transfer

Wait State Requirements

I/O Transfers

The LPC47M14x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us).

DMA Transfers

The LPC47M14x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers.

See the example timing for the LPC cycles in the “Timing Diagrams” section.

SMSC DS – LPC47M14X Page 23 Rev. 03/19/2001

6.4 USB HUB FUNCTIONAL DESCRIPTION

The USB Hub Block implements one upstream port and up to four downstream ports. The internal address/data/control connection is provided for programming by BIOS the USB Vendor ID, Product ID, Device Revision Number and number of down stream ports by accessing the Hub Control register. USB cable data is not transmitted or received via the internal connection.

The USB Hub Block implements the requirements defined in the USB Hub Device Class Specification Version 1.1 (USB Specification 1.1, Chapter 11), including Status Change Endpoint, Hub class specific descriptors and Hub class specific requests. The USB Hub Block supports Suspend and Resume both as a USB device and in terms of propagating Suspend and Resume signaling. It also supports remote wakeup by a device on downstream ports.

For wakeup requirements, the Hub Block is powered from VTR. VTR also powers the 24MHz OSC/PLL, 32 KHz clock input buffer, 48MHz CLK/OSC MUX and all Logical Device and Global Configuration Registers as well as programmable wakeup events in the PME interface.

The Hub Block clock requirements are derived from separate CLK/OSC pins (ICLK, OCLK). Clock pins ICLK and OCLK provide implementation flexibility for the system designer (see FIGURE 2). When a 48MHz clock signal is available, it may be connected directly to the ICLK pin. To reduce overall system EMI, a local 24MHz oscillator may alternately be connected between the ICLK and OCLK pins. The OSC_CLK control bit in the Logical Device C Configuration Register at 0xF0, selects between clock sources. The 32 KHz clock source is used to time certain port change events. This will ensure the USB Hub will respond to port change events while the hub is in Suspend.

Clocks for IO

Blocks

To Hub Block

and SIO

PLL

Buffer

CLOCKI

14.318 MHz. Clock

CLKI32

32.768 KHz.

ICLK

Clock

FIGURE 2 – LPC47M14X CLOCK GENERATOR

For power conservation the USB Hub Block turns off internal hub clocks during Suspend, as follows:

 The Hub Block responds to two types of Suspend. Selective (or Port) Suspend and Global Suspend.

Segments of the bus can be selectively suspended by sending the command SetPortFeature (PORT_SUSPEND) to the hub port to which that segment is attached. The suspended port will block activity to the suspended bus segment. Because other ports on the hub remain active, internal clocks are not turned off.

 Global Suspend is used when no communication is desired anywhere on the bus and the entire bus is

placed in the Suspend state. The host signals the start of global suspend by ceasing all its transmissions (including the SOF token). As the hub block, and each device on the bus, recognizes that the bus is in the idle state for the appropriate length of time, it goes into the Suspend state. Because all bus segments attached to the hub are in the Suspend state, the hub will turn off the internal 24MHz driven PLL. In addition, 48MHz is stopped in the Hub Block. The 48MHz clock signal at the ICLK pin, if enabled, is not stopped. Control logic external to the LPC47M14X should stop this clock, if desired.

 The Hub Block will Resume from a Suspend state by receiving any non-idle signaling by a remote wakeup

enabled device on its downstream ports or Resume signaling on its upstream port. If the Hub has been enabled as a remote wakeup source, it will also Resume from connects and disconnects on downstream

CLK/OSC

OSC/PLL

48 MHz.

Clock

48 Mhz. (to Hub Block)

MUX

OCLK

24 MHz.

Crystal

OSC_CLK (from config. registers)

PLL_EN (control from hub)

SMSC DS – LPC47M14X Page 24 Rev. 03/19/2001

ports. The internal 24MHz driven PLL (and the 48MHz in the Hub Block) will be started to complete the Resume.

6.4.1 USB Downstream Port Selection

The LPC47M14x USB Hub has the ability to program, via BIOS, control register access or through external PIN strapping options, the number of Down Stream Ports that are available to the User. There is also a “Pin Strapping” option that will allow the board designer the ability to define the number of down stream ports that will be active via during USB_PWR POR.

The LPC47M120 USB Hub block will make the following changes to its external signals and device class response parameters:

1) All related input and output signals such as the associated Over-current sense pins (nUSBOC[x]) and Power Enable (nPWREN[x]) pin are also disabled.

2) The USB Down Stream Port nUSBOC[x] input pin can be a NC (No Connect) pin or tied High (1). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

3) The Power Enable (nPWREN[x]) pin will be forced low (0). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

4) The associated PDx+ and PDx- pins will not be active can be a NC (No Connect) pin). For EMI and reduced Noise sensitivity, it is recommended that the pin be tied High (1).

5) All Hub Device Class return descriptor must respond with the appropriate information relating to the number of ports that are currently selected by the Strap Pins or control bits in the register described in Table 76 – HubControl_1 Register Definition, shown on page 171, below, describes what fields now need to be programmed bas on the number of enabled ports.

Table 2 – Hub Descriptor to be Modified

OFFSET FIELD PROGRAMMABLE SIZE DESCRIPTION

0 bDescLength 1 Number of bytes in this descriptor, including

1 bDescriptorType 1 Descriptor Type

2 bNbrPorts X 1 Number of downstream ports that this hub

3 wHubCharacteristics 2 D1..D0: Power Switching Mode

this byte.

supports. Selected by the “Strp0 and nStrp1” input pins or the HubControl_1 register defined in Table 76 – HubControl_1 Register Definition, shown on page 171, below.

00 - Ganged power switching (all ports’ power at once)

01 - Individual port power switching 1X - No power switching (ports always powered

on when hub is on and off when hub is off).

D2:Identifies a Compound Device 0 - Hub is not part of a compound device 1 - Hub is part of a compound device

D4..D3: Over-current Protection Mode 00 - Global Over-current Protection. The hub

reports over-current as a summation of all ports’ current draw, without a breakdown of individual port over-current status.

01 - Individual Port Over-current protection. The hub reports over-current on a per-port basis. Each port has an over-current indicator.

1X -No Over-Current Protection. This option is only allowed for bus-powered hubs that do not implement over-current protection.

D15..D5: Reserved

SMSC DS – LPC47M14X Page 25 Rev. 03/19/2001

OFFSET FIELD PROGRAMMABLE SIZE DESCRIPTION

5 bPwrOn2PwrGood 1 Time (in 2 ms intervals) from the time power on

6 bHubContrCurrent 1 Maximum current requirements of the hub

7 DeviceRemovable X Variable

depending on number of ports on

hub

Variable PortPwrCtrlMask X Variable

depending on number of ports on

hub

sequence begins on a port until power is good on that port. System software uses this value to determine how long to wait before accessing a powered-on port.

controller electronics in mA.

Indicates if a port has a removable device attached. If a non-removable device is attached to a port, that port will never receive an insertion change notification. This field is reported on byte-granularity. Within a byte, if no port exists for a given location, the field representing the port characteristics returns “0”.

Bit definition: 0 - Device is removable 1 - Device is not removable (permanently

attached) This is a bitmap corresponding to the individual

ports on the hub: Bit 0: Reserved for future use Bit 1: Port 1 Bit 2: Port 2 Etc. Bit n: Port n (implementation dependent, up to

a maximum of 255 ports).

Indicates if a port is not affected by a gangmode power control request. Ports that have this field set always require a manual SetPortFeature(PORT_POWER) request to control the port’s power state.

Bit definition: 0 - Port does not mask the gang-mode power

control capability. 1 - Port is not affected by gang-mode power

commands. Manual commands must be sent to this port to turn power on and off. This is a bitmap corresponding to the individual ports on the hub:

Bit 0: Reserved for future use. Bit 1: Port 1 Bit 2: Port 2 Etc. Bit n: Port n (implementation dependent, up to

a maximum of 255 ports).

6.5 FLOPPY DISK CONTROLLER

The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection.

The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core.

SMSC DS – LPC47M14X Page 26 Rev. 03/19/2001

6.5.1 FDC Internal Registers

The Floppy Disk Controller contains eight internal registers, which facilitate the interfacing between the host microprocessor and the disk drive. Table 3 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected.

Table 3 – Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

PRIMARY

ADDRESS

3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7

SECONDARY

ADDRESS

370 371 372 373 374 374 375 376 377 377

R/W REGISTER

R R/W R/W

R/W

Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TSR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR)

STATUS REGISTER A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0.

PS/2 Mode

INT

7 6 5 4 3 2 1 0

nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR

PENDIN

RESET

0 1 0 N/A 0 N/A N/A 0

COND.

BIT 0 DIRECTION

Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction.

BIT 1 nWRITE PROTECT

Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected.

BIT 2 nINDEX

Active low status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0.

BIT 4 nTRACK 0

Active low status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the STEP output disk interface output pin.

BIT 6 nDRV2

This function is not supported. This bit is always read as “1”.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt output.

SMSC DS – LPC47M14X Page 27 Rev. 03/19/2001

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

INT

PENDING

RESET

0 0 0 N/A 1 N/A N/A 1

DRQ STEP

F/F

TRK0 nHDSEL INDX WP nDIR

COND.

BIT 0 DIRECTION

Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction.

BIT 1 WRITE PROTECT

Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected.

BIT 2 INDEX

Active high status of the INDEX disk interface input.

BIT 3 HEAD SELECT

Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0.

BIT 4 TRACK 0

Active high status of the TRK0 disk interface input.

BIT 5 STEP

Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset.

BIT 6 DMA REQUEST

Active high status of the DMA request pending.

BIT 7 INTERRUPT PENDING

Active high bit indicating the state of the Floppy Disk Interrupt.

STATUS REGISTER B (SRB)

Address 3F1 READ ONLY

This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1.

PS/2 Mode

7 6 5 4 3 2 1 0

1 1 DRIVE

SEL0

RESET

1 1 0 0 0 0 0 0

WDATA

TOGGLE

RDATA

TOGGLE

WGATE MOT

EN1

MOT

EN0

COND.

BIT 0 MOTOR ENABLE 0

Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 1 MOTOR ENABLE 1

Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset.

BIT 2 WRITE GATE

Active high status of the WGATE disk interface output.

SMSC DS – LPC47M14X Page 28 Rev. 03/19/2001

BIT 3 READ DATA TOGGLE

Every inactive edge of the RDATA input causes this bit to change state.

BIT 4 WRITE DATA TOGGLE

Every inactive edge of the WDATA input causes this bit to change state.

BIT 5 DRIVE SELECT 0

Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset.

BIT 6 RESERVED

Always read as a logic "1".

BIT 7 RESERVED

Always read as a logic "1".

PS/2 Model 30 Mode

7 6 5 4 3 2 1 0

nDRV2 nDS1 nDS0 WDATA

F/F

RESET

N/A 1 1 0 0 0 1 1

RDATA

F/F

WGATE

F/F

nDS3 nDS2

COND.

BIT 0 nDRIVE SELECT 2

The DS2 disk interface is not supported.

BIT 1 nDRIVE SELECT 3

The DS3 disk interface is not supported.

BIT 2 WRITE GATE

Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register.

BIT 3 READ DATA

Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register.

BIT 4 WRITE DATA

Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE.

BIT 5 nDRIVE SELECT 0

Active low status of the DS0 disk interface output.

BIT 6 nDRIVE SELECT 1

Active low status of the DS1 disk interface output.

BIT 7 nDRV2

Active low status of the DRV2 disk interface input. Note: This function is not supported.

DIGITAL OUTPUT REGISTER (DOR)

Address 3F2 READ/WRITE

The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time.

RESET

7 6 5 4 3 2 1 0

MOT

EN3

MOT

EN2

MOT

EN1

MOT

EN0

DMAEN nRESET DRIVE

SEL1

DRIVE

SEL0

0 0 0 0 0 0 0 0

COND.

SMSC DS – LPC47M14X Page 29 Rev. 03/19/2001

BIT 0 and 1 DRIVE SELECT

These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time.

BIT 2 nRESET

A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.

BIT 3 DMAEN

PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes.

PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0".

BIT 4 MOTOR ENABLE 0

This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active.

BIT 5 MOTOR ENABLE 1

This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active.

DRIVE DOR VALUE

0 1CH 1 2DH

BIT 6 MOTOR ENABLE 2

The MTR2 disk interface output is not supported in the LPC47M14x.

BIT 7 MOTOR ENABLE 3

The MTR3 disk interface output is not supported in the LPC47M14x.

TAPE DRIVE REGISTER (TDR)

Address 3F3 READ/WRITE

The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 4 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset.

Table 4 – Tape Select Bits

TAPE SEL1

(TDR.1)

0 0 1 1

TAPE SEL0

(TDR.0)

0 1 0 1

DRIVE

SELECTED

None

1 2 3

Table 5 – Internal 2 Drive Decode - Normal

DIGITAL OUTPUT REGISTER

DRIVE SELECT OUTPUTS

(ACTIVE LOW)

MOTOR ON OUTPUTS

(ACTIVE LOW)

Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0

X X X 1 0 0 1 0 nBIT 5 nBIT 4

X X 1 X 0 1 0 1 nBIT 5 nBIT 4 X 1 X X 1 0 1 1 nBIT 5 nBIT 4 1 X X X 1 1 1 1 nBIT 5 nBIT 4

0 0 0 0 X X 1 1 nBIT 5 nBIT 4

SMSC DS – LPC47M14X Page 30 Rev. 03/19/2001

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SMSC LPC47M14x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual