Loading...SMSC LAN9311, LAN9311i User Manual
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LAN9311/LAN9311i
Two Port 10/100 Managed
Ethernet Switch with 16-Bit
Non-PCI CPU Interface
PRODUCT FEATURES |
Datasheet |
Highlights |
Ports |
High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP Snooping and management functions
Easily interfaces to most 16-bit embedded CPU’s
Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports as a single port MAC/PHY
Integrated IEEE 1588 Hardware Time Stamp Unit
Target Applications
Cable, satellite, and IP set-top boxes
Digital televisions
Digital video recorders
VoIP/Video phone systems
Home gateways
Test/Measurement equipment
Industrial automation systems
Key Benefits
Ethernet Switch Fabric
—32K buffer RAM
—1K entry forwarding table
—Port based IEEE 802.1Q VLAN support (16 groups)
–Programmable IEEE 802.1Q tag insertion/removal
—IEEE 802.1d spanning tree protocol support
—QoS/CoS Packet prioritization
–4 dynamic QoS queues per port
–Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value
–Programmable class of service map based on input priority
–Remapping of 802.1Q priority field on per port basis
–Programmable rate limiting at the ingress/egress ports with random early discard, per port / priority
—IGMP v1/v2/v3 snooping for Multicast packet filtering
—IPV6 Multicast Listener Discovery snoop
—Programmable filter by MAC address
Switch Management
—2 internal 10/100 PHYs with HP Auto-MDIX support
—Fully compliant with IEEE 802.3 standards
—10BASE-T and 100BASE-TX support
—Full and half duplex support
—Full duplex flow control
—Backpressure (forced collision) half duplex flow control
—Automatic flow control based on programmable levels
—Automatic 32-bit CRC generation and checking
—Automatic payload padding
—2K Jumbo packet support
—Programmable interframe gap, flow control pause value
—Full transmit/receive statistics
—Auto-negotiation
—Automatic MDI/MDI-X
—Loop-back mode
High-performance host bus interface
—Provides in-band network communication path
—Access to management registers
—Simple, SRAM-like interface
—16-bit data bus
—Big, little, and mixed endian support
—Large TX and RX FIFO’s for high latency applications
—Programmable water marks and threshold levels
—Host interrupt support
IEEE 1588 Hardware Time Stamp Unit
—Global 64-bit tunable clock
—Master or slave mode per port
—Time stamp on TX or RX of Sync and Delay_req packets per port, Timestamp on GPIO
—64-bit timer comparator event generation (GPIO or IRQ)
Comprehensive Power Management Features
—Wake on LAN
—Wake on link status change (energy detect)
—Magic packet wakeup
—Wakeup indicator event signal
Other Features
—General Purpose Timer
—Serial EEPROM interface (I2C master or MicrowireTM master) for non-managed configuration
—Programmable GPIOs/LEDs
Single 3.3V power supply
Available in Commercial & Industrial Temp. Ranges
—Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any ports or port pairs
—Fully compliant statistics (MIB) gathering counters
—Control registers configurable on-the-fly
SMSC LAN9311/LAN9311i |
DATASHEET |
Revision 1.4 (08-19-08)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
ORDER NUMBERS:
LAN9311-NU FOR 128-PIN, VTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9311-NZW FOR 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (0 TO 70°C TEMP RANGE) LAN9311i-NZW FOR 128-PIN, XVTQFP LEAD-FREE ROHS COMPLIANT PACKAGE (-40 TO 85°C TEMP RANGE)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.4 (08-19-08) |
2 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table of Contents
Chapter 1 Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 General Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Register Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 System Clocks/Reset/PME Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.2 System Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.5 Host Bus Interface (HBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.6 Host MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.7 EEPROM Controller/Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.8 1588 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.9 GPIO/LED Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.1 128-VTQFP Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.2 128-XVTQFP Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 4 Clocking, Resets, and Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 |
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
4.2 |
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
4.2.1 |
Chip-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
4.2.1.1 |
Power-On Reset (POR) .................................................................................................................................................................................. |
37 |
4.2.1.2 |
nRST Pin Reset .............................................................................................................................................................................................. |
38 |
4.2.2 |
Multi-Module Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
38 |
4.2.2.1 |
Digital Reset (DIGITAL_RST)......................................................................................................................................................................... |
38 |
4.2.2.2 |
Soft Reset (SRST) .......................................................................................................................................................................................... |
39 |
4.2.3 |
Single-Module Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
39 |
4.2.3.1 Port 2 PHY Reset............................................................................................................................................................................................ |
39 |
|
4.2.3.2 Port 1 PHY Reset............................................................................................................................................................................................ |
39 |
|
4.2.3.3 |
Virtual PHY Reset........................................................................................................................................................................................... |
40 |
4.2.4 |
Configuration Straps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
4.2.4.1 |
Soft-Straps...................................................................................................................................................................................................... |
40 |
4.2.4.2 |
Hard-Straps..................................................................................................................................................................................................... |
45 |
4.3 |
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
4.3.1 Port 1 & 2 PHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
|
4.3.2 Host MAC Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
|
Chapter 5 System Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2.1 1588 Time Stamp Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.2 Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2.3 Ethernet PHY Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.4 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.5 Host MAC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.6 Power Management Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SMSC LAN9311/LAN9311i |
3 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
5.2.7 General Purpose Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2.8 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.9 Device Ready Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Chapter 6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Switch Fabric CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2.1 Switch Fabric CSR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.2.2 Switch Fabric CSR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2.3 Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 10/100 Ethernet MACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1 Receive MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1.1 |
Receive Counters ........................................................................................................................................................................................... |
61 |
6.3.2 |
Transmit MAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
62 |
6.3.2.1 |
Transmit Counters .......................................................................................................................................................................................... |
62 |
6.4 Switch Engine (SWE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.4.1 MAC Address Lookup Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.4.1.1 |
Learning/Aging/Migration ................................................................................................................................................................................ |
64 |
6.4.1.2 |
Static Entries................................................................................................................................................................................................... |
64 |
6.4.1.3 |
Multicast Pruning ............................................................................................................................................................................................ |
64 |
6.4.1.4 |
Address Filtering ............................................................................................................................................................................................. |
64 |
6.4.1.5 Spanning Tree Port State Override................................................................................................................................................................. |
64 |
|
6.4.1.6 MAC Destination Address Lookup Priority...................................................................................................................................................... |
64 |
|
6.4.1.7 |
Host Access .................................................................................................................................................................................................... |
64 |
6.4.2 |
Forwarding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
66 |
6.4.3 |
Transmit Priority Queue Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
67 |
6.4.3.1 |
Port Default Priority......................................................................................................................................................................................... |
69 |
6.4.3.2 IP Precedence Based Priority ......................................................................................................................................................................... |
69 |
|
6.4.3.3 |
DIFFSERV Based Priority............................................................................................................................................................................... |
69 |
6.4.3.4 |
VLAN Priority .................................................................................................................................................................................................. |
69 |
6.4.4 |
VLAN Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
6.4.5 |
Spanning Tree Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
70 |
6.4.6 |
Ingress Flow Metering and Coloring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
71 |
6.4.6.1 |
Ingress Flow Calculation................................................................................................................................................................................. |
72 |
6.4.7 |
Broadcast Storm Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
6.4.8 |
IPv4 IGMP / IPv6 MLD Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
6.4.9 |
Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
6.4.10 |
Host CPU Port Special Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
6.4.10.1 Packets from the Host CPU ............................................................................................................................................................................ |
75 |
|
6.4.10.2 Packets to the Host CPU ................................................................................................................................................................................ |
76 |
|
6.4.11 |
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
76 |
6.5 |
Buffer Manager (BM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
6.5.1 |
Packet Buffer Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
6.5.1.1 Buffer Limits and Flow Control Levels ............................................................................................................................................................ |
77 |
|
6.5.2 |
Random Early Discard (RED). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
6.5.3 |
Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
6.5.4 |
Transmit Priority Queue Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
78 |
6.5.5 |
Egress Rate Limiting (Leaky Bucket) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
78 |
6.5.6 |
Adding, Removing, and Changing VLAN Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
79 |
6.5.7 |
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
6.6 |
Switch Fabric Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
81 |
Chapter 7 Ethernet PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1.1 PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.2 Port 1 & 2 PHYs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2.1 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.2.1.1 |
MII MAC Interface ........................................................................................................................................................................................... |
84 |
7.2.1.2 |
4B/5B Encoder................................................................................................................................................................................................ |
84 |
7.2.1.3 |
Scrambler and PISO....................................................................................................................................................................................... |
86 |
7.2.1.4 |
NRZI and MLT-3 Encoding ............................................................................................................................................................................. |
86 |
7.2.1.5 |
100M Transmit Driver ..................................................................................................................................................................................... |
86 |
Revision 1.4 (08-19-08) |
4 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
7.2.1.6 |
100M Phase Lock Loop (PLL) ........................................................................................................................................................................ |
86 |
7.2.2 |
100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
7.2.2.1 |
A/D Converter ................................................................................................................................................................................................. |
87 |
7.2.2.2 |
DSP: Equalizer, BLW Correction and Clock/Data Recovery .......................................................................................................................... |
87 |
7.2.2.3 |
NRZI and MLT-3 Decoding ............................................................................................................................................................................. |
88 |
7.2.2.4 |
Descrambler and SIPO ................................................................................................................................................................................... |
88 |
7.2.2.5 |
5B/4B Decoding.............................................................................................................................................................................................. |
88 |
7.2.2.6 |
Receiver Errors ............................................................................................................................................................................................... |
88 |
7.2.2.7 |
MII MAC Interface ........................................................................................................................................................................................... |
88 |
7.2.3 |
10BASE-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
7.2.3.1 |
MII MAC Interface ........................................................................................................................................................................................... |
89 |
7.2.3.2 |
10M TX Driver and PLL .................................................................................................................................................................................. |
89 |
7.2.4 |
10BASE-T Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
7.2.4.1 |
Filter and Squelch ........................................................................................................................................................................................... |
89 |
7.2.4.2 |
10M RX and PLL............................................................................................................................................................................................. |
89 |
7.2.4.3 |
MII MAC Interface ........................................................................................................................................................................................... |
90 |
7.2.4.4 |
Jabber Detection............................................................................................................................................................................................. |
90 |
7.2.5 |
PHY Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
90 |
7.2.5.1 |
PHY Pause Flow Control ................................................................................................................................................................................ |
92 |
7.2.5.2 |
Parallel Detection............................................................................................................................................................................................ |
92 |
7.2.5.3 |
Restarting Auto-Negotiation............................................................................................................................................................................ |
92 |
7.2.5.4 |
Disabling Auto-Negotiation ............................................................................................................................................................................. |
92 |
7.2.5.5 |
Half Vs. Full-Duplex ........................................................................................................................................................................................ |
93 |
7.2.6 |
HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
7.2.7 |
MII MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
7.2.8 |
PHY Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
94 |
7.2.8.1 |
PHY Interrupts ................................................................................................................................................................................................ |
94 |
7.2.9 |
PHY Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
94 |
7.2.9.1 |
PHY General Power-Down ............................................................................................................................................................................. |
95 |
7.2.9.2 |
PHY Energy Detect Power-Down ................................................................................................................................................................... |
95 |
7.2.10 |
PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
95 |
7.2.10.1 |
PHY Software Reset via RESET_CTL............................................................................................................................................................ |
95 |
7.2.10.2 |
PHY Software Reset via PHY_BASIC_CTRL_x ............................................................................................................................................. |
96 |
7.2.10.3 |
PHY Power-Down Reset................................................................................................................................................................................. |
96 |
7.2.11 |
LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
7.2.12 |
Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
7.3 |
Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
7.3.1 |
Virtual PHY Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
96 |
7.3.1.1 |
Parallel Detection............................................................................................................................................................................................ |
97 |
7.3.1.2 |
Disabling Auto-Negotiation ............................................................................................................................................................................. |
97 |
7.3.1.3 |
Virtual PHY Pause Flow Control ..................................................................................................................................................................... |
98 |
7.3.2 |
Virtual PHY Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
98 |
7.3.2.1 |
Virtual PHY Software Reset via RESET_CTL ................................................................................................................................................ |
98 |
7.3.2.2 |
Virtual PHY Software Reset via VPHY_BASIC_CTRL ................................................................................................................................... |
98 |
7.3.2.3 |
Virtual PHY Software Reset via PMT_CTRL .................................................................................................................................................. |
98 |
Chapter 8 Host Bus Interface (HBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.2 Host Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3 Host Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.1 16-Bit Bus Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.3.2 16-Bit Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.4 Host Endianess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.5 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.5.1 Special Situations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.5.1.1 Reset Ending During a Read Cycle .............................................................................................................................................................. |
102 |
|
8.5.1.2 Reset Ending Between Halves of a 16-Bit Read Pair ................................................................................................................................... |
102 |
|
8.5.1.3 Writes Following a Reset .............................................................................................................................................................................. |
102 |
|
8.5.2 Special Restrictions on Back-to Back Write-Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
102 |
|
8.5.3 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
|
8.5.4 |
PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
107 |
8.5.5 |
PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
8.5.6 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
109 |
|
8.5.7 RX Data FIFO Direct PIO Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
110 |
|
8.5.8 |
PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
111 |
8.5.9 TX Data FIFO Direct PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
|
SMSC LAN9311/LAN9311i |
5 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
8.6 HBI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 9 Host MAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.2 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.2.1 Full-Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.2.2 Half-Duplex Flow Control (Backpressure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.3 Virtual Local Area Network (VLAN) Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.4 Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.4.1 Perfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.4.2 Hash Only Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.4.3 Hash Perfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.4.4 Inverse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5 Wake-up Frame Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.5.1 Magic Packet Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.6 Host MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
9.7 FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.7.1 TX/RX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.7.2 MIL FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9.7.3 FIFO Memory Allocation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.8 TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.8.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.8.2 TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.8.2.1 |
TX Command ‘A’........................................................................................................................................................................................... |
126 |
9.8.2.2 |
TX Command ‘B’........................................................................................................................................................................................... |
127 |
9.8.3 |
TX Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
127 |
9.8.3.1 TX Buffer Fragmentation Rules .................................................................................................................................................................... |
127 |
|
9.8.3.2 Calculating Worst-Case TX MIL FIFO Usage ............................................................................................................................................... |
128 |
|
9.8.4 |
TX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
128 |
9.8.5 Calculating Actual TX Data FIFO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
|
9.8.6 |
Transmit Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
9.8.6.1 |
TX Example 1 ............................................................................................................................................................................................... |
129 |
9.8.6.2 |
TX Example 2 ............................................................................................................................................................................................... |
131 |
9.8.7 |
Transmitter Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
132 |
9.8.8 Stopping and Starting the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
132 |
|
9.9 RX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
133 |
|
9.9.1 RX Slave PIO Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
133 |
|
9.9.1.1 Receive Data FIFO Fast Forward ................................................................................................................................................................. |
135 |
|
9.9.1.2 Force Receiver Discard (Receiver Dump) .................................................................................................................................................... |
135 |
|
9.9.2 |
RX Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
9.9.3 |
RX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
9.9.4 Stopping and Starting the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
137 |
|
9.9.5 |
Receiver Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
137 |
Chapter 10 Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.2 I2C/Microwire Master EEPROM Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.2.1 EEPROM Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.2.2 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10.2.2.1 |
I2C Protocol Overview .................................................................................................................................................................................. |
141 |
10.2.2.2 I2C EEPROM Device Addressing................................................................................................................................................................. |
142 |
|
10.2.2.3 I2C EEPROM Byte Read.............................................................................................................................................................................. |
143 |
|
10.2.2.4 I2C EEPROM Sequential Byte Reads .......................................................................................................................................................... |
143 |
|
10.2.2.5 I2C EEPROM Byte Writes ............................................................................................................................................................................ |
144 |
|
10.2.3 |
Microwire EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
145 |
10.2.3.1 |
Microwire Master Commands ....................................................................................................................................................................... |
145 |
10.2.3.2 |
ERASE (Erase Location) .............................................................................................................................................................................. |
146 |
10.2.3.3 |
ERAL (Erase All)........................................................................................................................................................................................... |
147 |
10.2.3.4 |
EWDS (Erase/Write Disable) ........................................................................................................................................................................ |
147 |
10.2.3.5 |
EWEN (Erase/Write Enable)......................................................................................................................................................................... |
148 |
10.2.3.6 |
READ (Read Location) ................................................................................................................................................................................. |
148 |
Revision 1.4 (08-19-08) |
6 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
10.2.3.7 |
WRITE (Write Location) ................................................................................................................................................................................ |
149 |
10.2.3.8 |
WRAL (Write All)........................................................................................................................................................................................... |
149 |
10.2.4 |
EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
150 |
10.2.4.1 |
EEPROM Loader Operation ......................................................................................................................................................................... |
150 |
10.2.4.2 |
EEPROM Valid Flag ..................................................................................................................................................................................... |
152 |
10.2.4.3 |
MAC Address................................................................................................................................................................................................ |
152 |
10.2.4.3.1Host MAC Address Reload ...................................................................................................... |
152 |
|
10.2.4.4 |
Soft-Straps.................................................................................................................................................................................................... |
152 |
10.2.4.4.1PHY Registers Synchronization ............................................................................................... |
152 |
|
10.2.4.4.2Virtual PHY Registers Synchronization.................................................................................... |
153 |
|
10.2.4.4.3LED and Manual Flow Control Register Synchronization ........................................................ |
153 |
|
10.2.4.5 |
Register Data................................................................................................................................................................................................ |
153 |
10.2.4.6 EEPROM Loader Finished Wait-State.......................................................................................................................................................... |
154 |
|
10.2.4.7 Reset Sequence and EEPROM Loader........................................................................................................................................................ |
154 |
|
Chapter 11 IEEE 1588 Hardware Time Stamp Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.1.1 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
11.2 IEEE 1588 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
11.2.1 Capture Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.2.2 PTP Message Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.3 IEEE 1588 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.4 IEEE 1588 Clock/Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.5 IEEE 1588 GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.6 IEEE 1588 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Chapter 12 General Purpose Timer & Free-Running Clock. . . . . . . . . . . . . . . . . . . . . . . . 162
12.1 General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.2 Free-Running Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Chapter 13 GPIO/LED Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.2 GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.2.1 GPIO IEEE 1588 Timestamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.2.1.1 |
IEEE 1588 |
GPIO Inputs ................................................................................................................................................................................ |
164 |
13.2.1.2 |
IEEE 1588 |
GPIO Outputs ............................................................................................................................................................................. |
164 |
13.2.2 GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.2.2.1 |
GPIO Interrupt Polarity.................................................................................................................................................................................. |
164 |
13.2.2.2 |
IEEE 1588 GPIO Interrupts........................................................................................................................................................................... |
165 |
13.3 LED Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Chapter 14 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
14.1 TX/RX FIFO Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
14.1.1 TX/RX Data FIFO’s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
14.1.2 TX/RX Status FIFO’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
14.1.3 Direct FIFO Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
14.2 System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
14.2.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
14.2.1.1 Interrupt Configuration Register (IRQ_CFG) ................................................................................................................................................ |
173 |
14.2.1.2 Interrupt Status Register (INT_STS)............................................................................................................................................................. |
175 |
14.2.1.3 Interrupt Enable Register (INT_EN).............................................................................................................................................................. |
178 |
14.2.1.4 FIFO Level Interrupt Register (FIFO_INT) .................................................................................................................................................... |
180 |
14.2.2 Host MAC & FIFO’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
181 |
14.2.2.1 Receive Configuration Register (RX_CFG) .................................................................................................................................................. |
181 |
14.2.2.2 Transmit Configuration Register (TX_CFG).................................................................................................................................................. |
183 |
14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL).................................................................................................................................... |
184 |
14.2.2.4 RX FIFO Information Register (RX_FIFO_INF) ............................................................................................................................................ |
185 |
14.2.2.5 TX FIFO Information Register (TX_FIFO_INF)............................................................................................................................................. |
186 |
14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP)................................................................................................................... |
187 |
14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD)............................................................................................................... |
188 |
14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) ...................................................................................................................... |
189 |
14.2.2.9 Host MAC Automatic Flow Control Configuration Register (AFC_CFG) ...................................................................................................... |
190 |
SMSC LAN9311/LAN9311i |
7 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.2.3 |
GPIO/LED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
14.2.3.1 |
General Purpose I/O Configuration Register (GPIO_CFG) .......................................................................................................................... |
193 |
14.2.3.2 |
General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) ........................................................................................................... |
195 |
14.2.3.3 |
General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN)...................................................................................... |
196 |
14.2.3.4 |
LED Configuration Register (LED_CFG) ...................................................................................................................................................... |
197 |
14.2.4 |
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
198 |
14.2.4.1 |
EEPROM Command Register (E2P_CMD) .................................................................................................................................................. |
198 |
14.2.4.2 |
EEPROM Data Register (E2P_DATA).......................................................................................................................................................... |
201 |
14.2.5 |
IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
202 |
14.2.5.1 |
Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) .......................................................... |
202 |
14.2.5.2 |
Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) .......................................................... |
203 |
14.2.5.3 |
Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)..... |
204 |
14.2.5.4 |
Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)........................................ |
205 |
14.2.5.5 |
Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x).......................................................... |
206 |
14.2.5.6 |
Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) ......................................................... |
207 |
14.2.5.7 |
Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) .... |
208 |
14.2.5.8 |
Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) ....................................... |
209 |
14.2.5.9 |
GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8).................................................................. |
210 |
14.2.5.10 |
GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) ................................................................. |
211 |
14.2.5.11 |
GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9).................................................................. |
212 |
14.2.5.12 |
GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) ................................................................. |
213 |
14.2.5.13 |
1588 Clock High-DWORD Register (1588_CLOCK_HI)............................................................................................................................... |
214 |
14.2.5.14 |
1588 Clock Low-DWORD Register (1588_CLOCK_LO) .............................................................................................................................. |
215 |
14.2.5.15 |
1588 Clock Addend Register (1588_CLOCK_ADDEND) ............................................................................................................................. |
216 |
14.2.5.16 |
1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)................................................................................................... |
217 |
14.2.5.17 |
1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) .................................................................................................. |
218 |
14.2.5.18 |
1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) ..................................................................... |
219 |
14.2.5.19 |
1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO).............................................................. |
220 |
14.2.5.20 |
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) ................................................................................................ |
221 |
14.2.5.21 |
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) ............................................................................................. |
222 |
14.2.5.22 |
1588 Configuration Register (1588_CONFIG).............................................................................................................................................. |
223 |
14.2.5.23 |
1588 Interrupt Status and Enable Register (1588_INT_STS_EN)................................................................................................................ |
227 |
14.2.5.24 |
1588 Command Register (1588_CMD) ........................................................................................................................................................ |
229 |
14.2.6 |
Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
230 |
14.2.6.1 |
Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... |
230 |
14.2.6.2 |
Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... |
232 |
14.2.6.3 |
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) ......................................................................................................... |
234 |
14.2.6.4 |
Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... |
236 |
14.2.6.5 |
Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... |
237 |
14.2.6.6 |
Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ |
239 |
14.2.6.7 |
Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... |
240 |
14.2.6.8 |
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) ................................................................................. |
241 |
14.2.7 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
244 |
|
14.2.7.1 |
PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. |
244 |
14.2.7.2 |
PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... |
245 |
14.2.8 |
Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
246 |
14.2.8.1 |
Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... |
247 |
14.2.8.2 |
Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... |
249 |
14.2.8.3 |
Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... |
251 |
14.2.8.4 |
Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ |
252 |
14.2.8.5 |
Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... |
253 |
14.2.8.6 |
Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. |
255 |
14.2.8.7 |
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... |
257 |
14.2.8.8 |
Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. |
258 |
14.2.9 |
Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
260 |
14.2.9.1 |
Chip ID and Revision (ID_REV).................................................................................................................................................................... |
260 |
14.2.9.2 |
Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... |
261 |
14.2.9.3 |
Hardware Configuration Register (HW_CFG)............................................................................................................................................... |
262 |
14.2.9.4 |
Power Management Control Register (PMT_CTRL) .................................................................................................................................... |
264 |
14.2.9.5 |
General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... |
267 |
14.2.9.6 |
General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... |
268 |
14.2.9.7 |
Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. |
269 |
14.2.9.8 |
Reset Control Register (RESET_CTL) ......................................................................................................................................................... |
270 |
14.3 Host MAC Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
271 |
|
14.3.1 Host MAC Control Register (HMAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
272 |
|
14.3.2 Host MAC Address High Register (HMAC_ADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
275 |
|
14.3.3 Host MAC Address Low Register (HMAC_ADDRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
276 |
|
14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) . . . . . . . . . . . . . . . . . . . . . . . |
277 |
|
14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL). . . . . . . . . . . . . . . . . . . . . . . . |
278 |
|
14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
279 |
|
14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
280 |
|
14.3.8 Host MAC Flow Control Register (HMAC_FLOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
281 |
|
14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
283 |
|
Revision 1.4 (08-19-08) |
8 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) . . . . . . . . . . . . . . . . . . . . . 286 14.4 Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 14.4.1 Virtual PHY Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 14.4.2 Port 1 & 2 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.4.2.1 |
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) ................................................................................................................ |
289 |
14.4.2.2 |
Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) ..................................................................................................................... |
291 |
14.4.2.3 |
Port x PHY Identification MSB Register (PHY_ID_MSB_x).......................................................................................................................... |
293 |
14.4.2.4 |
Port x PHY Identification LSB Register (PHY_ID_LSB_x)............................................................................................................................ |
294 |
14.4.2.5 |
Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) ................................................................................................... |
295 |
14.4.2.6 |
Port x PHY Auto-Negotiation Link Partner Base Page Ability Register (PHY_AN_LP_BASE_ABILITY_x) ................................................. |
298 |
14.4.2.7 |
Port x PHY Auto-Negotiation Expansion Register (PHY_AN_EXP_x) ......................................................................................................... |
300 |
14.4.2.8 |
Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x)..................................................................................... |
301 |
14.4.2.9 |
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) .............................................................................................................. |
302 |
14.4.2.10 |
Port x PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND_x) .......................................................... |
304 |
14.4.2.11 |
Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x)........................................................................................... |
306 |
14.4.2.12 |
Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) ............................................................................................................ |
307 |
14.4.2.13 |
Port x PHY Special Control/Status Register (PHY_SPECIAL_CONTROL_STATUS_x).............................................................................. |
308 |
14.5 Switch Fabric Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
309 |
|
14.5.1 |
General Switch CSRs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
320 |
14.5.1.1 |
Switch Device ID Register (SW_DEV_ID) .................................................................................................................................................... |
320 |
14.5.1.2 |
Switch Reset Register (SW_RESET) ........................................................................................................................................................... |
321 |
14.5.1.3 |
Switch Global Interrupt Mask Register (SW_IMR)........................................................................................................................................ |
322 |
14.5.1.4 |
Switch Global Interrupt Pending Register (SW_IPR).................................................................................................................................... |
323 |
14.5.2 Switch Port 0, Port 1, and Port 2 CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
324 |
|
14.5.2.1 |
Port x MAC Version ID Register (MAC_VER_ID_x) ..................................................................................................................................... |
324 |
14.5.2.2 |
Port x MAC Receive Configuration Register (MAC_RX_CFG_x) ................................................................................................................. |
325 |
14.5.2.3 |
Port x MAC Receive Undersize Count Register (MAC_RX_UNDSZE_CNT_x) ........................................................................................... |
326 |
14.5.2.4 |
Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x).......................................................................................................... |
327 |
14.5.2.5 |
Port x MAC Receive 65 to 127 Byte Count Register (MAC_RX_65_TO_127_CNT_x)................................................................................ |
328 |
14.5.2.6 |
Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x)............................................................................ |
329 |
14.5.2.7 |
Port x MAC Receive 256 to 511 Byte Count Register (MAC_RX_256_TO_511_CNT_x)............................................................................ |
330 |
14.5.2.8 |
Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x)........................................................................ |
331 |
14.5.2.9 |
Port x MAC Receive 1024 to Max Byte Count Register (MAC_RX_1024_TO_MAX_CNT_x) ..................................................................... |
332 |
14.5.2.10 |
Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) ............................................................................................. |
333 |
14.5.2.11 |
Port x MAC Receive OK Count Register (MAC_RX_PKTOK_CNT_x)......................................................................................................... |
334 |
14.5.2.12 |
Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x).......................................................................................... |
335 |
14.5.2.13 |
Port x MAC Receive Multicast Count Register (MAC_RX_MULCST_CNT_x) ............................................................................................. |
336 |
14.5.2.14 |
Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) ........................................................................................... |
337 |
14.5.2.15 |
Port x MAC Receive Pause Frame Count Register (MAC_RX_PAUSE_CNT_x) ........................................................................................ |
338 |
14.5.2.16 |
Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x)........................................................................................ |
339 |
14.5.2.17 |
Port x MAC Receive Jabber Error Count Register (MAC_RX_JABB_CNT_x) ............................................................................................. |
340 |
14.5.2.18 |
Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) ...................................................................................... |
341 |
14.5.2.19 |
Port x MAC Receive Packet Length Count Register (MAC_RX_PKTLEN_CNT_x) ..................................................................................... |
342 |
14.5.2.20 |
Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) ................................................................ |
343 |
14.5.2.21 |
Port x MAC Receive Symbol Error Count Register (MAC_RX_SYMBOL_CNT_x) ...................................................................................... |
344 |
14.5.2.22 |
Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) .................................................................................... |
345 |
14.5.2.23 |
Port x MAC Transmit Configuration Register (MAC_TX_CFG_x) ................................................................................................................ |
346 |
14.5.2.24 |
Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) .................................................................................. |
347 |
14.5.2.25 |
Port x MAC Transmit Deferred Count Register (MAC_TX_DEFER_CNT_x) ............................................................................................... |
348 |
14.5.2.26 |
Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) ................................................................................................... |
349 |
14.5.2.27 |
Port x MAC Transmit OK Count Register (MAC_TX_PKTOK_CNT_x) ........................................................................................................ |
350 |
14.5.2.28 |
Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) ......................................................................................................... |
351 |
14.5.2.29 |
Port x MAC Transmit 65 to 127 Byte Count Register (MAC_TX_65_TO_127_CNT_x) ............................................................................... |
352 |
14.5.2.30 |
Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) ........................................................................... |
353 |
14.5.2.31 |
Port x MAC Transmit 256 to 511 Byte Count Register (MAC_TX_256_TO_511_CNT_x) ........................................................................... |
354 |
14.5.2.32 |
Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) ....................................................................... |
355 |
14.5.2.33 |
Port x MAC Transmit 1024 to Max Byte Count Register (MAC_TX_1024_TO_MAX_CNT_x)..................................................................... |
356 |
14.5.2.34 |
Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) .......................................................................................... |
357 |
14.5.2.35 |
Port x MAC Transmit Packet Length Count Register (MAC_TX_PKTLEN_CNT_x) .................................................................................... |
358 |
14.5.2.36 |
Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) .......................................................................................... |
359 |
14.5.2.37 |
Port x MAC Transmit Multicast Count Register (MAC_TX_MULCST_CNT_x) ............................................................................................ |
360 |
14.5.2.38 |
Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) ................................................................................... |
361 |
14.5.2.39 |
Port x MAC Transmit Excessive Collision Count Register (MAC_TX_EXCCOL_CNT_x)............................................................................ |
362 |
14.5.2.40 |
Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) ............................................................................. |
363 |
14.5.2.41 |
Port x MAC Transmit Multiple Collision Count Register (MAC_TX_MULTICOL_CNT_x) ............................................................................ |
364 |
14.5.2.42 |
Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x)................................................................................ |
365 |
14.5.2.43 |
Port x MAC Interrupt Mask Register (MAC_IMR_x) ..................................................................................................................................... |
366 |
14.5.2.44 |
Port x MAC Interrupt Pending Register (MAC_IPR_x) ................................................................................................................................. |
367 |
14.5.3 |
Switch Engine CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
368 |
14.5.3.1 |
Switch Engine ALR Command Register (SWE_ALR_CMD) ........................................................................................................................ |
368 |
14.5.3.2 |
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) .......................................................................................................... |
369 |
14.5.3.3 |
Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) .......................................................................................................... |
370 |
14.5.3.4 |
Switch Engine ALR Read Data 0 Register (SWE_ALR_RD_DAT_0)........................................................................................................... |
372 |
14.5.3.5 |
Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1)........................................................................................................... |
373 |
14.5.3.6 |
Switch Engine ALR Command Status Register (SWE_ALR_CMD_STS) .................................................................................................... |
375 |
14.5.3.7 |
Switch Engine ALR Configuration Register (SWE_ALR_CFG) .................................................................................................................... |
376 |
SMSC LAN9311/LAN9311i |
9 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface |
|
|
|
Datasheet |
14.5.3.8 |
Switch Engine VLAN Command Register (SWE_VLAN_CMD).................................................................................................................... |
377 |
14.5.3.9 |
Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA).......................................................................................................... |
378 |
14.5.3.10 |
Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) .......................................................................................................... |
379 |
14.5.3.11 |
Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS) ............................................................................................... |
380 |
14.5.3.12 |
Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG)................................................................................. |
381 |
14.5.3.13 |
Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA) ...................................................................... |
382 |
14.5.3.14 |
Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) ....................................................................... |
383 |
14.5.3.15 |
Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS) ............................................................ |
384 |
14.5.3.16 |
Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG)............................................................................. |
385 |
14.5.3.17 |
Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) ..................................................................................... |
387 |
14.5.3.18 |
Switch Engine Admit Only VLAN Register (SWE_ADMT_ONLY_VLAN)..................................................................................................... |
388 |
14.5.3.19 |
Switch Engine Port State Register (SWE_PORT_STATE)........................................................................................................................... |
389 |
14.5.3.20 |
Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE) ................................................................................................................ |
390 |
14.5.3.21 |
Switch Engine Port Mirroring Register (SWE_PORT_MIRROR).................................................................................................................. |
391 |
14.5.3.22 |
Switch Engine Ingress Port Type Register (SWE_INGRSS_PORT_TYP) ................................................................................................... |
392 |
14.5.3.23 |
Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) .......................................................................................................... |
393 |
14.5.3.24 |
Switch Engine Admit Non Member Register (SWE_ADMT_N_MEMBER)................................................................................................... |
394 |
14.5.3.25 |
Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) .................................................................................... |
395 |
14.5.3.26 |
Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD)......................................................................................... |
396 |
14.5.3.26.1Ingress Rate Table Registers................................................................................................. |
397 |
|
14.5.3.27 |
Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS) .................................................................... |
398 |
14.5.3.28 |
Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA)............................................................................... |
399 |
14.5.3.29 |
Switch Engine Ingress Rate Read Data Register (SWE_INGRSS_RATE_RD_DATA) ............................................................................... |
400 |
14.5.3.30 |
Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) .................................................................................. |
401 |
14.5.3.31 |
Switch Engine Port 1 Ingress Filtered Count Register (SWE_FILTERED_CNT_1) ..................................................................................... |
402 |
14.5.3.32 |
Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) ..................................................................................... |
403 |
14.5.3.33 |
Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) ........................................ |
404 |
14.5.3.34 |
Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ........................................... |
405 |
14.5.3.35 |
Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2) ........................................... |
406 |
14.5.3.36 |
Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) ............................................................................... |
407 |
14.5.3.37 |
Switch Engine Port 1 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_1) .................................................................................. |
408 |
14.5.3.38 |
Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) .................................................................................. |
409 |
14.5.3.39 |
Switch Engine Interrupt Mask Register (SWE_IMR)..................................................................................................................................... |
410 |
14.5.3.40 |
Switch Engine Interrupt Pending Register (SWE_IPR)................................................................................................................................. |
411 |
14.5.4 |
Buffer Manager CSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 413 |
14.5.4.1 |
Buffer Manager Configuration Register (BM_CFG) ...................................................................................................................................... |
413 |
14.5.4.2 |
Buffer Manager Drop Level Register (BM_DROP_LVL)............................................................................................................................... |
414 |
14.5.4.3 |
Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL)............................................................................................... |
415 |
14.5.4.4 |
Buffer Manager Flow Control Resume Level Register (BM_FC_RESUME_LVL) ........................................................................................ |
416 |
14.5.4.5 |
Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL)............................................................................................................. |
417 |
14.5.4.6 |
Buffer Manager Port 0 Drop Count Register (BM_DRP_CNT_SRC_MII) .................................................................................................... |
418 |
14.5.4.7 |
Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) ....................................................................................................... |
419 |
14.5.4.8 |
Buffer Manager Port 2 Drop Count Register (BM_DRP_CNT_SRC_2) ....................................................................................................... |
420 |
14.5.4.9 |
Buffer Manager Reset Status Register (BM_RST_STS) .............................................................................................................................. |
421 |
14.5.4.10 |
Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD) ................................................................ |
422 |
14.5.4.11 |
Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) ........................................................... |
423 |
14.5.4.12 |
Buffer Manager Random Discard Table Read Data Register (BM_RNDM_DSCRD_TBL_RDATA)............................................................ |
424 |
14.5.4.13 |
Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) ................................................................................................... |
425 |
14.5.4.14 |
Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) .................................................................. |
427 |
14.5.4.15 |
Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_02_03) .................................................................. |
428 |
14.5.4.16 |
Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) .................................................................. |
429 |
14.5.4.17 |
Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_12_13) .................................................................. |
430 |
14.5.4.18 |
Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) .................................................................. |
431 |
14.5.4.19 |
Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (BM_EGRSS_RATE_22_23) .................................................................. |
432 |
14.5.4.20 |
Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) .......................................................................................... |
433 |
14.5.4.21 |
Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) ............................................................................................. |
434 |
14.5.4.22 |
Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) ............................................................................................. |
435 |
14.5.4.23 |
Buffer Manager Port 0 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_MII) ................................................................... |
436 |
14.5.4.24 |
Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) ...................................................................... |
437 |
14.5.4.25 |
Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) ...................................................................... |
438 |
14.5.4.26 |
Buffer Manager Interrupt Mask Register (BM_IMR) ..................................................................................................................................... |
439 |
14.5.4.27 |
Buffer Manager Interrupt Pending Register (BM_IPR) ................................................................................................................................. |
440 |
Chapter 15 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
15.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
15.2 Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
15.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
15.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
15.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
15.5.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
15.5.2 Reset and Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
15.5.3 Power-On Configuration Strap Valid Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
15.5.4 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
15.5.5 PIO Burst Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
15.5.6 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Revision 1.4 (08-19-08) |
10 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface |
|
|
Datasheet |
|
|
15.5.7 |
RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
451 |
15.5.8 |
PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
452 |
15.5.9 |
TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
453 |
15.5.10 Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
454 |
|
15.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
455 |
|
Chapter 16 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.1 128-VTQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
16.2 128-XVTQFP Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Chapter 17 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
SMSC LAN9311/LAN9311i |
11 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
List of Figures
Figure 2.1 Internal LAN9311/LAN9311i Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2.2 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW) . . . . . . . . . . . . . . . . . . . . 27 Figure 4.1 PME and PME_INT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 5.1 Functional Interrupt Register Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 6.1 Switch Fabric CSR Write Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 6.2 Switch Fabric CSR Read Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 6.3 ALR Table Entry Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 6.4 Switch Engine Transmit Queue Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 6.5 Switch Engine Transmit Queue Calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 6.6 VLAN Table Entry Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 6.7 Switch Engine Ingress Flow Priority Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 6.8 Switch Engine Ingress Flow Priority Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 6.9 Hybrid Port Tagging and Un-tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 7.1 Port x PHY Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 7.2 100BASE-TX Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 7.3 100BASE-TX Receive Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 7.4 Direct Cable Connection vs. Cross-Over Cable Connection . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 8.1 Little Endian Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 8.2 Big Endian Byte Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 8.3 Functional Timing for PIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 8.4 Functional Timing for PIO Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation . . . . . . . . . . . . . . . . . . . . 109 Figure 8.6 Functional Timing for RX Data FIFO Direct PIO Burst Read Operation . . . . . . . . . . . . . . . 110 Figure 8.7 Functional Timing for PIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 8.8 Functional Timing for TX Data FIFO Direct PIO Write Operation . . . . . . . . . . . . . . . . . . . . 112 Figure 9.1 VLAN Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 9.2 Example EEPROM MAC Address Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 9.3 Simplified Host TX Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 9.4 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 9.5 TX Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 9.6 TX Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 9.7 Host Receive Routine Using Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 9.8 Host Receive Routine Using Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 9.9 RX Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 10.1 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 10.2 I2C Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 10.3 I2C EEPROM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 10.4 I2C EEPROM Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 10.5 I2C EEPROM Sequential Byte Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 10.6 I2C EEPROM Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 10.7 EEPROM ERASE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 10.8 EEPROM ERAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 10.9 EEPROM EWDS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 10.10EEPROM EWEN Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 10.11EEPROM READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 10.12EEPROM WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 10.13EEPROM WRAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 10.14EEPROM Loader Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 11.1 IEEE 1588 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 11.2 IEEE 1588 Message Time Stamp Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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Datasheet
Figure 14.1 LAN9311/LAN9311i Base Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 15.1 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Figure 15.2 nRST Reset Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Figure 15.3 Power-On Configuration Strap Latching Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Figure 15.4 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 Figure 15.5 PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Figure 15.6 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Figure 15.8 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Figure 15.9 TX Data FIFO Direct PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Figure 15.10Microwire Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Figure 16.1 LAN9311 128-VTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Figure 16.2 LAN9311 128-VTQFP Recommended PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . 457 Figure 16.3 LAN9311/LAN9311i 128-XVTQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Figure 16.4 LAN9311/LAN9311i 128-XVTQFP Recommended PCB Land Pattern . . . . . . . . . . . . . . . . 459
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
List of Tables
Table 1.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 1.2 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3.1 LAN Port 1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3.2 LAN Port 2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 3.3 LAN Port 1 & 2 Power and Common Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 3.4 Host Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3.5 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 3.6 Dedicated Configuration Strap Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 3.7 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 3.8 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 3.9 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 3.10 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 4.1 Reset Sources and Affected LAN9311/LAN9311i Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 4.2 Soft-Strap Configuration Strap Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 6.2 Spanning Tree States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 6.3 Typical Ingress Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 6.4 Typical Broadcast Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 6.5 Typical Egress Rate Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 7.1 Default PHY Serial MII Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 7.2 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 7.3 PHY Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 8.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 8.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 9.1 Address Filtering Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 9.2 Wake-Up Frame Filter Register Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 9.3 Filter i Byte Mask Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 9.4 Filter i Command Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 9.5 Filter i Offset Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 9.6 Filter i CRC-16 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 9.7 EEPROM Byte Ordering and Register Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 9.8 TX/RX FIFO Configurable Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 9.9 Valid TX/RX FIFO Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 9.10 TX Command 'A' Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 9.11 TX Command 'B' Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 9.12 TX DATA Start Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 10.1 I2C/Microwire Master Serial Management Pins Characteristics. . . . . . . . . . . . . . . . . . . . . . 138 Table 10.2 I2C EEPROM Size Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 10.3 Microwire EEPROM Size Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 10.4 Microwire Command Set for 7 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 10.5 Microwire Command Set for 9 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 10.6 Microwire Command Set for 11 Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Table 10.7 EEPROM Contents Format Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 10.8 EEPROM Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 11.1 IEEE 1588 Message Type Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 11.2 Time Stamp Capture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Table 11.3 PTP Multicast Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 11.4 Typical IEEE 1588 Clock Addend Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 13.1 LED Operation as a Function of LED_CFG[9:8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Table 14.1 System Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 14.2 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
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Datasheet
Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map . . . . . . . . . . . . 241 Table 14.4 Virtual PHY MII Serially Adressable Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values . . . . . . . . . . . . . . . . . . . . 256 Table 14.6 Host MAC Adressable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 14.8 10BASE-T Full Duplex Advertisement Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Table 14.10MODE[2:0] Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Table 14.11Auto-MDIX Enable and Auto-MDIX State Bit Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 305 Table 14.12Indirectly Accessible Switch Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 309 Table 14.13Metering/Color Table Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Table 15.1 Supply and Current (10BASE-T Full-Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Table 15.2 Supply and Current (100BASE-TX Full-Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Table 15.3 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Table 15.4 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 Table 15.5 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Table 15.6 nRST Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Table 15.7 Power-On Configuration Strap Latching Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Table 15.8 PIO Read Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 Table 15.9 PIO Burst Read Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Table 15.10RX Data FIFO Direct PIO Read Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Table 15.11RX Data FIFO Direct PIO Burst Read Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . 451 Table 15.12PIO Write Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 Table 15.13TX Data FIFO Direct PIO Write Cycle Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Table 15.14Microwire Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Table 15.15LAN9311/LAN9311iCrystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Table 16.1 LAN9311 128-VTQFP Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Table 17.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 1 Preface
1.1General Terms
100BT |
100BASE-T (100Mbps Fast Ethernet, IEEE 802.3u) |
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ADC |
Analog-to-Digital Converter |
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ALR |
Address Logic Resolution |
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BLW |
Baseline Wander |
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BM |
Buffer Manager - Part of the switch fabric |
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BPDU |
Bridge Protocol Data Unit - Messages which carry the Spanning Tree |
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Protocol information |
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Byte |
8-bits |
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CSMA/CD |
Carrier Sense Multiple Access / Collision Detect |
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CSR |
Control and Status Registers |
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CTR |
Counter |
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DA |
Destination Address |
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DWORD |
32-bits |
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EPC |
EEPROM Controller |
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FCS |
Frame Check Sequence - The extra checksum characters added to the end |
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of an Ethernet frame, used for error detection and correction. |
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FIFO |
First In First Out buffer |
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FSM |
Finite State Machine |
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GPIO |
General Purpose I/O |
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HBI |
Host Bus Interface. The physical bus connecting the LAN9311/LAN9311i to |
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the host. Also referred to as the Host Bus. |
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HBIC |
Host Bus Interface Controller. The hardware module that interfaces |
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theLAN9311/LAN9311i to the HBI. |
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Host |
External system (Includes processor, application software, etc.) |
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IGMP |
Internet Group Management Protocol |
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Inbound |
Refers to data input to the LAN9311/LAN9311i from the host |
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Level-Triggered Sticky Bit |
This type of status bit is set whenever the condition that it represents is |
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asserted. The bit remains set until the condition is no longer true, and the |
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status bit is cleared by writing a zero. |
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lsb |
Least Significant Bit |
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LSB |
Least Significant Byte |
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MDI |
Medium Dependant Interface |
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MDIX |
Media Independent Interface with Crossover |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
MII |
Media Independent Interface |
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MIIM |
Media Independent Interface Management |
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MIL |
MAC Interface Layer |
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MLD |
Multicast Listening Discovery |
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MLT-3 |
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method |
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where a change in the logic level represents a code bit “1” and the logic |
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msb |
Most Significant Bit |
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MSB |
Most Significant Byte |
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NRZI |
Non Return to Zero Inverted. This encoding method inverts the signal for a |
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“1” and leaves the signal unchanged for a “0” |
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N/A |
Not Applicable |
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NC |
No Connect |
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OUI |
Organizationally Unique Identifier |
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Outbound |
Refers to data output from the LAN9311/LAN9311i to the host |
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PIO cycle |
Program I/O cycle. An SRAM-like read or write cycle on the HBI. |
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PISO |
Parallel In Serial Out |
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PLL |
Phase Locked Loop |
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PTP |
Precision Time Protocol |
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RESERVED |
Refers to a reserved bit field or address. Unless otherwise noted, reserved |
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bits must always be zero for write operations. Unless otherwise noted, values |
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are not guaranteed when reading reserved bits. Unless otherwise noted, do |
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not read or write to reserved addresses. |
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RTC |
Real-Time Clock |
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SA |
Source Address |
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SFD |
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble |
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of an Ethernet frame. |
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SIPO |
Serial In Parallel Out |
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SMI |
Serial Management Interface |
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SQE |
Signal Quality Error (also known as “heartbeat”) |
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SSD |
Start of Stream Delimiter |
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UDP |
User Datagram Protocol - A connectionless protocol run on top of IP |
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networks |
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UUID |
Universally Unique IDentifier |
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WORD |
16-bits |
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Revision 1.4 (08-19-08) |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
1.2Buffer Types
Table 1.1 describes the pin buffer type notation used in Chapter 3, "Pin Description and Configuration," on page 26 and throughout this document.
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Table 1.1 Buffer Types |
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BUFFER TYPE |
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DESCRIPTION |
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IS |
Schmitt-triggered Input |
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O8 |
Output with 8mA sink and 8mA source |
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OD8 |
Open-drain output with 8mA sink |
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O12 |
Output with 12mA sink and 12mA source |
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OD12 |
Open-drain output with 12mA sink |
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PU |
50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull- |
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ups are always enabled. |
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Note: |
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on |
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internal resistors to drive signals external to the LAN9311/LAN9311i. When |
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connected to a load that must be pulled high, an external resistor must be added. |
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PD |
50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal |
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pull-downs are always enabled. |
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Note: |
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely |
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on internal resistors to drive signals external to the LAN9311/LAN9311i. When |
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connected to a load that must be pulled low, an external resistor must be added. |
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AI |
Analog input |
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AO |
Analog output |
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AIO |
Analog bi-directional |
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ICLK |
Crystal oscillator input pin |
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OCLK |
Crystal oscillator output pin |
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P |
Power pin |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
1.3Register Nomenclature
Table 1.2 describes the register bit attribute notation used throughout this document.
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Table 1.2 Register Bit Types |
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REGISTER BIT TYPE |
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NOTATION |
REGISTER BIT DESCRIPTION |
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R |
Read: A register or bit with this attribute can be read. |
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W |
Read: A register or bit with this attribute can be written. |
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RO |
Read only: Read only. Writes have no effect. |
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WO |
Write only: If a register or bit is write-only, reads will return unspecified data. |
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WC |
Write One to Clear: writing a one clears the value. Writing a zero has no effect |
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WAC |
Write Anything to Clear: writing anything clears the value. |
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RC |
Read to Clear: Contents is cleared after the read. Writes have no effect. |
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LL |
Latch Low: Clear on read of register. |
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LH |
Latch High: Clear on read of register. |
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SC |
Self-Clearing: Contents are self-cleared after the being set. Writes of zero have no |
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effect. Contents can be read. |
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SS |
Self-Setting: Contents are self-setting after being cleared. Writes of one have no |
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effect. Contents can be read. |
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RO/LH |
Read Only, Latch High: Bits with this attribute will stay high until the bit is read. After |
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it is read, the bit will either remain high if the high condition remains, or will go low if |
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the high condition has been removed. If the bit has not been read, the bit will remain |
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high regardless of a change to the high condition. This mode is used in some Ethernet |
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PHY registers. |
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NASR |
Not Affected by Software Reset. The state of NASR bits do not change on assertion |
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of a software reset. |
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RESERVED |
Reserved Field: Reserved fields must be written with zeros to ensure future |
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compatibility. The value of reserved bits is not guaranteed on a read. |
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Many of these register bit notations can be combined. Some examples of this are shown below:
R/W: Can be written. Will return current setting on a read.
R/WAC: Will return current setting on a read. Writing anything clears the bit.
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Revision 1.4 (08-19-08) |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 2 Introduction
2.1General Description
The LAN9311/LAN9311i is a full featured, 2 port 10/100 managed Ethernet switch designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9311/LAN9311i combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY transceivers, and host bus interface. The LAN9311/LAN9311i complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol specification and 802.1D/802.1Q network management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications.
At the core of the LAN9311/LAN9311i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed, and a 1K entry forwarding table provides ample room for MAC address forwarding tables. Each port is allocated a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the buffer manager block within the switch fabric. All aspects of the switch fabric are managed via the switch fabric configuration and status registers, which are indirectly accessible via the memory mapped system control and status registers.
The LAN9311/LAN9311i provides 2 switched ports. Each port is fully compliant with the IEEE 802.3 standard and all internal MACs and PHYs support full/half duplex 10BASE-T and 100BASE-TX operation. The LAN9311/LAN9311i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the Host MAC are used to connect the LAN9311/LAN9311i switch fabric to the host bus interface. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control. Automatic 32-bit CRC generation/checking and automatic payload padding are supported to further reduce CPU overhead. 2K jumbo packet (2048 byte) support allows for oversized packet transfers, effectively increasing throughput while deceasing CPU load. All MAC and PHY related settings are fully configurable via their respective registers within the LAN9311/LAN9311i.
The integrated Host Bus Interface (HBI) easily interfaces to most 16-bit embedded CPU’s via a simple SRAM like interface, enabling switch fabric access via the internal Host MAC and allowing full control over the LAN9311/LAN9311i via memory mapped system control and status registers. The HBI supports 16-bit operation with big, little, and mixed endian operations. Four separate FIFO mechanisms (TX/RX Data FIFO’s, TX/RX Status FIFO’s) interface the HBI to the Host MAC and facilitate the transferring of packet data and status information between the host CPU and the switch fabric. The LAN9311/LAN9311i also provides power management features which allow for wake on LAN, wake on link status change (energy detect), and magic packet wakeup detection. A configurable host interrupt pin allows the device to inform the host CPU of any internal interrupts.
The LAN9311/LAN9311i contains an I2C/Microwire master EEPROM controller for connection to an optional EEPROM. This allows for the storage and retrieval of static data. The internal EEPROM Loader can be optionally configured to automatically load stored configuration settings from the EEPROM into the LAN9311/LAN9311i at reset.
In addition to the primary functionality described above, the LAN9311/LAN9311i provides additional features designed for extended functionality. These include a configurable 16-bit General Purpose Timer (GPT), a 32-bit 25MHz free running counter, a 12-bit configurable GPIO/LED interface, and IEEE 1588 time stamping on all ports and select GPIOs. The IEEE time stamp unit provides a 64-bit tunable clock for accurate PTP timing and a timer comparator to allow time based interrupt generation.
The LAN9311/LAN9311i’s performance, features and small size make it an ideal solution for many applications in the consumer electronics and industrial automation markets. Targeted applications include: set top boxes (cable, satellite and IP), digital televisions, digital video recorders, voice over IP and video phone systems, home gateways, and test and measurement equipment.
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DATASHEET |
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.1 Revision |
2.2 |
Block Diagram |
08)-19-(08 4 |
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IEEE 1588 |
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Time Stamp |
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To Ethernet |
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MII |
1Port |
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Queues4 |
Dynamic QoS |
Queues4 |
Dynamic QoS |
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0Port |
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MDIO |
MDIO |
Virtual PHY |
10/100 |
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10/100 |
10/100 |
MII |
Registers |
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PHY |
MDIO |
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MAC |
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MAC |
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Registers |
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Host MAC |
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IEEE 1588 |
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MDIO |
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Search |
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Switch Engine |
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Time Stamp |
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Engine |
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TX/RX FIFOs |
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IEEE 1588 |
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Buffer Manager |
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Frame |
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21 DATASHEET |
Time Stamp |
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2Port |
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Queues4 |
Dynamic QoS |
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Buffers |
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To Ethernet |
10/100 |
MII |
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10/100 |
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Switch |
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Register |
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Host Bus Interface |
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To 16-bit |
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Registers |
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Access |
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PHY |
MDIO |
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MAC |
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(CSRs) |
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MUX |
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Host Bus |
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Registers |
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System |
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EEPROM Loader |
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Switch Fabric |
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Registers |
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(CSRs) |
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Datasheet |
10/100 Port Two |
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Interface CPU PCI-Non Bit-16 with Switch Ethernet Managed |
LAN9311/LAN9311i SMSC
GPIO/LED |
IEEE 1588 |
System |
System |
GP Timer |
EEPROM Controller |
I2C/Microwire |
Time Stamp |
Interrupt |
Clocks/ |
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Controller |
Reset/PME |
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I2C (master) |
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Clock/Events |
Controller |
Free-Run |
Microwire (master) |
To optional |
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Controller |
Clk |
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LAN9311/LAN9311i |
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EEPROM |
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To optional GPIOs/LEDs |
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IRQ |
External |
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25MHz Crystal |
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Figure 2.1 Internal LAN9311/LAN9311i Block Diagram
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
2.2.1System Clocks/Reset/PME Controller
A clock module contained within the LAN9311/LAN9311i generates all the system clocks required by the device. This module interfaces directly with the external 25MHz crystal/oscillator to generate the required clock divisions for each internal module, with the exception of the 1588 clocks, which are generated in the 1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit free-running clock are provided by this module for general purpose use.
The LAN9311/LAN9311i reset events are categorized as chip-level resets, multi-module resets, and single-module resets.
A chip-level reset is initiated by assertion of any of the following input events:
Power-On Reset
nRST Pin Reset
A multi-module reset is initiated by assertion of the following:
Digital Reset - DIGITAL_RST (bit 0) in the Reset Control Register (RESET_CTL)
-Resets all LAN9311/LAN9311i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY)
Soft Reset - SRST (bit 0) in the Hardware Configuration Register (HW_CFG)
-Resets the HBI, Host MAC, and System CSRs below address 100h
A single-module reset is initiated by assertion of the following:
Port 2 PHY Reset - PHY2_RST (bit 2) in the Reset Control Register (RESET_CTL) or Reset (bit
15)in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
-Resets the Port 2 PHY
Port 1 PHY Reset - PHY1_RST (bit 1) in the Reset Control Register (RESET_CTL) or Reset (bit 15) in the Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
-Resets the Port 1 PHY
Virtual PHY Reset - VPHY_RST (bit 0) in the Reset Control Register (RESET_CTL), (bit 10) in the Power Management Control Register (PMT_CTRL), or Reset (bit 15) in the Virtual PHY Basic Control Register (VPHY_BASIC_CTRL)
-Resets the Virtual PHY
The LAN9311/LAN9311i supports numerous power management and wakeup features. The Port 1 & 2 PHYs provide general power-down and energy detect power-down modes, which allow a reduction in PHY power consumption. The Host MAC provides wake-up frame detection and magic packet detection modes. The LAN9311/LAN9311i can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup events.
2.2.2System Interrupt Controller
The LAN9311/LAN9311i provides a multi-tier programmable interrupt structure which is controlled by the System Interrupt Controller. At the top level are the Interrupt Status Register (INT_STS) and Interrupt Enable Register (INT_EN). These registers aggregate and control all interrupts from the various LAN9311/LAN9311i sub-modules. The LAN9311/LAN9311i is capable of generating interrupt events from the following:
1588 Time Stamp
Switch Fabric
Ethernet PHYs
GPIOs
Host MAC (FIFOs, power management)
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SMSC LAN9311/LAN9311i |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
General Purpose Timer
Software (general purpose)
A dedicated programmable IRQ interrupt output pin is provided for external indication of any LAN9311/LAN9311i interrupts. The IRQ pin is controlled via the Interrupt Configuration Register (IRQ_CFG), which allows configuration of the IRQ buffer type, polarity, and de-assertion interval.
2.2.3Switch Fabric
The Switch Fabric consists of the following major function blocks:
10/100 MACs
There is one 10/100 Ethernet MAC per switch fabric port, which provides basic 10/100 Ethernet functionality, including transmission deferral, collision back-off/retry, TX/RX FCS checking/generation, TX/RX pause flow control, and transmit back pressure. The 10/100 MACs act as an interface between the switch engine and the 10/100 PHYs (for ports 1 and 2). The port 0 10/100 MAC interfaces the switch engine to the Host MAC. Each 10/100 MAC includes RX and TX FIFOs and per port statistic counters.
Switch Engine
This block, consisting of a 3 port VLAN layer 2 switching engine, provides the control for all forwarding/filtering rules and supports untagged, VLAN tagged, and priority tagged frames. The switch engine provides an extensive feature set which includes spanning tree protocol support, multicast packet filtering and Quality of Service (QoS) packet prioritization by VLAN tag, destination address, and port default value or DIFFSERV/TOS, allowing for a range of prioritization implementations. A 1K entry forwarding table provides ample room for MAC address forwarding tables.
Buffer Manager
This block controls the free buffer space, multi-level transmit queues, transmission scheduling, and packet dropping of the switch fabric. 32K of buffer RAM allows for the storage of multiple packets while forwarding operations are completed. Each port is allocated 1a cluster of 4 dynamic QoS queues which allow each queue size to grow and shrink with traffic, effectively utilizing all available memory. This memory is managed dynamically via the Buffer Manager block.
Switch CSRs
This block contains all switch related control and status registers, and allows all aspects of the switch fabric to be managed. These registers are indirectly accessible via the memory mapped system control and status registers
2.2.4Ethernet PHYs
The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface. The Virtual PHY provides the virtual functionality of a PHY and allows connection of the Host MAC to port 0 of the switch fabric as if it was connected to a single port PHY. All PHYs comply with the IEEE 802.3 Physical Layer for Twisted Pair Ethernet and can be configured for full/half duplex 100 Mbps (100BASE-TX) or 10Mbps (10BASE-T) Ethernet operation. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set.
2.2.5Host Bus Interface (HBI)
The Host Bus Interface (HBI) module provides a high-speed asynchronous SRAM-like slave interface that facilitates communication between the LAN9311/LAN9311i and a host system. The HBI allows access to the System CSRs and handles byte swapping based on the dynamic endianess select. The HBI interfaces to the switch fabric via the Host MAC, which contains the TX/RX Data and Status FIFOs, Host MAC registers and power management features. The main features of the HBI are:
Asynchronous 16-bit Host Bus Interface
-Host Data Bus Endianess Control
-Direct FIFO Access Modes
SMSC LAN9311/LAN9311i |
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Revision 1.4 (08-19-08) |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
System CSRs Access
Interrupt Support
2.2.6Host MAC
The Host MAC incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3- compliant node and provides an interface between the Host Bus Interface (HBI) and the Ethernet PHYs and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). The FIFOs are a conduit between the HBI and the Host MAC through which all transmitted and received data and status information is passed. An additional bus is used to access the Host MAC CSR’s via the Host MAC CSR Interface Command Register (MAC_CSR_CMD) and Host MAC CSR Interface Data Register (MAC_CSR_DATA) system registers.
On the back end, the Host MAC interfaces with the 10/100 Ethernet PHY’s (Virtual PHY, Port 1 PHY, Port 2 PHY) via an internal SMI (Serial Management Interface) bus. This allows the Host MAC access to the PHY’s internal registers via the Host MAC MII Access Register (HMAC_MII_ACC) and Host MAC MII Data Register (HMAC_MII_DATA). The Host MAC interfaces to the Switch Engine Port 0 via an internal MII (Media Independent Interface) connection allowing for incoming and outgoing Ethernet packet transfers.
The Host MAC can operate at either 100Mbps or 10Mbps in both half-duplex or full-duplex modes. When operating in half-duplex mode, the Host MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the Host MAC complies with IEEE 802.3 full-duplex operation standard.
2.2.7EEPROM Controller/Loader
The EEPROM Controller is an I2C/Microwire master module which interfaces an optional external EEPROM with the system register bus and the EEPROM Loader. Multiple types (I2C/Microwire) and sizes of external EEPROMs are supported. Configuration of the EEPROM type and size are accomplished via the eeprom_type_strap and eeprom_size_strap[1:0] configuration straps respectively. Various commands are supported for each EEPROM type, allowing for the storage and retrieval of static data. The I2C interface conforms to the Philips I2C-Bus Specification.
The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs. The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the LAN9311/LAN9311i at reset. The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset Control Register (RESET_CTL)), or upon the issuance of a RELOAD command via the EEPROM Command Register (E2P_CMD).
2.2.81588 Time Stamp
The IEEE 1588 Time Stamp modules provide hardware support for the IEEE 1588 Precision Time Protocol (PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping, and time driven event generation. Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9311/LAN9311i as a whole may function as a boundary clock.
A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related functions. The IEEE 1588 Clock/Events block provides IEEE 1588 clock comparison based interrupt generation and time stamp related GPIO event generation. Two LAN9311/LAN9311i GPIO pins (GPIO[8:9]) can be used to trigger a time stamp capture when configured as an input, or output a signal from the GPIO based on an IEEE 1588 clock target compare event when configured as an output. All features of the IEEE 1588 hardware time stamp unit can be monitored and configured via their respective IEEE 1588 configuration and status registers (CSRs).
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SMSC LAN9311/LAN9311i |
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DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
2.2.9GPIO/LED Controller
The LAN9311/LAN9311i provides 12 configurable general-purpose input/output pins which are controlled via this module. These pins can be individually configured via the GPIO/LED CSRs to function as inputs, push-pull outputs, or open drain outputs and each is capable of interrupt generation with configurable polarity. Two of the GPIO pins (GPIO[9:8]) can be used for IEEE 1588 timestamp functions, allowing GPIO driven 1588 time clock capture when configured as an input, or GPIO output generation based on an IEEE 1588 clock target compare event.
In addition, 8 of the GPIO pins can be alternatively configured as LED outputs. These pins, GPIO[7:0] (nP1LED[3:0] and nP2LED[3:0]), may be enabled to drive Ethernet status LEDs for external indication of various attributes of the switch ports.
2.3System Configuration
In a typical application, the LAN9311/LAN9311i Host Bus Interface (HBI) is connected to the host microprocessor/microcontroller via the asynchronous 16-bit interface, allowing access to the LAN9311/LAN9311i system configuration and status registers. The LAN9311/LAN9311i utilizes the internal Host MAC to provide a network path for the host CPU. The LAN9311/LAN9311i may share the host bus with additional system memory and/or peripherals. For more information on the HBI, refer to Chapter 8, "Host Bus Interface (HBI)," on page 99.
The 2 Ethernet ports of the LAN9311/LAN9311i must be connected to Auto-MDIX style magnetics for proper operation on the Ethernet network. Refer to the SMSC Application Note 8.13 “Suggested Magnetics” for further details.
The LAN9311/LAN9311i also supports optional EEPROM and GPIOs/LEDs. When an EEPROM is connected, the EEPROM loader can be used to load the initial device configuration from the external EEPROM via the I2C/Microwire interface.
A system configuration diagram of the LAN9311/LAN9311i in a typical embedded environment can be seen in Figure 2.2.
To Ethernet |
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I2C/Microwire |
EEPROM |
Magnetics |
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(optional) |
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LAN9311/LAN9311i |
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Microprocessor/ |
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Microcontroller |
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To Ethernet |
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Magnetics |
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System |
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Memory |
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External |
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25MHz Crystal |
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System |
Peripherals
Figure 2.2 System Block Diagram
SMSC LAN9311/LAN9311i |
25 |
Revision 1.4 (08-19-08) |
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DATASHEET |
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 3 Pin Description and Configuration
3.1Pin Diagrams
3.1.1128-VTQFP Pin Diagram
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EEDI/EE SDA |
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VDD33IO |
nP1LED0/GPIO0 |
nP1LED1/GPIO1 |
nP1LED2/GPIO2 |
nP1LED3/GPIO3 |
VDD18CORE |
VDD33IO |
nP2LED0/GPIO4 |
nP2LED1/GPIO5 |
nP2LED2/GPIO6 |
nP2LED3/GPIO7 |
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VDD33IO |
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VDD18CORE |
VDD33IO |
VDD33IO |
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AUTO MDIX 2 |
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AUTO MDIX 1 |
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PHY ADDR SEL |
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VDD33IO |
VDD18CORE |
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NC |
NC |
GPIO8 |
VSS |
GPIO9 |
GPIO10 |
GPIO11 |
NC |
TEST1 |
nRST |
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LED EN |
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64 |
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VDD33IO |
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EEPROM_SIZE_1 |
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62 |
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PME |
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EEDO/EEPROM_TYPE |
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98 |
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63 |
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EECLK/EE_SCL/ |
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LAN9311 |
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VDD33IO |
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61 |
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END_SEL |
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EECS/EEPROM_SIZE_0 |
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101 |
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128-VTQFP |
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60 |
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FIFO_SEL |
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102 |
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59 |
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nCS |
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TOP VIEW |
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NC |
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58 |
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nWR |
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VDD18CORE |
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104 |
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nRD |
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XI |
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56 |
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A1 |
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XO |
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106 |
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55 |
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A2 |
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VDD18PLL |
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107 |
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54 |
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VDD33IO |
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TEST2 |
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108 |
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53 |
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A3 |
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NC |
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109 |
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TXN1 |
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110 |
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51 |
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A5 |
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TXP1 |
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111 |
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VSS |
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112 |
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49 |
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A7 |
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VSS |
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113 |
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VDD33A1 |
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114 |
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47 |
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A8 |
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RXN1 |
|
115 |
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46 |
|
VDD33IO |
||
RXP1 |
|
116 |
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45 |
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A9 |
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|||||||
VDD33A1 |
|
117 |
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44 |
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D0 |
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|||||||
VDD18TX1 |
|
118 |
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43 |
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D1 |
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|||||||
EXRES |
|
119 |
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42 |
|
D2 |
||
VDD33BIAS |
|
120 |
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41 |
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D3 |
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|||||||
VDD18TX2 |
|
121 |
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40 |
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VDD18CORE |
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|||||||
VDD33A2 |
|
122 |
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39 |
|
VDD33IO |
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|||||||
RXP2 |
|
123 |
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38 |
|
D4 |
||
RXN2 |
|
124 |
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37 |
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D5 |
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|||||||
VDD33A2 |
|
125 |
|
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36 |
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D6 |
||
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|||||||
TXP2 |
|
126 |
|
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35 |
|
D7 |
||
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|||||||
TXN2 |
|
127 |
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34 |
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D8 |
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|||||||
VSS |
|
128 |
|
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|
33 |
|
VDD33IO |
||
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|||||||
|
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
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19 |
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20 |
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21 |
22 |
23 |
24 |
25 |
26 |
27 |
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28 |
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29 |
30 |
31 |
32 |
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||||||||||||||||||||||||||||||||
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NC |
NC |
VDD18CORE |
NC |
NC |
NC |
VDD33IO |
NC |
NC |
NC |
NC |
NC |
VDD33IO |
VDD18CORE |
NC |
NC |
NC |
VSS |
NC |
NC |
VDD33IO |
NC |
NC |
NC |
D15 |
D14 |
VDD33IO |
D13 |
D12 |
D11 |
D10 |
D9 |
|
|
||||||||||||||||||||||||||||||||||||||
Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW)
Revision 1.4 (08-19-08) |
26 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
3.1.2128-XVTQFP Pin Diagram
VSS 
EEDO/EEPROM_TYPE 
EECLK/EE_SCL/
EEPROM_SIZE_1
VDD33IO
EECS/EEPROM_SIZE_0 
NC
NC 
VDD18CORE 
XI 
XO 
VDD18PLL
TEST2 
NC 
TXN1 
TXP1 
VSS 
VSS 
VDD33A1 
RXN1 
RXP1 
VDD33A1 
VDD18TX1 
EXRES 
VDD33BIAS 
VDD18TX2 
VDD33A2 
RXP2 
RXN2 
VDD33A2 
TXP2 
TXN2 
VSS 
EEDI/EE SDA |
NC |
NC |
VDD33IO |
nP1LED0/GPIO0 |
nP1LED1/GPIO1 |
nP1LED2/GPIO2 |
|||||||
|
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|
96 |
95 |
94 |
93 |
92 |
91 |
90 |
|||||||
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
1 |
2 |
3 |
4 |
5 |
6 |
7 |
||||||
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|
|
NC |
NC |
VDD18CORE |
NC |
NC |
NC |
VDD33IO |
||||||
89 nP1LED3/GPIO3
NC 8
VDD18CORE |
VDD33IO |
nP2LED0/GPIO4 |
nP2LED1/GPIO5 |
nP2LED2/GPIO6 |
nP2LED3/GPIO7 |
GPIO8 |
VDD33IO |
VSS |
GPIO9 |
GPIO10 |
GPIO11 |
NC |
TEST1 |
VDD18CORE |
VDD33IO |
VDD33IO |
nRST |
AUTO MDIX 2 |
AUTO MDIX 1 |
PHY ADDR SEL |
LED EN |
VDD33IO |
VDD18CORE |
|
88 |
87 |
86 |
85 |
84 |
83 |
82 |
81 |
80 |
79 |
78 |
77 |
76 |
75 |
74 |
73 |
72 |
71 |
70 |
69 |
68 |
67 |
66 |
65 |
|
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|
SMSC |
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64 |
VDD33IO |
|||
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|
62 |
PME |
||||
|
LAN9311/LAN9311i |
|
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|
63 |
IRQ |
|||||||||||||
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61 |
END_SEL |
||||||||||||||
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||
|
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|
128-XVTQFP |
|
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|
60 |
FIFO_SEL |
||||||||
|
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59 |
nCS |
|||||||||
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||
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|
TOP VIEW |
|
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58 |
nWR |
|||
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57 |
nRD |
|
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56 |
A1 |
|
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55 |
A2 |
|
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54 |
VDD33IO |
|
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53 |
A3 |
|
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52 |
A4 |
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51 |
A5 |
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50 |
A6 |
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VSS |
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49 |
A7 |
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48 |
VSS |
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47 |
A8 |
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46 |
VDD33IO |
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45 |
A9 |
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44 |
D0 |
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43 |
D1 |
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D2 |
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D3 |
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40 |
VDD18CORE |
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39 |
VDD33IO |
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D4 |
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D5 |
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D6 |
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D7 |
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D8 |
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33 |
VDD33IO |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
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NC |
NC |
NC |
NC |
VDD33IO |
VDD18CORE |
NC |
NC |
NC |
VSS |
NC |
NC |
VDD33IO |
NC |
NC |
NC |
D15 |
D14 |
VDD33IO |
D13 |
D12 |
D11 |
D10 |
D9 |
|
NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND
Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW)
SMSC LAN9311/LAN9311i |
27 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
3.2Pin Descriptions
This section contains the descriptions of the LAN9311/LAN9311i pins. The pin descriptions have been broken into functional groups as follows:
LAN Port 1 Pins
LAN Port 2 Pins
LAN Port 1 & 2 Power and Common Pins
Host Bus Interface Pins
EEPROM Pins
Dedicated Configuration Strap Pins
Miscellaneous Pins
PLL Pins
Core and I/O Power and Ground Pins
No-Connect Pins
Note: A list of buffer type definitions is provided in Section 1.2, "Buffer Types," on page 18.
Table 3.1 LAN Port 1 Pins
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|
BUFFER |
|
PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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|
Port 1 LED |
nP1LED[3:0] |
OD12 |
LED Indicators: When configured as LED outputs |
|
Indicators |
|
|
via the LED Configuration Register (LED_CFG), |
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these pins are open-drain, active low outputs and |
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the pull-ups and input buffers are disabled. The |
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functionality of each pin is determined via the |
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LED_CFG[9:8] bits. |
|
General |
GPIO[3:0] |
IS/O12/ |
General Purpose I/O Data: When configured as |
89-92 |
Purpose I/O |
|
OD12 |
GPIO via the LED Configuration Register |
Data |
|
(PU) |
(LED_CFG), these general purpose signals are |
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fully programmable as either push-pull outputs, |
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open-drain outputs or Schmitt-triggered inputs by |
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writing the General Purpose I/O Configuration |
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Register (GPIO_CFG) and General Purpose I/O |
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Data & Direction Register (GPIO_DATA_DIR). The |
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pull-ups are enabled in GPIO mode. The input |
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buffers are disabled when set as an output. |
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Note: See Chapter 13, "GPIO/LED Controller," |
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on page 163 for additional details. |
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Port 1 |
TXN1 |
AIO |
Ethernet TX Negative: Negative output of Port 1 |
110 |
Ethernet TX |
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Ethernet transmitter. See Note 3.1 for additional |
|
Negative |
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information. |
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Port 1 |
TXP1 |
AIO |
Ethernet TX Positive: Positive output of Port 1 |
111 |
Ethernet TX |
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Ethernet transmitter. See Note 3.1 for additional |
|
Positive |
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|
information. |
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Port 1 |
RXN1 |
AIO |
Ethernet RX Negative: Negative input of Port 1 |
115 |
Ethernet RX |
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Ethernet receiver. See Note 3.1 for additional |
|
Negative |
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information. |
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Port 1 |
RXP1 |
AIO |
Ethernet RX Positive: Positive input of Port 1 |
116 |
Ethernet RX |
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Ethernet receiver. See Note 3.1 for additional |
|
Positive |
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information. |
|
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|
Revision 1.4 (08-19-08) |
28 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Note 3.1 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally.
Table 3.2 LAN Port 2 Pins
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|
BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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Port 2 LED |
nP2LED[3:0] |
OD12 |
LED indicators: When configured as LED outputs |
|
Indicators |
|
|
via the LED Configuration Register (LED_CFG), |
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these pins are open-drain, active low outputs and |
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the pull-ups and input buffers are disabled. The |
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functionality of each pin is determined via the |
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LED_CFG[9:8] bits. |
|
General |
GPIO[7:4] |
IS/O12/ |
General Purpose I/O Data: When configured as |
83-86 |
Purpose I/O |
|
OD12 |
GPIO via the LED Configuration Register |
Data |
|
(PU) |
(LED_CFG), these general purpose signals are |
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fully programmable as either push-pull outputs, |
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open-drain outputs or Schmitt-triggered inputs by |
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writing the General Purpose I/O Configuration |
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Register (GPIO_CFG) and General Purpose I/O |
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Data & Direction Register (GPIO_DATA_DIR). The |
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pull-ups are enabled in GPIO mode. The input |
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buffers are disabled when set as an output. |
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Note: See Chapter 13, "GPIO/LED Controller," |
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|
on page 163 for additional details. |
|
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Port 2 |
TXN2 |
AIO |
Ethernet TX Negative: Negative output of Port 2 |
127 |
Ethernet TX |
|
|
Ethernet transmitter. See Note 3.2 for additional |
|
Negative |
|
|
information. |
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Port 2 |
TXP2 |
AIO |
Ethernet TX Positive: Positive output of Port 2 |
126 |
Ethernet TX |
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Ethernet transmitter. See Note 3.2 for additional |
|
Positive |
|
|
information. |
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Port 2 |
RXN2 |
AIO |
Ethernet RX Negative: Negative input of Port 2 |
124 |
Ethernet RX |
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Ethernet receiver. See Note 3.2 for additional |
|
Negative |
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|
information. |
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Port 2 |
RXP2 |
AIO |
Ethernet RX Positive: Positive input of Port 2 |
123 |
Ethernet RX |
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Ethernet receiver. See Note 3.2 for additional |
|
Positive |
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information. |
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Note 3.2 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally.
Table 3.3 LAN Port 1 & 2 Power and Common Pins
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|
BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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Bias |
EXRES |
AI |
Bias Reference: Used for internal bias circuits. |
119 |
Reference |
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Connect to an external 12.4K ohm, 1% resistor to |
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ground. |
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+3.3V Port 1 |
VDD33A1 |
P |
+3.3V Port 1 Analog Power Supply |
114,117 |
Analog Power |
|
|
Refer to the LAN9311/LAN9311i application note |
Supply |
|
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||
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for additional connection information. |
|
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|
|
SMSC LAN9311/LAN9311i |
29 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.3 LAN Port 1 & 2 Power and Common Pins (continued)
|
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|
BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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+3.3V Port 2 |
VDD33A2 |
P |
+3.3V Port 2 Analog Power Supply |
122,125 |
Analog Power |
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Refer to the LAN9311/LAN9311i application note |
Supply |
|
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||
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for additional connection information. |
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+3.3V Master |
VDD33BIAS |
P |
+3.3V Master Bias Power Supply |
120 |
Bias Power |
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Refer to the LAN9311/LAN9311i application note |
Supply |
|
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||
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for additional connection information. |
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Port 2 |
VDD18TX2 |
P |
Port 2 Transmitter +1.8V Power Supply: This pin |
|
Transmitter |
|
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is supplied from the internal PHY voltage regulator. |
|
+1.8V Power |
|
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This pin must be tied to the VDD18TX1 pin for |
121 |
Supply |
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proper operation. |
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||
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Refer to the LAN9311/LAN9311i application note |
|
|
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|
for additional connection information. |
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Port 1 |
VDD18TX1 |
P |
+1.8V Port 1 Transmitter Power Supply: This pin |
|
Transmitter |
|
|
must be connected directly to the VDD18TX2 pin |
118 |
+1.8V Power |
|
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for proper operation. |
|
Supply |
|
|
Refer to the LAN9311/LAN9311i application note |
|
|
|
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for additional connection information. |
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Table 3.4 Host Bus Interface Pins |
||
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BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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25,26, |
Host Bus |
D[15:0] |
IS/O8 |
Host Bus Data: Bits 15-0 of the Host Bus data |
28-32, |
Data |
|
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port. |
34-38, |
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Note: Big and little endianess is supported. |
41-44 |
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Host Bus |
A[9:1] |
IS |
Host Bus Address: 9-bit Host Bus Address Port |
45,47, |
Address |
|
|
used to select Internal CSR’s and TX and RX |
49-53, |
|
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FIFO’s. |
55,56 |
|
|
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Note: The A0 bit is not used because the |
|
|
|
|
LAN9311/LAN9311i must be accessed on |
|
|
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WORD boundaries. |
|
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57 |
Read Strobe |
nRD |
IS |
Read Strobe: Active low strobe to indicate a read |
|
|
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cycle. This signal is qualified by the nCS chip |
|
|
|
|
|
select. |
|
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58 |
Write Strobe |
nWR |
IS |
Write Strobe: Active low strobe to indicate a write |
|
|
|
cycle. This signal is qualified by the nCS chip |
|
|
|
|
|
select. |
|
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59 |
Chip Select |
nCS |
IS |
Chip Select: Active low signal used to qualify read |
|
|
|
and write operations. |
|
|
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|
|
|
|
|
|
Revision 1.4 (08-19-08) |
30 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.4 Host Bus Interface Pins (continued)
|
|
|
BUFFER |
|
PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
|
|
|
|
|
|
Data FIFO |
FIFO_SEL |
IS |
Data FIFO Direct Access Select: When driven |
|
Direct Access |
|
|
high, all accesses to the LAN9311/LAN9311i are |
|
Select |
|
|
directed to the RX and TX Data FIFO’s. All reads |
60 |
|
|
|
are from the RX Data FIFO, and all writes are to |
|
|
|
the TX Data FIFO. In this mode, the address input |
|
|
|
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|
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|
|
is ignored. Refer to Section 14.1.3, "Direct FIFO |
|
|
|
|
Access Mode," on page 168 for additional |
|
|
|
|
information. |
|
|
|
|
|
|
Endianess |
END_SEL |
IS |
Endianess Select: When this signal is set high, |
|
Select |
|
|
big endian mode is selected. When low, little |
61 |
|
|
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endian mode is selected. This signal may be |
|
|
|
dynamically changed or held static. Refer to |
|
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|
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|
|
Chapter 8, "Host Bus Interface (HBI)," on page 99 |
|
|
|
|
for additional information. |
|
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|
|
Note: Refer to Chapter 8, "Host Bus Interface (HBI)," on page 99 for additional information regarding the use of these signals.
Table 3.5 EEPROM Pins
|
|
|
BUFFER |
|
|
PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
|
|
|
|
|
|
|
|
EEPROM |
EEDI |
IS |
EEPROM Microwire Data Input (EEDI): In |
|
|
Microwire |
|
(PD) |
Microwire EEPROM mode (EEPROM_TYPE = 0), |
|
|
Data Input |
|
|
this pin is the Microwire EEPROM serial data input. |
|
96 |
|
|
|
|
|
EEPROM I2C |
EE_SDA |
IS/OD8 |
EEPROM I2C Serial Data Input/Output |
||
|
|||||
|
Serial Data |
|
|
(EE_SDA): In I2C EEPROM mode |
|
|
Input/Output |
|
|
(EEPROM_TYPE = 1), this pin is the I2C EEPROM |
|
|
|
|
|
serial data input/output. |
|
|
|
|
|
|
|
|
EEPROM |
EEDO |
O8 |
EEPROM Microwire Data Output: In Microwire |
|
|
Microwire |
|
|
EEPROM mode (EEPROM_TYPE = 0), this pin is |
|
|
Data Output |
|
|
the Microwire EEPROM serial data output. |
|
|
|
|
|
Note: In I2C mode (EEPROM_TYPE=1), this pin |
|
98 |
|
|
|
is not used and is driven low. |
|
|
EEPROM |
EEPROM_TYPE |
IS |
EEPROM Type Strap: Configures the EEPROM |
|
|
Type Strap |
|
Note 3.3 |
type. See Note 3.4 |
|
|
|
|
|
0 = Microwire Mode |
|
|
|
|
|
1 = I2C Mode |
|
|
EEPROM |
EECLK |
O8 |
EEPROM Microwire Serial Clock (EECLK): In |
|
|
Microwire |
|
|
Microwire EEPROM mode (EEPROM_TYPE = 0), |
|
|
Serial Clock |
|
|
this pin is the Microwire EEPROM clock output. |
|
|
|
|
|
|
|
|
EEPROM I2C |
EE_SCL |
IS/OD8 |
EEPROM I2C Serial Clock (EE_SCL): In I2C |
|
99 |
Serial Clock |
|
|
EEPROM mode (EEPROM_TYPE=1), this pin is |
|
|
|
|
the I2C EEPROM clock input/open-drain output. |
||
|
EEPROM |
EEPROM_SIZE_1 |
IS |
EEPROM Size Strap 1: Configures the high bit of |
|
|
Size Strap 1 |
|
Note 3.5 |
the EEPROM size range as specified in Section |
|
|
|
|
|
10.2, "I2C/Microwire Master EEPROM Controller," |
|
|
|
|
|
on page 138. This bit is not used for I2C |
|
|
|
|
|
EEPROMs. See Note 3.4. |
|
|
|
|
|
|
SMSC LAN9311/LAN9311i |
31 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.5 EEPROM Pins (continued)
|
|
|
BUFFER |
|
PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
|
|
|
|
|
|
EEPROM |
EECS |
O8 |
EEPROM Microwire Chip Select: In Microwire |
|
Microwire |
|
|
EEPROM mode (EEPROM_TYPE = 0), this pin is |
|
Chip Select |
|
|
the Microwire EEPROM chip select output. |
|
|
|
|
Note: In I2C mode (EEPROM_TYPE=1), this pin |
101 |
|
|
|
is not used and is driven low. |
|
EEPROM |
EEPROM_SIZE_0 |
IS |
EEPROM Size Strap 0: Configures the low bit of |
|
Size Strap 0 |
|
Note 3.3 |
the EEPROM size range as specified in Section |
|
|
|
|
10.2, "I2C/Microwire Master EEPROM Controller," |
|
|
|
|
on page 138. See Note 3.4. |
|
|
|
|
|
Note 3.3 The IS buffer type is valid only during the time specified in Section 15.5.2, "Reset and Configuration Strap Timing," on page 446.
Note 3.4 Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap pins are identified by an underlined symbol name. Refer to Section 4.2.4, "Configuration Straps," on page 40 for more information.
Note 3.5 The IS buffer type is valid only during the time specified in Section 15.5.2, "Reset and Configuration Strap Timing," on page 446 and when in I2C mode.
Table 3.6 Dedicated Configuration Strap Pins
|
|
|
BUFFER |
|
|
|
|
|
|
PIN |
NAME |
SYMBOL |
TYPE |
|
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DESCRIPTION |
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LED Enable |
LED_EN |
IS |
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LED Enable Strap: Configures the default value |
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Strap |
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for the LED_EN bits in the LED Configuration |
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67 |
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Register (LED_CFG). When latched low, all 8 |
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LED/GPIO pins are configured as GPIOs. When |
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latched high, all 8 LED/GPIO pins are configured |
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as LEDs. See Note 3.6. |
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PHY Address |
PHY_ADDR_SEL |
IS |
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PHY Address Select Strap: Configures the default |
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Strap |
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MII management address values for the PHYs |
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(Virtual, Port 1, and Port 2) as detailed in Section |
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7.1.1, "PHY Addressing," on page 82. |
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68 |
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_ADDRPHY _SEL VALUE |
VIRTUALPHY ADDRESS |
PORT1 PHY ADDRESS |
PORT2 PHY ADDRESS |
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0 |
0 |
1 |
2 |
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1 |
1 |
2 |
3 |
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See Note 3.6. |
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Revision 1.4 (08-19-08) |
32 |
SMSC LAN9311/LAN9311i |
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DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.6 Dedicated Configuration Strap Pins (continued)
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BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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Port 1 Auto- |
AUTO_MDIX_1 |
IS |
Port 1 Auto-MDIX Enable Strap: Configures the |
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MDIX Enable |
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(PU) |
Auto-MDIX functionality on Port 1. When latched |
69 |
Strap |
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low, Auto-MDIX is disabled. When latched high, |
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Auto-MDIX is enabled. |
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See Note 3.6. |
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Port 2 Auto- |
AUTO_MDIX_2 |
IS |
Port 2 Auto-MDIX Enable Strap: Configures the |
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MDIX Enable |
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(PU) |
Auto-MDIX functionality on Port 2. When latched |
70 |
Strap |
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low, Auto-MDIX is disabled. When latched high, |
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Auto-MDIX is enabled. |
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See Note 3.6. |
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Note: For more information on configuration straps, refer to Section 4.2.4, "Configuration Straps," on page 40. Additional strap pins, which share functionality with the EEPROM pins, are described in Table 3.5.
Note 3.6 Configuration strap values are latched on power-on reset or nRST de-assertion. Configuration strap pins are identified by an underlined symbol name. Some configuration straps can be overridden by values from the EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 40 for more information.
Table 3.7 Miscellaneous Pins
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BUFFER |
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PIN |
NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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General |
GPIO[11:8] |
IS/OD12/ |
General Purpose I/O Data: These general |
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Purpose I/O |
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O12 |
purpose signals are fully programmable as either |
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Data |
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(PU) |
push-pull outputs, open-drain outputs, or Schmitt- |
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Note 3.7 |
triggered inputs by writing the General Purpose I/O |
77-79, |
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Configuration Register (GPIO_CFG) and General |
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Purpose I/O Data & Direction Register |
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82 |
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(GPIO_DATA_DIR). For more information, refer to |
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Chapter 13, "GPIO/LED Controller," on page 163. |
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Note: The remaining GPIO[7:0] pins share |
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functionality with the LED output pins, as |
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described in Table 3.1 and Table 3.2. |
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Interrupt |
IRQ |
O8/OD8 |
Interrupt Output: Interrupt request output. The |
63 |
Output |
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polarity, source and buffer type of this signal is |
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programmable via the Interrupt Configuration |
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Register (IRQ_CFG). For more information, refer to |
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Chapter 5, "System Interrupts," on page 49. |
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System Reset |
nRST |
IS |
System Reset Input: This active low signal allows |
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Input |
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(PU) |
external hardware to reset the LAN9311/LAN9311i. |
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The LAN9311/LAN9311i also contains an internal |
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power-on reset circuit. Thus, this signal may be left |
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unconnected if an external hardware reset is not |
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needed. When used, this signal must adhere to the |
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reset timing requirements as detailed in Section |
71 |
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15.5.2, "Reset and Configuration Strap Timing," on |
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page 446. |
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Note: The LAN9311/LAN9311i must always be |
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read at least once after power-up or reset |
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to ensure that write operations function |
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properly. |
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SMSC LAN9311/LAN9311i |
33 |
Revision 1.4 (08-19-08) |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.7 Miscellaneous Pins (continued)
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BUFFER |
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PIN |
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NAME |
SYMBOL |
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TYPE |
DESCRIPTION |
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75 |
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Test 1 |
TEST1 |
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AI |
Test 1: This pin must be tied to VDD33IO for |
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proper operation. |
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108 |
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Test 2 |
TEST2 |
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AI |
Test 2: This pin must be tied to VDD33IO for |
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proper operation. |
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Power |
PME |
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O8/OD8 |
Power Management Event: When programmed |
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Management |
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accordingly, this signal is asserted upon detection |
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Event |
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of a wakeup event. The polarity and buffer type of |
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this signal is programmable via the PME_EN bit of |
62 |
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the Power Management Control Register |
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(PMT_CTRL). |
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Refer to Chapter 4, "Clocking, Resets, and Power |
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Management," on page 36 for additional |
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information on the LAN9311/LAN9311i power |
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management features. |
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Note 3.7 The input buffers are enabled when configured as GPIO inputs only. |
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Table 3.8 PLL Pins |
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BUFFER |
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PIN |
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NAME |
SYMBOL |
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TYPE |
DESCRIPTION |
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PLL +1.8V |
VDD18PLL |
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P |
PLL +1.8V Power Supply: This pin must be |
107 |
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Power Supply |
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connected to VDD18CORE for proper operation. |
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Refer to the LAN9311/LAN9311i application note |
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for additional connection information. |
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Crystal Input |
XI |
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ICLK |
Crystal Input: External 25MHz crystal input. This |
105 |
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signal can also be driven by a single-ended clock |
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oscillator. When this method is used, XO should be |
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left unconnected. |
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106 |
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Crystal |
XO |
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OCLK |
Crystal Output: External 25MHz crystal output. |
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Output |
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Table 3.9 Core and I/O Power and Ground Pins |
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BUFFER |
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PIN |
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NAME |
SYMBOL |
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TYPE |
DESCRIPTION |
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7,13,21,27, |
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+3.3V I/O |
VDD33IO |
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P |
+3.3V Power Supply for I/O Pins and Internal |
33,39,46, |
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Power |
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Regulator |
54,64,66, |
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Refer to the LAN9311/LAN9311i application note |
72,73,81, |
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for additional connection information. |
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87,93,100 |
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Digital Core |
VDD18CORE |
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P |
Digital Core +1.8V Power Supply Output: +1.8V |
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+1.8V Power |
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power from the internal core voltage regulator. All |
3,14,40,65, |
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Supply |
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VDD18CORE pins must be tied together for proper |
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Output |
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operation. |
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74,88,104 |
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Refer to the LAN9311/LAN9311i application note |
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for additional connection information. |
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Revision 1.4 (08-19-08) |
34 |
SMSC LAN9311/LAN9311i |
|
DATASHEET |
|
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Table 3.9 Core and I/O Power and Ground Pins (continued)
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BUFFER |
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PIN |
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NAME |
SYMBOL |
TYPE |
DESCRIPTION |
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