SMSC LAN91C111 User Manual

LAN91C111

10/100 Non-PCI
Ethernet Single Chip
MAC + PHY

PRODUCT FEATURES

 Singl e Chip Ethernet Controller
 Du al Speed - 10/100 Mbps
 F ully Supports Full Duplex Switched Ethernet
 Sup ports Burst Data Transfer
 8 Kbytes Internal Memory for Receive and Transmit

FIFO Buffers

 Enh anced Power Management Features
 Optional Configuration via Serial EEPROM Interface
 Sup ports 8, 16 and 32 Bit CPU Accesses
 Interna l 32 Bit Wide Data Path (Into Packet Buffer

Memory)

 Bui lt-in Transparent Arbitration for Slave Sequential

Access Architecture

 Flat MMU Architecture with Symmetric Transmit and

Receive Structures and Queues

 3 .3V Operation with 5V Tolerant IO Buffers (See Pin

List Description for Additional Details)

 Sin gle 25 MHz Reference Clock for Both PHY and

MAC

 External 25Mhz-output pin for an external PHY

supporting PHYs physical media.

 L ow Power CMOS Design
 Sup ports Multiple Embedded Processor Host

Interfaces

—ARM
—SH
— Power PC
— Coldfire
— 680X0, 683XX
— MIPS R3000

Datasheet

 3 .3V MII (Media Independent Interface) MAC-PHY

Interface Running at Nibble Rate

 MII Management Serial Interface
 128-Pin QFP package; lead-free RoHS compliant

package also available.

 1 28-Pin TQFP package, 1.0 mm height; lead-free

RoHS compliant package also available.

 C ommercial Temperature Range from 0 °C to 70°C

(LAN91C111)

 Ind ustrial Temperature Range from -40°C to 85°C

(LAN91C111i)

Network Interface

 Fully Integrated IEEE 802.3/802.3u-100Base-TX/

10Base-T Physical Layer

 Au to Negotiation: 10/100, Full / Half Duplex
 On C hip Wave Shaping - No External Filters

Required

 Ad aptive Equalizer
 Ba seline Wander Correction
 L ED Outputs (User selectable – Up to 2 LED

functions at one time)

—Link
—Activity
— Full Duplex
— 10/100
— Transmit
— Receive

SMSC LAN91C111 REV C DATASHEET Revision 1.91 (08-18-08)

10/100 Non-PCI Ethernet Single Chip MAC + PHY

ORDER NUMBERS:

LAN91C111-NC, LAN91C111i-NC (INDUSTRIAL TEMPERATURE)

FOR 128-PIN QFP PACKAGES
LA N 91 C 111- N S, L AN 9 1C 111 i- N S (INDUSTRIAL TEMPERATURE)
FOR 128-PIN QFP LEAD-FREE ROHS COMPLIANT PACKAGES

LAN91C111-NE (1.0MM HEIGHT); LAN91C111i-NE (INDUSTRIAL TEMPERATURE)

FOR 128-PIN TQFP PACKAGES

LAN91C111-NU (1.0MM HEIGHT); LAN91C111i-NU (INDUSTRIAL TEMPERATURE)

FOR 128-PIN TQFP LEAD-FREE ROHS COMPLIANT PACKAGES

Datasheet

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 [phone], FAX [phone]

Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a mean s of illustrating typical applications. Conse quently, complete information sufficient for

construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHE RS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.91 (08-18-08) 2 SMSC LAN91C111 REV C

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Table of Contents

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 5 Description of Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 6 Signal Description Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.1 Clock Generator Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2 CSMA/CD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.1 DMA Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.2.2 Arbiter Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.3 MMU Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 BIU Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5 MAC-PHY Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5.1 Management Data Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5.2 Management Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5.3 MI Serial Port Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.5.4 MII Packet Data Communication with External PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.6 Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.7 Internal Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.7.1 MII Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.7.2 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.7.3 Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.7.4 Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7.5 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7.6 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.7.7 Twisted Pair Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.7.8 Twisted Pair Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.7.9 Collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.7.10 Start of Packet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.7.11 End of Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.7.12 Link Integrity & AutoNegotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.7.13 Jabber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.7.14 Receive Polarity Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.7.15 Full Duplex Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.7.16 Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.7.17 PHY Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.7.18 PHY Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Chapter 8 MAC Data Structures and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1 Frame Format In Buffer Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.2 Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.3 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

SMSC LAN91C111 REV C 3 Revision 1.91 (08-18-08)

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

8.4 Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.5 Bank 0 - Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.6 Bank 0 - EPH Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.7 Bank 0 - Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.8 Bank 0 - Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.9 Bank 0 - Memory Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.10 Bank 0 - Receive/Phy Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.11 Bank 1 - Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.12 Bank 1 - Base Address Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.13 Bank 1 - Individual Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.14 Bank 1 - General Purpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.15 Bank 1 - Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.16 Bank 2 - MMU Command Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.17 Bank 2 - Packet Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.18 Bank 2 - FIFO Ports Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.19 Bank 2 - Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.20 Bank 2 - Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.21 Bank 2 - Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.22 Bank 3 - Multicast Table Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.23 Bank 3 - Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.24 Bank 3 - Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.25 Bank 3 - RCV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

8.26 Bank 7 - External Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Chapter 9 PHY MII Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

9.1 Register 0. Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.2 Register 1. Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

9.3 Register 2&3. PHY Identifier Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.4 Register 4. Auto-Negotiation Advertisement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.5 Register 5. Auto-Negotiation Remote End Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.6 Register 16. Configuration 1- Structure and Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.7 Register 17. Configuration 2 - Structure and Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.8 Register 18. Status Output - Structure and Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.9 Register 19. Mask - Structure and Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.10 Register 20. Reserved - Structure and Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 10 Software Driver and Hardware Sequence Flow . . . . . . . . . . . . . . . . . . . . . . . . . 84

10.1 Software Driver and Hardware Sequence Flow for Power Management. . . . . . . . . . . . . . . . . . . . 84

10.2 Typical Flow of Events for Transmit (Auto Release = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10.3 Typical Flow of Events for Transmit (Auto Release = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

10.4 Typical Flow of Event For Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Chapter 11 Board Setup Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Chapter 12 Application Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 13 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.1 Maximum Guaranteed Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13.3 Twisted Pair Characteristics, Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

13.4 Twisted Pair Characteristics, Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Chapter 14 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Revision 1.91 (08-18-08) 4 SMSC LAN91C111 REV C

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 15 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Chapter 16 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

SMSC LAN91C111 REV C 5 Revision 1.91 (08-18-08)

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

List of Figures

Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 3.1 Basic Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.1 MI Serial Port Frame Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.2 MII Frame Format & MII Nibble Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7.3 TX/10BT Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7.4 TP Output Voltage Template - 10 MBPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7.5 TP Input Voltage Template -10MBPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 7.6 SOI Output Voltage Template - 10MBPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 7.7 Link Pulse Output Voltage Template - NLP, FLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 7.8 NLP VS. FLP Link Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8.1 Data Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 8.2 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 10.1 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 10.2 RX INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 10.3 TX INTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 10.4 TXEMPTY INTR (Assumes Auto Release Option Selected) . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 10.5 Drive Send and Allocate Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 10.6 Interrupt Generation for Transmit, Receive, MMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 11.1 64 X 16 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 12.1 LAN91C111 on VL BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 12.2 LAN91C111 on ISA BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 12.3 LAN91C111 on EISA BUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 14.1 Asynchronous Cycle - nADS=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 14.2 Asyn chr o nous Cycle - Using nADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 14.3 Asynchronous Cycle - nADS=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 14.4 Asynchronous Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 14.5 Burst Write Cycles - nVLBUS=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 14.6 Burst Read Cycles - nVLBUS=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 14.7 Address Latching for All Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 14.8 Synchronous Write Cycle - nVLBUS=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 14.9 Synchronous Read Cycle - nVLBUS=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 14.10MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 14.11Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 14.12Receive Timing, End of Packet - 10 MBPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 14.13Collision Timing, Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Figure 14.14Collision Timing, Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Figure 14.15Jam Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 14.16Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 14.17FLP Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 15.1 128 Pin TQFP Package Outline, 14X14X1.0 Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 15.2 128 Pin QFP Package Outline, 3.9 MM Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Revision 1.91 (08-18-08) 6 SMSC LAN91C111 REV C

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

List of Tables

Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package) . . . . . . . . . . . . . . 14

Table 7.1 4B/5B Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7.2 Transmit Level Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8.1 Internal I/O Space Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 9.1 MII Serial Frame Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 9.2 MII Serial Port Register MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode . . . . . . . . . . . . . . . . . . . . . . 84

Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 12.1 VL Local Bus Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors . . . . . . . . . . . . . . . . . . . . . . 100

Table 12.3 EISA 32 Bit Slave Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 14.1 Transmit Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 14.2 Receive Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 14.3 Collision and Jam Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 14.4 Link Pulse Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 15.1 128 Pin TQFP Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 15.2 128 Pin QFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 16.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

SMSC LAN91C111 REV C 7 Revision 1.91 (08-18-08)

DATASHEET

Chapter 1 General Description

The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast
Ethernet connectivity solutions for embedded applications. For this third generation of products,
flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal
Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and
100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit
bus Host interface in embedded applications.

The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and
receive operations.

The SMSC LAN91C111 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit)

architecture and a 32-bit wide internal data path. This I/O mapped architecture can sustain back-to­back frame transmission and reception for superior data throughput and optimal performance. It also
dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks
and relieving the host CPU from performing these housekeep ing functions.

The SMSC LAN91C111 provides a flexible slave interface for easy connectivity with industry-standard
buses. The Bus Interface Unit (BIU) can handle synchronous as well as asyn chronous transfers, with
different signals being used for each one. Asynchronous bus support for ISA is sup ported even though
ISA cannot sustain 100 Mbps traffic. Fast Ethernet data rates are attainable for ISA-based nodes on
the basis of the aggregate traffic benefits.

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Two different interfaces are supported on the network side. The first Interface is a standard Magnetics
transmit/receive pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second
interface follows the MII (Media Independent Interface) specification standard, consisting o f 4 bit wide
data transfers at the nibble rate. This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps
Ethernet networks. Three of the LAN91C111’s pins are used to interface to the two-line MII serial
management protocol.

The SMSC LAN91C111 integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications.
The PHY can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet
operation. The Analog PHY block consists of a 4B5B/Manchester encoder/decoder, scrambler/de­scrambler, transmitter with wave shaping and output driver, twisted pair receiver with on chip equalizer
and baseline wander correction, clock and data recovery, Auto-Negotiation, controller interface (MII),
and serial port (MI). Internal output wave shaping circuitry and on-chip filters eliminate the ne ed for
external filters normally required in 100Base-TX and 10Base-T applications.

The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation
with the on-chip Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for
embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T a dapter cards,
motherboards, repeaters, switching hubs. The LAN91C111 operates from a single 3.3V supply. The
inputs and outputs of the host Interface are 5V tolerant and will directly interface to other 5V devices.

Revision 1.91 (08-18-08) 8 SMSC LAN91C111 REV C

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 2 Pin Configurations

Pin Configuration

XTAL2

XTAL1

RX_ER

RX_DV

RXD0

RXD1

RXD2

RXD3

VDD

CRS100

RX25

GND

TXD0

TXD1

TXD2

TXD3

COL100

TXEN100

VDD

TX25

GNDD0D1D2D3

GNDD4D5D6D7

VDD

nBE3

VDD

nCSOUT

IOS0
IOS1
IOS2

ENEEP

EEDO

EEDI
EESK
EECS

AVDD

RBIAS

AGND

TPO+

TPO-

AVDD

TPI+

TPI-

AGND

nLNK

LBK
nLEDA
nLEDB

GND

MDI

MDO

MCLK

nCNTRL

INTR0

RESET

nRD

nWR

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

33343536373839404142434445464748495051525354555657585960616263

LAN91C111-

FEAST

TM

128 PIN TQFP

104

103

102

101

100

999897

96

nBE2

95

nBE1

94

nBE0

93

GND

92

A15

91

A14

90

A13

89

A12

88

A11

87

A10

86

A9

85

A8

84

A7

83

A6

82

A5

81

A4

80

A3

79

A2

78

A1

77

VDD

76

D8

75

D9

74

D10

73

D11

72

GND

71

D12

70

D13

69

D14

68

D15

67

GND

66

D16

65

D17

64

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

VDD

nDATACS

W/nR

nADS

nCYCLE

GND

ARDY

AEN

LCLK

nVLBUS

VDD

nSRDY

nLDEV

nRDYRTN

GND

X25OUT

GND

VDD

D18

Figure 2.1 Pin Configuration - LAN91C111-FEAST 128 PIN TQFP

SMSC LAN91C111 REV C 9 Revision 1.91 (08-18-08)

DATASHEET

XTAL1
XTAL2

VDD

nCSOUT

IOS0
IOS1
IOS2

ENEEP

EEDO

EEDI
EESK
EECS

AVDD

RBIAS

AGND

TPO+

TPO-

AVDD

TPI+

TPI-

AGND

nLNK

LBK
nLEDA
nLEDB

GND

MDI

MDO

MCLK

nCNTRL

INTR0

RESET

nRD

nWR

VDD

nDATACS

nCYCLE

W/nR

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Pin Configuration

RX_ER

RX_DV

RXD0

RXD1

RXD2

RXD3

VDD

CRS100

RX25

GND

TXD0

TXD1

TXD2

TXD3

COL100

TXEN100

VDD

TX25

GNDD0D1D2D3

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110
1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

39404142434445464748495051525354555657585960616263

LAN91C111-

FEAST

TM

128 PIN QFP

109

108

107

GNDD4D5

106

105

104

103

64

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

Datasheet

D6
D7
VDD
nBE3
nBE2
nBE1
nBE0
GND
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
VDD
D8
D9
D10
D11
GND
D12
D13
D14
D15
GND
D16
D17
D18
D19

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

nADS

ARDY

GND

nVLBUS

AEN

LCLK

nSRDY

VDD

nLDEV

X25OUT

nRDYRTN

GND

GND

D20

VDD

Figure 2.2 Pin Configuration - LAN91C111-FEAST 128 PIN QFP

Revision 1.91 (08-18-08) 10 SMSC LAN91C111 REV C

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 3 Block Diagrams

The diagram shown in Figure 3.1, "Basic Functional Block Diagram", describes the device basic
functional blocks. The SMSC LAN91C111 is a single chip solution for embedded designs with minimal
Host and external supporting devices required to implement 10/100 Ethernet conne ctivity solutions.

The optional Serial EEPROM is used to store information relating to default IO offset parameters as
well as which of the Interrupt line are used by the ho st.

LAN91C111

ISA,Embedded

Processor

Host System

TX/RX Buffer (8K)

Ethernet

Internal IEEE 802.3 MII (Media

Independent Interface)

MAC

Serial

EEProm

(Optional)

Figure 3.1 Basic Functional Block Diagr am

PHY

Core

Transformer

Minimal LAN91C111

Configuration

RJ45

SMSC LAN91C111 REV C 11 Revision 1.91 (08-18-08)

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Control

Address

Data

EEPROM

INTERFACE

8-32 bit

Bus

Interface

Unit

Control

Control

WR

FIFO

RD

FIFO

Control

Arbiter

MMU

8K Byte

Dynamically

Allocated

SRAM

Control

32-bit Data

32-bit Data

TX/RX

FIFO

Pointer

DMA

Control

TX Data

RX Data

Ethernet
Protocol

Handler

(EPH)

MII

Control

TPO

10/100

PHY

TXD[0-3]

TPI

RXD[0-3]

Figure 3.2 Block Diagram

The diagram shown in Figure 3.2 describes the supported Host interfaces, which include ISA or
Generic Embedded. The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions
for 32, 16 and 8 bit embedded RISC and ARM processors.

The figure shown next page describes the SMSC LAN91C111 functional blocks required to integrate
a 10/100 Ethernet Physical layer framer to the internal MAC.

Revision 1.91 (08-18-08) 12 SMSC LAN91C111 REV C

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

A

D

Datasheet

MII External

Signals

EECS

EESK

EEDO

EEDI

EEPROM

CONTROL

B

5

B

4

R

E

N

E

C

D

TXD[3:0]

TX_ER

TXEN100

TX25

O

S

A

B

I

R

X

T

E

-

B

A

S

0

0

1

E

R

T

T

I

S

M

A

N

R

T

T

C

H

D

E

I

W

E

M

B

L

A

R

S

C

M

R

R

E

N

E

C

D

O

T

-

S

E

0

B

A

1

E

T

R

T

I

M

S

A

N

R

T

N

E

T

C

U

R

R

E

O

R

U

S

C

C

K

L

O

C

E

N

G

L

)

P

L

(

S

3

L

T

P

L

E

T

L

I

F

+

-

R

+

P

O

T

-

P

O

T

MII

SERIAL

Manage

-ment

CSMA/CD

Power

Reset

On

MII

To MII External Signals

CRS100

COL100

RXD[3:0]

RX_ER

RX_DV

RX25

MDI

MCLK

MDO

L

O

L

C

CONTROLS

S

I

PHY

D

C

E

R

S

T

H

M

C

A

N

E

N

O

I

R

M

O

C

K

L

O

C

E

N

G

L

)

P

L

(

A

1

H

L

C

U

S

E

Q

&

C

K

O

L

4

D

C

E

AUTONEG

LOGIC

B

B

5

D

R

E

O

C

R

A

M

E

S

D

R

E

C

B

L

A

A

T

D

E

R

Y

V

O

E

C

R

T

U

O

A

N

E

N

G

O

I

A

T

T

I

O

K

&

N

L

I

H

L

C

U

S

E

Q

&

C

K

L

O

C

A

A

T

D

y

e

r

v

o

e

c

R

t

e

s

e

r

h

n

c

M

a

(

)

r

d

e

o

e

c

D

E

1

R

P

L

E

T

L

I

F

X

T

E

-

B

A

S

0

0

E

I

E

C

R

V

E

R

L

T

M

D

R

E

N

C

O

-

T

S

E

A

0

B

I

V

E

R

E

E

C

LED

Control

R

+
+

-

+
+

-

nPLED[0-5]

LS[2-0]A

+

-

h

V

t

-

+

/

I

+

P

V

E

P

T

I

A

A

D

L

I

R

Z

E

U

E

A

Q

h

V

t

-

+

/

P

L

E

T

R

L

I

F

Multiplex er

S

D

1

S

8

EN

C

C

1

3C2

B

Multiplex er

S

D

1

S

8

EN

C

C

1

3C2

B

T

P

I

T

-

LED

LE

LS[2-0]B

Figure 3.3 LAN91C111 Physical Layer to Internal MAC Block Diagram

SMSC LAN91C111 REV C 13 Revision 1.91 (08-18-08)

DATASHEET

Chapter 4 Signal Descriptions

Table 4.1 LAN91C111 Pin Requirements (128 Pin QFP and 1.0mm TQFP package)

FUNCTION PIN SYMBOLS NUMBER OF PINS

System Address Bus A1-A15, AEN, nBE0-nBE3 20

System Data Bus D0-D31 32

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Datasheet

System Control Bus RESET, nADS, LCLK, ARDY,

nRDYRTN, nSRDY, INTR0, nLDEV,

nRD, nWR, nDATACS, nCYCLE, W/nR,

nVLBUS

Serial EEPROM EEDI, EEDO, EECS, EESK, ENEEP,

IOS0-IOS2

LEDs nLEDA, nLEDB 2

PHY TPO+, TPO-, TPI+, TPI-, nLNK, LBK,

nCNTRL, RBIAS

Crystal Oscillator XTAL1, XTAL2 2

Power VDD, AVDD 10

Ground GND, AGND 12

Physical Interface (MII) TXEN100, CRS100, COL100, RX_DV,

RX_ER, TXD0-TXD3, RXD0-RXD3,

MDI, MDO, MCLK, RX25, TX25

MISC nCSOUT, X25OUT 2

TOTAL 128

14

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Datasheet

Chapter 5 Description of Pin Functions

PIN NO.

NAME SYMBOL

TQFP QFP

81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C111 to

78-80 80-82 Address A1-A3 I** Input. Used by LAN91C111 for internal

41 43 Address Enable AEN I** Input. Used as an address qualifier.

94-97 96-99 nByte Enable nBE0-

107-104,
102-99, 76­73, 71-68,
66-63, 61­58, 56-53,
51-48

30 32 Reset RESET IS** Input. When this pin is asserted high, the

109-106,
104-101,
78-75, 73­70, 68-65,
63-60, 58­55, 53-50

Data Bus D0-D31 I/O24** Bidirecti onal. 32 bit data bus used to

nBE3

BUFFER
TYPE

I** Input. Used during LAN91C111 register

DESCRIPTION

determine access to its registers.

register selection.

Address decoding is only enabled when
AEN is low.

accesses to determine the width of the
access and the register(s) being
accessed. nBE0-nBE3 are ignored when
nDATACS is low (burst accesses)
because 32 bit transfers are assumed.

access the LAN91C111’s internal
registers. Data bus has weak internal
pullups. Supports direct connection to the
system bus without external buffering.
For 16 bit systems, only D0-D15 are
used.

controller performs an internal system
(MAC & PHY) reset. It programs all the
registers to their default value, the
controller will read the EEPROM device
through the EEPROM interface
This input is not considered active unless
it is active for at least 100ns to filter
narrow glitches.

(Note 5.1).

37 39 nAddress

Strobe

35 37 nCycle nCYCLE I** Input. This active l ow signal is used to

36 38 Write/

nRead

40 42 nVL Bus Access nVLBUS I with

SMSC LAN91C111 REV C 15 Revision 1.91 (08-18-08)

nADS IS** Input. For systems that require address

W/nR IS** Input. Defines th e direction of

pullup**

latching, the rising edge of nADS
indicates the latching moment for A1-A15
and AEN. All LAN91C111 internal
functions of A1-A15, AEN are latched
except for nLDEV decoding.

control LAN91C111 EISA burst mode
synchronous bus cycles.

synchronous cycles. Write cycles when
high, read cycles when low.

Input. When low, the LAN91C111
synchronous bus interface is configured
for VL Bus accesses. Otherwise, the
LAN91C111 is configured for EISA DMA
burst accesses. Does not affect the
asynchronous bus interface.

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

PIN NO.

NAME SYMBOL

TQFP QFP

BUFFER
TYPE

DESCRIPTION

42 44 Local Bus Clock LCLK I** Input. Used to interface synchronous

buses. Maximum frequency is 50 MHz.
Limited to 8.33 MHz for EISA DMA burst
mode. This pin should be tied high if it is
in asynchronous mode.

38 40 Asynchronous

Ready

ARDY OD16 Open drain output. ARDY may be used

when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the
XTAL1 clock and, therefore,
asynchronous to the host CPU or bus
clock. ARDY is negated during
Asynchronous cycle when one of the
following conditions occurs:
No_Wait Bit in the Configuration Register
is cleared.
Read FIFO contains less than 4 bytes
when read.
Write FIFO is full when write.

43 45 nSynchronous

Ready

nSRDY O16 Output. This output is used when

interfacing synchronous buses and
nVLBUS=0 to extend accesses. This
signal remains normally inactive, and its
falling edge indicates completion. This
signal is synchronous to the bus clock
LCLK.

46 48 nReady Return nRDYRTN I** Input. This input is used to complete

synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK
edges, and synchronous cycles are
delayed until it is sampled high.

29 31 Interrupt INTR0 O24 Interrupt Output – Active High, it’s used to

interrupt the Host on a status event.
Note: The selection bits used to
determined by the value of INT SEL 1-0
bits in the Configuration Register are no
longer required and have been set to
reserved in this revision of the FEAST
family of devices.

45 47 nLocal Device nLDEV O16 Output. This active low output is asserted

when AEN is low and A4-A15 decode to
the LAN91C111 address programmed
into the high byte of the Base Address
Register. nLDEV is a combinatorial
decode of unlatched address and AEN
signals.

31 33 nRead Strobe nRD IS** Input. Used in asyn chronous bus

interfaces.

32 34 nWrite Strobe nWR IS** Input. Used in a synchronous bus

interfaces.

34 36 nData Path

Chip Select

nDATACS I with

pullup**

Input. When nDATACS is low, the Data
Path can be accessed regardless of the
values of AEN, A1-A15 and the content of
the BANK SELECT Register. nDATACS
provides an interface for bursting to and
from the LAN91C111 32 bits at a time.

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Datasheet

PIN NO.

NAME SYMBOL

TQFP QFP

BUFFER
TYPE

DESCRIPTION

9 11 EEPROM Clock EESK O4 Output. 4 μsec clock used to shift data in

and out of the serial EEPROM.

10 12 EEPROM

Select

EECS O4 Output. Serial EEPROM chip select.

Used for selection and command framing
of the serial EEPROM.

7 9 EEPROM Data

Out

8 10 EEPROM Data InEEDI I with

3-5 5-7 I/O Base IOS0-IOS2 I with

EEDO O4 Output. Connected to the DI input of the

serial EEPROM.
Input. Connected to the DO output of the

pulldown **

serial EEPROM.
Input. External switches can be

pullup**

connected to these lines to select
between predefined EEPROM
configurations.

68Enable

EEPROM

ENEEP I with

pullup**

Input. Enables (when high or open)
LAN91C111 accesses to the serial
EEPROM. Must be grounded if no
EEPROM is connected to the
LAN91C111.

127, 128 1, 2 Crystal 1

Crystal 2

XTAL1
XTAL2

Iclk** An external 25 MHz crystal is connected

across these pins. If a TTL clock is
supplied instead, it should be connected
to XTAL1 and XTAL2 should be left open.
XTAL1 is the 5V tolerant input of the
internal amplifier and XTAL2 is the output
of the internal amplifier.

1, 33, 44,
62, 77, 98,
110, 120

3, 35, 46,
64, 79,
100, 112,

Power VDD +3.3V Power supply pins.

122
11, 16 13, 18 Analog Power AVDD +3.3V Analog power supply pins.
24, 39, 52,

57, 67, 72,
93, 103,
108, 117

26, 41, 54,

59, 69, 74,

95, 105,

110 , 11 9

Ground GND Ground pins.

13, 19 15, 21 Analog Ground AGND Analog Ground pins
21 23 Loopback LBK O4 Outp ut. Active when LOOP bit is set

(TCR bit 1).

20 22 nLink Status nLNK I with

pullup

Input. General-purpose input port used to

convey LINK status (EPHSR bit 14).
28 30 nCNTRL nCNTRL O12 General Purpose Control Pin
47 49 X25out X25out O12 25Mhz Output to external PHY
111 113 Transmit Enable

100 Mbps

119 121 Carrier Sense

100 Mbps

TXEN100 O12 Output to MII PHY. Envelope to 100

Mbps transmission.

CRS100 I with

pulldown

Input from MII PHY. Envelope of packet

reception used for deferral and backoff

purposes.

SMSC LAN91C111 REV C 17 Revision 1.91 (08-18-08)

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

PIN NO.

NAME SYMBOL

TQFP QFP

125 127 Receive Data

RX_DV I with

Valid

112 114 Collision Detect

COL100 I with

100 Mbps

113-116 115-118 Transmit Data TXD3-

BUFFER
TYPE

pulldown

pulldown
O12 Outputs. Transmit Data nibble to MII

TXD0

109 111 Transmit Clock TX25 I with

pullup

118 120 Receive Clock RX25 I with

pullup

121-124 123-126 Receive Data RXD3-

RXD0

25 27 Management

MDI I with

Data Input

26 28 Management

MDO O4 MII management d ata output.

I with
pullup

pulldown

Data Output

DESCRIPTION

Input from MII PHY. Envelope of data

valid reception. Used for receive data

framing.

Input from MII PHY. Collision detection

input.

PHY.

Input. Transmit clock input from MII.

Nibble rate clock (25MHz for 100Mbps &

2.5MHz for 10Mbps).

Input. Receive clock input from MII PHY.

Nibble rate clock. (25MHz for 100Mbps &

2.5MHz for 10Mbps).

Inputs. Received Data nibble from MII

PHY.

MII management data input.

27 29 Management

MCLK O4 MII management cl ock.

Clock

126 128 Receive Error RX_ER I with

pulldown

Input. Indicates a code error detected by

PHY. Used by the LAN91C111 to discard

the packet being received. The error

indication reported for this event is the

same as a bad CRC (Receive Status

Word bit 13).
2 4 nChip Select

Output

nCSOUT O4 Outp ut. Chip Select provided for

mapping of PHY functions into

LAN91C111 decoded space. Active on

accesses to LAN91C111’s eight lower

addresses when the BANK SELECTED is

7.

12 14 External

Resistor

RBIAS NA Transmit Current Set. An external

resistor connected between this pin and

GND will set the output current for the TP

transmit outputs
14 16 TPO+ O/I Twisted Pair Transmit Output, Positive.
15 17 TPO- O/I Twisted Pair Transmit Output, Negative
17 19 TPI+ I/O Twisted Pair Receive Input, Positive
18 20 TPI- I/O Twisted Pair Receive Input, Negative.
22 24 nLEDA OD24 PHY LED Output
23 25 nLEDB OD24 PHY LED Output

Note 5.1 If the EEPROM is enabled.

Revision 1.91 (08-18-08) 18 SMSC LAN91C111 REV C

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10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

Chapter 6 Signal Description Parameters

This section provides a detailed description of each SMSC LAN91C111 signal. The signals are
arranged in functional groups according to their associated function.

The ‘n’ symbol at the beginning of a signal name indicates that it is an active low signal. When ‘n’ is
not present before the signal name, it indicates an active high signal.

The term “assert” or “assertion” indicates that a signal is active; i ndependent of whether that level is
represented by a high or low voltage. The term negates or negation indicates that a signa l is inactive.

The term High-Z means tri-stated.
The term Undefined means the signal could be high, low, tri-stated, or in some in-between level.

6.1 Buffer Types

O4 Output buffer with 2mA source and 4mA sink
O12 Output buffer with 6mA source and 12mA sink
O16 Output buffer with 8mA source and 16mA sink
O24 Output buffer with 12mA source and 24mA sink
OD16 Open drain buffer with 16mA sink
OD24 Open drain buffer with 24mA sink
I/O4 Bidirectional buffer with 2mA source and 4mA sink
I/O24 Bidirectional buffer with 12mA source and 24mA sink
I/OD Bidirectional Open drain buffer with 4mA sink
I Input buffer
IS Input buffer with Schmitt Trigger Hysteresis
Iclk Clock input buffer
I/O Differential Input
O/I Differential Output
** 5V tolerant. Input pins are able to accept 5V signals

DC levels and conditions defined in the DC Electrical Characteristics section.

SMSC LAN91C111 REV C 19 Revision 1.91 (08-18-08)

DATASHEET

Chapter 7 Functional Description

7.1 Clock Generator Block

1. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal.

2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5
MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).

3. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and
running the receive state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).

4. LCLK - Bus clock - Used by the BIU for synchronous accesses. Maximum frequency is 50 MHz
for VL BUS mode, and 8.33 MHz for EISA slave DMA.

7.2 CSMA/CD Block

This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in
and out of the block consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The
DMA port of the FIFO stores 32 bits to exploit the 32 bit data path into memory, but the FIFOs
themselves are 16 bit wide. The Control Path consists of a set of registers interfaced to the CPU via
the BIU.

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

7.2.1 DMA Block

This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing
received data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side and the Arbiter
block on the other. To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block,
and the data path is 32 bits wide.

For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the
Receive FIFO every 160ns. The DMA will read the FIFO and accumulate two words on the output port
to request a memory cycle from the Arbiter every 320ns.

The DMA machine is able to support full duplex operation. Independe nt receive and transmit counters
are used. Transmit and receive cycles are alternated when simultaneous receive and transmit
accesses are needed.

7.2.2 Arbiter Block

The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks.
BIU requests represent pipelined CPU accesses to the Data Register, while DMA requests represent
CSMA/CD data movement.

Internal SRAM read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to
the appropriate lanes as a function of the address.

The CPU Data Path consists of two uni-directional FIFOs mapped at the D ata Register locatio n. These
FIFOs can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate
'Not Ready' whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO.

7.3 MMU Block

The Hardware Memory Management Unit allocates memory and transmit and receive packet queues.
It also determines the value of the transmit and receive interrupts as a function of the queues. The
page size is 2048 bytes, with a maximum memory size of 8kbytes. MIR values are interpreted in 2048
byte units.

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Datasheet

7.4 BIU Block

The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are
used for each one. Transparent latches are added on the address path using rising nADS for latching.

When working with an asynchronous bus like ISA, the read and write operations are controlled by the
edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle.
The leading edge of ARDY is generated by the leading ed ge of nRD or nWR while the trailing edge
of ARDY is controlled by the internal LAN91C111 clock and, therefore, asynchronous to the bus.

In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations.
Completion of the cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and
synchronous to the bus.

Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting
nDATACS, external DMA type of devices will bypass the BIU address decoders and can sequentially
access memory with no CPU intervention. nDATACS accesses can be used in the EISA DMA burst
mode (nVLBUS=1) or in asynchronous cycles. These cycles MUST be 32 bit cycles. Please refer to
the corresponding timing diagrams for details on these cycles.

The BIU is implemented using the following principles:
a. Address decoding is based on the values of A15-A4 and AEN.

b. Address latching is performed by using transparent latches that are transparent when nADS=0 and

nRD=1, nWR=1 and latch on nADS rising edge.

c. Byte, word and doubleword accesses to all registers and Data Path are supported except a

doubleword write to offset Ch will only write the BANK SELECT REGISTER (offset 0x0Fh).

d. No bus byte swapping is implemented (no eight bit mode).
e. Word swapping as a function of A1 i s implemented for 16 bit bus support.
f. The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the

leading edge of the strobe. The ARDY trailing edge is controlled by CLK.

g. The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA

specification as well as nCYCLE to control read and write operations an d generate nSRDY.

h. EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA

Slave Mode "C" specification when nDATACS is driven by nDAK.

i. Synchronous and asyn chrono us cycles can be mi xed as long a s they are not active simul taneously.
j. Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating

the nDATACS pin.

7.5 MAC-PHY Interface

The LAN91C111 integrates the IEEE 802.3 Physical Layer (PHY) and Media Access Control (MAC)
into the same silicon. The data path connection between the MAC and the internal PHY is provided
by the internal MII. The LAN91C111 also supports the EXT_PHY mode for the use of an external PHY,
such as HPNA. This mode isolates the internal PHY to allow interface with an external PHY through
the MII pins. To enter this mode, set EXT PHY bit to 1 in the Configuration Register.

7.5.1 Management Data Software Implementation

The MII interface contains of a pair of signals that physically transport the management informa tion
across the MII, a frame format and a protocol specification for exchanging management frames, and
a register set that can be read and written using these frames. MII management refers to the ability
of a management entity to communicate with PHY via the MII serial ma nagement interface (MI) for the
purpose of displaying, selecting and/or controlling different PHY options. The host manipulates the
MAC to drive the MII management serial interface. By manipulating the MAC's registers, MII
management frames are generated on the management interface for reading or writing information
from the PHY registers. Timing and framing for each management command is to be generated by
the CPU (host).

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DATASHEET

The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface.
MDIO:Management Data input/output. Bi-directional between MAC and PHY that carries management

data. All control and status information sent over this pin is driven and sampled synchronously to the
rising edge of MDC signal.

MDC:Management Data Clock. Sourced by the MAC as a timing reference for transfer of information
on the MDIO signal. MDC is a periodic signal with no maximum h igh or low times. T he minimum high
and low times should be 160ns each and the minimum period of the signal shou ld be 400ns. These
values are regardless of the nominal period of the TX and RX clocks.

7.5.2 Management Data Timing

A timing diagram for a Ml serial port frame is shown in Figure 7.1. The Ml serial port is idle when at
least 32 continuous 1's are detected on MDIO and remains idle as long as continuous 1's are detected.
During idle, MDIO is in the high impedance state. When the Ml serial port is in the idle state, a 01
pattern on the MDIO initiates a serial shift cycle. Data on MDIO is then shifted in on the next 14 rising
edges of MDC (MDIO is high impedance). If the register access mode is not enabled, on the next 16
rising edges of MDC, data is either shifted in or out on MDIO, depending on whether a write or re ad
cycle was selected with the bits READ and WRITE. After the 32 MDC cycles have been completed,
one complete register has been read/written, the serial sh ift process is halted, data is latched into the
device, and MDIO goes into high impedance state. Another serial shift cycle cannot be initiated until
the idle condition (at least 32 continuous 1's) is detected.

10/100 Non-PCI Ethernet Single Chip MAC + PHY

Datasheet

7.5.3 MI Serial Port Frame Structure

The structure of the PHY serial port frame is shown in Table 9.1 and timing diagram of a frame is
shown in Figure 7.1. Each serial port access cycl e consists of 32 bits (or 192 bits if multiple register
access is enabled and REGAD[4:0]=11111 ) , e x c l u s i v e o f i d l e . T h e f i r s t 1 6 b i t s o f t h e s e r i a l p o r t cycle
are always write bits and are used for addressing. The last 16/176 bits are from one/all of the 11 data
registers.

The first 2 bit in Table 9.1and Figure7.1 are start bits and need to be wr itten as a 01 for the serial po rt
cycle to continue. The next 2 bits are a read and write bit which determine if the accessed data register
bits will be read or write. The next 5 bits are device addresses. The next 5 bits are register address
select bits, which select one of the five data registers for access. The next 1 bit is a turnaround bit
which is not an actual register bit but extra time to switch MDIO from write to read if ne cessary, as
shown in Figure 7.1. The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple register
access is enabled and REGAD[4:0]=11111) come from the specific data register designated by the
register address bits REGAD[4:0].

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Datasheet

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Figure 7.1 MI Serial Port Frame Timing Diagra m

SMSC LAN91C111 REV C 23 Revision 1.91 (08-18-08)

DATASHEET

10/100 Non-PCI Ethernet Single Chip MAC + PHY

7.5.4 MII Packet Data Communication with External PHY

The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the
MIl requirements outlined in IEEE 802.3 and shown in Figure 7.2.

Datasheet

TX_EN = 0

IDLE

MII
NIBBLE
STREAM

PREAMBLE

PRMBLE

FIRST BIT

FIRST
NIBBLE

TXD0 / RXD0
TXD1 / RXD1

TXD2 / RXD2
TXD3 / RXD3

TX_EN = 1

OF

SFD

DATA 1

2 BT

= [ 1 0 1 0 ... ] 62 BITS LONG
= [ 1 1 ]

= [ BETWEEN 64-1518 DATA BYTES ]

MAC's SERIAL BIT STREAM

DATA NIBBLES

DATA 2

DATA N-1 DATA N

62 BT

LSB

START

FRAME

DELIM.

PREAMBLE

SFD

DATAn

IDLE = TX_EN = 0

D0 D1 D2 D3 D4 D5 D6 D7

Figure 7.2 MII Frame Format & MII Nibble Order

TX_EN = 0

IDLE

MSB

SECOND
NIBBLE

The Mll consists of the following signals: four transmit data bits (TXD[3:0]), transmit clock
(TX25),transmit enable (TXEN100), four receive data bits(RXD[3:0]), receive clock(RX25), carrier
sense (CRS100), receive data valid (RX_DV), receive data error (RX_ER), and collision (COL100).
Transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. Th e
transmit and receive clocks operate at 25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps.

In 100 Mbps mode, the LAN91C111 provides the following interface signals to the PHY:

 For transmission: TXEN100, TX D0-3, TX25
 For reception: RX_DV, RX_ER, RXD0-3, RX25
 For CSMA/CD state machines: CRS100, COL100

A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid
preamble nibble. TXD0 carries the least significant bit of the nibble (that is the one tha t would go first
out of the EPH at 100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and
TXD0-TXD3 are clocked by the LAN91C111 using TX25 rising edges. TXEN100 goe s inactive at the
end of the packet on the last nibble of the CRC.

During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous
to the LAN91C111’s clocks and will be synchronized internally to TX25.

Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will
be present at RXD0-RXD3 when RX_DV is activated. The LAN91C111 requires no training sequence
beyond a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising

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Datasheet

edges. RXD0 carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV
goes inactive when the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.

RX_ER might be asserted during packet reception to signal the L AN91C111 that the present receive
packet is invalid. The LAN91C111 will discard the packet by treating it as a CRC error.

RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag d etection does not
consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the
packet on non-preamble patterns.

CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and
backoff functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal
and it will be active whenever there is activity on the cable, including LAN9 1C111 transmissions and
collisions.

7.6 Serial EEPROM Interface

This block is responsible for reading the serial EEPROM upon hardware reset (or equivalent
command) and defining defaults for some key registers. A write operation is also implemented b y this
block, that under CPU command will program specific locations in the EEPROM. This block is an
autonomous state machine and controls the internal Data Bus of the LAN91C111 during active
operation.

7.7 Internal Physical Layer

The LAN91C111 integrates the IEEE 802.3 physical layer (PHY) internally. The EXT PHY bit in the
Configuration Register is 0 as the default configuration to set the internal PHY enabled. The internal
PHY address is 00000, the driver must use this address to talk to the internal PHY. The inte rnal PHY

is placed in isolation mode at power up and reset. It can be removed from isolation mode by clearing
the MII_DIS bit in the PHY Control Register. If necessary, the internal PHY can be enabled by clearing
the EXT_PHY bit in the Configuration Register.

The internal PHY of LAN91C111 has nine main sections: controller interface, encoder, decoder,
scrambler, descrambler, clock and data recovery, twisted pair transmitter, twisted pair receiver, and MI
serial port.

The LAN91C111 can operate as a 100BASE-TX device (hereafter referred to as 100Mbps mode) or
as a 10BASE-T device (hereafter referred to as 10Mbps mode). The difference between the 100Mbps
mode and the 10Mbps mode is data rate, signaling protocol, and allowed wiring. The 100Mbps TX
mode uses two pairs of category 5 or better UTP or STP twisted pair cable with 4B5B encoded,
scrambled, and MLT-3 coded 62.5 MHz ternary data to achieve a throughput of 100Mbps. The 10Mbps
mode uses two pairs of category 3 or better UTP or STP twisted pair cable with Manchester encoded,
10MHz binary data to achieve a 10Mbps throughput. The data symbol format on the twisted pair cable
for the 100 and 10Mbps modes are defined in IEEE 802.3 specifications and shown in Figure 7.3.

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INTERFRAME

GAP

IDLE

IDLE

PREAMBLE

SSD

DA, SA, LN, LLC DATA, FCS

PREAMBLE

PREAMBLE

DA, SA, LN, LLC DATA, FCS

PREAMBLE

IDLE

PREAMBLE

SFD

= [ 1 1 ] WITH NO MID BIT TRANSITION

SOI

ETHERNET MAC

FRAME

SFD DA

100 BASE-TX DATA SYMBOL S

SFD

IDLE
SSD

= [ 1 1 0 0 0 1 0 0 0 1]

= [ 1 0 1 0 ...] 62 BITS LONG

SFD

= [ 1 1]

= [ DATA]

= [ 0 1 1 0 1 0 0 1 1 1]

ESD

10 BASE-T DATA SYMBOLS

SFD

= [ NO TRANSITIONS]
= [ 1 0 1 0 ... ] 62 BITS LONG

= [ 1 1]

= [ DATA]

DA

= [ 1 1 1 1...]

DA

SA

SA

SA

LN

LLC DATA

LN ESD

LLC DATA

BEFORE / AFTER

4B5B ENCODING,

SCRAMBLING,

AND MLT3

CODING

LN

LLC DATA

BEFORE / AFTER

MANCHESTER

ENCODING

FCS

FCS

FCS

SOI

INTERFRAME

GAP

IDLE

IDLE

Figure 7.3 TX/10BT Frame Format

On the transmit side for 100Mbps TX operation, data is received on the controller and then se nt to the
4B5B encoder for formatting. The encoded data is then sent to the scrambler. The scrambled and
encoded data is then sent to the TP transmitter. The TP transmitter converts the encoded and
scrambled data into MLT-3 ternary format, reshapes the output, and drives the twisted pair cable.

On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming e ncoded
and scrambled MLT-3 data from the twisted pair cable, remove any h igh frequency noise, equalizes
the input signal to compensate for the effects of the cabl e, qualifies the data with a squelch algorithm,
and converts the data from MLT-3 coded twisted pair levels to internal digital levels. The output of the
twisted pair receiver then goes to a clock and data recovery block which recovers a clock from the
incoming data, uses the clock to latch in valid data into the devic e, and converts the data back to NRZ
format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler,
respectively, and outputted to the Ethernet controller.

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10Mbps operation is similar to the 100Mbps TX operation except, (1) there is no
scrambler/descrambler, (2) the encoder/decoder is Manchester instead of 4B5B, (3) the data rate is
10Mbps instead of 100Mbps, and (4) the twisted pair symbol data is two level Manche ster instead of
ternary MLT-3.

The Management Interface, (hereafter referred to as the MI serial port), is a two pin bi-directional link
through which configuration inputs can be set and status outputs can be read. Each block plus the
operating modes are described in more detail in the following sections.

7.7.1 MII Disable

The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control
register. When the MII is disabled, the MII inputs are ignored, the MII outputs are placed in high
impedance state, and the TP output is high impedance.

7.7.2 Encoder

4B5B Encoder - 100 Mbps

100BASE-TX requires that the data be 4B5B encoded. 4B5B coding converts the 4-Bit data nibbles
into 5-Bit date code words. The mapping of the 4B nibbles to the 5B code words is specified in IEEE

802.3. The 4B5B encoder on the LAN91C111 takes 4B nibbles from the controller interface, converts
them into 5B words and sends the 5B words to the scrambl er. The 4B5B encoder also substitutes the
first 8 bits of the preamble with the SSD delimiters (a.k.a. /J/K/ symbo ls) and adds an ESD delimiter
(a.k.a. MR/ symbols) to the end of every packet, as defined in IEEE 802.3. The 4B5B encoder also
fills the period between packets, called the idle period, with the continuou s stream of idle symbols.

Manchester Encoder - 10 Mbps

The Manchester encoding process combines clock and NRZ data such that the first half of the data
bit contains the complement of the data, and the second half of the data bit contains the true data, as
specified in IEEE 802.3. This guarantees that a transition always occurs in the middle of the bit call.
The Manchester encoder on the LAN91C111 converts the 10Mbps NRZ data from the controller
interface into a Manchester Encoded data stream for the TP transmitter and adds a start of idle pulse
(SOI) at the end of the packet as specified in IEEE 802.3. The Manchester encoding process is only
done on actual packet data, and the idle period between packets is not Manchester encoded and filled
with link pulses.

7.7.3 Decoder

4B5B Decoder - 100 Mbps

Since the TP input data is 4B5B encoded on the transmit side, it must also be decoded by the 4B5B
decoder on the receive side. The mapping of the 5B nibbles to the 4B code words i s specified in IEEE

802.3. The 4B5B decoder on the LAN91C111 takes the 5B code words from the descrambler, converts
them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B
decoder also strips off the SSD delimiter (a.k.a. /J/K/ symbols) and replaces them with two 4B Data 5
nibbles (a.k.a. /5/ symbol), and strips off the ESD delimiter (a.k.a. /T/R/ symbols) and replaces it with
two 4B Data 0 nibbles (a.k.a. /I/symbol), per IEEE 802.3 specifications and shown in Figure 7.3.

T a ble 7.1 4B/5B Symbol Mapping

SYMBOL NAME DESCRIPTION 5B CODE 4B CODE

0 Data 0 11110 0000
1 Data 1 01001 0001
2 Data 2 10100 0010

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Table 7.1 4B/5B Symbol Mapping (continued)

SYMBOL NAME DESCRIPTION 5B CODE 4B CODE

3 Data 3 10101 0011
4 Data 4 01010 0100
5 Data 5 01011 0101
6 Data 6 01110 0110
7 Data 7 01111 0111
8 Data 8 10010 1000

9 Data 9 10011 1001
A Data A 10110 1010
B Data B 10111 1011
C Data C 11010 1100
D Data D 11011 1101

Datasheet

E Data E 11100 1110
F Data F 11101 1111

I Idle 11111 0000

J SSD #1 11000 0101
K SSD #2 10001 0101
T ESD #1 01101 0 000
R ESD #2 00111 0000
H Halt 00100 Undefined

--- Invalid codes All others* 0000*

* These 5B codes are not used. For decod er, these 5B codes are decoded to 4B 0000. For encoder,
4B 0000 is encoded to 5B 11110, as shown in symbol Data 0.

The 4B5B decoder detects SSD, ESD and codeword errors in the incoming data stream as specified
in IEEE 802.3. These errors are indicated by asserting RX_ER output while the errors are being
transmitted across RXD[3:0], and they are also indicated in the serial port by setting SSD, ESD, and
codeword error bits in the PHY MI serial port Status Output register.

Manchester Decoder - 10 Mbps

In Manchester coded data, the first half of the data bit contains the complement of the data, and the
second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts
the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface
by decoding the data and stripping off the SOI pulse. Since the clock and data recovery block has
already separated the clock and data from the TP receiver, the Manchester decoding process to NRZ
data is inherently performed by that block.

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7.7.4 Clock and Data Recovery

Clock Recovery - 100 Mbps

Clock recovery is done with a PLL. If there is no vali d data present on the T P inputs, the PLL is locked
to the 25 MHz TX25. When valid data is detected on the TP inputs with the squelch circuit and when
the adaptive equalizer has settled, the PLL input is switch ed to the incoming data on the TP input.
The PLL then recovers a clock by locking onto the transitions o f the incoming signal from the twisted
pair wire. The recovered dock frequency is a 25 MHz nibble dock, and that clock is outputted on the
controller interface signal RX25.

Data Recovery - 100 Mbps

Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted
by the PLL. The data is then converted from a single bit stream i nto nibble wide data word according
to the format shown in Figure 7.2.

Clock Recovery - 10 Mbps

The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the
recovered clock frequency is 2.5 MHz nibble clock, (2) the PLL is switched from TX25 to the TP input
when the squelch indicates valid data, (3) The PLL takes up to 12 transitions (bit times) to lock onto
the preamble, so some of the preamble data symbols are lost, but the dock recovery block recovers
enough preamble symbols to pass at least 6 nibbles of preamble to the receive controller interface as
shown in Figure 7.2.

Data Recovery - 10 Mbps

The data recovery process for 10Mbps mode is identical to the 100Mbps mode. As mentioned in the
Manchester Decoder section, the data recovery process inherently performs decoding of Manchester
encoded data from the TP inputs.

7.7.5 Scrambler

100 Mbps

100BASE-TX requires scrambling to reduce the radiated emissions on the twisted pair. The
LAN91C111 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE

802.3 specifications, and sends it to the TP transmitter.

10 Mbps

A scrambler is not used in 10Mbps mode.

Scrambler Bypass

The scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY Ml serial
port Configuration 1 register. When this bit is set, the 5B data bypasses the scrambler and goes
directly from the 4B5B encoder to the twisted pair transmitter.

7.7.6 Descrambler

100 Mbps

The LAN91C111 descrambler takes the scrambled data from the data recovery block, descrambles it
per the IEEE 802.3 specifications, aligns the data on the correct 5B word boundaries, and sends it to
the 4B5B decoder.

The algorithm for synchronization of the descrambler is the same as the algorithm outli ned in the IEEE

802.3 specification. Once the descrambler is synchronized, i t will maintain synchronization as long as
enough descrambled idle pattern 1's are defected within a given interval. To stay in synchronization,
the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1ms interval.

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If 25 consecutive descrambled idle pattern 1's are not detected within the 1ms interval, the descrambler
goes out of synchronization and restarts the synchronization process.

If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is
set in the Ml serial port Status Output register to indicate this condition. Once this bit is set, it will stay
set until the descrambler achieves synchronization.

10 Mbps

A descrambler is not used in 10 Mbps mode.

Descrambler Bypass

The descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the PHY MI
serial port Configuration 1 register. When this bit is set, the data bypasses the descrambler and goes
directly from the TP receiver to the 4B5B decoder.

7.7.7 Twisted Pair Transmitter

Transmitter - 100 Mbps

The TX transmitter consists of MLT-3 encoder, waveform generator and line driver.
The MLT-3 encoder converts the NRZ data from the scrambler into a three level MLT-3 code required

by IEEE 802.3. MLT-3 coding uses three levels and converts 1's to transitions between the three levels,
and converts 0's to no transitions or changes in level.

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The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator
takes the MLT-3 three level encoded waveform and uses an array of switched current sources to
control the rise/fall time and level of the signal at the Output. The output of the switched current
sources then goes through a low pass filter in order to "smooth" the current output and remove any
high frequency components. In this way, the waveform generator preshapes the output waveform
transmitted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE 802.3.
The waveform generator eliminates the need fo r any external filters on the TP transmit output.

The line driver converts the shaped and smoothed waveform to a curr ent output that can drive 100
meters of category 5 unshielded twisted pair cable or 150 Ohm shielded twisted pair cable.

Transmitter - 10 Mbps

The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so,
the transmitter still consists of a waveform generator and line driver.

The purpose of the waveform generator is to shape the output transmit pulse. The waveform generator
consists of a ROM, DAC, dock generator, and filter. The DAC generates a stair-stepped representation
of the desired output waveform. The stairstepped DAC output then goes thro ugh a low pass filter in
order to "smooth' the DAC output and remove any high frequency components. The DAC values are
determined from the ROM outputs; the ROM contents are chosen to shape the pulse to the desired
template and are clocked into the DAC at high speed by the clock generator. In this way, the waveform
generator preshapes the output waveform to be transmitted onto the twi sted pair cable to meet the
pulse template requirements outlined in IEEE 802.3 Clause 14 and also shown in Figure 7.4. The
waveshaper replaces and eliminates external filters on the T P transmit output.

The line driver converts the shaped and smoothed waveform to a curr ent output that can drive 100
meters of category 3/4/5 100 Ohm unshielded twisted pair cable or 150 Ohm shielded twisted pair
cable tied directly to the TP output pins without any extern al filters. During the idle period, no output
signal is transmitted on the TP outputs (except link pulse).

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