SMSC LAN91C111 User Manual 2

1 Overview
This Technical Reference Manual provides detailed part-specific information and general system design guidelines for the SMSC LAN91C111. Hardware engineers and software engineers should be familiar with this material before interfacing the SMSC LAN91C111 to a microprocessor or microcontroller.
This Manual is an active document and will be updated as required. The most recent version is available from the SMSC Web site (www.smsc.com

1.1 Audience

This manual assumes that the users have some familiarity with hardware design; Ethernet protocols, and various bus architectures. The audience of this technical reference manual is design engineers familiar with the microprocessor / microcontroller architecture of their choice, and is not intended to steer a customer towards any particular architecture. In contrast, the goal of this application note is to provide information pertaining to the LAN91C111 to allow a design engineer to be able to connect the device to any architecture.
AN 9.6
SMSC LAN91C111 32/16/8-Bit Three-In­One Fast Ethernet Controller ­Technical Reference Manual
).
2 Introduction
The SMSC LAN91C111 is a 32/16/8-bit Non-PCI Fast Ethernet controller that integrates on one chip a Media Access Control (MAC) Layer, a Physical Layer (PHY), 8K Byte internal Dynamically Configurable TX/RX FIFO SRAM.
The LAN91C111 supports dual speed 100Mbps or 10Mbps and the AutoNegotiation algorithm. By turning on the AutoNegotiation mode, the chip automatically configures itself for either 10 or 100Mbps modes, and either Full-Duplex or Half-Duplex mode; the results depend on the outcome of the negotiation process.
The LAN91C111 is a 3.3V device; but its inputs and output of the host interface are 5V tolerant and can directly interface to other 5V devices.
This 32-bit device can interface with multiple Embedded Microprocessor Host Interfaces due to its flexible Bus Interface Unit (BIU). It can handle both asynchronous and synchronous transfers as long as they are not simultaneously active. The synchronous bus clock can be supported up to 50Mhz.
There are two selectable LED's, they can be programmed to the following functions: Link, Activity, Transmit, Receive, Full Duplex, and 10/100Mbps.
The SMSC LAN91C111 silicon has the following main sections:
Bus Interface Unit
Arbiter
Memory Management Unit
8Kbytes Internal SRAM
CSMA/CD
SMSC AN 9.6 APPLICATION NOTE Revision 1.0 (08-14-08)
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Collision Detection
Encoder
Decoder
Scrambler
De-scrambler
Squelch Circuits
Clock & Data Recovery
AutoNegotiation & Link
Twisted Pair Transmitter
Twisted Pair Receiver
Control
Address
Data
EEPROM
INTERFACE
8-32 bit
Bus
Interface
Unit
Control
Control
Control
Control
WR
FIFO
RD
FIFO
Arbiter
MMU
8K Byte
Dynamically
Allo cate d
SRAM
TX/RX
FIFO
Pointer
32-bit Data
32-bit Data
DMA

Figure 2.1 Detailed Internal Block Diagram

Control
TX Data
RX Data
Ethernet Protocol
Handler
(EPH)
MII
Control
TPO
10/100
PHY
TXD[0-3]
TPI
RXD[0-3]
Revision 1.0 (08-14-08) 2 SMSC AN 9.6
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
3 Description Of Bus Interface Unit (BIU)
This section is intended to aid design engineers connecting the SMSC LAN91C111 device to a microprocessor or microcontroller. This section will discuss in detail the functional block, and the individual control signals of the LAN91C111 involved in the connection between the device and an associated microprocessor / microcontroller.

3.1 Pin Function Listing

The LAN91C111 consist of the following major pin groups:
PIN DESCRIPTION NUMBER OF PINS USED
System Address Pins 20
System Data Pins 32
System Control Pins 14
Serial EEPROM Pins 8
LED Pins 2
PHY Pins 8
Crystal Oscillator 2
Power Pins 10
Ground Pins 12
MII Connection Pins 18
Misc. Pins 2
The interfacing of the LAN91C111 is based on the use of the control lines to control the flow of information to and from the controller. The LAN91C111 is designed with the flexibility required to allow a design engineer to connect the LAN91C111 to just about any standard microprocessor architecture. This document should provide a design engineer the information needed to connect the LAN91C111 to the microprocessor or microcontroller of their choice.
SMSC AN 9.6 3 Revision 1.0 (08-14-08)
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
For those interested in designing connected to an ISA bus, SMSC provides both a reference design and evaluation board. Please contact your SMSC Sales Representative or Distributor for information regarding either of these products. The Data Sheet also contains block diagrams of a typical ISA, EISA, and VL-Bus based designs.

3.2 ISA Bus

The LAN91C111 supports both an asynchronous and a synchronous bus interface. The industry standard ISA bus is one of the typical asynchronous buses. This bus interface is well defined and documented and as previously mentioned, details are available from SMSC regarding interfacing the LAN91C111 to an asynchronous ISA type interface.

3.3 8-Bit Bus

The LAN91C111 supports 8-bit bus interface. Please see the following signal connection table.
8-BIT BUS (HOST) LAN91C111 NOTES
A1-A15 A1-A15 Address Bus

Figure 3.1 BIU Section of functional Block Diagram

Table 3.1 Single Connection Table

D0-D7 D0-D7 Data pins D0-D7 and D8-D15 of the
D0-D7 D8-D15
nBE0 nBE0 Assert nBE0 to enable the lowest byte
nBE1 nBE1 Assert nBE1 to enable the second lowest
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LAN91C111 both connect to D0-D7 of the 8-bit bus
byte
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.3.1 Address Decoding Example

BYTE
A3 A2 A1 IO-ADDRESS
0 0 0 300 nBE0 Assert nBE0 to enable the lowest byte
0 0 0 301 nBE1 Assert nBE1 to enable the second lowest byte
0 0 1 302 nBE0 Assert nBE0 to enable the lowest byte
0 0 1 303 nBE1 Assert nBE1 to enable the second lowest byte
0 1 0 304 nBE0 Assert nBE0 to enable the lowest byte
0 1 0 305 nBE1 Assert nBE1 to enable the second lowest byte
0 1 1 306 nBE0 Assert nBE0 to enable the lowest byte
0 1 1 307 nBE1 Assert nBE1 to enable the second lowest byte
ENABLE NOTES

3.3.2 I/O Base Address 300h Decoding

The chart below shows the decoding of I/O Base Address 300h:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000001100000000

3.4 Asynchronous Interface

When the LAN91C111 working with an asynchronous bus, the read and write operation are controlled by the edges of nRD and nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C111 clock and, therefore, asynchronous to the bus.
SMSC AN 9.6 5 Revision 1.0 (08-14-08)
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.4.1 Typical Signal Connection with Asynchronous Buses

LAN91C111
HOST SIGNALS
A1-A15 A1-A15 Address
D0-D31 D0-D31 Data
nBE [0-3] nBE[0-3] Byte Enable
SIGNALS NOTES
AEN/CS AEN Active low address enable. It can be connected to ship select if the
Reset Reset Reset
nADS/Ground nADS Active low address latch signal. It can be tied low, please see the
IOCHRDY/Wait ARDY Asynchronous Ready Signal
INT INTRO Interrupt
nRD nRD Asynchronous read strobe
nWR nWR Asynchronous write strobe
CS nDATACS Use only for direct access to data register
nEX32/nIOCS16 nLDEV Active low local device signal. It must be buffered using an open
Unused Pins (Use only for Synchronous bus interface)
nCYCLE Pull up externally (May through 10KΩ resistor)
W/nR Pull up externally (May through 10KΩ resistor)
nVLBUS Leave open or Pull up externally
LCLK Pull up externally (May through 10KΩ
chip select timing matches to AEN
timing diagrams figure 24 to 26 of the database.
collector driver is ISA bus.
nSRDY Leave open
nRDYRTN Pull up externally (May through 10K
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Ω resistor
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.4.2 Signal Connection with Asynchronous Interfacing

Figure 3.2 Asynchronous Interface Connection

3.5 Synchronous Interface (VL-Bus)

The LAN91C111 also supports a 32-bit synchronous interface. This interface is intended to duplicate the VESA standard (www.vesa.org widely understood as the ISA bus we will go over this interface in some detail in this document. The purpose of this discussion is not to necessarily duplicate a VL-Bus but to better explain the use of the control signals and requirements to support a synchronous interface. With this information a design engineer should be able to successfully interface the LAN91C111 to any generic synchronous bus interface. All registers except the DATA REGISTER will be accessed using byte or word instructions. Accesses to the DATA REGISTER could use byte, word, or double word (dword) instructions.
), otherwise known as the VL-Bus. Since this interface is not as
SMSC AN 9.6 7 Revision 1.0 (08-14-08)
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.5.1 Typical Connection with Synchronous Interface (VL-Bus)

HOST (VL BUS)
SIGNAL
LAN91C111
SIGNAL NOTES
A2-A15 A2-A15 Address bus used for I/O space and register
decoding, latched by nADS rising edgeand transparent on nADS low time.
M/nIO AEN Qualifies valid I/O decoding - enabled access
when low. This signal is latched by nADS rising edge and transparent on nADS low time.
W/nR W/nR Direction of access. Sampled by the
LAN91C111 on first rising clock that has nCYCLE active. High on writes, low on reads.
nRDYRTN nRDYRTN Ready return. Direct connection to VL bus.
nLRDY nSRDY and some
logic
nSRDY has the appropriate functionality and timing to create the VL nLRDY except that nLRDY behaves like an open drain output most of the time.
LCLK LCLK Local Bus Clock. Rising edges used for
synchronous bus interface transactions.
nRESET RESET Connected via inverter to the LAN91C111.
nBE0 nBE1 nBE2 nBE3 nBE0 nBE1 nBE2
nBE3
Byte enables. Latched transparently by nADS rising edge.
nADS nADS, nCYCLE Address Strobe is connected directly to the VL
bus. nCYCLE is created typically by using nADS delayed by one LCLK.
IRQn INTR0 Typically uses the interrupt lines on the ISA
edge connector of VL bus
D0-D31 D0-D31
32 bit data bus. The bus byte(s) used to access
the device are a function of nBE0-nBE3:
n
BE0 nBE1 nBE2 nBE3
0 0 0 0 Double word access 0 0 1 1 Low word access 1 1 0 0 High word access 0 1 1 1 Byte 0 access 1 0 1 1 Byte 1 access 1 1 0 1 Byte 2 access 1 1 1 0 Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that nBE2 and nBE3 override the value of A1, which is tied low in this application.
nLDEV nLDEV nLDEV is a totem pole output. nLDEV is active
on valid decodes of A15-A4 and AEN=0.
UNUSED PINS
VCC nRD nWR Pull up externally (May through 10KΩ resistor)
GND A1 nVLBUS Pull down externally (May through 10KΩ
resistor)
OPEN nDATACS Leave Open
Revision 1.0 (08-14-08) 8 SMSC AN 9.6
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.5.2 Signal Connection with Synchronous Interfacing

+VCC
A2-A15
M/nIO
nRESET
IRQn
D0-D31
nRDYRTN
nBE0-nBE3
nADS
nLRDY
O.C.
simulated
O.C.
delay1
nLDEV
W/nRW/nR
A2-A15
LCLKLCLK
AEN
RESET
LAN91C111
INTR0
D0-D31
nRDYRTN
nBE0-nBE3
nADS
nCYCLE
nSRDY
nWR
nVLBUS
nDATACS
nLDEV
nR
D
A1
(Open)

Figure 3.3 Synchronous Interface (VL-Bus) Connection

3.5.3 Address Bus

The 13 address lines form the address bus. It is presented to the LAN91C111 in these pins. The address remains transparent until it is latched on the rising edge of the nADS signal. Each VL-Bus operation starts with an address phase during which the pins A15-A2 transfer an address. Since the LAN91C111 is considered an I/O device, there is no need for additional address lines.

3.5.4 AEN

AEN – Address Enable is an input to the LAN91C111. AEN is an address qualifier used to indicate that the address presented to LAN91C111 is valid. AEN is active low. Address decoding on the LAN91C111 is only enabled when AEN is active. This active low signal is typically connected to a nCS signal of the microprocessor or microcontroller.

3.5.5 W/NR

W/nR indicates whether the cycle is to be a Read or a Write cycle. A high indicates Write and subsequently a low indicates a Read cycle. This signal pin is used during synchronous bus operations and can be either connected directly to the CPU or to tri-state buffers. The W/nR is sampled on the rising edge of the LCLK signal. For asynchronous bus operations, this signal pin should be pulled high for proper operation.
SMSC AN 9.6 9 Revision 1.0 (08-14-08)
APPLICATION NOTE

3.5.6 NRDYRTN

Ready Return is an input signal generated by the host controller to establish a handshake signal to inform the LAN91C111 that the cycle has ended. For LCLK speeds up to 33Mhz, nRDYRTN is typically asserted in the same LCLK cycle as nSRDY is asserted. For higher LCLK speed, nRDYRTN may trail nSRDY by one LCLK cycle due to signal resynchronization.
In Non-VL-Bus mode, Ready Return is an input signal generated by the host controller to indicate that the cycle is not completed and that the next cycle needs to be delayed. nRDYRTN is used to insert wait states during burst operations. A wait state will be inserted if nRDYRTN is asserted and subsequently for each clock period that nRDYRTN is held. nRDYRTN is sampled on the falling edge of LCLK and will insert a wait state on each subsequent falling edge of LCLK that nRDYRTN is held.

3.5.7 NSRDY

nSRDY is an output signal from the LAN91C111 to inform the CPU that it has completed the data transfer and the CPU can terminate the current active bus cycle. When the bus controller detects the nSRDY asserted, it may immediately assert nRDYRTN or, at speed greater than 33Mhz, it may resynchronize nSRDY and assert nRDYRTN on the next LCLK cycle. If the current transfer is a read, the LAN91C111 holds the read data on the data bus until the LCLK which nRDYRTN is sampled asserted. nSRDY is asserted low for one LCLK period.

3.5.8 LCLK – Clock Input

SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
LCLK is the system bus clock required for synchronous operation. The clock is input on the LCLK pin and can be a maximum of 50MHz in operation. The duty cycle of the clock should be 50/50 with the least amount of jitter as possible well. Typically the clock will be the same clock used on the microprocessor or microcontroller of the design. The LCLK pin is 5V tolerant. All timings specified in synchronous or VL-Bus will be in respect to the LCLK. This pin should be tied high or clocked if the LAN91C111 operates in Asynchronous mode.

3.5.9 Reset

RESET causes the LAN91C111 to go to its default states. RESET must be held for 100nS in order to force the LAN91C111 into it’s reset state. This is to avoid potential problems with glitches. Once the 100nS-time parameter has been met, the device will remain in reset as long as RESET is held high.

3.5.10 NBE0-NBE3

Byte Enable lines 0 through 3 indicate what type of transfer is occurring, byte, word, or double word. The LAN91C111 does support all modes of operation. Below is a chart of how transfers are decoded using the Byte Enable lines:
NBE0 NBE1 NBE2 NBE3
0 0 0 0 Double word access
0 0 1 1 Low word access
1 1 0 0 High word access
0 1 1 1 Byte 0 access
1 0 1 1 Btye 1 access
1 1 0 1 Btye 2 access
1 1 1 0 Byte 3 access
Revision 1.0 (08-14-08) 10 SMSC AN 9.6
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.5.11 32-Bit Access and nBE0-nBE3

The LAN91C111 can operate in 32, 16, or 8-bit mode. Since the registers are assigned to different banks, changing bank is required if accessing to registers at other bank. Changing bank can be done by writing to Offset E – Bank Select Register, however offset C, D, E, F are in the same double word (32-bit) alignment, writing a double word to offset C, will only write to offset E, and will not write to Offset C, D, and F, because the chip only decodes the bank select register bits. Thus when writing to Offset C, D, it must be 8 or 16-bit mode. In 8 or 16-bit access, nBE pins have to be asserted appropriately. For example, if Low word is accessed, nBE[0-1] pins has to be asserted, and nBE[2-3] must be pulled high.
For read, all registers can be read in 32, 16, or 8-bit mode.

3.5.12 NADS and NCYCLE

nADS (Address Strobe) and nCYCLE indicate that the address is valid to the LAN91C111. The nCYCLE signal is created externally by delaying the ADS signal by one LCLK cycle. The processor or bus master must drive valid data on the bus prior to asserting nCYCLE. The nCYCLE pin is discussed in detail under the nDATACS mode of operations.
The LAN91C111 does not support burst mode operations on the VL-Bus interface in VL-Bus mode. There is burst type capabilities using nDATACS mode, please see nDATACS mode of operations described in detail later on in this document.

3.5.13 INTR0

This pin operates as a level-triggered interrupt pin with an active high level. It is typically connected to IRQ9 but can be connected to whatever interrupt input pin is suitable for your design.

3.5.14 Data Bus

32-bit Data Bus of the LAN91C111. Byte steering is controlled using the BE0-BE3 pins.

3.5.15 NLDEV

nLDEV is used to indicate that the cycle being presented has been claimed by an external device, in this case the LAN91C111 is claiming the cycle once a valid qualified address decode is accomplished. The LAN91C111 will assert nLDEV to acknowledge the cycle being presented to it. The timing required for nLDEV to be asserted is processor specific. Please review the timing requirements for your particular design. On the LAN91C111 nLDEV is designed to assert in a minimum of 20nS after a valid address decode. It must be buffered using an open collector driver in ISA bus.

3.6 Timing Analysis

One way to better understand how this interface works is to examine the timing diagrams presented in the Data Sheet in some details. This is the goal of this section. Below are a timing diagram and the parameter table for a write cycle presented to the LAN91C111 device.
SMSC AN 9.6 11 Revision 1.0 (08-14-08)
APPLICATION NOTE
Address, AEN, nBE[3:0]
Clock
nADS
W/nR
nCYCLE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
t23
t20
t10
t24
t9
Valid
t8
t16
t11
Read Data
Valid
t21t21
nSRDY
nRDYRTN

Figure 3.4 Synchronous Write Cycle - nVLBUS=0

PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns
t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns
t10 nCYCLE Setup to LCLK Rising 5 ns
t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns
t16 W/nR Setup to nCYCLE Active 0 ns
t17A W/nR Hold after LCLK Rising with nSRDY Active 3 ns
t18 Data Setup to LCLK Rising (Write) 15 ns
t20 Data Hold from LCLK Rising (Write) 4 ns
t21 nSRDY Delay from LCLK Rising 7 ns
It is important to remember that timings are determined by the LCLK signal since this is a synchronous bus. If you examine the timing diagram for the write cycle in VL-Bus (Synchronous) mode you should observe the following:

3.6.1 Write Cycle Address Phase - Cycle Start

The Address Bus, AEN, and the Byte Enable lines (BE0-BE3), as presented by the microprocessor/ microcontroller, should be stable 8nS prior to the de-assertion of nADS. The de-assertion of nADS latches in the address and transfer size to the LAN91C111. These lines should also be held for a minimum of 5nS after the de-assertion of nADS to ensure this latching. nLDEV will assert at a minimum of 30nS after the address has been decoded by the de-assertion of nADS and the LAN91C111 claims the cycle. The signal nCYCLE is synchronous to LCLK, the generation of nCYCLE will need to be
Revision 1.0 (08-14-08) 12 SMSC AN 9.6
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
accomplished through external circuitry. Signal W/nR has to be asserted high no later than nCYCLE assertion.

3.6.2 Write Cycle Data Phase - Cycle End

During next rising edge after de-assertion of nCYCLE, write data has to be presented to the LAN91C111. The data bus will need to be stable at least 15nS prior to the rising edge of LCLK and are required to hold 4nS, as specified by timing parameter t18 and t20. nSRDY (translated to nLRDY for the VL-Bus) is asserted during data latching for one cycle. Data input latch is transparent during nSRDY is low, data is being written to internal registers. nSRDY will de-assert indicating that the data was written to the LAN91C111 successfully. The W/nR signal can be released 3nS after the rising edge of LCLK during the data phase of the cycle.

3.6.3 Read Cycle

We will now examine a Read Cycle using the VL-Bus on the LAN91C111. Below is the timing diagram and parameter listing from the Data Sheet. As you can see the Read cycle requires one more clock cycle than the Write cycle. This extra time is required for the LAN91C111 to fetch the data internally prior to presenting it on the Data Bus.
Clock
t10
t23
t20
t24
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Read Data
nSRDY
nRDYRTN
t9
Valid
t8
t16
t11
Valid
t21t21

Figure 3.5 Synchronous Read Cycle - NVLBUS=0

PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE [3:0] Setup to
nADS Rising
t9 A1-A15, AEN, nBE[3:0] Hold After
nADS Rising
t10 nCYCLE Setup to LCLK Rising 5 ns
SMSC AN 9.6 13 Revision 1.0 (08-14-08)
8ns
5ns
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
PARAMETER MIN TYP MAX UNITS
t11 nCYCLE Hold after LCLK Rising
(Non-Burst Mode)
t16 W/nR Setup to nCYCLE Active 0 ns
t20 Data Hold from LCLK Rising
(Read)
t21 nSRDY Delay from LCLK Rising 7 ns
t23 nRDYRTN Setup to LCLK Rising 3 ns
t24 nRDYRTN Hold after LCLK Rising 3 ns
3ns
4ns

3.6.4 Read Cycle Address Phase – Cycle Start

As with the Write Cycle, the Address Bus, AEN, and the Byte Enable lines (nBE0-nBE3) are required to be stable 8nS prior to the de-assertion of nADS and 5nS after this rising edge to guarantee a valid address latching. nLDEV is asserted within 30nS to indicate that the LAN91C111 has claimed this cycle. The nCYCLE signal will also again need to be generated externally and asserted after address latching. W/nR should be stable at a low logic level after nCYCLE assertion.

3.6.5 Read Cycle Delay Phase

Unlike the Write Cycle, there is a delay required during read operations to allow the LAN91C111 to fetch the required data. This phase occurs immediately after the address phase and is completed in one LCLK cycle. During this time the Data Bus is not required to be stable, nor is the address bus.

3.6.6 Read Cycle Data Phase – Cycle End

As the timing diagram represents, the read data is presented from the LAN91C111 on the data bus and it is guaranteed to be stable at the rising edge when nSRDY (translated to nLRDY for the VL-Bus) is asserted. nSRDY and data remain stable until the LAN91C111 receives nRDYRTN asserted on the rising edge of LCLK plus hold time as specified by t20. The nRDYRTN and nSRDY signals indicate that the LAN91C111 has completed the cycle successfully. W/nR signal should be de-asserted only after nSRDY is de-asserted, therefore 7nS after LCLK rising with nSRDY active.

3.6.7 VL-Burst Mode Operation

Burst Mode operations as defined by the VESA standard are not supported by the LAN91C111 device in VL-Bus mode.

3.7 Direct Data Register Access interface (nDATACS)

Another option available for design engineers to connect to the LAN91C111 is through a direct interface. This interface is controlled using the nDATACS pin and allows a designer to connect a controller directly to the LAN91C111 Data Register by bypassing the internal BIU decoders. This section will discuss in some detail the information necessary to accomplish this interface. This interface is always
The LAN91C111 offers the design engineer several options as to how this mode of operation can be implemented. The choices are between synchronous and asynchronous, burst and non-burst modes. Each of these options will be discussed in detail below.
32-bits in nature and therefore the use of the BE0-BE3 pins are ignored.
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APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.7.1 The Use of NDATACS

Direct access to the Data Register is controlled via the nDATACS pin. This is can be accomplished whether the LAN91C111 is configured for synchronous or asynchronous operations. Accessing the LAN91C111 via the nDATACS pin bypasses the internal Bus Interface Unit (BIU) decoders and accesses designated by the nDATACS are steered towards the Data Register only 32-bits in nature and used to read or write directly to the internal data register memory of the LAN91C111 device.
In addition to direct access to the Data Register via the nDATACS signal, there is also an additional feature available, Burst Mode operation. Burst mode operations can be accomplished in synchronous mode. By using the nCYCLE pin in conjunction with the nDATACS, the design engineer is capable of direct data register access in a burst style operation. Control of the speed of bursting to the LAN91C111 can be accomplished via the nRDYRTN signal. The nRDYRTN signal is used to insert wait states in a burst type cycle. By combining these signals, multiple speeds of memory can be controlled. We will examine both a burst and non-burst mode (asynchronous) transfers later on in this document.
The proper use of this type of accesses does require that the LAN91C111 be configured correctly. The entire setup of the LAN91C111 is beyond the scope of this document and a design engineer should review the LAN91C111 Data Sheet. One area of significance that will be covered and is common among all caveats of nDATACS operation is the use of the Pointer Register.

3.7.2 Pointer Register

. All accesses are
The Pointer Register is an internal register where the control of the internal Data Register(s) (FIFO’s) is done. This register defines where the cycle is being presented to the Data Register and also other control information and options.
The Pointer Register also controls the Auto-Increment feature of the FIFO. This will be discussed in detail as well. Control as to whether to information is read or written is done by the READ bit within this register. The RCV bit controls the area written to or read from. If this bit is set, the receive area of the FIFO is accessed, if cleared the transmit area of the FIFO is accessed. The contents and settings of this register will be discussed next.
OFFSET NAME TYPE SYMBOL
6 POINTER REGISTER READ/WRITE PTR
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE
0 0 0 0 0 0 0 0
RCV
AUTO INCR.
READ Reserved
POINTER LOW
NOT
EMPTY
POINTER HIGH

Figure 3.6 Pointer Register

RCV
The RCV bit being set indicates that the operation is to access the receive area and accesses the RX FIFO as the packet number. When this bit is cleared, the write area of the TX FIFO is being accessed.
AUTOINCR
The AUTOINCR bit indicates whether the internal MMU is to automatically change the address for the next Data Register accesses. Note: If AUTOINCR is not set, the pointer must be loaded with a dword­aligned value prior to the next access of the Data Register.
SMSC AN 9.6 15 Revision 1.0 (08-14-08)
APPLICATION NOTE
READ
When set (1) the operation is a read; when cleared (0) the operation is a write.
NOT EMPTY
This read-only bit indicates whether the Write Data FIFO is empty or not. The FIFO is not empty when this bit is set.
POINTER HIGH
These bits comprise the upper three bits of the address.
POINTER LOW
These bits comprise the lower 8-bits of the address. Remember that all access is 32-bits in nature and therefore the lower two bits are ignored thus allowing all 8K bytes to be accessed.
Reserved
Must be 0.

3.7.3 Data Register

The Data Register comprises the FIFO’s for both transmit and receive side of the Ethernet port. This FIFO is unidirectional in nature and can normally be read or written in byte, word, or dword aligned accesses. These accesses can be mixed or matched on the fly. The ability to do byte, word, or dword access is controlled via the address line A1 and the BE0-BE3 control lines during normal mode of operation.
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
If using the nDATACS line to accomplish direct access then all transfers are 32-bits in nature and the use of A1 and BE0-BE3 is ignored.
The Data Register is mapped into two consecutive word locations for double word operations regardless of the bus width of the target device (16 or 32 bit). The FIFO depth is 12 bytes each.
For the purpose of this discussion all accesses will be 32-bits in nature because we are using nDATACS to access the Data Register.
OFFSET
8 THROUGH Bh
X X X X X X X X
X X X X X X X X
NAME
DATA REGISTER

Figure 3.7 Data Register

DATA H IGH
DATA LOW
TYPE
READ/ WRITE
SYMBOL

3.7.4 Timing Analysis Of Direct Access

In this section we will examine the timing diagrams using the nDATACS line to control direct access.

3.8 Asynchronous Read or Write Operation – Non Burst

This section will discuss the asynchronous Read or Write operations using the nDATACS signal in a non-Burst mode.
DATA
The timing diagram below details a typical cycle, this could be either a read or write cycle. The use of the nRD and nWR signals controls the data flow to and from the Data Register. The asynchronous nature of the nRD or nWR signals along with the absence of an LCLK is why this is referred to as an asynchronous mode of operation.
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APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
nDATACS
Read Data
nRD, nWR
Write Data

Figure 3.8 Asynchronous Cycle - nADS=0

(nDATACS Used to Select Data Register; Must Be 32 Bit Access)
t2
t4t3A
Valid
t6At6A
t5t1
t5A
D 0-D 31 V alid
PARAMETER MIN TYP MAX UNITS
t1 nDATACS Setup to nRD, nWR
Active
t2 nDATACS Hold After nRD, nWR
Inactive (Assuming nADS Tied Low)
t3A nRD Low to Valid Data 30 ns
t4 nRD High to Data Invalid 2 15 ns
t5 Data Setup to nWR Inactive 10 ns
t5A Data Hold After nWR Inactive 5 ns
t6A nRD Strobe Width 30 ns
This timing diagram and subsequent parameter information detail a typical reads or write operation. As you can see by the timing diagram the first step is to have the address qualified with the assertion of nADS. Since this discussion is focused on the use of the nDATACS signal, this step is accomplished by programming the pointer register to where the access is going to occur. By using nDATACS the values on the address bus and the byte enable lines (BE0-BE3) are ignored.
There is a minimum delay of 2nS prior to the assertion of nRD or nWR. For a read operation the data becomes valid on the data bus a maximum of 30nS after the assertion of the nRD line. For a write operation the data needs to be valid for a minimum of 10nS prior to the de-assertion of nWR and needs to be held for 5nS after this de-assertion.
2ns
5ns
In asynchronous mode of operation, to accomplish multiple back-to-back transfers (either nWR or nRD) the minimum time between transactions is 80nS. This means that you can pulse either nWR or nRD at 80nS intervals. In the case of full duplex mode the timing changes to 100nS between pulses.

3.9 Burst Mode Operation Timing – Synchronous Operation

Burst mode operations using the LAN91C111 require that the nVLBUS pin to be de-asserted and that an LCLK be provided. The nCYCLE pin is used to indicate that bursting is to be done and the
SMSC AN 9.6 17 Revision 1.0 (08-14-08)
APPLICATION NOTE
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
nRDYRTN can be used to insert wait states. In Synchronous mode back to back time between read or write is limited by access times. From timing diagram, it is 3 clocks for read and 2 clocks for write, but it has to be bigger than 100ns for read and 80ns for write.

3.10 Burst Mode Write Operation

The timing diagram below details a burst mode write operation and shows three separate packets of data being transferred. The first two packets occur sequentially and the third packet is held off using the nRDYRTN signal.
t12
Clock
nDATACS
W/nR
nCYCLE
Write Data
nR DY RTN
t22t17
ab c

Figure 3.9 Burst Mode Write Operation

PARAMETER MIN TYP MAX UNITS
t12 nDATACS Setup to LCLK
Rising
t18t14t18
t12A
t17A
t22A
t20t20t20
t15
20 ns
t12A nDATACS Hold After LCLK
0ns
Rising
t14 nRDYRTN Setup to LCLK
10 ns
Falling
t15 nRDYRTN Hold after LCLK
10 ns
Falling
t17 W/nR Setup to LCLK Falling 15 ns
t17A W/nR Hold After LCLK Falling 3 ns
t18 Data Setup to LCLK Rising
15 ns
(Write)
t20 Data Hold from LCLK Rising
4ns
(White
t22 nCYCLE Setup to LCLK
5ns
Rising
t22A nCYCLE Hold After LCLK
10 ns
Rising
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