SMSC LAN1198 User Manual
1 Introduction
This application note describes how to successfully develop a network device driver for LAN9118
Family products. It covers device features, software design techniques, network operating system
interfaces, and critical design points. It provides basic design guidelines for incorporating LAN9118
Family products into networked applications. It overviews topics as microprocessor-LAN hardware
interactions; initialization, interrupts, operating system, and communication protocol stack
considerations.It also reviews good design practice for engineers getting acquainted with network
device design.
1.1 References
This manual references the following documents:
SMSC LAN9118 Datasheet
SMSC LAN9117 Datasheet
SMSC LAN9116 Datasheet
SMSC LAN9115 Datasheet
SMSC LAN9118 Reference Design Schematic
SMSC LAN9117 Reference Design Schematic
SMSC LAN9116 Reference Design Schematic
SMSC LAN9115 Reference Design Schematic
AN 12.12
LAN9118 Family Programmer
Reference Guide
Always refer to these documents for complete and current device information. Circuit examples shown
in this document are for illustration only. Follow the corresponding Reference Design Schematic when
implementing an actual circuit design of a LAN9118 Family device.
Please visit SMSC’s website at http://www.smsc.com
for the latest updated documentation.
1.2 Document Conventions
In this document, the terms device, network device, controller, and network controller all refer to a
controller in the LAN9118 Family, which includes the LAN9118, LAN9117, LAN9116 and LAN9115.
Host refers to the system into which the device is designed, including the processor, and
application software, etc.
MAC stands for Media Access Controller; the portion of the device responsible for sending or
receiving blocks of data from the network.
A packet is a complete Ethernet frame not yet sent through the MAC, or a frame after it has been
received by the MAC.
A frame is a complete Ethernet data frame with the 802.3 Layer 2 (MAC) header included.
A bit is a single binary digit that has a value of 1 (high) or 0 (low). A field is a continuous string of
bits of whatever length specified.
SMSC AN 12.12 APPLICATION NOTE Revision 1.0 (12-14-09)
An octet or byte is a group of 8 bits, treated as a single unit, with a value of 0-255 unsigned, or -
10/100 Ethernet
PHY
10/100 Ethernet MAC
2kB to 14kB
Configurable TX FIFO
2kB to 14kB
Configurable RX FIFO
Host Bus Interface
(HBI)
SRAM I/F
Interrupt
Controller
GP Timer
PIO Controller
IRQ
FIFO_SEL
+3.3V to +1.8V
PLL Regulator
PLL
25MHz
+3.3V
EEPROM
Controller
EEPROM
(Optional)
RX Status FIFO
TX Status FIFO
MIL - TX Elastic
Buffer - 2K
MIL - RX Elastic
Buffer - 128bytes
+3.3V to +1.8V
Core Regulator
+3.3V
127 to +127 signed. A byte is generally the smallest unit of data that can be individually addressed.
A word or short int is a group of 16 bits or two bytes,2 adjacent bytes, representing a 16-bit, single
symbol or a numeric range from 0 – 65,535 unsigned, or +/- 32,767 as a signed value. WORD
values are aligned on 2-byte memory boundaries. Their addresses are always expressed in even
number terms ending in 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, and 0xe.
A DWORD or long int always refers to 4 adjacent bytes, representing a 32-bit, single symbol or a
numeric range from 0 – 4,294,967,295, or +/- 2,147,483,647 as a signed value. DWORD values
are aligned on 4-byte memory boundaries. Their addresses are always expressed in even number
terms ending in 0x0, 0x4, 0x8, and 0xc.
2 Controller Overview
LAN9118 Family devices are full-featured, single-chip 10/100 Ethernet controllers designed for
embedded applications where performance, flexibility, ease of integration and low cost are required.
LAN9118 Family devices are fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant.
LAN9118 Family devices include an integrated Ethernet MAC and PHY with a high-performance
SRAM-like slave interface. The simple, yet highly functional host bus interface provides glue-less
connection to most common 32- and 16-bit microprocessors and microcontrollers, including those 32bit microprocessors presenting a 16-bit data bus interface to the device. LAN9118 Family Devices
include large transmit and receive data FIFOs with a high-speed host bus interface to accommodate
high bandwidth, high latency applications. In addition, the devices memory buffer architecture allows
the most efficient use of memory resources by optimizing packet granularity.
LAN9118 Family Programmer Reference Guide
2.1 Block Diagrams
2.1.1 Internal Block Diagram
Figure 2.1 LAN9118 Family Device Internal Block Diagram
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LAN9118 Family Programmer Reference Guide
Microprocessor/
Microcontroller
LAN9118
Family
Member
Magnetics Ethernet
System
Peripherals
System Memory
System Bus
EEPROM
(Optional)
LEDS/GPIO
25MHz
XTAL
System Memory
2.1.2 System Level Block Diagram
Figure 2.2 LAN9118 Family Device System-Level Block-Diagram
2.2 Common Product Family Features
Single chip Ethernet controller
Fully compliant with IEEE 802.3/802.3u standards
Integrated Ethernet MAC and PHY
10BASE-T and 100BASE-TX support
Full- and Half-duplex support
Full-duplex flow control
Backpressure for half-duplex flow control
Preamble generation and removal
Automatic 32-bit CRC generation and checking
Automatic payload padding and pad removal
Loop-back modes
Flexible address filtering modes
Integrated Ethernet PHY
One 48-bit perfect address
64 hash-filtered multicast addresses
Pass all multicast
Promiscuous mode
Inverse filtering
Pass all incoming with status report
Disable reception of broadcast packets
Auto-negotiation
Automatic polarity correction
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High-Performance host bus interface
Simple SRAM-like interface
Large, 16Kbyte FIFO memory with adjustable Tx/Rx allocation
Memory Alignment Technology (MAT) supports interleaved transmit/receive/command/status
access
One configurable Host interrupt
Burst read support
Comprehensive power management features
Numerous power management modes
Wake on LAN
“Packet-of-Interest” wakeup
Wakeup indicator event signal
Link Status Change
Miscellaneous features
Low profile 100-pin TQFP package
Single 3.3V power supply with 5V tolerant I/O
General Purpose Timer
Support for optional serial EEPROM
Supports for 3 LEDs/GPIO signals
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MAC CSR Port
SLAVE CSR's
A4h
B0h
Base + 00h
RESERVED
B4h
A0h
RX Data FIFO Port
TX Data FIFO Port
RX Status FIFO Port40h
20h
50h
FCh
EEPROM Port
04h
1Ch
RX Data FIFO Alias Ports
24h
3Ch
TX Data FIFO Alias Ports
RX Status FIFO PEEK44h
TX Status FIFO Port48h
TX Status FIFO PEEK4Ch
3 Register Description
Refer to the LAN9118 Family datasheets for complete descriptions of the Control and Status Registers
(CSRs), as well as for descriptions of register and bit names, nomenclature and attributes used in this
application note. Highlights are reproduced here for quick reference.
Figure 3.1 LAN9118 Family Device Memory MAP
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3.1 Directly Addressable Registers
These registers are also referred to as “Slave Registers”.
OFFSET SYMBOL REGISTER NAME DEFAULT
50h ID_REV Chip IP and Rev 01180001h
54h INT_CFG Main Interrupt Configuration 00000000h
58h INT_STS Interrupt Status 00000000h
5Ch INT_EN Interrupt Enable Register 00000000h
60h RESERVED Reserved for future use -
64h BYTE_TEST Read-only byte order testing register 87654321h
68h FIFO_INT FIFO Level Interrupts 48000000h
6Ch RX_CFG Receive Configuration 00000000h
70h TX_CFG Transmit Configuration 00000000h
Table 3.1 LAN9118 Family Directly Addressable Register Map
74h HW_CFG Hardware Configuration 00000800h
78h RX_DP_CTRL RX Datapath Control 00000000h
7Ch RX_FIFO_INF Receive FIFO Information 00000000h
80h TX_FIFO_INF Transmit FIFO Information 00001200h
84h PMT_CTRL Power Management Control 00000000h
88h GPIO_CFG General Purpose IO Configuration 00000000h
8Ch GPT_CFG General Purpose Timer 0000FFFFh
90h GPT_CNT General Purpose Timer Count 0000FFFFh
94h RESERVED Reserved for future use -
98h WORD_SWAP WORD_SWAP 00000000h
9Ch FREE_RUN Free Run Counter -
A0h RX_DROP RX Dropped Frames Counter 00000000h
A4h MAC_CSR_CMD These two registers are used to
access the MAC CSRs.
A8h MAC_CSR_DATA 00000000h
ACh AFC_CFG Automatic Flow Control 00000000h
B0h E2P_CMD These two registers are used to
access the EEPROM
B4h E2P_DATA 00000000h
00000000h
00000000h
B8h - FCh RESERVED Reserved for future use -
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3.2 MAC Control and Status Registers
The registers listed below are accessed indirectly through the MAC_CSR_CMD and MAC_CSR_DATA
Registers. These registers are used in Section 5.1.2 and Section 5.5.
.
INDEX SYMBOL REGISTER NAME DEFAULT
1 MAC_CR MAC Control Register 00040000h
2 ADDRH MAC Address High 0000FFFFh
3 ADDRL MAC Address Low FFFFFFFFh
4 HASHH Multicast Hash Table High 00000000h
5 HASHL Multicast Hash Table Low 00000000h
6 MII_ACC MII Access 00000000h
7 MII_DATA MII Data 00000000h
Table 3.2 LAN9118 Family MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
8 FLOW Flow Control 00000000h
9 VLAN1 VLAN1 Tag 00000000h
10 VLAN2 VLAN2 Tag 00000000h
11 WUFF Wake-up Frame Filter 00000000h
12 WUCSR Wake-up Status and Control 00000000h
3.3 PHY Registers
The PHY registers are accessed through two levels of indirection: through MAC_CSR_CMD/DATA
Registers and the MII_ACCESS/DATA Registers. The PHY provides its own interrupt source and mask
register; a “master” enable/disable bit for the PHY interrupts is found in the PHY_INT_EN bit in the
INT_STS/INT_EN registers.
Individual PHY Registers are identified through an index field located in the MII_ACC register . PHY
Register Indices are shown in Table 3.3 below. These registers are used in Section 5.6.
Note: PHY Register bits designated as NASR are reset when the SIM CSR Software Reset is
generated. The NASR designation is only applicable when bit 15 of the PHY Basic Control
Register (Reset) is set.
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Table 3.3 LAN9118 Family PHY Control and Status Register
PHY CONTROL AND STATUS REGISTERS
INDEX
(IN DECIMAL) REGISTER NAME
0 Basic Control Register
1 Basic Status Register
2 PHY Identifier 1
3 PHY Identifier 2
4 Auto-Negotiation Advertisement Register
5 Auto-Negotiation Link Partner Ability Register
6 Auto-Negotiation Expansion Register
17 Mode Control/Status Register
29 Interrupt Source Register
30 Interrupt Mask Register
31 PHY Special Control/Status Register
3.4 Restrictions on Read-Follow-Write CSR Accesses
There are timing restrictions on successive operations to some CSRs. These restrictions come into
play whenever a write operation to a control register is followed by a read operation from a related
register. These restrictions arise because of internal delays between write operations and their effects.
For example, when the TX Data FIFO is written, there is a delay of up to 135ns before the
TX_FIFO_INF register changes.
In order to prevent the host from reading invalid status, minimum wait periods have been established
following write operations to each CSR. These periods are specified in Ta bl e 3 .4 below. For each CSR,
the host is required to wait the specified period of time after a write before performing any read. These
wait periods are for read operations that immediately follow any write cycle. Note that the required wait
period is dependant upon the register being read after the write.
Performing “dummy” reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met. Tab le 3 .4 below also shows the number of dummy
reads that are required before reading the register indicated. The number of BYTE_TEST reads in this
table is based on the minimum timing for Tcyc (45ns). For microprocessors with slower busses, the
number of reads may be reduced as long as the total time is equal to, or greater than the time specified
in Ta bl e 3. 4. Note that dummy reads of the BYTE_TEST register are not required as long as the
minimum time period is met.
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Table 3.4 Read after Write Timing Rules
MINIMUM WAIT AFTER ANY
REGISTER NAME
ID_REV 0 0
INT_CFG 135 3
INT_STS 90 2
INT_EN 45 1
BYTE_TEST 0 0
FIFO_INT 45 1
RX_CFG 45 1
TX_CFG 45 1
HW_CFG 45 1
RX_DP_CTRL 45 1
RX_FIFO_INF 0 0
TX_FIFO_INF 135 3
PMT_CTRL 513 7
GPIO_CFG 45 1
WRITE CYCLE (IN NS)
NUMBER OF BYTE_TEST READS
(ASSUMING 45NS T
CYC)
GPT_CFG 45 1
GPT_CNT 135 3
WORD_SWAP 45 1
FREE_RUN 180 4
RX_DROP 0 0
MAC_CSR_CMD 45 1
MAC_CSR_DATA 45 1
AFC_CFG 45 1
E2P_CMD 45 1
E2P_DATA 45 1
3.5 Restrictions on Read-Follow-Read CSR Accesses
There are also restrictions on certain CSR read operations following other read operations. These
restrictions arise when a read operation has a side-effect that affects another read operation. In many
cases there is a delay between reading the a CSR and the subsequent side-effect. To prevent the host
from reading invalid status, minimum wait periods have been established. These wait periods are
implemented by having the host perform “dummy” reads of the BYTE_TEST register. The required
dummy reads are listed in the Ta bl e 3. 5 below:
SMSC AN 12.12 9 Revision 1.0 (12-14-09)
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Table 3.5 Special Back-to-Back Cycles
AFTER READING... PERFORM X READS OF BYTE_TEST BEFORE READING...
RX Data FIFO 3 RX_FIFO_INF
RX Status FIFO 3 RX_FIFO_INF
TX Status FIFO 3 TX_FIFO_INF
RX_DROP 4 RX_DROP
4 Programming Recommendations
The fundamental operations of the driver are initialization, transmit packet processing, receive packet
processing, and interrupt processing. In addition, the driver needs to manage link negotiation and
interact with the operating system. The driver may be required to keep statistics, manage power
consumption, and control other functions.
4.1 The Necessity of Register Ownership
Writing a driver is a complex task. Every possible sequence of operations needs to be considered. A
commonly encountered problem is having to share a resource, such as a CSR, between two or more
code threads. Having multiple code threads access the same resource only increases the challenge.
If one thread is interrupted by a second thread, such that both threads are attempting to modify the
resource at the same time, unpredictable behavior may result. Collectively, these conflicts are known
as synchronization issues.
4.2 The Importance of Planning (strcmp(“Fail to Plan”) == strcmp (“Plan to Fail”))
To prevent this type of unpredictable behavior, the first step in writing a driver is to plan which portions
of the driver will access which registers. Every potential synchronization issue needs to be considered
before the first line of code is written. Failure to do so will result in errors that are intermittent and
extremely difficult to reproduce. Even worse, these problems may not even surface until well into the
driver development. Initially, the driver may appear to work, but as integration proceeds and more
threads are added, and the environment becomes more complex, the driver may suddenly and
inexplicably develop problems.
4.3 Orthogonal Register Set
In order to prevent these types of synchronization issues, the register set of every LAN9118 Family
device has been organized so that each register only needs to be accessed by a single thread.
Registers which are accessed by the receive process do not need to be accessed by the transmit or
initialization processes, and so on. In addition, registers used to manage flow control and separated
from those used to manage the link.
The design of the register set, which is “orthogonal” allows the multiple threads within the driver to be
interweaved, or run concurrently without interfering with each other.
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4.4 Register Functionality in the LAN9118 Family Devices
Table 4.1, "Independent Data Threads Register Usage" details the functions of the most important
LAN9118 Family CSRs
Table 4.1 Independent Data Threads Register Usage
RECEIVE REGISTER NAME OFFSET PURPOSE
RX_FIFO_INF 0x7c Determine whether a packet is available
RX_STATUS_FIFO_PORT 0x40 Determine receive packet properties, such as size
RX_DATA_FIFO_PORT 0x00 Read received packet from device
TRANSMIT REGISTER NAME OFFSET PURPOSE
TX_FIFO_INF 0x80 Determine remaining free space in transmit FIFO, and
TX_STATUS_FIFO_PORT 0x48 Determine whether packets were sent successfully
TX_DATA_FIFO_PORT 0x20 Write packet data to device
FILTER REGISTER NAME OFFSET PURPOSE
MAC_CSR_CMD 0xa4 Access to MAC_CR, HASHH, and HASHL
MAC_CSR_DATA 0xa8 Access to MAC_CR, HASHH, and HASHL
LINK REGISTER NAME OFFSET PURPOSE
MAC_CSR_CMD 0xa4 Access to MII_ACC and MII_DATA
MAC_CSR_DATA 0xa8 Access to MII_ACC and MII_DATA
MII_ACC 0x6 Determine remaining free space in transmit FIFO, and
MII_DATA 0x7 Determine whether packets were sent successfully
Note: Notice that both the filter and link management functions depend upon the MAC_CSR_
registers. This shows the importance of synchronizing access to these particular registers
between the filter and link management threads.
number of packet statuses available
number of packet statuses available
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4.5 An Example of Concurrency
The need of maintaining the independence of the transmit and receive packet processing functions
has already been mentioned. For example, suppose that the transmit thread needs to execute
operations T0-T9 below as part of transmitting a packet:
TIME 0, T+1, T+2, T+3, … T+19
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
At the same time the receive thread needs to execute operations R0-R9 as part of receiving a packet:
TIME 0, T+1, T+2, T+3, … T+19
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
It is entirely possible for these operations to be interleaved as follows:
TIME 0, T+1, T+2, T+3, … T+19
T0 T1 R0 T2 R1 R2 T3 R3 R4 T4 T5 T6 T7 R5 R6 T8 R7 R8 R9 T9
The only requirement is that within each thread, proper order of the data stream must be maintained;
Receive operations must remain properly ordered and transmit operations likewise must remain
properly ordered. Aside from the required ordering within each data stream, the streams can be
interweaved arbitrarily; the controller must be capable of handling any legitimate possibility.
Interleaving also applies to the host interface. If both transmit and receive DMA channels are used,
the transmit DMA channel can be writing a packet while the receive DMA channel is concurrently
reading a packet. LAN9118 Family devices have been designed specifically to handle these kinds of
cases.
Interleaved accesses also support interleaving between the link and filter management threads
concurrent with the transmit and receive threads already described. This could occur if the transmit
and receive threads were both involved in DMA activities, while the CPU was handling the filter thread
at the moment a link-state change interrupted the processor. Because of the orthogonality of the
register set, all four threads could be interleaved successfully without errors.
4.6 Software Interrupt Feature (SwInt)
LAN9118 Family devices provide a software interrupt feature (Swint). This feature allows the driver to
force the device to activate its IRQ signal. This is done by setting the INT_EN:SW_INT_EN bit. One
use of this feature is to allow the driver to verify that it has properly registered the Interrupt Service
Routine to the correct IRQ during initialization.
Another use of this feature is to protect critical registers. One case where this feature can be used is
when an ISR accesses a register and it is critical that this register not be accessed outside the ISR.
If a code segment outside the ISR needs to access this register, rather than access the register directly,
the segment can set a flag bit indicating that the register should be accessed and then invoke the ISR
via the Swint feature. When the ISR sees the flag bit, it performs the register access on behalf of the
code segment. The thread which called the ISR would also need some mechanism for determining
that the request had completed, such as polling a status bit from the ISR.
Of course, this only works if there is only one segment of code outside the ISR needing to access the
critical register. If there are multiple threads accessing the register, they need additional
synchronization between them. Otherwise the activity of one thread may undo another; and if multiple
threads call the ISR using the same flag bit, the ISR will not be able to tell which thread called it.
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The first example works because of the assumption that only one thread will ever write to the flag and
signal the SwInt. The SwInt handler can use the flag to interpret the requested operation. This is known
as a producer-consumer relationship. That is, it is safe for multiple threads to share a variable if only
one thread is the writer, or producer of the variable, and all other threads are readers, or consumers
of that variable.
4.7 Ownership Policy in the Simple Driver
As a convenience to its customers, SMSC provides a simple driver for LAN9118 Family members,
written to run under the Linux, which has been reduced in complexity and function in order to highlight
the function of the device over the capabilities of a Linux device driver. Questions regarding register
usage, synchronization and ownership can generally be resolved through this reference work.
Table 4.2 below details the register ownership policy in the simple driver.
Table 4.2 Register Ownership Policy in the Simple Driver
REGISTER NAME OWNERSHIP POLICY
RX_DATA_FIFO Only used by the Rx thread, Rx_ProcessPackets
TX_DATA_FIFO Only used by the TX thread, Tx_SendSkb
RX_STATUS_FIFO Only used by the Rx thread, Rx_ProcessPackets
RX_STATUS_FIFO_PEEK Not Used
TX_STATUS_FIFO Used in Tx_CompleteTx in Tx_UpdateTxCounters.
TX_STATUS_FIFO_PEEK Not Used.
ID_REV Read Only
INT_CFG Set in Lan_Initialize,
INT_STS Sharable
INT_EN Initialized at startup.
BYTE_TEST Read Only
FIFO_INT Initialized at start up.
Tx_UpdateTxCounters is called by Tx_SendSkb in Simp911x_hard_start_xmit.
Tx_UpdateTxCounters is also called by Simp911x_stop but only after disabling
the TX queue in a multithreaded safe manner using the xmit_lock
Read in Simp911x_ISR
1) ClrBits in Simp911x_ISR
2) ClrBits in Rx_HandleInterrupt
3) SetBits in Rx_PopRxStatus
4) SetBits in Rx_ProcessPacketsTasklet
Items 1, 2, 3, 4 are not in contention because 1 and 2, are part of the ISR, and
3 and 4 is the tasklet which is only called while the ISR is disabled.
Used in Simp911x_stop
During run time only accessed by Tx_HandleInterrupt, and Tx_SendSkb and
done in a safe manner.
RX_CFG Only used during initialization
TX_CFG Only used during initialization
HW_CFG Only used during initialization
RX_DP_CTRL Only used in Rx thread, in Rx_FastForward
RX_FIFO_INF Read Only. Only used in Rx Thread, in Rx_PopRxStatus
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Table 4.2 Register Ownership Policy in the Simple Driver (continued)
REGISTER NAME OWNERSHIP POLICY
TX_FIFO_INF Read Only. Used in TX thread, in Tx_GetTxStatusCount, Tx_SendSkb, and
PMT_CTRL Only used during initialization, in Phy_Initialize
GPIO_CFG Only used during initialization, in Lan_Initialize
GPT_CFG Not Used
GPT_CNT Not Used
WORD_SWAP Not Used
FREE_RUN Not Used
RX_DROP Only used in Rx thread, in Rx_ProcessPackets
MAC_CSR_CMD Protected by MacPhyAccessLock
MAC_CSR_DATA Protected by MacPhyAccessLock
All MAC and PHY registers Protected by MacPhyAccessLock
AFC_CFG Used during initialization, in Lan_Initialize.
E2P_CMD Used during initialization, in Lan_Initialize
Tx_CompleteTx
Except during initialization where only one thread is running.
Except during initialization where only one thread is running.
Because MAC_CSR_ registers are protected, then all MAC and PHY registers
are protected as well since they are access through the MAC_CSR_ registers.
Also used during run time in timer call back, in Phy_UpdateLinkMode
E2P_DATA Not Used
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