SMSC GT3200, USB3250 User Manual

查询GT3200供应商查询GT3200供应商

GT3200

(64-PIN TQFP PACKAGES)

USB3250

(56-PIN QFN PACKAGE)

USB2.0 PHY IC

PRODUCT FEATURES

■ USB-IF "Hi-Speed" certified to USB2.0 electrical

specification

■ Interface compliant with the UTMI specification

(60MHz 8-bit unidirectional interface or 30MHz 16-bit
bidirectional interface)

■ Supports 480Mbps High Speed (HS) and 12Mbps

Full Speed (FS) serial data transmission rates

■ Integrated 45Ω and 1.5kΩ termination resistors

reduce external component count

■ Internal short circuit protection of DP and DM lines

■ On-chip oscillator operates with low cost 12MHz

crystal

■ Robust and low power digital clock and data recovery

circuit

■ SYNC and EOP generation on transmit packets and

detection on receive packets

Datasheet

■ NRZI encoding and decoding

■ Bit stuffing and unstuffing with error detection

■ Supports the USB suspend state, HS detection, HS

Chirp, Reset and Resume

■ Support for all test modes defined in the USB2.0

specification

■ Draws 72mA (185mW) maximum current

consumption in HS mode - ideal for bus powered
functions

■ On-die decoupling capacitance and isolation for

immunity to digital switching noise

■ Available in three 64-pin TQFP packages (GT3200)

or a 56-pin QFN package (USB3250)

■ Full industrial operating temperature range from

-40oC to +85oC (ambient)

SMSC GT3200, SMSC USB3250 DATASHEET Revision 1.3 (10-05-04)

ORDER NUMBER(S):

r

A

GT3200 - JD FOR 64 PIN 10 X 10 X 1.4MM TQFP PACKAGE

GT3200 - JN FOR 64 PIN 7 X 7 X 1.4MM TQFP PACKAGE

GT3200 - JV FOR 64 PIN 7 X 7 X 1.4MM TQFP LEAD FREE PACKAGE

USB3250 - ABZJ FOR 56 PIN 8 X 8 X 0.85MM QFN LEAD FREE PACKAGE

USB2.0 PHY IC

Hauppauge, NY 11788

[phone]

FAX [phone]

80 Arkay Drive

Copyright © SMSC 2004. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believ ed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and furthe
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

greement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 1.3 (10-05-04) ii SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

Table of Contents

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers. . . . . . . . . . . . 13

6.2 High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.5 RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.6 FS/HS RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.7 FS/HS TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.8 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.9 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Chapter 8 Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1 Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.2 OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.3 Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.4 SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.5 Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.6 Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.7 HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.8 HS Detection Handshake - FS Downstream Facing Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.9 HS Detection Handshake - HS Downstream Facing Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.10 HS Detection Handshake - Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.11 Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.12 Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.13 HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.14 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SMSC GT3200, SMSC USB3250 iii Revision 1.3 (10-05-04)

DATASHEET

USB2.0 PHY IC

List of Figures

Figure 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 3.1 64 pin GT3200 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 3.2 56 pin USB3250 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 13

Figure 6.2 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 14

Figure 6.3 Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6.4 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6.5 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7.1 Bidirectional 16-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7.2 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 20

Figure 7.3 FS CLK Relationship to Receive Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 20

Figure 7.4 Transmit Timing for a Data Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7.5 Transmit Timing for 16-bit Data, Even Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7.6 Transmit Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.7 Receive Timing for Data with Unstuffed Bits (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.8 Receive Timing for 16-bit Data, Even Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7.9 Receive Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7.10 Receive Timing for Data (with CRC-16 in 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7.11 Receive Timing for Setup Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7.12 Receive Timing for Data Packet with CRC-16 (8-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8.1 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8.2 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 8.3 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 8.5 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 8.6 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 8.7 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 8.9 Application Diagram for 64-pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 8.10 Application Diagram for 56-pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 9.1 GT3200-JD 64 Pin TQFP Package Outline, 10x10x1.4mm Body . . . . . . . . . . . . . . . . . . . . . 42

Figure 9.2 GT3200-JN, JV (lead free) 64 Pin TQFP Package Outline, 7x7x1.4mm Body . . . . . . . . . . . 44

Figure 9.3 USB3250-ABZJ (lead free) 56 Pin QFN Package Outline, 8x8x0.85mm Body . . . . . . . . . . 45

Revision 1.3 (10-05-04) iv SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

List of Tables

Table 4.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4.4 Biasing and Clock Oscillator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6.2 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6.5 Dynamic Characteristics: Digital UTMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6.6 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . 16

Table 6.7 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8.3 USB2.0 Test Mode to Macrocell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 8.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9.1 GT3200-JD 64 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 9.2 GT3200-JN, JV (lead free) 64 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . 44

Table 9.3 USB3250-ABZJ (lead free) 56 Pin QFN Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . 45

SMSC GT3200, SMSC USB3250 v Revision 1.3 (10-05-04)

DATASHEET

Chapter 1 General Description

The GT3200 and USB3250 provide the Physical Layer (PHY) interface to a USB2.0 Device Controller.
The IC is available in a 64 pin lead TQFP (GT3200) or a 56 pin QFN (USB3250).

1.1 Applications

The Universal Serial Bus (USB) is the preferred interface to connect high-speed PC peripherals.

■ Scanners

■ Printers

■ External Storage and System Backup

■ Still and Video Cameras

■ PDAs

■ CD-RW

■ Gaming Devices

1.2 Product Description

USB2.0 PHY IC

The GT3200 and USB3250 are USB2.0 physical layer transceiver (PHY) integrated circuits. SMSC's
proprietary technology results in low power dissipation, which is ideal for building a bus powered
USB2.0 peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit
bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI)
specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1
legacy protocol at 12Mbps.

All required termination for the USB2.0 Transceiver is internal. Internal 5.25V short circuit protection of
DP and DM lines is provided for USB compliance.

While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs
needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming
data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.

Revision 1.3 (10-05-04) 1 SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

Chapter 2 Functional Block Diagram

VDD3.3

VDD1.8

XO

XI

DATABUS16_8

RESET

SUSPENDN

XCVRSELECT

TERMSELECT

P

O

E

O

D

M

[

:

1

LINESTATE[1:0]

CLKOUT

A

T

D

[

1

:

A

5

0

]

TXVALID

E

X

R

T

Y

D

A

I

L

A

V

H

D

A

V

X

R

D

I

L

RXACTIVE

R

R

R

X

E

R

O

PWR

CONTROL

TX

LOGIC

TX State
Machine

Parallel to

Serial

Conversion

Bit Stuff

NRZI

Encode

0

]

RX

LOGIC

*

RX State

UTMI Interface

Machine

Serial to

Parallel

Conversion

Bit Unstuff

NRZI

Decode

PLL and

XTAL OSC

RPU_EN

VPO

VMO

OEB

HS_DATA

HS_DRIVE_ENABLE

HS_CS_ENABLE

VP
VM

Clock

Recovery Unit

Clock

and

Data

Recovery

Elasticity

Buffer

System

Clocking

TX

Ω

1.5k

FS TX

HS TX

DP

RX

FS SE+

FS SE-

FS RX

MUX

HS RX

DM

BIASING

Bandgap Voltage Reference

Current Reference

RBIAS

HS SQ

Figure 2.1 Block Diagram

Note: See Section 7.1, "Modes of Operation," on page 18 for a description of the digital interface.

SMSC GT3200, SMSC USB3250 2 Revision 1.3 (10-05-04)

DATASHEET

Chapter 3 Pinout

VSS

VSS

VSS

VSS

USB2.0 PHY IC

DATABUS16_8

VDD1.8

RXERROR

TXREADY

RXACTIVE

CLKOUT

VSS

VALIDH

RXVALID

TXVALID

DATA[0]

VDD3.3

NC

VSSA

NC

DM

DP

VDDA3.3

VSSA

RBIAS

VDDA3.3

VSSA

XO

VDDA1.8

NC

SUSPENDN

VSS

646362

1

2

3

4

5

6

7

8

9

10

XI

11

12

13

14

15

16

17

VSS

61

6059585756555453525150

USB2.0

GT3200

PHY IC

212223

20

18

19

VSS

VDD1.8

VDD3.3

XCVRSELECT

TERMSELECT

252627

24

OPMODE[1]

OPMODE[0]

LINESTATE[1]

LINESTATE[0]

293031

28

RESET

VDD1.8

DATA[15]

49

VSS

48

DATA[1]

47

DATA[2]

46

45

DATA[3]

44

DATA[4]

VDD1.8

43

DATA[5]

42

DATA[6]

41

DATA[7]

40

39

DATA[8]

38

VSS

DATA[9]

37

DATA[10]

36

DATA[11]

35

DATA[12]

34

VSS

33

32

VDD3.3

DATA[14]

DATA[13]

Figure 3.1 64 pin GT3200 Pinout

Revision 1.3 (10-05-04) 3 SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

VSSA

DM

DP

VDDA3.3

VSSA

RBIAS

VDDA3.3

VSSA

VSSA

XI

XO

VDDA1.8

SUSPENDN

VSS

VDD1.8

DATABUS16_8

VSS

VSS

56555453525150

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15161718192021222324252627

VDD1.8

VDD3.3

RXERROR

USB2.0

USB3250

PHY IC

OPMODE[1]

XCVRSELECT

TERMSELECT

CLKOUT

TXREADY

RXACTIVE

OPMODE[0]

LINESTATE[1]

VALIDH

VSS

4847464544

49

RESET

VDD1.8

LINESTATE[0]

VDD3.3

TXVALID

DATA[0]

RXVALID

43

42

DATA[1]

41

DATA[2]

40

DATA[3]

39

DATA[4]

38

VDD1.8

37

DATA[5]

36

DATA[6]

35

DATA[7]

34

DATA[8]

33

VSS

32

DATA[9]

31

DATA[10]

30

DATA[11]

29

DATA[12]

28

DATA[15]

VDD3.3

DATA[14]

DATA[13]

Figure 3.2 56 pin USB3250 Pinout

SMSC GT3200, SMSC USB3250 4 Revision 1.3 (10-05-04)

DATASHEET

Chapter 4 Interface Signal Definition

Table 4.1 System Interface Signals

USB2.0 PHY IC

NAME DIRECTION

RESET Input High Reset. Reset all state machines. After coming out of reset, must

XCVRSELECT Input N/A Transceiver Select. This signal selects between the FS and HS

TERMSELECT Input N/A Termination Select. This signal selects between the FS and HS

SUSPENDN Input Low Suspend. Places the transceiver in a mode that draws minimal

CLKOUT Output Rising Edge System Clock. This output is used for clocking receive and

OPMODE[1:0] Input N/A Operational Mode. These signals select between the various

LINESTATE[1:0] Output N/A Line State. These signals reflect the current state of the USB

DATABUS16_8 Input N/A Databus Select. Selects between 8-bit and 16-bit data transfers.

ACTIVE

LEVEL DESCRIPTION

wait 5 rising edges of clock before asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to CLKOUT
De-assertion of Reset: Must be synchronous to CLKOUT

transceivers:
0: HS transceiver enabled
1: FS transceiver enabled.

terminations:
0: HS termination enabled
1: FS termination enabled

power from supplies. Shuts down all blocks not necessary for
Suspend/Resume operation. While suspended, TERMSELECT
must always be in FS mode to ensure that the 1.5k Ω pull-up on
DP remains powered.
0: Transceiver circuitry drawing suspend current
1: Transceiver circuitry drawing normal current

transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit
mode). When in 8-bit mode, this specification refers to CLKOUT
as CLK60. When in 16-bit mode, CLKOUT is referred to as
CLK30.

operational modes:
[1] [0] Description
0 0 0: Normal Operation
0 1 1: Non-driving (all terminations removed)
1 0 2: Disable bit stuffing and NRZI encoding
1 1 3: Reserved

data bus in FS mode, with [0] reflecting the state of DP and [1]
reflecting the state of DM. When the device is suspended or
resuming from a suspended state, the signals are combinatorial.
Otherwise, the signals are synchronized to CLKOUT.
[1] [0] Description
0 0 0: SE0
0 1 1: J State
1 0 2: K State
1 1 3: SE1

0: 8-bit data path enabled. VALIDH is undefined. CLKOUT =
60MHz.
1: 16-bit data path enabled. CLKOUT = 30MHz.

Revision 1.3 (10-05-04) 5 SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

Table 4.2 Data Interface Signals

ACTIVE

NAME DIRECTION

DATA[15:0] Bidir N/A

TXVALID Input High Tra nsmi t Valid. Indicates that the TXDATA bus is valid for

LEVEL DESCRIPTION

DATA BUS. 16-BIT BIDIRECTIONAL MODE.

TXVALID RXVALID VALIDH DATA[15:0]

0 0 X Not used

0 1 0 DATA[7:0] output is valid

for receive

0 1 1 DATA[15:0] output is

valid for receive

1 X 0 DATA[7:0] input is valid

for transmit

1 X 1 DATA[15:0] input is valid

for transmit

DATA BUS. 8-BIT UNIDIRECTIONAL MODE.

TXVALID RXVALID DATA[15:0]

00Not used

0 1 DATA[15:8] output is valid for receive

1 X DATA[7:0] input is valid for transmit

transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.

Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.

TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the SIE must

VAL IDH Bi dir N/ A Transmit/Receive High Data Bit Valid (used in 16-bit mode

RXVALID Output High Receive Data Valid. Indicates that the RXDATA bus has received

RXACTIVE Output High Receive Active. Indicates that the receive state machine has

RXERROR Output High Receive Error. 0: Indicates no error. 1: Indicates a receive error

always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.

only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs. If VALIDH is asserted, DATA[15:0] is valid for
transmission. If deasserted, only DATA[7:0] is valid for
transmission. The DATA bus is driven by the SIE.

When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs. If VALIDH is asserted, the
DATA[15:0] outputs are valid for receive. If deasseted, only
DATA[7:0] is valid for receive. The DATA bus is read by the SIE.

valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.

detected Start of Packet and is active.

has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.

SMSC GT3200, SMSC USB3250 6 Revision 1.3 (10-05-04)

DATASHEET

USB2.0 PHY IC

Table 4.3 USB I/O Signals

ACTIVE

NAME DIRECTION

DP I/O N/A USB Positive Data Pin.

DM I/O N/A USB Negative Data Pin.

LEVEL DESCRIPTION

Table 4.4 Biasing and Clock Oscillator Signals

ACTIVE

NAME DIRECTION

RBIAS Input N/A External 1% bias resistor. Requires a 12KΩ resistor to ground.

XI/XO Input N/A External crystal. 12MHz crystal connected from XI to XO.

LEVEL DESCRIPTION

Used for setting HS transmit current level and on-chip termination
impedance.

Table 4.5 Power and Ground Signals

ACTIVE

NAME DIRECTION

VDD3.3 N/A N/A 3.3V Digital Supply. Powers digital pads. See Note 4.1

VDD1.8 N/A N/A 1.8V Digital Supply. Powers digital core.

VSS N/A N/A Digital Ground. See Note 4.2

VDDA3.3 N/A N/A 3.3V Analog Supply. Powers analog I/O and 3.3V analog

VDDA1.8 N/A N/A 1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 4.1

VSSA N/A N/A Analog Ground. See Note 4.2

LEVEL DESCRIPTION

circuitry.

Note 4.1 A Ferrite Bead (with DC resistance <.5 Ohms) is recommended for filtering between both

the VDD3.3 and VDDA3.3 supplies and the VDD1.8 and VDDA1.8 Supplies. See

Figure 8.9 Application Diagram for 64-pin TQFP Package on page 40.

Note 4.2 56-pin QFN package will down-bond all VSS and VSSA to exposed pad under IC.

Exposed pad must be connected to solid GND plane on printed circuit board.

Revision 1.3 (10-05-04) 7 SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

Chapter 5 Limiting Values

Table 5.1 Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

1.8V Supply Voltage
(VDD1.8 and VDDA1.8)

3.3V Supply Voltage
(VDD3.3 and VDDA3.3)

Input Voltage V

Storage Temperature T

[1] Equivalent to discharging a 100pF capacitor via a 1.5kΩ resistor (HBM).

Note: In accordance with the Absolute Maximum Rating System (IEC 60134

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

1.8V Supply Voltage
(VDD1.8 and VDDA1.8)

3.3V Supply Voltage
(VDD3.3 and VDDA3.3)

Input Voltage on Digital Pins V

Input Voltage on Analog I/O
Pins (DP, DM)

Ambient Temperature T

V

DD1.8

V

DD3.3

I

STG

Table 5.2 Recommended Operating Conditions

V

DD1.8

V

DD3.3

I

V

I(I/O)

A

-0.5 TBD V

-0.5 4.6 V

-0.5 4.6 V

-40 +125

o

1.6 1.8 2.0 V

3.0 3.3 3.6 V

0.0 V

0.0 V

-40 +85

DD3.3

DD3.3

o

C

V

V

C

Table 5.3 Recommended External Clock Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

System Clock Frequency XO driven by the

external clock; and no
connection at XI

System Clock Duty Cycle XO driven by the

45 50 55 %

12

(+/- 100ppm)

MHz

external clock; and no
connection at XI

SMSC GT3200, SMSC USB3250 8 Revision 1.3 (10-05-04)

DATASHEET

Chapter 6 Electrical Characteristics

Table 6.1 Electrical Characteristics: Supply Pins

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS transmitting at 12Mb/s;
50pF load on DP and DM

FS receiving at 12Mb/s 75 115 mW

HS transmitting into a 45Ω
load

HS receiving at 480Mb/s 155 185 mW

15kΩ pull-down and 1.5kΩ
pull-up resistor on pin DP
not connected.

) 15kΩ pull-down and 1.5kΩ

pull-up resistor on pin DP
connected.

FS
TRANSMIT

FS RECEIVE

HS
TRANSMIT

HS RECEIVE

SUSPEND
MODE 1

SUSPEND
MODE 2

=1.6 to 2.0V; V

(V

DD1.8

Total Power P

VDD3.3
Power

VDD1.8
Power

Total Power P

VDD3.3
Power

VDD1.8
Power

Total Power P

VDD3.3
Power

VDD1.8
Power

Total Power P

VDD3.3
Power

VDD1.8
Power

Total Current I

VDD3.3
Current

VDD1.8
Current

Total Current I

VDD3.3
Current

VDD1.8
Current

=3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)

DD3.3

TOT(FSTX)

P

3.3V(FSTX)

P

1.8V(FSTX)

TOT(FSRX)

P

3.3V(FSRX)

P

1.8V(FSRX)

TOT(HSTX)

P

3.3V (HSTX)

P

1.8V (HSTX)

TOT(HSRX)

P

3.3V (HSRX)

P

1.8V (HSRX)

DD(SUSP1)

I

3.3V (SUSP1)

I

1.8V (SUSP1)

DD(SUSP2

I

3.3V (SUSP2)

I

1.8V (SUSP2)

USB2.0 PHY IC

86 115 mW

57 76 mW

29 39 mW

46 76 mW

29 39 mW

158 185 mW

110 130 mW

48 55 mW

107 130 mW

48 55 mW

123 240 uA

68 120 uA

55 120 uA

323 460 uA

268 340 uA

55 120 uA

Revision 1.3 (10-05-04) 9 SMSC GT3200, SMSC USB3250

DATASHEET

USB2.0 PHY IC

Table 6.2 DC Electrical Characteristics: Logic Pins

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Low-Level Input Voltage V

High-Level Input Voltage V

Low-Level Output Voltage V

High-Level Output Voltage V

Input Leakage Current I

Pin Capacitance C

=1.6 to 2.0V; V

(V

DD1.8

Pins Data[15:0] and VALIDH have passive pull-down elements.)

=3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.

DD3.3

IL

IH

OL

OH

LI

pin

IOL = 4mA 0.4 V

IOH = -4mA V

Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

SS

2.0 V

DD3.3

- 0.5

0.8 V

DD3.3

V

V

± 1 uA

4pF

FS FUNCTIONALITY

INPUT LEVELS

Differential Receiver Input

V

Sensitivity

Differential Receiver

V

Common-Mode Voltage

Single-Ended Receiver Low

V

Level Input Voltage

Single-Ended Receiver High

V

Level Input Voltage

Single-Ended Receiver

V

Hysteresis

OUTPUT LEVELS

Low Level Output Voltage V

High Level Output Voltage V

TERMINATION

Driver Output Impedance for

Z

HS and FS

Input Impedance Z

Pull-up Resistor Impedance Z

Termination Voltage For Pull-

V

up Resistor On Pin DP

DIFS

CMFS

ILSE

IHSE

HYSSE

FSOL

FSOH

HSDRV

INP

PU

TERM

| V(DP) - V(DM) | 0.2 V

0.8 2.5 V

0.8 V

2.0 V

0.050 0.150 V

Pull-up resistor on DP;
RL = 1.5kΩ to V

DD3.3

Pull-down resistor on

2.8 3.6 V

0.3 V

DP, DM;
RL = 15kΩ to GND

Steady state drive (See

40.5 45 49.5 Ω

Figure 6.1)

TX, RPU disabled 10 MΩ

1.425 1.575 KΩ

3.0 3.6 V

HS FUNCTIONALITY

INPUT LEVELS

HS Differential Input
Sensitivity

=1.6 to 2.0V; V

(V

DD1.8

SMSC GT3200, SMSC USB3250 10 Revision 1.3 (10-05-04)

DD3.3

V

DIHS

| V(DP) - V(DM) | 100 mV

=3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)

DATASHEET

Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

HS Data Signaling Common
Mode Voltage Range

HS Squelch Detection
Threshold (Differential)

OUTPUT LEVELS

High Speed Low Level Output
Voltage (DP/DM referenced to
GND)

High Speed High Level Output
Voltage (DP/DM referenced to
GND)

High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)

Chirp-J Output Voltage
(Differential)

Chirp-K Output Voltage
(Differential)

V

CMHS

Squelch Threshold 100 mV

V

HSSQ

-50 500 mV

Unsquelch Threshold 150 mV

V

HSOL

V

HSOH

V

OLHS

V

CHIRPJ

45Ω load -10 10 mV

45Ω load 360 440 mV

45Ω load -10 10 mV

HS termination resistor

700 1100 mV
disabled, pull-up resistor
connected. 45Ω load.

V

CHIRPK

HS termination resistor
disabled, pull-up resistor

-900 -500 mV

connected. 45Ω load.

USB2.0 PHY IC

LEAKAGE CURRENT

OFF-State Leakage Current I

PORT CAPACITANCE

Transceiver Input Capacitance C

(V

=1.6 to 2.0V; V

DD1.8

=3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)

DD3.3

Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FS OUTPUT DRIVER TIMING

Rise Time T

Fall Time T

Output Signal Crossover
Volta ge

Differential Rise/Fall Time
Matching

=1.6 to 2.0V; V

(V

DD1.8

DD3.3

V

F

=3.0 to 3.6V; VSS = 0V; TA = -40 oC to +85oC; unless otherwise specified.)

LZ

IN

FSR

FFF

CRS

RFM

± 1 uA

Pin to GND 5 10 pF

CL = 50pF; 10 to 90% of

420ns

|VOH - VOL|

CL = 50pF; 10 to 90% of

420ns

|VOH - VOL|

Excluding the first

1.3 2.0 V
transition from IDLE
state

Excluding the first

90 111.1 %
transition from IDLE
state

Revision 1.3 (10-05-04) 11 SMSC GT3200, SMSC USB3250

DATASHEET