SK hynix HMT451R7BFR8A, HMT41GR7BFR8A, HMT41GR7BFR4A, HMT42GR7BFR4A, HMT84GR7BMR4A User Manual

240pin DDR3L SDRAM Registered DIMM

DDR3L SDRAM Registered DIMM

Based on 4Gb B-die

HMT451R7BFR8A HMT41GR7BFR8A HMT41GR7BFR4A HMT42GR7BFR4A

HMT84GR7BMR4A

*SK hynix reserves the right to change products or specifications without notice.

Rev. 1.0 /May. 2014 1

Revision History

Revision No. History Draft Date Remark

0.1 Initial Release Mar.2014

1.0 Revision 1.0 Release May.2014

Rev. 1.0 / May. 2014 2

Description

SK hynix Registered DDR3L SDRAM DIMMs (Register ed Double Data Rate Synchr onous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations.

Features

• Power Supply: VDD=1.35V (1.283V to 1.45V)

• VDDQ = 1.35V (1.283V to 1.45V)

• VDDSPD=3.0V to 3.6V

• Backward Compatible with 1.5V DDR3 Memory Module

• 8 internal banks

• Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500

• Bi-Directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)

• Supports ECC error correction and detection

• On-Die Termination (ODT)

• Temperature sensor with integrated SPD

• Backward compatible with 1.5V DDR3 Memory module.

• This product is in compliance with the RoHS directive.

Ordering Information

Part Number Density Organization Component Composition

HMT451R7BFR8A-H9/PB/RD 4GB 512Mx72 512Mx8(H5TC4G83BFR)*9 1 X

HMT41GR7BFR8A-H9/PB/RD 8GB 1Gx72 512Mx8(H5TC4G83BFR)*18 2 X

HMT41GR7BFR4A-H9/PB/RD 8GB 1Gx72 1Gx4(H5TC4G43BFR)*18 1 X

HMT42GR7BFR4A-H9/PB/RD 16GB 2Gx72 1Gx4(H5TC4G43BFR)*36 2 O

HMT84GR7BMR4A-G7/H9/PB 32GB 4Gx72 DDP 2Gx4(H5TC8G43BMR)*36 4 O

* In order to uninstall FDHS, please contact sales administrator

Rev. 1.0 / May. 2014 3

# of

ranks

FDHS

Key Parameters

MT/s Grade

DDR3L-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7

DDR3L-1333 -H9 1.5 9

DDR3L-1600 -PB 1.25 11

DDR3L-1866 -Rd 1.07 13

tCK

(ns)

CAS

Latency

(tCK)

tRCD

(ns)

13.5

(13.125)*

13.75

(13.125)*

13.91

(13.125)*

tRP

(ns)

13.5

(13.125)*

13.75

(13.125)*

13.91

(13.125)*

tRAS

(ns)

36

35

34

tRC

(ns)

49.5

(49.125)*

48.75

(48.125)*

47.91

(48.125)*

CL-tRCD-tRP

9-9-9

11-11-11

13-13-13

*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.

Speed Grade

Frequency [Mbps]

Grade

CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13

-G7 800 1066 1066

-H9 800 1066 1066 1333 1333

Remark

-PB 800 1066 1066 1333 1333 1600

-RD 800 1066 1066 1333 1333 1600 1866

Address Table

4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 32GB(4Rx4)

Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms

Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15

Column Address A0-A9 A0-A9,A11 A0-A9 A0-A9,A11 A0-A9,A11

Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2

Page Size 1KB 1KB 1KB 1KB 1KB

Rev. 1.0 / May. 2014 4

Pin Descriptions

Pin Name Description

Num ber

Pin Name Description

CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2 CK0

Clock Input, negative line 1 DQ[63:0] Data Input/Output 64 CK1 Clock Input, positive line 1 CB[7:0] Data check bits Input/Output 8 CK1 Clock Input, negative line 1 DQS[8:0] Data strobes 9

CKE[1:0] Clock Enables 2 DQS[8:0]

DM[8:0]/

RAS

Row Address Strobe 1

DQS[17:9],

TDQS[17:9]

CAS Column Address Strobe 1

DQS[17:9], TDQS[17:9]

WE Write Enable 1 EVENT

S

[3:0] Chip Selects 4 TEST

A[9:0],A11,

A[15:13]

A10/AP Address Input/Autoprecharge 1 A12/BC Address Input/Burst chop 1

BA[2:0] SDRAM Bank Addresses 3

SCL

SDA SPD Data Input/Output 1

SA[2:0] SPD Address Inputs 3

Par_In

Err_Out

Address Inputs 14 RESET

V

DD

V

SS

V

REFDQ

Serial Presence Detect (SPD)

Clock Input

Parity bit for the Address and

Control bus

Parity error found on the

Address and Control bus

1

V

REFCA

V

DDSPD

TT

Data strobes, negative line 9 Data Masks / Data strobes,

Termination data strobes Data strobes, negative line,

Termination data strobes Reserved for optional hardware

temperature sensing Memory bus test tool (Not Con-

nected and Not Usable on DIMMs)

Register and SDRAM control pin 1

Power Supply 22 Ground 59 Reference Voltage for DQ 1

Reference Voltage for CA 1

Termination Voltage 4 SPD Power 1

Num ber

9

1

Rev. 1.0 / May. 2014 5

Input/Output Functional Descriptions

Symbol Type Polarity Function

CK0 IN

CK0

IN

CK1 IN

CK1

IN

CKE[1:0] IN

S

[3:0] IN

ODT[1:0] IN

AS, CAS, WE IN

R

V

REFDQ

V

REFCA

Supply Reference voltage for DQ0-DQ63 and CB0-CB7.

Supply

BA[2:0] IN —

A[15:13,

12/BC

,11,

IN —

10/AP,[9:0]

DQ[63:0],

CB[7:0]

I/O — Data and Check Bit Input/Output pins

DM[8:0] IN

V

DD

, V

SS

V

TT

Supply Power and ground for the DDR SDRAM input buffers and core logic. Supply Termination Voltage for Address/Command/Control/Clock nets.

Positive

Line

Negative

Line

Positive

Line

Negative

Line

Active

High

Active

Low

Active

High

Active

Low

Active

High

Positive line of the differential pair of system clock inputs that drives input to the onDIMM Clock Driver.

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

Terminated but not used on RDIMMs.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, a nd device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control wo rds in the register device(s). For modules with two registers, S[3:2]

operate similarly to S[1:0] for the second set of register out-

puts or register control words.

On-Die Termination control signals

When sampled at the positive rising edge of the clock, CAS

, RAS, and WE define the

operation to be executed by the SDRAM.

Reference voltage for A0-A15, BA0-BA2, RAS

, CAS, WE, S0, S1, CKE0, CKE1, Par_In,

ODT0 and ODT1. Selects which SDRAM bank of eight is activated.

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected b y BA. A12 is also utiliz ed fo r BL 4/8 identification for ‘’BL on the fly’’ during CAS

command. The address inputs also pro-

vide the op-code during Mode Register Set commands.

Masks write data when high, issued concurrently with input data.

Rev. 1.0 / May. 2014 6

Symbol Type Polarity Function

DQS[17:0] I/O

DQS[17:0]

TDQS[17:9] TDQS[17:9]

OUT

I/O

Positive

Edge

Negative

Edge

Positive line of the differential data strobe for input and output data.

Negative line of the differential data strobe for input and output data.

TDQS/TDQS

is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1,DRAM will enable the same termination resistance function on TDQS/TDQS applied to DQS/DQS provide the data mask function and TDQS

. When disabled via mode register A11=0 in MR1, DM/TDQS will

is not used. X4/X16 DRAMs must disable the

TDQS function via mode register A11=0 in MR1

SA[2:0] IN —

These signals are tied at the system planar to either V serial SPD EEPROM address range.

SS

or V

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

SDA I/O —

must be connected from the SDA bus line to V

on the system planar to act as a

DDSPD

pullup.

SCL IN —

OUT

EVENT

(open

Active Low

drain)

V

DDSPD

RESET

Supply

IN

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V

on the system planar to act as a pullup.

DDSPD

This signal indicates that a thermal event has been d e tected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the EVENT

pin on TS/SPD part.

No pull-up resister is provided on DIMM. Serial EEPROM positive power supply wired to a separate power pin at the connector

which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET

pin is connected to the RESET pin on the register and to the RESET pin on

the DRAM.

Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)

Err_Out

OUT (open drain)

Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out

bus line to VDD on the system planar to act as a pull up.

TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)

to configure the

DDSPD

that is

Rev. 1.0 / May. 2014 7

Pin Assignments

Pin #

Front Side

(left 1–60)

1VREFDQ 121

V

2

SS

Pin #

122 DQ4 62 VDD 182 VDD

Back Side

(right 121–180)

V

SS

Pin #

Front Side

(left 61–120)

Pin #

Back Side

(right 181–240)

61 A2 181 A1

3 DQ0 123 DQ5 63 NC, CK1 183 VDD 4 DQ1 124

5

V

SS

125

6DQS0126 7 DQS0 127

V

8

SS

128 DQ6 68 Par_In, NC 188 A0

V

SS

DM0,DQS9,

TDQS9

NC,DQS9

TDQS9

V

SS

64 NC, CK1 184 CK0 65 VDD 185 CK0

,

66 VDD 186 VDD 67 VREFCA 187 EVENT, NC

9 DQ2 129 DQ7 69 VDD 189 VDD

10 DQ3 130

V

11

SS

131 DQ12 71 BA0 191 VDD

V

SS

70 A10 / AP 190 BA1

12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133

14

V

SS

134

15 DQS1 135 16 DQS1 136

V

17

SS

137 DQ14 77 ODT1, NC 197 VDD

V

SS

DM1,DQS10,

TDQS10

NC,DQS10

TDQS10

V

SS

73 WE 193 S0 74 CAS 194 VDD

,

75 VDD 195 ODT0 76 S1, NC 196 A13

18 DQ10 138 DQ15 78 VDD 198 S3, NC 19 DQ11 139 20

V

SS

140 DQ20 80

SS

79 S2, NC 199

V

SS

200 DQ36

V

21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142

23

24 DQS2

V

SS

143

144

25 DQS2 145 26

V

SS

146 DQ22 86

SS

DM2,DQS11,

TDQS11

NC,DQS11

TDQS11

V

SS

,

82 DQ33 202 83

V

SS

203

84 DQS4 204 85 DQS4 205

V

SS

206 DQ38

DM4,DQS13,

TDQS13

NC,DQS13

TDQS13

V

27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 29

V

SS

149 DQ28 89

SS

88 DQ35 208

V

SS

209 DQ44

V

30 DQ24 150 DQ29 90 DQ40 210 DQ45

V

31 DQ25 151

SS

91 DQ41 211

V

SS

V

SS

,

V

SS

V

SS

V

SS

NC = No Connect; RFU = Reserved Future Use

Rev. 1.0 / May. 2014 8

Pin #

32

Front Side

(left 1–60)

V

SS

33 DQS3 34 DQS3 154

35

V

SS

Pin #

152

153

155 DQ30 95

Back Side

(right 121–180)

DM3,DQS12,

TDQS12

NC,DQS12

TDQS12

,

V

SS

Pin #

92

Front Side

(left 61–120)

V

SS

93 DQS5 213 94 DQS5 214

V

SS

Pin #

212

Back Side

(right 181–240)

DM5,DQS14,

TDQS14

NC,DQS14

TDQS14

215 DQ46

36 DQ26 156 DQ31 96 DQ42 216 DQ47

V

37 DQ27 157 38

V

SS

158 CB4, NC 98

SS

39 CB0, NC 159 CB5, NC 40 CB1, NC 160

41

42 DQS8

V

SS

161

162

43 DQS8 163 44

V

SS

164 CB6, NC 104

V

SS

NC,DM8,DQS17,

TDQS17

NC,DQS17

TDQS17

V

SS

,

97 DQ43 217

V

SS

218 DQ52

99 DQ48 219 DQ53

100 DQ49 220 101

V

SS

221

102 DQS6 222

DM6,DQS15,

TDQS15

NC,DQS15

TDQS15

103 DQS6 223

V

SS

224 DQ54 45 CB2, NC 165 CB7, NC 105 DQ50 225 DQ55 46 CB3, NC 166 47

V

SS

167 NC(TEST) 107

SS

106 DQ51 226

V

SS

227 DQ60

V

48 VTT, NC 168 RESET 108 DQ56 228 DQ61

KEY KEY 109 DQ57 229

49 VTT, NC 169 CKE1, NC 110

50 CKE0 170 V

DD 111 DQS7 231

V

SS

230

DM7,DQS16,

TDQS16

NC,DQS16

TDQS16 51 VDD 171 A15 112 DQS7 232 52 BA2 172 A14 113

V

SS

233 DQ62 53 Err_Out, NC 173 VDD 114 DQ58 234 DQ63 54 V 55 A11 175 A9 116

DD 174 A12 / BC 115 DQ59 235

V

SS

236 VDDSPD 56 A7 176 VDD 117 SA0 237 SA1 57 VDD 177 A8 118 SCL 238 SDA 58 A5 178 A6 119

SA2

239 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3

,

V

SS

V

SS

V

SS

,

V

SS

V

SS

V

SS

,

V

SS

V

SS

V

SS

NC = No Connect; RFU = Reserved Future Use

Rev. 1.0 / May. 2014 9

Registering Clock Driver Specifications

Capacitance Values

Symbol Parameter Conditions Min Typ Max Unit

Input capacitance, Data inputs 1.5 - 2.5 pF

C

I

Input capacitance, CK, CK, FBIN, FBIN (up to DDR3-1600)

1.5 - 2.5 pF

C

Input capacitance, RESET, MIRROR,

IR

QCSEN

Input & Output Timing Requirements

DDR3L-800

Symbol Parameter Conditions

f

clock

f

TEST

t

SU

H

Input clock fre-

quency

Input clock fre-

quency

Setup time

Hold time

Application fre-

quency

Test frequency 70 300 70 300 70 300 Mhz

Input valid before

CK/CK

Input to remain

valid after CK/CK

Propagation

t

PDM

delay, single-bit

to output 0.65 1.0 0.65 1.0 0.65 1.0 ns

CK/CK

switching

1066/1333

Min Max Min Max Min Max

300 670 300 810 300 945 Mhz

100 - 50 - 40 - ps

175-125- 75 -ps

VI = VDD or GND; VDD = 1.5v

DDR3L-1600 DDR3L-1866

--3pF

Unit

Output disable

t

DIS

time (1/2-Clock

prelaunch)

Output enable

t

time (1/2-Clock

EN

prelaunch)

Rev. 1.0 / May. 2014 10

to output

Yn/Yn

float

Output driving to

Yn/Yn

0.5 +

tQSK1(min)

0.5 -

tQSK1(max)

-

0.5 +

tQSK1(min)

0.5 -

tQSK1(max)

-

0.5 +

tQSK1(min)

0.5 -

tQSK1(max)

-ps

On DIMM Thermal Sensor

EVENT SCL

SDA

SA0 SA1

SA2

EVENT SCL

SDA

SA0

SA1 SA2

SPD with

Integrated

TS

The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.

Connection of Thermal Sensor

Temperature-to-Digital Conversion Performance

Parameter Condition Min Typ Max Unit

Active Range,

< 95°C

A

< 125°C

A

Temperature Sensor Accuracy (Grade B)

75°C < T

Monitor Range,

40°C < T

-20°C < TA < 125°C

Resolution 0.25

Rev. 1.0 / May. 2014 11

- ± 0.5 ± 1.0 °C

- ± 1.0 ± 2.0 °C

- ± 2.0 ± 3.0 °C °C

Functional Block Diagram

CB[7:0]

DQS8 DQS8 DM8/DQS17 DQS17

RRASA

RCASA

RS0A

RWEA

PCK0A

RCKE0A

RODT0A

A[N:O]A

Vtt

DQ[31:24]

DQS3 DQS3 DM3/DQS12 DQS12

DQ[23:16]

DQS2 DQS2 DM2/DQS11 DQS11

DQ[15:8]

DQS1 DQS1 DM1/DQS10 DQS10

DQ[7:0]

DQS0 DQS0 DM0/DQS9 DQS9

DQS DQS TDQS TDQS

D8

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D3

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQS DQS TDQS TDQS

D2

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQS DQS TDQS TDQS

D1

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D0

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A

[N

:O]/BA[N:O]

DQ[39:32]

DQS4 DQS4 DM4/DQS13 DQS13

RRASB

RCASB

RS0B

RWEB

PCK0B

RCKE0B

RODT0B

A[N:O]B

Vtt

DQ[47:40]

DQS5 DQS5 DM5/DQS14 DQS14

DQ[55:48]

DQS6 DQS6 DM6/DQS15 DQS15

DQ[63:56]

DQS7 DQS7 DM7/DQS16 DQS16

DQS DQS TDQS TDQS

D4

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQS DQS TDQS TDQS

D5

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQS DQS TDQS TDQS

D6

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQS DQS TDQS TDQS

D7

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

/BA[N:O]A

/BA[N:O]B

S0 S1

BA[N:0] A[N:0] RAS

CAS WE

CKE0

ODT0

CK0

PAR_IN

RS0A

→CS0: SDRAMs D[3:0], D8 RS0B → CS0: SDRAMs D[7:4] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8

RRASA → RAS: SDRAMs D[7:4]

RBA[N:0]A → BA[N:0]: SDRAMs D[7:4] RA[N:0]A → A[N:0]: SDRAMs D[7:4]

RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8

RRASA → RAS: SDRAMs D[3:0], D8

RCASA → CAS: SDRAMs D[7:4]

RCASA →CAS: SDRAMs D[3:0], D8

RWEA → WE: SDRAMs D[7:4]

RWEA → WE: SDRAMs D[3:0], D8

RCKE0B→ CKE0: SDRAMs D[7:4]

RCKE0A→ CKE0: SDRAMs D[3:0], D8

RODT0B → ODT0: SDRAMs D[7:4]

RODT0A → ODT0: SDRAMs D[3:0], D8

PCK0B → CK: SDRAMs D[7:4]

PCK0A → CK: SDRAMs D[3:0], D8

PCK0B→ CK: SDRAMs D[7:4]

PCK0A→ CK: SDRAMs D[3:0], D8

Err_Out

OERR

RESET

RST

RST: SDRAMs D[8:0]

S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330

Ω

resistor to ground

1: 2 R E G I S T E R / P

D0–D8

V

DD

V

TT

V

DDSPD

D0–D8

VREFDQ

SPD

VREFCA

V

SS

D0–D8

Note:

1.DQ-to-I/O wiring may be changed within byte.

2.ZQ resistors are 240

Ω±1%.For all other resistor values refer to the

appropriate wiring diagram.

VDDSPD EVENT SCL

SDA

SA0

SPD with

Integrated

TS

SA1 SA2 VSS

VDDSPD

EVENT

SCL

SDA

SA0 SA1 SA2 VSS

Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative

120

Ω

±

1%

CK0 CK0

120

Ω

±

1%

L L

4GB, 512Mx72 Module(1Rank of x8)

Rev. 1.0 / May. 2014 12

8GB, 1Gx72 Module(1Rank of x4) - page1

RRASA

RCASA

RS0A

RWEA

PCK0A

RCKE0A

RODT0A

A[O:N]A

Vtt

/BA[O:N]A

CB[3:0]

DQS8 DQS8

DQS DQS DM

D8

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

CB[7:4]

DQS17 DQS17 VSS

DQS DQS DM

D17

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[27:24]

DQS3 DQS3

DQS DQS DM

D3

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[31:28]

DQS12 DQS12 VSS

DQS DQS DM

D12

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[19:16]

DQS2 DQS2

DQS DQS DM

D2

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ23:20]

DQS11 DQS11 VSS

DQS DQS DM

D11

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[11;8]

DQS1 DQS1

DQS DQS DM

D1

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[15:12]

DQS10 DQS10 VSS

DQS DQS DM

D10

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[3:0]

DQS0 DQS0

DQS DQS DM

D0

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[7:4]

DQS9 DQS9 VSS

DQS DQS DM

D9

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

RRASB

RCASB

RS0B

RWEB

PCK0B

RCKE0B

RODT0B

A[O:N]B

Vtt

/BA[O:N]B

DQ[35:32]

DQS4 DQS4

DQS DQS DM

D4

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[39:36]

DQS13 DQS13 VSS

DQS DQS DM

D13

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[43:40]

DQS5 DQS5

DQS DQS DM

D5

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[47:44]

DQS14 DQS14 VSS

DQS DQS DM

D14

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[51:48]

DQS6 DQS6

DQS DQS DM

D6

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[55;52]

DQS15 DQS15 VSS

DQS DQS DM

D15

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

DQ[59:56]

DQS7 DQS7

DQS DQS DM

D7

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

DQ[63:60]

DQS16 DQS16 VSS

DQS DQS DM

D16

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[O:N]

VSS

D0–D17

V

DD

D0–D17

V

TT

V

DDSPD

D0–D17

VREFDQ

SPD

VREFCA

V

SS

D0–D17

Note:

1. DQ-to-I/O wiring may be changed within a nibble.

2. Unless otherwise noted, resistor values are 15%.

3. See the wiring diagrams for all resistors associated with the command, address and control bus.

4. ZQ resistors are 240%. For all other resistor values refer to the appropriate wiring diagram.



1



5

VDDSPD EVENT SCL

SDA

SA0

SPD with

Integrated

TS

SA1 SA2 VSS

VDDSPD

EVENT

SCL

SDA

SA0 SA1 SA2 VSS

Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative

Rev. 1.0 / May. 2014 13

8GB, 1Gx72 Module(1Rank of x4) - page2

S0

S1 BA[N:0] A[N:0] RAS

CAS WE

CKE0 ODT0

CK0

PAR_IN

RS0A

→CS0: SDRAMs D[3:0], D[12:8], D17

RS0B → CS0: SDRAMs D[7:4], D[16:13]

RRASB → RAS: SDRAMs D[7:4], D[16:13]

RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]

RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17

RRASA → RAS: SDRAMs D[3:0], D[12:8], D17

RCASB → CAS: SDRAMs D[7:4], D[16:13]

RCASA →CAS: SDRAMs D[3:0], D[12:8], D17

RWEB→ WE: SDRAMs D[7:4], D[16:13]

RWEA → WE: SDRAMs D[3:0], D[12:8], D17

RCKE0B→ CKE0: SDRAMs D[7:4], D[16:13]

RCKE0A→ CKE0: SDRAMs D[3:0], D[12:8], D17

RODT0B → ODT0: SDRAMs D[7:4], D[16:13]

RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17

PCK0B → CK: SDRAMs D[7:4]

PCK0A → CK: SDRAMs D[3:0], D8

PCK0B→ CK: SDRAMs D[7:4]

PCK0A→ CK: SDRAMs D[3:0], D8

Err_Out

OERR

RESET

RST

RST: SDRAMs D[17:0]

1:2 R

E

G

I S T E R / P

RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13]

RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17

L

* S[3:2], CKE1, ODT1, CK1 and CK1 ar e NC (Unused register inputs ODT1 and C K E 1 h ave a 330 resistor to ground.)



RS1A → CS1: SDRAMs D[12:9], D17 RS1B → CS1: SDRAMs D[16:13]

Rev. 1.0 / May. 2014 14

8GB, 1Gx72 Module(2Rank of x8) - page1

DQS DQS TDQS TDQS

D17

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

RRASA

RCASA

RS0A

RWEA

PCK0A

RCKE0A

RODT0A

A[N:O]A

Vtt

/BA[N:O]A

RS1A

PCK1A

RCKE1A

RODT1A

DQ[31:24]

DQS3 DQS3 DM3/DQS12 DQS12

DQS DQS TDQS TDQS

D3

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D12

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQ[23:16]

DQS2 DQS2 DM2/DQS11 DQS11

DQS DQS TDQS TDQS

D2

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D11

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQ[15:8]

DQS1 DQS1 DM1/DQS10 DQS10

DQS DQS TDQS TDQS

D1

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQS DQS TDQS TDQS

D10

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQ[7:0]

DQS0 DQS0 DM0/DQS9 DQS9

DQS DQS TDQS TDQS

D0

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D9

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

CB[7:0]

DQS8 DQS8 DM8/DQS17 DQS17

DQS DQS TDQS TDQS

D8

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D13

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

RRASB

RCASB

RS0B

RWEB

PCK0B

RCKE0B

RODT0B

A[N:O]B

Vtt

/BA[N:O]B

RS1B

PCK1B

RCKE1B

RODT1B

DQ[47:40]

DQS5 DQS5 DM5/DQS14 DQS14

DQS DQS TDQS TDQS

D5

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D14

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQ55:48]

DQS6 DQS6 DM6/DQS15 DQS15

DQS DQS TDQS TDQS

D6

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D15

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQ[63:56]

DQS7 DQS7 DM7/DQS16 DQS16

DQS DQS TDQS TDQS

D7

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS TDQS TDQS

D16

DQ [7:0] ZQ

RAS

CASCSWECKCK

CKE

ODT

A[O:N]/BA[N:O]

DQ[39:32]

DQS4 DQS4 DM4/DQS13 DQS13

DQS DQS TDQS TDQS

D4

DQ [7:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D0–D17

V

DD

D0–D17

V

TT

V

DDSPD

D0–D17

VREFDQ

Serial PD

VREFCA

V

SS

D0–D17

Note:

1. DQ-to-I/O wiring may be changed within a byte.

2. Unless otherwise noted, resistor values are 15Ω±5%.

3. ZQ resistors are 240Ω±1%. For all other resistor values refer to the appropriate wiring diagram.

4. See the wiring diagrams for all resistors associated with the command, address and control bus.

VDDSPD EVENT SCL SDA

SA0

SPD with

Integrated

TS

SA1 SA2 VSS

VDDSPD

EVENT

SCL

SDA

SA0 SA1 SA2 VSS

Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative

Rev. 1.0 / May. 2014 15

8GB, 1Gx72(2Rank of x8) - page2

S0 S1

BA[N:0]

A[N:0] RAS

CAS WE

CKE0

ODT0

CK0

PAR_IN

RS0A

→CS0: SDRAMs D[3:0], D8

RS0B → CS0: SDRAMs D[7:4] RS1A → CS1: SDRAMs D[12:9], D17

RRASB → RAS: SDRAMs D[7:4], D[16:13]

RS1B → CS1: SDRAMs D[16:13] RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]

RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17

RRASA → RAS: SDRAMs D[3:0], D[12:8], D17

RCASB → CAS: SDRAMs D[7:4], D[16:13]

RCASA →CAS: SDRAMs D[3:0], D[12:8], D17

RWEB→ WE: SDRAMs D[7:4], D[16:13]

RWEA → WE: SDRAMs D[3:0], D[12:8], D17

RCKE0B→ CKE0: SDRAMs D[7:4]

RCKE0A→ CKE0: SDRAMs D[3:0], D8

RODT0B → ODT0: SDRAMs D[7:4]

RODT0A → ODT0: SDRAMs D[3:0], D8

PCK0B → CK: SDRAMs D[7:4]

PCK0A → CK: SDRAMs D[3:0], D8

PCK0B→ CK: SDRAMs D[7:4]

PCK0A→ CK: SDRAMs D[3:0], D8

Err_Out

OERR

RESET

RST

RST : SDRAMs D[17:0]

1:2

R E G I S T E R / P

RCKE1B→ CKE1: SDRAMs D[16:13]

RCKE1A→ CKE1: SDRAMs D[12:9], D17

ODT1

RODT1A

→

ODT1: SDRAMs D[16:13]

RODT1A → ODT1: SDRAMs D[12:9], D17

CKE1

RA[N:0]B

→

A[N:0]: SDRAMs D[7:4], D[16:13]

RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17

PCK1B → CK: SDRAMs D[16:13]

PCK1A → CK: SDRAMs D[12:9], D17

PCK1B→ CK: SDRAMs D[16:13

]

PCK1A→ CK: SDRAMs D[12:9], D17

L L

* S[3:2], CK1 and CK1 are NC

S[3:2] NC

120

Ω

±5%

CK1 CK1

120

Ω

±5%

Rev. 1.0 / May. 2014 16

16GB, 2Gx72 Module(2Rank of x4) - page1

RRASA

RCASA

RS0A

RWEA

PCK0A

RCKE0A

RODT0A

A[O:N]A

/BA[O:N]A

CB[7:4]

DQS17

DQS DQS DM

D17

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D35

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[31:28]

DQS12

DQS DQS DM

D12

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS

D30

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[23:20]

DQS11

DQS DQS DM

D11

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D29

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[15:12]

DQS10

DQS DQS DM

D10

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D28

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[3:0]

DQS0 DQS0

DQS DQS DM

D0

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D18

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

Vtt

CB[3:0]

DQS8 DQS8

DQS DQS DM

D8

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D26

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[27:24]

DQS3 DQS3

DQS DQS DM

D3

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS

D21

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[19:16]

DQS2 DQS2

DQS DQS DM

D2

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D20

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[11:8]

DQS1 DQS1

DQS DQS DM

D1

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D19

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[7:4]

DQS9 DQS9

DQS DQS DM

D9

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D27

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

RS1A

RCKE1A

R0DT1A

DM DM

Vtt

RRASA

RCASA

RS0A

RWEA

PCK0A

RCKE0A

RODT0A

A[O:N]A

/BA[O:N]A

RS

1A

RCKE1A

R0DT1A

PCK1

A

PCK1A

Rev. 1.0 / May. 2014 17

16GB, 2Gx72 Module(2Rank of x4) - page2

D0–D35

V

DD

D0–D35

V

TT

V

DDSPD

D0–D35

VREFDQ

SPD

VREFCA

V

SS

D0–D35

Note:

1. DQ-to-I/O wiring may be changed within a nibble.

2. See wiring diagrams for all resistors values.

3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.

VDDSPD EVENT SCL

SDA

SA0

SPD with

Integrated

TS

SA1 SA2 VSS

VDDSPD

EVENT

SCL

SDA

SA0 SA1 SA2 VSS

RRASB

RCASB

RS0B

RWEB

PCK0B

RCKE0B

RODT0B

A[N:O]B

/BA[N:O]B

DQ[47:44]

DQS14

DQS DQS DM

D14

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D32

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQS4 DQS4

DQS DQS DM

D4

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS

D22

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQS16

DQS DQS DM

D16

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D34

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQS7 DQS7

DQS DQS DM

D7

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D25

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

Vtt

DQ[39:36]

DQS13 DQS13

DQS DQS DM

D13

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D31

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[43:40]

DQS5 DQS5

DQS DQS DM

D5

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS

D23

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[55:52]

DQS15 DQS15

DQS DQS DM

D15

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D33

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

DQ[51:48]

DQS6 DQS6

DQS DQS DM

D6

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D24

DQ [3:0]

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

RS1B

RCKE1B

R0DT1B

DM DM

Vtt

RRASB

RCASB

RS0B

RWEB

PCK0B

RCKE0B

RODT0B

A[N:O]B

/BA[N:O]B

RS

1B

RCKE1B

R0DT1B

PCK1

B

PCK1B

DQ[35:32]

DQ[63:60]

DQ[59:56]

Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative

Rev. 1.0 / May. 2014 18

16GB, 2Gx72 Module(2Rank of x4) - page3

S0 S1

BA[N:0]

A[N:0] RAS

CAS WE

CKE0

ODT0

CK0

PAR_IN

RS0A

→CS0: SDRAMs D[3:0], D[12:8], D17

RS0B → CS0: SDRAMs D[7:4], D[16:13] RS1A → CS1: SDRAMs D[21:18], D[30:26], D35

RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31 ]

RS1B → CS1: SDRAMs D[25:22], D[34:31] RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[3 4:31 ]

RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RCASA →CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

RWEB→ WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:2 6], D35

RCKE0B→ CKE0: SDRAMs D[7:4], D[16:13]

RCKE0A→ CKE0: SDRAMs D[3:0], D[12:8], D17

RODT0B → ODT0: SDRAMs D[7:4], D[16:13]

RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17

PCK0B → CK: SDRAMs D[7:4], D[16:13]

PCK0A → CK: SDRAMs D[3:0], D[12:8], D17

PCK0B→ CK: SDRAMs D[7:4], D[16:13]

PCK0A→ CK: SDRAMs D[3:0], D[12:8], D17

Err_Out

RESET RST

RST : SDRAMs D[35:0]

1:2

R E G I S T E R / P

RCKE1B→ CKE1: SDRAMs D[25:22], D[34:31]

RCKE1A→ CKE1: SDRAMs D[21:18], D[30:26], D35

ODT1

RODT1A

→

ODT1: SDRAMs D[25:22], D[34:31]

RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35

CKE1

RA[N:0]B

→

A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

PCK1B → CK: SDRAMs D[25:22], D[34:31]

PCK1A → CK: SDRAMs D[21:18], D[30:26], D35

PCK1B→ CK: SDRAMs D[25:22], D[34:31]

PCK1A→ CK: SDRAMs D[21:18], D[30:26], D35

L L

* S[3:2], CK1 and CK1 are NC

CK1 CK1

120

Ω

±5%

Rev. 1.0 / May. 2014 19

32GB, 4Gx72 Module(4Rank of x4) - page1

ZQ

ARRASA

ARCASA

ARS0A

ARWEA

APCK0A

ARCKE0A

ARODT0A

ARA[N:O]A

Vtt

/ARBA[N:O]A

CB[3:0]

DQS8

DQS DQS DM

D9

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D8

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

D7

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D6

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D5

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D4

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D3

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D2

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D1

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D0

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

BRRASA

BRCASA

BRS2A

BRWEA

BPCK0A

BRCKE0A

BRODT1A

BRA[N:O]A

/BRBA[N:O]A

DQS DQS DM

D45

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D44

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D47

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D46

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D49

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D48

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D51

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D50

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D53

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D52

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSSVSSVSSVSS

ARS1A

ARCKE1A

VDD

BRS3A

BRCKE1A

VDD

DQ[27:24]

DQS3

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[19:16]

DQS2

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[11:8]

DQS1

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

ZQ

DQ[3:0]

DQS0

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

Rev. 1.0 / May. 2014 20

32GB, 4Gx72 Module(4Rank of x4) - page2

ZQ

ARRASA

ARCASA

ARS0A

ARWEA

APCK0A

ARCKE0A

ARODT0A

ARA[N:O]A

Vtt

/ARBA[N:O]A

CB[7:4]

DQS17

DQS DQS DM

D27

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D26

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

D25

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D24

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D23

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D22

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D21

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D20

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D19

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D18

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

BRRASA

BRCASA

BRS2A

BRWEA

BPCK0A

BRCKE0A

BRODT1A

BRA[N:O]A

/BRBA[N:O]A

DQS DQS DM

D63

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D62

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D65

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D64

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D67

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D66

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D69

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D68

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D71

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D70

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSSVSSVSSVSS

ARS1A

ARCKE1A

VDD

BRS3A

BRCKE1A

VDD

DQ[31:28]

DQS12 DQS12

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[23:20]

DQS11 DQS11

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[11:8]

DQS10 DQS10

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

ZQ

DQ[7:4]

DQS9

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

Rev. 1.0 / May. 2014 21

32GB, 4Gx72 Module(4Rank of x4) - page3

ZQ

ARRASB

ARCASB

ARS0B

ARWEB

APCK0B

ARCKE0B

ARODT0B

ARA[N:O]B

Vtt

/ARBA[N:O]B

DQ[35:32]

DQS4

DQS DQS DM

D11

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D10

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

D13

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D12

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D15

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D14

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D17

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D16

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

BRRASB

BRCASB

BRS2B

BRWEB

BPCK0B

BRCKE0B

BRODT1B

BRA[N:O]B

/BRBA[N:O]B

DQS DQS DM

D13

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D42

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D41

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D40

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D39

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D38

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D37

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D36

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSSVSSVSSVSS

ARS1B

ARCKE1B

VDD

BRS3B

BRCKE1B

VDD

DQ[43:40]

DQS5

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[51:48]

DQS6

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[59:56

DQS7

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

ZQ

Rev. 1.0 / May. 2014 22

32GB, 4Gx72 Module(4Rank of x4) - page4

ZQ

ARRASB

ARCASB

ARS0B

ARWEB

APCK0B

ARCKE0B

ARODT0B

ARA[N:O]B

Vtt

/ARBA[N:O]B

DQ[39:36]

DQS13 DQS13

DQS DQS DM

D29

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D28

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSS

D31

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D30

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D33

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D32

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D35

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D34

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

BRRASB

BRCASB

BRS2B

BRWEB

BPCK0B

BRCKE0B

BRODT1B

BRA[N:O]B

/BRBA[N:O]B

DQS DQS DM

D61

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

DQS DQS DM

D60

DQ [3:0]

ZQ

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D59

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D58

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D57

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D56

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D55

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

D54

RAS

CASCSWECKCK

CKE

ODT

A[N:O]/BA[N:O]

VSSVSSVSSVSS

ARS1B

ARCKE1B

VDD

BRS3B

BRCKE1B

VDD

DQ[47:44]

DQS14 DQS14

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[55:52]

DQS15 DQS15

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

DQ[63:60]

DQS16 DQS16

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQ

VSS

DQS DQS DM DQ [3:0]

ZQ

DQS DQS DM DQ [3:0]

ZQVSSVSSVSSVSS

ZQ

D0–D71

V

DD

V

TT

V

DDSPD

D0–D71

VREFDQ

SPD

VREFCA

V

SS

D0–D71

Note:

1. DQ-to-I/O wiring may be change d within a nibble.

2. Unless otherwise noted, resistor values are 15 Ohms ±5%.

3. See the wiring diagrams for all resistors associated with the command, address and control bus.

4. ZQ resistors are 240 Ohms ±1%. For all other resistor values refer to the appropriate wiring diagram.

VDDSPD EVENT SCL SDA

SA0

SPD with

Integrated

TS

SA1 SA2 VSS

VDDSPD

EVENT

SCL

SDA

SA0 SA1 SA2 VSS

Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative

Rev. 1.0 / May. 2014 23

32GB, 4Gx72 Module(4Rank of x4) - page5

CK1 CK1

120

Ω

±5%

S2

S3

BA[N:0] A[N:0]

RAS

CAS WE

CKE0

CK0

PAR_IN

BRS2A

→CS1: SDRAMs D45,D47,D49,D51,D53

BRS2B → CS1: SDRAMs D37,D39,D41,D43,

BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52,

BRRASB → RAS: SDRAMs D[43:36],D[61:54]

BRS3B → CS0: SDRAMs D36,D38,D40,D42,

BRBA[N:0]B→BA[N:0]: SDRAMs D[43:36],D[61:54]

BRBA[N:0]A→BA[N:0]: SDRAMs D[53:44],D[71:62]

BRRASA → RAS: SDRAMs D[53:44],D[71:62]

BRCASB → CAS: SDRAMs D[43:36],D[61:54]

BRCASA →CAS: SDRAMs D[53:44],D[71:62]

BRWEB→ WE: SDRAMs D[43:36],D[61:54]

BRWEA → WE: SDRAMs D[53:44],D[71:62]

BRCKE0B→ CKE1: SDRAMs D37,D39,D41,D43,

BRCKE0A→ CKE1: SDRAMs D45,D47,D49,D51,D53,

BRODT1B → ODT0: SDRAMs D37,D39,D41,D43

BRODT1A→ODT1: SDRAMs D45,D47,D49,D51,D53

BPCK0B → CK: SDRAMs D[43:36]

BPCK0A → CK: SDRAMs D[53:44]

BPCK0B→ CK: SDRAMs D[43:36]

BPCK0A→ CK: SDRAMs D[53:44]

Err_Out

RESET RST

1:2

R E G I S T E R / P

BRCKE1B→ CKE0: SDRAMs D36,D38,D40,D42,

BRCKE1A→ CKE0: SDRAMs D44.D46,D48,D50,D52,

ODT1

CKE1

BRA[N:0]B

→

A[N:0]: SDRAMs D[43:36],D[61:54]

BRA[N:0]A→ A[N:0]: SDRAMs D[55:44],D[71:62]

BPCK1B → CK: SDRAMs D[61:54]

BPCK1A → CK: SDRAMs D[71:62]

BPCK1B→ CK: SDRAMs D[61:54]

BPCK1A→ CK: SDRAMs D[71:62]

L L

B

D63,D65,D67,D69,D71

D55,D57,D59,D61

D62,D64,D66,D68,D70

D54,D56,D58,D60

D63,D65,D67,D69,D71

D55,D57,D59,D61

D62,D64,D66,D68,D70

D54,D56,D58,D60

D63,D65,D67,D69,D71

D55,D57,D59,D61

120

Ω

±5%

S0

S1

BA[N:0] A[N:0]

RAS

CAS WE

CKE0

CK0

PAR_IN

ARS0A

→CS1: SDRAMs D1,D3,D5,D7 D9,

ARS0B → CS1: SDRAMs D11, D13, D15, D17,

ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8,

ARRASB → RAS: SDRAMs D[17:10],D[35:28]

ARS1B → CS0: SDRAMs D10, D12, D14, D16,

ARBA[N:0]B→BA[N:0]: SDRAMs D[17:10],D[35 :28]

ARBA[N:0]A→BA[N:0]: SDRAMs D[9:0],D[27:18]

ARRASA → RAS: SDRAMs D[9:0],D[27:18]

ARCASB → CAS: SDRAMs D[17:10],D[35:28]

ARCASA →CAS: SDRAMs D[9:0],D[27:18]

ARWEB→ WE: SDRAMs D[17:10],D[35:28]

ARWEA → WE: SDRAMs D[9:0],D[27:18]

ARCKE0B→ CKE1: SDRAMs D11,D13,D15,D17,

ARCKE0A→ CKE1: SDRAMs D1,D3,D5,D7,D9,

ARODT0B → ODT0: SDRAMs D11,D13,D15,D17,

ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9,

APCK0B → CK: SDRAMs D[17:10]

APCK0A → CK: SDRAMs D[9:0]

APCK0B→ CK: SDRAMs D[17:10]

APCK0A→ CK: SDRAMs D[9:0]

Err_Out

RESET RST

RST : SDRAMs D[35:0]

1:2

R E G I S T E R / P

ARCKE1B→ CKE0: SDRAMs D10,D12,D14,D16,

ARCKE1A→ CKE0: SDRAMs D0,D2,D4,D6,D8,

ODT0

CKE1

ARA[N:0]B

→

A[N:0]: SDRAMs D[17:10],D[35:28]

ARA[N:0]A→ A[N:0]: SDRAMs D[9:0],D[27:18]

APCK1B → CK: SDRAMs D[35:28]

APCK1A → CK: SDRAMs D[27:18]

APCK1B→ CK: SDRAMs D[35:28]

APCK1A→ CK: SDRAMs D[27:18]

L L

A

D19, D21, D23, D25, D27

D29, D31, D33, D35

D18, D20, D22, D24, D26

D28, D30, D32, D34

D19, D21, D23, D25, D27

D29, D31, D33, D35

D18, D20, D22, D24, D26

D28, D30, D32, D34

D19, D21, D23, D25, D27

D29, D31, D33, D35

120

Ω

±5%

1. CK0 and CK0 are differentially terminated with a single

120 Ohms ±5% resistor.

2.

CK1 and CK1 are differentially terminated with a single

120 Ohms ±5% resistor, but is not used.

3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.

4. The module drawing on this page is not drawn to scale.

Rev. 1.0 / May. 2014 24

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol Parameter Rating Units Notes

VDD

VDDQ

, V

V

IN

T

Notes:

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat ing conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.



Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss

OUT

Storage Temperature

STG

DRAM Component Operating Temperature Range

Temperature Range

- 0.4 V ~ 1.80 V V 1,3

- 0.4 V ~ 1.80 V V 1

-55 to +100

o

C1, 2

-

Symbol Parameter Rating Units Notes

T

OPER

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

Normal Operating Temperature Range Extended Temperature Range

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It

is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Rang e. Please refer to the DIMM SPD for option availability

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the

Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b). DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the DIMM SPD for tFEFI requirements in the Extended Temperature Range.

0 to 85

85 to 95

o

C 1,2

o

C1,3

Rev. 1.0 / May. 2014 25

AC & DC Operating Conditions

Recommended DC Operating Conditions

Recommended DC Operating Conditions - DDR3L (1.35V) operation

Symbol Parameter

VDD

VDDQ

Notes:

1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a very long period of time (e.g., 1 sec).

2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.

3. Under these supply voltages, the device operates to this DDR3L specification.

4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 0).

Supply Voltage Supply Voltage for Output

Min. Typ. Max.

1.283 1.35 1.45 V 1,2,3,4

Rating

Units Notes

Recommended DC Operating Conditions - - DDR3 (1.5V) operation

Symbol Parameter

VDD

VDDQ

Notes:

1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.

2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as defined for this device.

3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 0).

Supply Voltage Supply Voltage for Output

Min. Typ. Max.

1.425 1.5 1.575 V 1,2,3

Rating

Units Notes

Rev. 1.0 / May. 2014 26

NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.

Ta

CK,CK#

RESET#

Tb Tc Td Te Tf Tg Th Ti Tj Tk

MRS1) 1)MRS MRS

CKE

DON’T CARE

READ MRS

T = 500us

COMMAND

ODT

BA

RTT

MR3 MR1 MR0READ MR2

READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

VDD, VDDQ (DDR3)

VDD, VDDQ (DDR3L)

ZQCL VALID

VALID

Tmin = 200us

Tmin = 10ns

tCKSRX

Tmin = 10ns

tIS

tIS tIS

tXPR tMRD tMRD tMRD tMOD tZQinit

tDLLK

TIME BREAK

Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3

Rev. 1.0 / May. 2014 27

AC & DC Input Measurement Levels

AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals

Single Ended AC and DC Input Levels for Command and Address

Symbol Parameter

VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1

VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V 1

VIH.CA(AC160) AC input logic high Vref + 0. 160 Note2 Vref + 0.160 Note2 - - V 1,2,5

VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 Note2 Vref - 0.160 - - V 1,2,5

VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5

VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5

VIH.CA(AC125) AC Input logic high - - - - Vref + 0.125 Note2 V 1,2,5

VIL.CA(AC125) AC input logic low - - - - Note2 Vref - 0.125 V 1,2,5

Reference Voltage for

V

RefCA(DC

Notes:

)

ADD, CMD inputs

1. For input only pins except RESET, Vref = VrefCA (DC).

2. Refer to "Overshoot and Undershoot Specifications" on page 41.

3. The ac peak noise on V ence: approx. +/- 13.5 mV).

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single Ended AC and DC Input Levels for DQ a nd DM" on page 29), the r espective levels in JESD7 9-3 (VIH/L.CA(DC100) , VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/ L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when the device is operated in the 1.35 voltage range.

Ref

DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866

Min Max Min Max Min Max

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4

may not allow V

to deviate from V

Ref

RefCA(DC)

by more than +/-1% VDD (for refer-

Unit Notes

Rev. 1.0 / May. 2014 28

AC and DC Input Levels for Single-Ended Signals

DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Opera-

tion”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels.

Single Ended AC and DC Input Levels for DQ and DM

Symbol Parameter

Unit Notes

Min Max Min Max Min Max

VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1 VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V 1

VIH.DQ(AC160) AC input logic high Vref + 0.160 Note2 - - - - V 1, 2, 5

VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160 - - - - V 1, 2, 5

VIH.DQ(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 - - V 1, 2, 5

VIL.DQ(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 - - V 1, 2, 5

VIH.DQ(AC130)AC Input logic high----Vref + 0.130Note2V1, 2, 5

VIL.DQ(AC130)AC input logic low----Note2Vref - 0.130V1, 2, 5

DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866

Reference Voltage

V

RefDQ(DC

)

for DQ, DM inputs

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4

Notes:

1. Vref = VrefDQ (DC).

2. Refer to "Overshoot and Undershoot Specifications" on page 41.

3. The ac peak noise on V

may not allow V

Ref

to deviate from V

Ref

RefDQ(DC)

by more than +/-1% VDD (for reference:

approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV

4. For reference: approx. VDD/2 +/- 13.5 mV

5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on page 28) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/ L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/ L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is operated in the 1.35 voltage range.

Rev. 1.0 / May. 2014 29

Vref Tolerances

VDD

VSS

VDD/2

V

Ref(DC)

V

Ref

ac-noise

voltage

time

V

Ref(DC)max

V

Ref(DC)min

V

Ref

(t)

The dc-tolerance limits and ac-noise limits for the reference voltages figure below. It shows a valid reference voltage V

likewise).

V

RefDQ

(DC) is the linear average of V

V

Ref

(t) over a very long period of time (e.g. 1 sec). This average has to

Ref

(t) as a function of time. (V

Ref

VRefCA

and V

are illustrated in

RefDQ

stands for V

Ref

RefCA

and

meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 36. Furthermore V

(t) may temporarily deviate from V

Ref

Illustration of V

Ref(DC)

Ref (DC)

by no more than +/- 1% VDD.

tolerance and V

ac-noise limits

Ref

The voltage levels for setup and hold time measurements V dent on V

” shall be understood as V

“V

Ref

This clarifies that dc-variations of V

Ref

.

, as defined in figure above.

Ref(DC)

affect the absolute voltage a signal has to reach to achieve a valid

Ref

IH(AC)

, V

IH(DC)

, V

IL(AC)

, and V

IL(DC)

high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V

deviations from the optimum position within the data-eye of the input

Ref(DC)

signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and

voltage associated with V

ac-noise. Timing and voltage effects due to ac-noise on V

Ref

up to the speci-

Ref

fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.

Rev. 1.0 / May. 2014 30

are depen-

AC and DC Logic Input Levels for Differential Signals

time

Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)

V

IL.DIFF.AC.MAX

V

IL.DIFF.MAX

0

V

IL.DIFF.MIN

V

IL.DIFF.AC.MIN

t

DVAC

half cycle

t

DVAC

Differential signal definition

Definition of differential ac-swing and “time above ac-level” t

DVAC

Rev. 1.0 / May. 2014 31

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)

Differential AC and DC Input Levels

Symbol Parameter

VIHdiff Differential input high + 0.180 Note 3 V 1

VILdiff Differential input logic low Note 3 - 0.180 V 1

VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2

VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL (ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 41.

DDR3L-800, 1066, 1333, 1600

Unit Notes

Min Max

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

DDR3L-800/1066/1333/1600 DDR3L-1866

Slew Rate

[V/ns]

tDVAC [ps]

@ |VIH/Ldiff

(ac)| = 320mV

min max min max min max min max min max

> 4.0 189 - 201 - 163 - 168 - 176 -

4.0 189 - 201 - 163 - 168 - 176 -

3.0 162 - 179 - 140 - 147 - 154 -

2.0 109 - 134 95 105 111

1.8 91 - 119 - 80 - 91 - 97 -

1.6 69 - 100 - 62 - 74 - 78 -

1.4 40 - 76 - 3 7 - 52 - 56 -

1.2 note - 44 - 5 - 22 - 24 -

1.0 note - note - note - note - note -

< 1.0 note - note - note - note - note -

note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.

tDVAC [ps]

@ |VIH/Ldiff

(ac)| = 270mV

tDV AC [ps]

@ |VIH/Ldiff

(ac)| = 270mV

tDVAC [ps]

@ |VIH/Ldiff

(ac)| = 250mV

tDVAC [ps]

@ |VIH/Ldiff

(ac)| = 260mV

-

Rev. 1.0 / May. 2014 32

Single-ended requirements for differential signals

VDD or VDDQ

VSEHmin

VDD/2 or VDDQ/2

VSEH

VSELmax

VSS or VSSQ

CK or DQS

VSEL

time

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.

DQS, DQSL, DQSU, DQS / VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK

, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)

.

Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin ha s no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

Rev. 1.0 / May. 2014 33

Single-ended requirements for differential signals.

Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU

Symbol Parameter

VSEH

VSEL

Notes:

1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs.

2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 41.

Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2

Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V 1,2

Single-ended low level for strobes Note 3 (VDD / 2) - 0.175 V 1,2

Single-ended low level for CK, CK Note 3 (VDD / 2) - 0.175 V 1,2

DDR3L-800, 1066, 1333, 1600, 1866

Unit Notes

Min Max

Rev. 1.0 / May. 2014 34

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS

and DQS, DQS) must meet the

Vix Definition

Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

VIX(CK)

VIX(DQS)

Notes:

1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK CK is larger than 3 V/ns.

2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following. (VDD/2) + Vix (Min) - VSEL  25mV  VSEH - ((VDD/2) + Vix (Max))  25mV

Differential Input Cross Point Voltage

relative to VDD/2 for CK,

Differential Input Cross Point Voltage

relative to VDD/2 for DQS,

CK

DQS

DDR3L-800, 1066, 1333, 1600, 1866

Unit Notes

Min Max

-150 150 mV 2

-175 175 mV 1

-150 150 mV 2

Rev. 1.0 / May. 2014 35

Slew Rate Definitions for Single-Ended Input Signals

Delta

TFdiff

Delta

TRdiff

V

IHd iffm in

VILdiffma x

0

Differential Input Voltage (i.e. DQS-DQS; CK-CK)

See 7 .5 “ Addr ess / Command Setup, Hold and Der ating” in “DDR3 Device Oper ation” f or single-ended slew rate definitions for address and command signals.



See 7 .6 “Data Setup, Hold and Slew Rate Derating” in “DDR3 Device Oper ation” for single-ended slew r ate definition for data signals.

Slew Rate Definitions for Differential Input Signals

Input slew rate for differ ential signals (CK, CK and DQS, DQS) are defined and measur ed as shown in table and figure below.

Differential Input Slew Rate Definition

Description

Differential input slew rate for rising edge (CK-CK

and DQS-DQS)

Differential input slew rate for falling edge (CK-CK

Notes:

The differential signal (i.e. CK-CK and DQS - DQS) must be linear between these thresholds.

and DQS-DQS)

Min

V

ILdiffmax

V

IHdiffmin

Measured

V

Max

IHdiffmin

ILdiffmax

[V

IHdiffmin-VILdiffmax

[V

IHdiffmin-VILdiffmax

Defined by

] / DeltaTRdiff

] / DeltaTFdiff

Differential Input Slew Rate Definition for DQS, DQS and CK, CK

Rev. 1.0 / May. 2014 36

AC & DC Output Measurement Levels

Single Ended AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Single-ended AC and DC Output Levels

Symbol Parameter

DDR3L-800, 1066,

1333, 1600, 1866

V

OH(DC)

V

OM(DC)

V

OL(DC)

V

OH(AC)

V

OL(AC)

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

0.8 x V

0.5 x V

0.2 x V + 0.1 x V

V

TT

V

- 0.1 x V

TT

DDQ DDQ DDQ

Notes:

1. The swing of ±0.1 x V a driver impedance of 40Ω and an effective test load of 25Ω to VTT = V

is based on approximately 50% of the static single ended output high or low swing with

DDQ

/ 2.

Differential AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.

Differential AC and DC Output Levels

Symbol Parameter

V

OHdiff (AC)

V

OLdiff (AC)

AC differential output high measurement level (for output SR)

AC differential output low measurement level (for output SR)

Notes:

1. The swing of ±0.2 x V a driver impedance of 40

is based on approximately 50% of the static differential output high or low swing with

DDQ

Ω and an effective test load of 25Ω to VTT = V

DDR3L-800, 1066,

1333, 1600, 1866

+ 0.2 x V

- 0.2 x V

/2 at each of the differential outputs.

DDQ

Unit Notes

V V V V1 V1

Unit Notes

V1 V1

Rev. 1.0 / May. 2014 37

Single Ended Output Slew Rate

Delta TFse

Delta TRse

V

OH(AC)

V

Ol(AC)

V

∏

Single Ended Output Voltage(l.e.DQ)

When the Reference load for timing measurements, output slew rate for f alling and rising edges is defined and measured between V

OL(AC)

and V

for single ended signals are shown in table and figure below.

OH(AC)

Single-ended Output slew Rate Definition

Description

Defined by

From To

Measured

Single-ended output slew rate for rising edge Single-ended output slew rate for falling edge

V

OL(AC)

V

OH(AC)

V

OH(AC)

V

OL(AC)

[V

OH(AC)-VOL(AC)

[V

OH(AC)-VOL(AC)

Notes:

1. Output slew rate is verified by design and characterisation, and may not be subject to production test.

Single Ended Output slew Rate Definition

] / DeltaTRse ] / DeltaTFse

Output Slew Rate (single-ended)

DDR3L-800 DDR3L-1066DDR3L-1333DDR3L-1600DDR3L-1866

Parameter Symbol Min Max Min Max Min Max Min Max Min Max

Single-ended Output Slew Rate SRQse 1.75

1)

1.75

5

Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. Case 1 is a defined for a single DQ signal within a byte lane which is switching i n to a certain direction (either from high

to low or low to high) while a ll rem aining D Q sign als in th e sam e byte lane ar e stati c (i.e. th ey sta y at eithe r high or low). Case 2 is a defined for a single DQ signal within a byte lane which is switching i n to a certain direction (either from high

to low or low to high) while all remain ing DQ sig nals in the s ame byte la ne switchin g into the op posite directio n (i.e. fr om low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular maximum limite of 5 V/ns applies.

Rev. 1.0 / May. 2014 38

1)

1.75

5

1)

1.75

5

1)

1.75

5

Units

1)

V/ns

5

Differential Output Slew Rate

Delta

TFdiff

Delta

TRdiff

V

OHdiff(AC)

VOLdiff(AC)

O

Differential Output Voltage(i.e. DQS-DQS)

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure

below.

Differential Output Slew Rate Definition

Description

Defined by

From To

Measured

Differential output slew rate for rising edge

Differential output slew rate for falling edge

V

OLdiff (AC)

V

OHdiff (AC)

V

OHdiff (AC)

V

OLdiff (AC)

[V

OHdiff (AC)-VOLdiff (AC)

[V

OHdiff (AC)-VOLdiff (AC)

Notes:

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

] / DeltaTRdiff ] / DeltaTFdiff

Differential Output slew Rate Definition

Differential Output Slew Rate

DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866

Parameter Symbol Min Max Min Max Min Max Min Max Min Max

Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 V/ns

Description: SR; Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting

Rev. 1.0 / May. 2014 39

Units

Reference Load for AC Timing and Output Slew Rate

DUT

DQ

DQS DQS

VDDQ

25 Ohm

VTT = VDDQ/2

CK, CK

Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.

Reference Load for AC Timing and Output Slew Rate

Rev. 1.0 / May. 2014 40

Overshoot and Undershoot Specifications

Maximum Amplitude

Overshoot Area

VDD

VSS

Maximum Amplitude

Undershoot Area

Time (ns)

Volts

(V)

Address and Control Overshoot and Undershoot Specifications

AC Overshoot/Undershoot Specification for Address and Control Pins

DDR3

Parameter

Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD (See Figure below) 0.67 0.5 0.4 0.33 0.28 V-ns Maximum undershoot area below VSS (See Figure below) 0.67 0.5 0.4 0.33 0.28 V-ns

L-800

L-1066

L-1333

L-1600

(A0-A15, BA0-BA3, CS, RAS, CAS, W E, CKE, ODT)

See figure below for each parameter definition

DDR3

Units

L-1866

Address and Control Overshoot and Undershoot Definition

Rev. 1.0 / May. 2014 41

Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Maximum Amplitude

Undershoot Area

Time (ns)

Volts

(V)

AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask

DDR3

Parameter

Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD (See Figure below) 0.25 0.19 0.15 0.13 0.11 V-ns Maximum undershoot area below VSS (See Figure below) 0.25 0.19 0.15 0.13 0.11 V-ns

L-800

L-1066

L-1333

L-1600

(CK, CK, DQ, DQS, DQS, DM)

See figure below for each parameter definition

DDR3

Units

L-1866

Clock, Data, Strobe and Mask Overshoot and Undershoot Definition

Rev. 1.0 / May. 2014 42

Refresh parameters by device density

Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes

REF command ACT or

REF command time

Average periodic refresh interval

Notes:

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to dete rmine if DDR3 SDRAM devices support the following options or requirements referred to in this materia.

tREFI

tRFC 90 110 160 260 350 ns

C  T

0

85

C  T

 85 C 7.8 7.8 7.8 7.8 7.8 us

CASE

 95 C 3.9 3.9 3.9 3.9 3.9 us 1

CASE

Rev. 1.0 / May. 2014 43

Standard Speed Bins

DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

DDR3L-800 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 49.

Speed Bin DDR3L-800E

CL - nRCD - nRP 6-6-6

Parameter

Symbol min max

Unit Notes

Internal read command to first data

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

ACT to PRE command period

CL = 6 CWL = 5

Supported CL Settings

Supported CWL Settings

t

AA

t

RCD

t

RP

t

RC

t

RAS

t

CK(AVG)

15 20 ns

15 — ns

52.5 — ns

37.5 9 * tREFI ns

2.5 3.3 ns 6 5

n n

1,2,3

CK CK

Rev. 1.0 / May. 2014 44

DDR3L-1066 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 49.

Speed Bin DDR3L-1066F

CL - nRCD - nRP 7-7-7

Parameter Symbol min max

Internal read command to

first data

t

AA

13.125 20 ns

Unit Note

ACT to internal read or

write delay time

PRE command period

ACT to ACT or REF

command period

ACT to PRE command

period

CL = 6

CL = 7

CL = 8

CWL = 5 CWL = 6 CWL = 5 CWL = 6 CWL = 5 CWL = 6

t

RCD

t

RP

t

RC

t

RAS

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

13.125 — ns

50.625 — ns

37.5 9 * tREFI ns

2.5 3.3 ns 1,2,3,6

1.875 < 2.5 ns 1,2,3,4

1.875 < 2.5 ns 1,2,3

Supported CL Settings 6, 7, 8

Supported CWL Settings 5, 6

Reserved ns 1,2,3,4 Reserved ns 4

Reserved ns 4

n

CK

n

CK

Rev. 1.0 / May. 2014 45

DDR3L-1333 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 49.

Speed Bin DDR3L-1333H

CL - nRCD - nRP 9-9-9

Parameter Symbol min max

Internal read

command to first data

ACT to internal read or

write delay time

PRE command period

ACT to ACT or REF

command period

t

RCD

t

AA

RP

RC

13.5

(13.125)

13.5

(13.125)

13.5

(13.125)

49.5

(49.125)

5,10

20 ns

—ns

Unit Note

ACT to PRE command

period

CWL = 5

CL = 6

CWL = 6 CWL = 7 CWL = 5

CL = 7

CWL = 6

CWL = 7 CWL = 5

CL = 8

CWL = 6 CWL = 7

CL = 9

CWL = 5, 6

CWL = 7

CWL = 5, 6

CL = 10

CWL = 7

t

RAS

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

36 9 * tREFI ns

2.5 3.3 ns 1,2,3,7

1.875 < 2.5 (Optional)

1.875 < 2.5 ns 1,2,3,7

1.5 <1.875 ns 1,2,3,4

1.5 <1.875 ns 1,2,3

Supported CL Settings 6, 7, 8, 9, 10

Supported CWL Settings 5, 6, 7

Reserved ns 1,2,3,4,7 Reserved ns 4 Reserved ns 4

5,10

ns 1,2,3,4,7

Reserved ns 1,2,3,4 Reserved ns 4

Reserved ns 4

(Optional) ns 5

n

CK

n

CK

Rev. 1.0 / May. 2014 46

DDR3L-1600 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 49.

Speed Bin DDR3L-1600K

CL - nRCD - nRP 11-11-11

Parameter Symbol min max

Internal read

command to first data

ACT to internal read or

write delay time

PRE command period

ACT to ACT or REF

command period

ACT to PRE command

period

CWL = 5

CL = 6

CWL = 6 CWL = 7 CWL = 5

CL = 7

CWL = 6 CWL = 7

CWL = 8 CWL = 5

CL = 8

CWL = 6 CWL = 7 CWL = 8

CWL = 5, 6

CL = 9

CWL = 7 CWL = 8

CWL = 5, 6

CL = 10

CWL = 7 CWL = 8

CL = 11

CWL = 5, 6,7

CWL = 8

t

AA

t

RCD

t

RP

t

RC

t

RAS

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

Supported CL Settings 5, 6, 7, 8, 9, 10, 11

Supported CWL Settings 5, 6, 7, 8

13.75

(13.125)

13.75

(13.125)

13.75

(13.125)

48.75

(48.125)

5,10

20 ns

—ns

35 9 * tREFI ns

2.5 3.3 ns 1,2,3,8 Reserved ns 1,2,3,4,8 Reserved ns 4 Reserved ns 4

1.875 < 2.5 (Optional)

5,10

Reserved ns 1,2,3,4,8 Reserved ns 4 Reserved ns 4

1.875 < 2.5 ns 1,2,3,8

Reserved ns 1,2,3,4,8 Reserved ns 1,2,3,4 Reserved ns 4

1.5 <1.875 (Optional)

5,10

Reserved ns 1,2,3,4 Reserved ns 4

1.5 <1.875 ns 1,2,3,8

Reserved ns 1,2,3,4 Reserved ns 4

1.25 <1.5 ns 1,2,3

Unit Note

ns 1,2,3,4,8

n

CK

n

CK

Rev. 1.0 / May. 2014 47

DDR3L-1866 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 49.

Speed Bin DDR3L-1866M

CL - nRCD - nRP 13-13-13

Parameter Symbol min max

Internal read command

to first data

ACT to internal read or

write delay time

PRE command period

ACT to PRE command

period

ACT to ACT or PRE

command period

CWL = 5

CL = 6

CWL = 6

CWL = 7,8,9

CWL = 5

CL = 7

CWL = 6

CWL = 7,8,9

CWL = 5

CL = 8

CWL = 6 CWL = 7

CWL = 8,9

CWL = 5, 6

CL = 9

CWL = 7 CWL = 8 CWL = 9

CWL = 5, 6

CL = 10

CWL = 7 CWL = 8

CWL = 5,6,7

CL = 11

CWL = 8 CWL = 9

CL = 12

CL = 13

CWL = 5,6,7,8

CWL = 9

CWL = 5,6,7,8

CWL = 9

t

AA

t

RCD

t

RP

t

RAS

t

RC

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

t

CK(AVG)

Supported CL Settings 6, 7, 8, 9, 10, 11, 13

Supported CWL Settings 5, 6, 7, 8, 9

13.91

(13.125)

5,11

20 ns

13.91

(13.125)

5,11

—ns

13.91

(13.125)

5,11

—ns

34 9 * tREFI ns

47.91

(47.125)

5,11

-ns

2.5 3.3 ns 1,2,3,9 Reserved ns 1,2,3,4,9 Reserved ns 4 Reserved ns 4

1.875 < 2.5 ns 1,2,3,4,9 Reserved ns 4 Reserved ns 4

1.875 < 2.5 ns 1,2,3,9 Reserved ns 1,2,3,4,9 Reserved ns 4 Reserved ns 4

1.5 <1.875 ns 1,2,3,4,9 Reserved ns 1,2,3,4,9 Reserved ns 4 Reserved ns 4

1.5 <1.875 ns 1,2,3,9 Reserved ns 1,2,3,4,9 Reserved ns 4

1.25 <1.5 ns 1,2,3,4,9 Reserved ns 1,2,3,4 Reserved ns 4 Reserved ns 1,2,3,4 Reserved ns 4

1.07 <1.25 ns 1, 2, 3

Unit Note

n

CK

n

CK

Rev. 1.0 / May. 2014 48

Speed Bin Table Notes

Absolute Specification (T

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. Wh en making a selection of tCK(AVG), both need to be fulfilled: R equir ements f rom CL set ting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =

3.0 ns should only be used for CL = 5 calculation.

3. tCK(AVG).MAX limits: Calculate tCK(A VG) = tAA.MAX / CL SELECTED and round the resulting tCK(A V G) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is supported.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

10. DDR3 SDRAM d evices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.

11. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices sup porting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes f or tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRCmin(byte 21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns +

13.125ns)

OPER

; V

= VDD = 1.35V +0.100/- 0.067 V);

DDQ

-

Rev. 1.0 / May. 2014 49

Environmental Parameters

Symbol Parameter Rating Units Notes

T H T H P

OPR

STG

BAR

Operating temperature Operating humidity (relative) 10 to 90 % 1

Storage temperature -50 to +100 Storage humidity (without condensation) 5 to 95 % 1 Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2

Note:

1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility.

2. Up to 9850 ft.

3. The designer must meet the case temperature specifications for individual module components.

See Note 3

o

C

1

Rev. 1.0 / May. 2014 50

IDD and IDDQ Specification Parameters and Test Conditions

IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and pat terns are defined. F igur e

1. shows the setup and test load for IDD and IDDQ measurements.

• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.

• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur rents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply:

-

• ”0” and “LOW” is defined as VIN <= V

• ”1” and “HIGH” is defined as VIN >= V

• “MID_LEVEL” is defined as inputs are VREF = VDD/2.

• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.

• Basic IDD and IDDQ Measurement Conditions are described in Table 2.

• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.

• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1);

RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1

• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}

ILAC(max).

IHAC(max).

Rev. 1.0 / May. 2014 51

Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements

VDD

DDR3L

SDRAM

VDDQ

RESET CK/CK

DQS, DQS CS RAS, CAS, WE

A, BA ODT ZQ

VSS VSSQ

DQ, DM,

TDQS, TDQS

CKE

RTT = 25 Ohm

VDDQ/2

IDD

IDDQ (optional)

Application specific

memory channel

environment

Channel

IO Power

Simulation

IDDQ

Simulation

IDDQ

Simulation

Channel IO Power

Number

IDDQ

Test Load

Correction

[Note: DIMM level Output test load condition may be different from above

Rev. 1.0 / May. 2014 52

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported

by IDDQ Measurement

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns

Symbol

t

CK

DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866

7-7-7 9-9-9 11-11-11 13-13-13

1.875 1.5 1.25 1.07 ns

Unit

CL 7 9 11 13 nCK

n

RCD

n

RC

n

RAS

n

RP

1KB page size 20 20 24 26 nCK

n

FAW

2KB page size 27 30 32 33 nCK 1KB page size 4 4 5 5 nCK

n

RRD

2KB page size 6 5 6 6 nCK

n

-512Mb 48 60 72 85 nCK

RFC

n

-1 Gb 59 74 88 103 nCK

RFC

n

- 2 Gb 86 107 128 150 nCK

RFC

n

- 4 Gb 139 174 208 243 nCK

RFC

n

- 8 Gb 187 234 280 328 nCK

RFC

7 9 11 13 nCK 27 33 39 45 nCK 20 24 28 32 nCK

7 9 11 13 nCK

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol Description

Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and

I

PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;

DD0

DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-

b)

fer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 3.

Operating One Bank Active-Precharge Current

a)

; AL: 0; CS: High between ACT,

I

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8 RD and PRE; Command, Address; Bank Address Inputs, Data IO: pa rtially toggling according to Table 4; DM:

DD1

stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and

b)

RTT: Enabled in Mode Registers

Rev. 1.0 / May. 2014 53

; ODT Signal: stable at 0; Pattern Details: see Table 4.

Symbol Description

Precharge Standby Current

I

DD2N

I

DD2NT

I

DD2P0

I

DD2P1

CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

b)

banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 5. Precharge Standby ODT Current

CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

b)

banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6. Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

c)

Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

b)

; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

c)

Precharge Quiet Standby Current

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

I

DD2Q

CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all ba nks closed; Output Buf-

b)

fer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

Active Standby Current

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

b)

; ODT Signal: stable at 0; Pattern Details: see

I

DD3N

CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8 Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all

banks open; Output Buffer and RTT: Enabled in Mode Registers Table 5. Active Power-Down Current

I

DD3P

Rev. 1.0 / May. 2014 54

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer

b)

and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0

a)

; AL: 0; CS: stable at 1; Command, Address, Bank

Symbol Description

Operating Burst Read Current

I

DD4R

I

DD4W

I

DD5B

CKE: High; External clock: On; tCK, CL: see T able 1; BL: 8

a)

; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode

b)

Registers

; ODT Signal: stable at 0; Pattern Details: see Table 7.

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

a)

; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode

b)

Registers

; ODT Signal: stable at HIGH; Pattern Details: see Table 8.

Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8

Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;

a)

; AL: 0; CS: High between REF; Command,

Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Reg isters ODT Signal: stable at 0; Pattern Details: see Table 9. Self-Refresh Current: Normal Temperature Range

b)

;

T

: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:

CASE

I

DD6

Low; External clock: Off; CK and CK

: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer

b)

and RTT: Enabled in Mode Registers

; ODT Signal: MID_LEVEL

Self-Refresh Current: Extended Temperature Range (optional)

T

: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);

CASE

I

DD6ET

CKE: Low; External clock: Off; CK and CK

: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank

Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh

b)

operation; Output Buffer and RTT: Enabled in Mode Registers

Rev. 1.0 / May. 2014 55

; ODT Signal: MID_LEVEL

Symbol Description

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8

a),f)

; AL: CL-1; CS:

High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table

I

10; Data IO: read data burst with different data between one burst and the next one according to Table 10;

DD7

DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-

b)

ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern

Details: see Table 10.

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;

RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Rev. 1.0 / May. 2014 56

Table 3 - IDD0 Measurement-Loop Pattern

CK, CK

toggling

CKE

Sub-Loop

0

Static High

1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Cycle

Number

0

1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 3,4 D ... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ... repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 1*nRC+3, 4 D ... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary 1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 ... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary

ACT 0 0 1 1 0 0 00 0 0 0 0 -

, D 1111000000 00 -

, D 1111000000 F0 -

CS

Command

RAS

CAS

a)

WE

b)

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

Data

A[2:0]

a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL. b) DQ signals are MID-LEVEL.

Rev. 1.0 / May. 2014 57

Table 4 - IDD1 Measurement-Loop Pattern

CK, CK

toggling

CKE

Sub-Loop

0

Static High

1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Cycle

Number

0

1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 3,4 D ... repeat pattern 1...4 until nRCD - 1, truncate if necessary nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE001000000000 ... repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 1*nRC+3,4 D ... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary 1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011 ... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary 1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 ... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary

ACT001100000000 -

, D 111100000000 -

, D 1111000000F0 -

CS

Command

RAS

CAS

a)

WE

b)

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

Data

A[2:0]

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.

Rev. 1.0 / May. 2014 58

Table 5 - IDD2N and IDD3N Measurement-Loop Pattern

CKE

CK, CK

toggling

a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL. b) DQ signals are MID-LEVEL.

Sub-Loop

0

1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead

Static High

4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-17 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead

Cycle

Number

0

1D100000000002D 3D

D10000000000 -

CS

RAS

Command

1111 0000 0F0 1111 0000 0F0 -

CAS

WE

ODT

BA[2:0]

A[15:11]

a)

b)

Data

A[10]

A[9:7]

A[6:3]

A[2:0]

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern

CKE

CK, CK

toggling

a) DM must be driven LOW all the time. DQS, DQS are MID-LEV EL. b) DQ signals are MID-LEVEL.

Sub-Loop

0

1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3

Static High

4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-17 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7

Cycle

Number

0

1D100000000002D 3D

D10000000000 -

CS

RAS

Command

1111000 00 F0 1111000 00 F0 -

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

a)

A[9:7]

A[2:0]

A[6:3]

Data

b)

Rev. 1.0 / May. 2014 59

A[15:11]

a)

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern

CKE

CK, CK

toggling

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Sub-Loop

0

1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2

Static High

3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

Cycle

Number

0

1D1000000000002,3 D 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5D1000000000F06,7 D

RD 0 1 0 1 0 0 00 0 0 0 0 00000000

,D 111100000 0 00 -

,D 111100000 0 F0 -

CS

Command

RAS

Table 8 - IDD4W Measurement-Loop Pattern

CAS

WE

ODT

BA[2:0]

a)

b)

CKE

CK, CK

toggling

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.0 / May. 2014 60

Sub-Loop

0

1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2

Static High

3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

Cycle

Number

0

1D1000100000002,3 D 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 5D1000100000F06,7 D

WR 0 1 0 0 1 0 00 0 0 0 0 00000000

CS

RAS

Command

,D 111110000 0 00 -

,D 111110000 0 F0 -

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

Data

A[2:0]

Table 9 - IDD5B Measurement-Loop Pattern

CKE

CK, CK

toggling

a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. b) DQ signals are MID-LEVEL.

Sub-Loop

0

11.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -

Static High

2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.

Cycle

Number

0

3,4 D

5...8 repeat cycles 1...4, but BA[2:0] = 1

9...12 repeat cycles 1...4, but BA[2:0] = 2

13...16 repeat cycles 1...4, but BA[2:0] = 3

17...20 repeat cycles 1...4, but BA[2:0] = 4

21...24 repeat cycles 1...4, but BA[2:0] = 5

25...28 repeat cycles 1...4, but BA[2:0] = 6

29...32 repeat cycles 1...4, but BA[2:0] = 7

REF 0 0 0 1 0 0 0 0 0 0 0 -

, D 111100000 0 F0 -

CS

Command

RAS

CAS

WE

a)

b)

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

Data

A[2:0]

Rev. 1.0 / May. 2014 61

Table 10 - IDD7 Measurement-Loop Pattern

a)

ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9

CK, CK

toggling

Command

CS

RAS

CKE

Sub-Loop

0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -

1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 ... repeat above D Command until nRRD - 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011

1

nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -

... repeat above D Command until 2* nRRD - 1 2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2 3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3

4*nRRD 4

5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4 6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5 7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7

nFAW+4*nRRD 9

2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -

Static High

2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011

10

2&nFAW+2

2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -

2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000

11

2&nFAW+nRRD+2

12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3

14 2*nFAW+4*nRRD 15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4

16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7

19 3*nFAW+4*nRRD

Cycle

Number

D 1 0 0 0 0 3 00 0 0 F 0 -

Assert and repeat above D Command until nFAW - 1, if necessary

D 1 0 0 0 0 7 00 0 0 F 0 -

Assert and repeat above D Command until 2* nFAW - 1, if necessary

D 1 0 0 0 0 0 00 0 0 F 0 -

Repeat above D Command until 2* nFAW + nRRD - 1

D 1 0 0 0 0 1 00 0 0 0 0 -

Repeat above D Command until 2* nFAW + 2* nRRD - 1

D 1 0 0 0 0 3 00 0 0 0 0 Assert and repeat above D Command until 3* nFAW - 1, if necessary

D 1 0 0 0 0 7 00 0 0 0 0 Assert and repeat above D Command until 4* nFAW - 1, if necessary

CAS

WE

ODT

BA[2:0]

A[15:11]

A[10]

A[9:7]

A[6:3]

A[2:0]

Data

b)

a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.

Rev. 1.0 / May. 2014 62

IDD Specifications (Tcase: 0 to 95oC)

* Module IDD values in the datasheet are only a calculation based on the component IDD spec and r egister power. The actual measurements may vary according to DQ loading cap.

4GB, 512M x 72 R-DIMM: HMT451R7BFR8A

Symbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit note

IDD0 998 998 1016 mA IDD1 1070 1070 1088 mA

IDD2N 881 890 899 mA

IDD2NT 908 926 935 mA

IDD2P0 300 300 309 mA IDD2P1 300 300 309 mA

IDD2Q 872 881 890 mA IDD3N 917 917 935 mA IDD3P 327 327 336 mA IDD4R 1349 1394 1502 mA

IDD4W 1394 1439 1529 mA

IDD5B 1889 1889 1889 mA

IDD6 318 318 318 mA

IDD6ET 345 345 345 mA

IDD7 1799 1844 1934 mA

8GB, 1G x 72 R-DIMM: HMT41GR7BFR4A

Symbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit note

IDD0 1232 1232 1268 mA IDD1 1376 1376 1412 mA

IDD2N 998 1016 1034 mA

IDD2NT 1052 1088 1106 mA

IDD2P0 372 372 390 mA IDD2P1 372 372 390 mA

IDD2Q 980 998 1016 mA IDD3N 1070 1070 1106 mA IDD3P 426 426 444 mA IDD4R 1844 1934 2168 mA

IDD4W 1934 2024 2204 mA

IDD5B 3014 3014 3014 mA

IDD6 408 408 408 mA

IDD6ET 462 462 462 mA

IDD7 2834 2924 3104 mA

Rev. 1.0 / May. 2014 63

8GB, 1G x 72 R-DIMM: HMT41GR7BFR8A

Symbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit note

IDD0 1115 1151 1187 mA IDD1 1187 1223 1259 mA

IDD2N 998 1016 1034 mA

IDD2NT 1052 1088 1106 mA

IDD2P0 372 372 390 mA IDD2P1 372 372 390 mA

IDD2Q 980 998 1016 mA IDD3N 1070 1070 1106 mA IDD3P 426 426 444 mA IDD4R 1466 1547 1673 mA

IDD4W 1511 1592 1700 mA

IDD5B 2006 2042 2060 mA

IDD6 408 408 408 mA

IDD6ET 462 462 462 mA

IDD7 1916 1997 2105 mA

16GB, 2G x 72 R-DIMM: HMT42GR7BFR4A

Symbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit note

IDD0 1466 1538 1610 mA IDD1 1610 1682 1754 mA

IDD2N 1232 1268 1304 mA

IDD2NT 1340 1412 1448 mA

IDD2P0 516 516 552 mA IDD2P1 516 516 552 mA

IDD2Q 1196 1232 1268 mA IDD3N 1376 1376 1448 mA IDD3P 624 624 660 mA IDD4R 2078 2240 2510 mA

IDD4W 2168 2330 2546 mA

IDD5B 3248 3320 3356 mA

IDD6 588 588 660 mA

IDD6ET 696 696 696 mA

IDD7 3068 3230 3446 mA

Rev. 1.0 / May. 2014 64

32GB, 4G x 72 R-DIMM: HMT84GR7BMR4A

Symbol DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit note

IDD0 1916 1934 2150 mA IDD1 2060 2078 2294 mA

IDD2N 1700 1700 1772 mA

IDD2NT 1916 1916 2060 mA

IDD2P0 804 804 804 mA IDD2P1 804 804 804 mA

IDD2Q 1628 1628 1700 mA IDD3N 1916 1988 1988 mA IDD3P 1020 1020 1020 mA IDD4R 2456 2546 2852 mA

IDD4W 2546 2636 2942 mA

IDD5B 3716 3716 3932 mA

IDD6 948 948 948 mA

IDD6ET 1164 1164 1164 mA

IDD7 3356 3536 3842 mA

Rev. 1.0 / May. 2014 65

Module Dimensions

5.175

Detail C

2.10±0.15

47.00

71.00

2X3.00±0.10

Front

1

30.00

9.50

17.30

120

5.0

1

240

121

Back

133.35

128.95

Registering

Clock Driver

SPD/TS

4X3.00±0.10

1.27

±010

mm

Side

max

3.64mm max

0.35

2.50

±

0.20

1.00

0.80± 0.05

Detail of Contacts B

1.50 ±0.10

Detail of Contacts C

0.3

±

0.15

0.3~0.1

5.00

3.80

2.50

±

0.20

3± 0.1

1.20

±

0.15

Detail of Contacts A

Detail B

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.75 Max

512Mx72 - HMT451R7BFR8A

Rev. 1.0 / May. 2014 66

1Gx72 - HMT41GR7BFR4A

5.175

Detail B

Detail C

2.10±0.15

47.00

71.00

2X3.00±0.10

Front

1

4X3.00±0.10

120

5.0

1

240

121

Back

133.35

128.95

Registering

Clock Driver

SPD/TS

1.27

±010

mm

Side

max

3.64mm max

0.35

2.50

±

0.20

1.00

0.80± 0.05

Detail of Contacts B

1.50 ±0.10

Detail of Contacts C

0.3

±

0.15

0.3+0.1

5.00

3.80

2.50

±

0.20

3± 0.1

1.20

±

0.15

Detail of Contacts A

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

30.00

9.50

17.30

23.30

2x R0.75 Max

Rev. 1.0 / May. 2014 67

1Gx72 - HMT41GR7BFR8A

5.175

Detail B

Detail C

2.10±0.15

47.00

71.00

2X3.00±0.10

Front

1

4X3.00±0.10

120

5.0

1

240

121

Back

133.35

128.95

Registering

Clock Driver

SPD/TS

1.27

±010

mm

Side

max

3.64mm max

0.35

2.50

±

0.20

1.00

0.80± 0.05

Detail of Contacts B

1.50 ±0.10

Detail of Contacts C

0.3

±

0.15

0.3+0.1

5.00

3.80

2.50

±

0.20

3± 0.1

1.20

±

0.15

Detail of Contacts A

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

30.00

9.50

17.30

23.30

2x R0.75 Max

Rev. 1.0 / May. 2014 68

30.00

9.50

17.30

23.30

5.175 Detail C

Detail D

2.10±0.15

47.00

71.00

2X3.00±0.10

Front

1

120

5.0

1

240

121

Back

133.35

128.95

Registering

Clock Driver

SPD/TS

4X3.00±0.10

1.27

±010

mm

Side

max

3.64mm max

0.20

2.50

±

0.20

1.00

0.80± 0.05

Detail of Contacts C

1.50 ±0.10

Detail of Contacts D

0.3

±

0.15

0.3~0.1

5.00

3.80

2.50

±

0.20

3± 0.1

1.20

±

0.15

0.4

13.60

14.90

Detail of Contacts A

Detail of Contacts B

Detail B

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.75 Max

2Gx72 - HMT42GR7BFR4A

Rev. 1.0 / May. 2014 69

2Gx72 - HMT42GR7BFR4A - Heat Spreader

Front

30.20

120

Back

133.35

22.00

Registering

Clock Driver

127

121

Registering

Clock Driver

1.27

±010

mm

Side

max

7.65mm max

1

240

133.75

14.214

2.786

6.35

36.7

42.7

20.9

10

33.4 33.4

3.69

5.39

6.3

7.36

46.46

80.54

2.15

57.2

7.74

119.64

2.7

15.36

22.00

8

Note:

1. tolerance on all dimensions unless otherwise stated.

2.In order to uninstall FDHS, please contact sales administrator.

0.13

Units: millimeters

2x R0.75 Max

Rev. 1.0 / May. 2014 70

30.00

9.50

17.30

23.30

5.175 Detail C

Detail D

±

0.15

47.00

71.00

±

0.10

Front

1

120

5.0

1

240

121

Back

133.35

128.95

Registering

Clock Driver

SPD/TS

Registering

Clock Driver

4X3.00±0.10

1.27

±010

mm

Side

max

3.64mm max

0.20

2.50

±

0.20

1.00

0.80± 0.05

Detail of Contacts C

1.50 ±0.10

Detail of Contacts D

0.3

±

0.15

0.3~0.1

5.00

3.80

2.50

±

0.20

3± 0.1

1.20

±

0.15

0.4

13.60

14.90

Detail of Contacts A

Detail of Contacts B

Detail A

Detail B

DDP DDP DDP DDP DDP

DDP DDP DDP DDP

DDP DDP DDP

DDP

DDP DDP DDP DDP

DDP DDP DDP DDP DDP

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

SPD/TS

2x R0.75 Max

4Gx72 - HMT84GR7BMR4A

Rev. 1.0 / May. 2014 71

4Gx72 - HMT84GR7BMR4A - Heat Spreader

Front

30.20

120

Back

133.35

22.00

Registering

Clock Driver

127

121

Registering

Clock Driver

1.27

±010

mm

Side

max

7.65mm max

1

240

133.75

14.214

2.786

6.35

36.7

42.7

20.9

10

33.4 33.4

3.69

5.39

6.3

7.36

46.46

80.54

2.15

57.2

7.74

119.64

2.7

15.36

22.00

8

Note:

1. tolerance on all dimensions unless otherwise stated.

2.In order to uninstall FDHS, please contact sales administrator.

0.13

Units: millimeters

2x R0.75 Max

Rev. 1.0 / May. 2014 72