SK hynix HMA851S6CJR6N, HMA81GS6CJR8N, HMA81GS7CJR8N, HMA82GS6CJR8N, HMA82GS7CJR8N User Manual

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Page 1

260pin DDR4 SDRAM SODIMM

DDR4 SDRAM SO-DIMM

Based on 8Gb C-die

HMA851S6CJR6N HMA81GS6CJR8N HMA81GS7CJR8N HMA82GS6CJR8N HMA82GS7CJR8N

*SK hynix reserves the right to change products or specifications without notice.

Rev. 1.5 / Jun.2018 1

Page 2

Revision History

Revision No. History Draft Date Remark

0.1 Initial Release Jul.2017

1.0 IDD spec update Aug.2017

1.1 Changed features (Temperature s for ECC SODIMM)

CS released for 2666 non-ECC SODIMM

1.2 Corrected module dimensions P/N Feb.2018

1.3 Updated JEDEC Specification Apr.2018

1.4 Speed bin table note update Apr.2018

1.5 Define IDD specification(2666)

Modify IDD specification table /

Updated JEDEC specification

ensor with integrated SPD

Sep.2017

Jun.2018

Rev. 1.5 / Jun.2018 2

Page 3

Description

SK hynix Unbuffered Small Outline DDR4 SDRAM DIMMs (Unbuffered Small Outine Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. These DDR4 SDRAM Unbuffered Small Outline DIMMs are intended for use as main memory when installed in systems such as micro servers and mobile personal computres.

Features

• Power Supply: VDD=1.2V (1.14V to 1.26V)

• VDDQ = 1.2V (1.14V to 1.26V)

• VPP - 2.5V (2.375V to 2.75V)

• VDDSPD=2.25V to 3.6V

• Functionality and operations comply with the DDR4 SDRAM datasheet

• 16 internal banks

• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available

• Data transfer rates: PC4-3200, PC4-2933, PC4-2666, PC4-2400, PC4-2133, PC4-1866, PC4-1600

• Bi-Directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)

• Supports ECC error correction and detection

• On-Die Termination (ODT)

• Temperature sensor with integrated SPD for ECC SODIMM

• This product is in compliance with the RoHS directive.

• Per DRAM Addressability is supported

• Internal Vref DQ level generation is available

Ordering Information

Part Number Density Organization Component Composition

HMA851S6CJR6N- UH/VK 4GB 512Mx64 512Mx16(H5AN8G6NCJR)*4 1

HMA81GS6CJR8N-UH/VK 8GB 1Gx64 1Gx8(H5AN8G8NCJR)*8 1

HMA81GS7CJR8N-VK 8GB 1Gx72 1Gx8(H5AN8G8NCJR)*9 1

HMA82GS6CJR8N-UH/VK 16GB 2Gx64 1Gx8(H5AN8G8NCJR)*16 2

HMA82GS7CJR8N-VK 16GB 2Gx72 1Gx8(H5AN8G8NCJR)*18 2

Rev. 1.5 / Jun.2018 3

# of

ranks

Page 4

Key Parameters

MT/s Grade

DDR4-1600 -PB 1.25 11

DDR4-1866 -RD 1.071 13

DDR4-2133 -TF 0.937 15

DDR4-2400 -UH 0.833 17

DDR4-2666 -VK 0.75 19

DDR4-2933 -WM 0.682 21

DDR4-3200 -XN 0.625 22 13.75 13.75 32 47.0 22-22-22

*SK hynix DRAM devices support optional downbinning to CL21, CL19, CL17, CL15, CL13 and CL11. SPD setting is programmed to match.

tCK

(ns)

CAS

Latency

(tCK)

tRCD

(ns)

13.75

(13.50)*

13.92

(13.50)*

14.06

(13.50)*

14.16

(13.75)*

14.25

(13.75)*

14.32

(13.75)*

tRP

(ns)

13.75

(13.50)*

13.92

(13.50)*

14.06

(13.50)*

14.16

(13.75)*

14.25

(13.75)*

14.32

(13.75)*

tRAS

(ns)

tRC

(ns)

48.75

(48.50)*

47.92

(47.50)*

47.06

(46.50)*

46.16

(45.75)*

46.25

(45.75)*

46.32

(45.75)*

CL-tRCD-tRP

11-11-11

13-13-13

15-15-15

17-17-17

19-19-19

21-21-21

Address Table

4GB(1Rx16) 8GB(1Rx8) 16GB(2Rx8)

# of Bank Groups 244

Bank Address

Row Address A0~A15 A0~A15 A0~A15

Column Address A0~ A9 A0~ A9 A0~ A9

Page size 2KB 1 KB 1 KB

Rev. 1.5 / Jun.2018 4

BG Address BG0 BG0~BG1 BG0~BG1

Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1

Page 5

Pin Descriptions

Pin Name Description Pin Name Description

A0-A16

SDRAM address bus SCL

BA0, BA1 SDRAM bank select SDA

BG0, BG1 SDRAM bank group select SA0-SA2

RAS_n

CAS_n

WE_n

CS0_n, CS1_n,

CS2_n, CS3_n

SDRAM row address strobe PARITY SDRAM parity input

SDRAM column address strobe VDD SDRAM I/O & core power supply

SDRAM write enable VPP SDRAM activating power supply

Rank Select Lines C0, C1 Chip ID lines for 3DS components

CKE0, CEK1 SDRAM clock enable lines VREFCA

C serial bus clock for SPD/TS

C serial bus data line for SPD/TS

C slave address select for SPD/TS

SDRAM command/address reference supply

ODT0, ODT1 SDRAM on-die termination control lines VSS Power supply return (ground)

ACT_n SDRAM activate VDDSPD Serial SPD/TS positive power supply

DQ0-DQ63 DIMM memory data bus ALERT_n SDRAM ALERT_n

CB0-CB7 DIMM ECC check bits

DQS0_t-DQS8_t

DQS0_c-DQS8_c

DM0_n-DM8_n, DBI0_n-DBI8_n

CK0_t, CK1_t

CK0_c, CK1_c

SDRAM data strobes

(positive line of differential pair)

SDRAM data strobes

(negative line of differential pair)

SDRAM data masks/data bus inversion

(x8-based x72 DIMMs)

SDRAM clocks (positive line of differential pair)

SDRAM clocks (negative line of differential pair)

RESET_n Set SDRAMs to a Known State

EVENT_n

VTT

SPD signals a thermal event has occurred

Termination supply for the Address, Command and Control bus

NC No connection

1. RAS_n is a multiplexed function with A16.

2. CAS_n is a multiplexed function with A15.

3. WE_n is a multiplexed function with A14.

Rev. 1.5 / Jun.2018 5

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Input/Output Functional Descriptions

Symbol Type Function

CK0_t, CK0_c,

CK1_t, CK1_c

CKE0, CKE1 Input

CS0_n, CS1_n,

CS2_n, CS3_n

C0, C1

ODT0, ODT1

ACT_n

Input

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during SelfRefresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code.

Chip ID: Chip ID is only used for 3DS for 2 and 4 high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code.

On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n, signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15, and A14.

Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the RAS_n/A16, CAS_n/A15,

WE_n/A14

DM_n/DBI_n

BG0-BG1

BA0-BA1

Rev. 1.5 / Jun.2018 6

Input

Input/

Output

Input

command being entered. Those pins have multi function. For example, for activation

with ACT_n Low, these are Addresses like A16, A15, and A14 but for non-activation

command with ACT_n High, these are Command pins for Read, Write, and other

command defined in command truth table.

Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data.

Input data is masked when DM_n is sampled LOW coincident with that input data during

a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function.

DBI_n is an input/output identifying wherther to store/output the true or inverted data.

If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM

and not inverted if DBI_n is HIGH.

Bank Group Inputs: BG0 - BG1 define which bank group an Active, Read, Write, or

Precharge command is being applied. BG0 also determines which mode register is to be

accessed during a MRS cycle. For x4/8 based SDRAMs, BG0 and BG1 are valid. For x16

based SDRAM components, only BG0 is valid.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write, or

Precharge command is being applied. Bank address also determines which mode

Page 7

Symbol Type Function

Address Inputs: Provide the row address for ACTIVATE Commands and the column

address for Read/Write commands to select one location out of the memory array in the

A0 - A16

Input

respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 have

additional functions. See other rows. The address inputs also provide the op-code during

Mode Register Set commands.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write

A10 / AP

Input

operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a

Precharge command to determine whether the Precharge applies to one bank (A10

LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected

by bank addresses.

Burst Chop: A12/BC_n is sampled during Read and Write commands to determine if

A12 / BC_n

Input

burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped).

See command truth table for details.

RESET_n

DQS_t, DQS_c,

PARITY

ALERT_n

SA0-SA1

CMOS

Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive

when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then

Input / Output

CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the

internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor

specific data sheets to determine which DQ is used.

Input / Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. DDR4 SDRAMs support differential data strobe only and does not

support single-ended.

Command and Address Parity Input : DDR4 Supports Even Parity check in DRAMs with

MR setting. Once it’s enabled via Register in MR5, then DSRAM calculates Parity with

Input

ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A16-A0. Input parity

should be maintained at the rising edge of the clock and at the same time with

command & address with CS_n LOW.

ALERT: It has multiple functions, such as CRC error flag or Command and Address Parity

error flag, as an Output signal. If there is an error in CRC, then ALERT_n goes LOW for

the period time interval and goes back HIGH. If there is an error in Command Address

Output

Parity Check, then ALERT_n goes LOW for relatively long period until on going DRAM

internal recovery transaction is complete.

During Connectivity Test mode, this pin functions as an input.

Use of this signal or not is dependent on the system.

Input Device address for the SPD.

RFU

VDD

VSS

VTT

Rev. 1.5 / Jun.2018 7

Supply

Reserved for Future Use. No on DIMM electrical connection is present.

No Connect: No on DIMM electrical connection is present.

Power Supply: 1.2 V +/- 0.06 V

Ground

Power Supply : 0.6V

Page 8

Symbol Type Function

VPP

VREFCA

VDDSPD

Supply

DRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)

Reference voltage for CA

Power supply used to power the I2C bus on the SPD.

Note:

1. For PC4, VDD 1.2V. For PC4L VDD is TBD.

2. For PC4, VTT is 0.6V. For PC4L VTT is TBD.

Rev. 1.5 / Jun.2018 8

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Pin Assignments

1 VSS 2 VSS 131 A3 132 A2

3DQ54

7 DQ1 8 DQ0 137 CK0_t 138 CK1_t

9VSS10

13 DQS0_t 14 VSS 143 PARITY 144 A0

17 DQ7 18 VSS

19 VSS 20

23 VSS 24 DQ12 149 CS0_n 150 BA0

25 DQ13 26

29 DQ9 30 VSS 155 ODT0 156 A15/CAS_n

31 VSS 32

33 DM1_n, DBI1_n 34 DQS1_t 159 VDD 160 VDD

35 VSS 36 VSS 161 ODT1 162 C0, CS2_n, NC

37 DQ15 38

41 DQ10 42 DQ11 167 VSS 168 VSS

43 VSS 44

47 VSS 48 VSS 173 DQ33 174 DQ32

49 DQ17 50

53 DQS2_c 54 DM2_n, DBI2_n 179 DQS4_t 180 VSS

55 DQS2_t 56

59 DQ23 60 VSS 185 VSS 186 DQ35

61 VSS 62

65 VSS 66 DQ28 191 DQ44 192 VSS

67 DQ29 68

71 DQ25 72 VSS 197 VSS 198 DQS5_c

73 VSS 74

75 DM3_n, DBI3_n 76 DQS3_t 201

Front Side

Pin Label

VSS

DQS0_

VSS

DQ3

VSS

DQ21

VSS

DQ19

VSS

6 VSS 135

12 DM0_n, DBI0_n 141

16 DQ6

22 VSS 147 VDD 148 VDD

28 DQ8 153 VDD 154 VDD

40 VSS 165

46 DQ20 171

52 VSS 177

58 DQ22 183

64 VSS 189

70 DQ24 195

Back Side

Pin Label

DQ4

VSS

DQ2

VSS

DQS1_

DQ14

VSS

DQ16

VSS

DQ18

VSS

DQS3_c

133 A1 134

139 CK0_c 140

145 BA1 146 A10/AP

151 A14/WE_n 152 A16/RAS_n

157 CS1_n 158 A13

163 VDD 164

169 DQ37 170

175 VSS 176

181 VSS 182

187 DQ34 188

193 VSS 194

199 DM5_n, DBI5_n 200

Front Side

Pin Label

VDD

C1, CS3

_n, NC

VSS

DQS4_

DQ38

VSS

DQ40

VSS

136 VDD

142 VDD

KEY

166 SA2

172 VSS

178 DM4_n, DBI4_n

184 VSS

190 DQ45

196 VSS

202 VSS

Back Side

Pin Label

EVENT_

CK1_

VREFCA

DQ36

VSS

DQ39

VSS

DQ41

DQS5

Rev. 1.5 / Jun.2018 9

Page 10

77 VSS 78 VSS 203 DQ46 204 DQ47

79 DQ30 80

83 DQ26 84 DQ27 209 VSS 210 VSS

85 VSS 86

89 VSS 90 VSS 215 DQ49 216 DQ48

91 CB1, NC 92

95 DQS8_c 96 DM8_n, DBI8_n 221 DQS6_t 222 VSS

97 DQS8_t 98 VSS 223 VSS 224 DQ54

99 VSS 100 CB6, NC 225

101 CB2, NC 102 VSS 227 VSS 228 DQ50

103 VSS 104 CB7, NC 229 DQ51 230

105 CB3, NC 106 VSS 231

107 VSS 108 RESET_n 233 DQ61 234 VSS

109 CKE0 110 CKE1 235 VSS 236

111 VDD 112 VDD 237

113 BG1 114 ACT_n 239 VSS 240 DQS7_c

115 BG0 116 ALERT_n 241 DM7_n, DBI7_n 242 DQS7_t

117 VDD 118 VDD 243

119 A12 120 A11 245 DQ62 246 DQ63

121 A9 122 A7 247 VSS 248 VSS

123 VDD 124 VDD 249 DQ58 250 DQ59

125 A8 126 A5 251 VSS 252 VSS

127 A6 128 A4 253 SCL 254 SDA

129 VDD 130 VDD 255 VDDSPD 256 SA0

Front Side

Pin Label

VSS

CB5, NC

VSS

82 VSS 207

88 CB4, NC 213

94 VSS 219

Back Side

Pin Label

DQ31

VSS

CB0, NC

205 VSS 206

211 DQ52 212

217 VSS 218

257 VPP 258 VTT

259 VPP 260 SA1

Front Side

Pin Label

DQ42

VSS

DQS6_

DQ55

VSS

DQ56

VSS

208 DQ43

214 VSS

220 DM6_n, DBI6_n

226 VSS

232 DQ60

238 VSS

244

Back Side

Pin Label

VSS

DQ53

VSS

DQ57

VSS

Rev. 1.5 / Jun.2018 10

Page 11

Functional Block Diagram

VSS

CK0_t, CK0_c

A[16:0], BA[1:0]

CS0_n

ACT_n, PARITY,BG[0]

ODT0

CKE0

D0–D4

DDSPD

D0–D4

VREFCA

SPD

D0–D4

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. CK1_t, CK1_c terminated with 75

Ω±5% resistor.

CKE

ODT

CS_n

Address

DQS0_t

DQS0_c

DQ [7:0]

DQSL_t DQSL_c DQL[7:0]

DM1_n/DBI1_n DM_n/DBI_n

DM0_n/DBI0_n DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQSU_t DQSU_c DQU[7:0]

VSS

CKE

ODT

CS_n

Address

DQS2_t

DQS2_c

DQ [23:16]

DQSL_t DQSL_c DQL[7:0]

DM3_n/DBI3_n DM_n/DBI_n

DM2_n/DBI2_n DM_n/DBI_n

DQS3_t

DQS3_c

DQ [15:8]

DQSU_t DQSU_c DQU[7:0]

VSS

CKE

ODT

CS_n

Address

DQS4_t

DQS4_c

DQ [39:32]

DQSL_t DQSL_c DQL[7:0]

DM5_n/DBI5_n DM_n/DBI_n

DM4_n/DBI4_n DM_n/DBI_n

DQS5_t

DQS5_c

DQ [47:40]

DQSU_t DQSU_c DQU[7:0]

VSS

CKE

ODT

CS_n

Address

DQS6_t

DQS6_c

DQ [55:48]

DQSL_t DQSL_c DQL[7:0]

DM7_n/DBI7_n DM_n/DBI_n

DM6_n/DBI6_n DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQSU_t DQSU_c DQU[7:0]

Serial PD

SA0 SA1

SDA

SCL

SA2

4GB, 512Mx64 Module(1Rank of x16)

Rev. 1.5 / Jun.2018 11

Page 12

8GB, 1Gx64 Module(1Rank of x8)

DQS2_t

DQS2_c

DQ [23:16]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM2_n/DBI2_n DM_n/DBI_n

DQS0_t

DQS0_c

DQ [7:0]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Addressr

DM0_n/DBI0_n DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM1_n/DBI1_n DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM3_n/DBI3_n DM_n/DBI_n

CK0_t, CK0_c

A[16:0], BA[1:0]

CS0_n

ACT_n, PARITY,BG[1:0]

ODT0

CKE0

D0–D7

DDSPD

D0–D7

VREFCA

SPD

D0–D7

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. To connect the SPD A2 input to the edge connector pin 166 install R1. To tie the SPD input A2 to ground install R2. Do not install both R1 and R2. The values for R1 and R2 are not critical. Any value less than 100 Ohms may be used.

Serial PD

SA0 SA1

SDA

SCL

SA2 (pin 166)

EVENT_n

DQS4_t

DQS4_c

DQ [39:32]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM4_n/DBI4_n DM_n/DBI_n

DQS6_t

DQS6_c

DQ [55:48]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM6_n/DBI6_n DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Addressr

DM7_n/DBI7_n DM_n/DBI_n

DQS5_t

DQS5_c

DQ [47:40]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Addressr

DM5_n/DBI5_n DM_n/DBI_n

VSS

Rev. 1.5 / Jun.2018 12

Page 13

8GB, 1Gx72 Module(1Rank of x8)

DQS8_t DQS8_c CB[7:0]

DQS_t DQS_c DQ [7:0]

D0–D8

DDSPD

D0–D8

VREFCA

SPD

D0–D8

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

CKE

ODT

CS_n

VSS

CK1_t, CK1_c

A[16:0], BA[1:0]

CS0_n

A,BA,BG,Par

DM8_n/DBI8_n DM_n/DBI_n

DQS4_t DQS4_c

DQ [39:32]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM4_n/DBI4_n DM_n/DBI_n

DQS6_t DQS6_c

DQ [55:48]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM6_n/DBI6_n DM_n/DBI_n

DQS7_t DQS7_c

DQ [63:56]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM7_n/DBI7_n DM_n/DBI_n

ACT_n, PARITY,BG[1:0]

ODT0

CKE0

DQS2_t

DQS2_c

DQ [23:16]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM2_n/DBI2_n DM_n/DBI_n

DQS0_t

DQS0_c

DQ [7:0]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM0_n/DBI0_n DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM1_n/DBI1_n DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM3_n/DBI3_n DM_n/DBI_n

DQS5_t DQS5_c

DQ [47:40]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

DM5_n/DBI5_n DM_n/DBI_n

CK0_t, CK0_c

A[16:0], BA[1:0]

CS0_n

ACT_n, PARITY,BG[1:0]

ODT0

CKE0

Serial PD with Thermal sensor

SA0 SA1

SDA

SCL

EVENT_n/NC

pin 166

EVENT_n

VSS

Rev. 1.5 / Jun.2018 13

Page 14

16GB, 2Gx64 Module(2Rank of x8) - page1

DQS2_t DQS2_c

DQ [23:16]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM2_n/DBI2_n DM_n/DBI_n

DQS0_t DQS0_c

DQ [7:0]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Addressr

DM0_n/DBI0_n DM_n/DBI_n

DQS1_t DQS1_c

DQ [15:8]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM1_n/DBI1_n DM_n/DBI_n

DQS3_t DQS3_c

DQ [31:24]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM3_n/DBI3_n DM_n/DBI_n

CK0_t, CK0_c

A[16:0], BA[1:0]

CS0_n

ACT_n, PARITY,BG[1:0]

ODT0

CKE0

DQS_t DQS_c DQ [7:0]

D14

CKE

ODT

CS_n

VSS

Address

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D15

CKE

ODT

CS_n

VSS

Address

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D11

CKE

ODT

CS_n

VSS

Addressr

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D10

CKE

ODT

CS_n

VSS

Addressr

DM_n/DBI_n

CK1_t, CK1_c

A[16:0], BA[1:0]

CS1_n

ACT_n, PARITY,BG[1:0]

ODT1

CKE1

Rev. 1.5 / Jun.2018 14

Page 15

16GB, 2Gx64 Module(2Rank of x8) - page2

DQS4_t DQS4_c

DQ [39:32]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM4_n/DBI4_n DM_n/DBI_n

DQS6_t DQS6_c

DQ [55:48]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Addressr

DM6_n/DBI6_n DM_n/DBI_n

DQS7_t DQS7_c

DQ [63:56]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM7_n/DBI7_n DM_n/DBI_n

DQS5_t DQS5_c

DQ [47:40]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM5_n/DBI5_n DM_n/DBI_n

CK0_t, CK0_c

A[16:0], BA[1:0]

CS0_n

ACT_n, PARITY,BG[1:0]

ODT0

CKE0

D0–D15

DDSPD

D0–D15

VREFCA

SPD

D0–D15

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

3. SDRAMs for ODD ranks (D8 to D15), which are placed on the back side of the module use the address mirroing for A4-A3, A6-A5, A8-A7, A13-A11, BA1-BA0 and BG1-BG0. More detail can be found in the DDR4 SODIMM Common Section of the Design Specification.

Serial PD

SA0 SA1

SDA

SCL

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

Address

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D12

CKE

ODT

CS_n

VSS

Addressr

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D13

CKE

ODT

CS_n

VSS

Addressr

DM_n/DBI_n

CK1_t, CK1_c

A[16:0], BA[1:0]

CS1_n

ACT_n, PARITY,BG[1:0]

ODT1

CKE1

SA2

Rev. 1.5 / Jun.2018 15

Page 16

16GB, 2Gx72 Module(2Rank of x8)

DQS0_t

DQS0_c

DQ [7:0]

DQS_t DQS_c DQ [7:0]

D0–D17

DDSPD

D0–D17

VREFCA

SPD

D0–D17

Note:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. Unless otherwize noted, resistor values are 15

Ω±5%.

3. See the Net Structure diagrams for all resistors associated with the command, address and control bus.

4. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

CKE

ODT

CS_n

VSS

CK0_t, CK0_c

PARITY

CS0_n

A,BA,BGACT

PAR

DM0_n/DBI0_n DM_n/DBI_n

DQS1_t

DQS1_c

DQ [15:8]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM1_n/DBI1_n DM_n/DBI_n

DQS2_t

DQS2_c

DQ [23:16]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM2_n/DBI2_n DM_n/DBI_n

DQS3_t

DQS3_c

DQ [31:24]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM3_n/DBI3_n DM_n/DBI_n

A[16:0],BA[1:0],BG[1:0],ACT_n

ODT0

CKE0

DQS4_t

DQS4_c

DQ [39:32]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM4_n/DBI4_n DM_n/DBI_n

CK1_t, CK1_c

CS1_n

ODT1

CKE1

CK CK CK CK CK

Serial PD with Thermal sensor

SA0 SA1

SDA

SCL

EVENT_n

SA2

DQS5_t

DQS5_c

DQ [47:40]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM5_n/DBI5_n DM_n/DBI_n

DQS6_t

DQS6_c

DQ [55:48]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM6_n/DBI6_n DM_n/DBI_n

DQS7_t

DQS7_c

DQ [63:56]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM7_n/DBI7_n DM_n/DBI_n

DQS8_t

DQS8_c CB [7:0]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM8_n/DBI8_n DM_n/DBI_n

CK CK CK CK

DQS_t DQS_c DQ [7:0]

D10

CKE

ODT

CS_n

VSS

A,BA,BGACT

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D11

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D12

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D14

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

CK CK CK CK CK

DQS_t DQS_c DQ [7:0]

D17

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D15

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D16

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

DQS_t DQS_c DQ [7:0]

D13

CKE

ODT

CS_n

VSS

A,BA,BG,Par

PAR

DM_n/DBI_n

CK CK CK CK

EVENT_n

Rev. 1.5 / Jun.2018 16

Page 17

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD

VDDQ

VPP

IN, VOUT

STG

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times

5. Overshoot area above 1.5V is specified in DDR4 Device Operation.

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VPP pin relative to Vss

Voltage on any pin except VREFCA relative to Vss

Storage Temperature

-0.3 ~ 1.5 V 1,3

-0.3 ~ 3.0 V 4

-0.3 ~ 1.5 V 1,3,5

-55 to +100 °C 1,2

DRAM Component Operating Temperature Range

Temperature Range

Symbol Parameter Rating Units Notes

OPER

NOTE:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85 tions.

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

Normal Operating Temperature Range

Extended Temperature Range

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is

also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use

the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

0 to 85

85 to 95

C under all operating condi-

C 1,2

C1,3

C and 95oC

Rev. 1.5 / Jun.2018 17

Page 18

AC & DC Operating Conditions

Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Supply Voltage for DRAM Activating 2.375 2.5 2.75 V 3

NOTE:

Min. Typ. Max.

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. DC bandwidth is limited to 20MHz.

Rating

Unit NOTE

Rev. 1.5 / Jun.2018 18

Page 19

AC & DC Input Measurement Levels

AC & DC Logic input levels for single-ended signals

Single-ended AC & DC input levels for Command and Address

DDR4-1600/1866/2133/

Symbol Parameter

2400

Min. Max. Min. Max.

IH.CA

IL.CA

IH.CA

IL.CA

(DC75)

(AC100)

DC input logic

high

DC input logic low VSS

AC input logic

high

AC input logic low Note 2

REF

REFCA

0.075

+ 0.1

VDD

REFCA

0.075

Note 2

REF

- 0.1

Reference Volt-

REFCA

(DC)

age for ADD, CMD

0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V 2,3

inputs

NOTE :

1. See “Overshoot and Undershoot Specifications”

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

DDR4-2666/3200

REFCA

0.065

VSS

+ 0.09

REF

Note 2

Unit NOTE

VDD V

REFCA

0.065

Note 2 V 1

REF

- 0.09

Rev. 1.5 / Jun.2018 19

Page 20

AC and DC Input Measurement Levels: V

voltage

time

Tolerances

REF

The DC-tolerance limits and ac-noise limits for the reference voltages V It shows a valid reference voltage V

(DC) is the linear average of V

REF

meet the min/max requirement in Table X. Furthermore V no more than ± 1% V

(t) as a function of time. (V

REF

(t) over a very long period of time (e.g. 1 sec). This average has to

REF

(t) may temporarily deviate from V

is illustrated in Figure below.

REFCA

stands for V

REFCA

REF

(DC) by

Illustration of V

(DC) tolerance and V

REF

The voltage levels for setup and hold time measurements V dependent on V

" shall be understood as V

REF

This clarifies, that DC-variations of V

REF

(DC), as defined in Figure above.

REF

affect the absolute voltage a signal has to reach to achieve a valid

REF

(AC), VIH(DC), VIL(AC) and VIL(DC) are

AC-noise limits

REF

high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V

(DC) deviations from the optimum position within the data-eye of the

REF

input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

ified limit (+/-1% of V

AC-noise. Timing and voltage effects due to AC-noise on V

REF

) are included in DRAM timings and their associated deratings.

up to the spec-

REF

Rev. 1.5 / Jun.2018 20

Page 21

AC and DC Logic Input Levels for Differential Signals

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

(CK_t - CK_c)

Differential signal definition

NOTE:

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

Definition of differential ac-swing and “time above ac-level” t

DVAC

Rev. 1.5 / Jun.2018 21

Page 22

Differential swing requirements for clock (CK_t - CK_c)

Differential AC and DC Input Levels

DDR4 -

Symbol Parameter

ILdiff

differential

input high

differential

input low

IHdiff

NOTE :

1600,1866,21

min max min max min max min max min max

+0.150 NOTE 3 +0.135 NOTE 3 +0.135 NOTE 3 +0.125 NOTE 3 +0.110 NOTE 3 V 1

NOTE 3 -0.150 NOTE 3 -0.135 NOTE 3 -0.135 NOTE 3 -0.125 NOTE 3 -0.110 V 1

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V

IH.CA/VIL.CA

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

(DC) max, V

IH.CA

overshoot and undershoot.

Allowed time before ringback (tDVAC) for CK_t - CK_c

DDR4 -2400 DDR4 -2666 DDR4 -2933 DDR4 -3200

(AC) of ADD/CMD and V

(DC)min) for single-ended signals as well as the limitations for

IL.CA

REFCA

;

unitNO

Slew Rate [V/ns]

> 4.0 120 - TBD -

4.0 115 - TBD -

3.0 110 - TBD -

2.0 105 - TBD -

1.8 100 - TBD -

1.6 95 - TBD -

1.4 90 - TBD -

1.2 85 - TBD -

1.0 80 - TBD -

< 1.0 80 - TBD -

tDVAC [ps] @ |V

min max min max

(AC)| = 200mV tDVAC [ps] @ |V

IH/Ldiff

(AC)| = TBDmV

IH/Ldiff

Rev. 1.5 / Jun.2018 22

Page 23

Single-ended requirements for differential signals

VDD or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

VSS or V

SSQ

SEL

time

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c

Single-ended requirement for differential signals

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

Rev. 1.5 / Jun.2018 23

Page 24

Single-ended levels for CK_t, CK_c

Sym

Parameter

bol

Single-ended

high-level for

SEH

CK_t , CK_c

Single-ended

low-level for

SEL

CK_t , CK_c

NOTE :

1. For CK_t - CK_c use V

(AC)/VIL(AC) for ADD/CMD is based on V

2. V

DDR4-1600/

1866/2133

Min Max Min Max Min Max Min Max Min Max

(VDD/

NOTE3

+0.100

(VDD/

NOTE3

2)-

0.100

IH.CA/VIL.CA

DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

(VDD/

+0.095

NOTE3

(VDD/

0.095

2)-

(VDD/

+0.095

NOTE3

(VDD/

2)-

0.095

(VDD/

+0.085

NOTE3

(VDD/

2)-

0.085

(VDD/

+0.085

NOTE3

NOTE3 V 1, 2

(VDD/

(AC) of ADD/CMD;

;

REFCA

2)-

0.085

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V

(DC) max, V

IH.CA

(DC)min) for single-ended signals as well as the limitations for

IL.CA

overshoot and undershoot.

V1, 2

Rev. 1.5 / Jun.2018 24

Page 25

Address and Control Overshoot and Undershoot specifications

Overshoot Area Between

Undershoot Area below VSS

VDD Absolute Max

Volts

(V)

1 tCK

VDD Absolute Max and VDD Max

Overshoot Area above VDD Absolute Max

AC overshoot/undershoot specification for Address, Command and Control pins

Specification

Parameter

Maximum peak amplitude above VDD Absolute Max allowed for overshoot area

Delta value between VDD Absolute Max and VDD Max allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area per 1tCK Above Absolute Max

Maximum overshoot area per 1tCK Between Absolute Max

Maximum undershoot area per 1tCK Below VSS

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

DDR4-

1600

0.0083 0.0071 0.0062 0.0055 0.0055

0.2550 0.2185 0.1914 0.1699 0.1699

0.2644 0.2265 0.1984 0.1762 0.1762

DDR4-

1866

DDR4-

2133

0.06 0.06 V

VDD + 0.24 VDD + 0.24 V

0.30 0.30

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200

Uni

Vns

Address,Command and Control Overshoot and Undershoot Definition

Rev. 1.5 / Jun.2018 25

Page 26

Clock Overshoot and Undershoot Specifications

Overshoot Area Between

Undershoot Area below VSS

VDD Absolute Max

Volts

(V)

1 UI

VDD Absolute Max and VDD Max

Overshoot Area above VDD Absolute Max

AC overshoot/undershoot specification for Clock

Parameter

Maximum peak amplitude above VDD Absolute Max allowed for overshoot area

Delta value between VDD Absolute Max and VDD Max allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area per 1UI Above Absolute Max

Maximum overshoot area per 1UI Between Absolute Max

Maximum undershoot area per 1UI Below VSS

Specification

DDR4-

1600

0.0038 0.0032 0.0028 0.0025 0.0025

0.1125 0.0964 0.0844 0.0750 0.0750

0.1144 0.0980 0.0858 0.0762 0.0762

DDR4-

1866

(CK_t, Ck_c)

DDR4-

2133

0.06 0.06 V

VDD + 0.24 VDD + 0.24 V

0.30 0.30 V

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200

Uni

Vns

Clock Overshoot and Undershoot Definition

Rev. 1.5 / Jun.2018 26

Page 27

Data, Strobe and Mask Overshoot and Undershoot Specifications

Overshoot Area Between

VDDQ

Undershoot Area below Min absolute level of Vin, Vout

Max absolute level of Vin,Vout

VSSQ

Volts

(V)

1 UI

Max absolute level of Vin,Vout and VDDQ

Overshoot Area above Max absolute level of Vin,Vout

Undershoot Area Between Min absolute level of Vin,Vout and VSSQ

Min absolute level of Vin,Vout

AC overshoot/undershoot specification for Data, Strobe and Mask

Parameter

Maximum peak amplitude above Max absolute level of Vin,Vout

Overshoot area Between Max Absolute level of Vin, Vout and VDDQ Max

Undershoot area Between Min absolute level of Vin,Vout and VDDQ Max

Maximum peak amplitude below Min absolute level of Vin,Vout

Maximum overshoot area per 1UI Above Max absolute level of Vin,Vout

Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max

Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ

Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout

(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)

Specification

DDR4-

1600

0.16 0.16 0.16 0.16 0.16 V

0.30 0.30 0.30 0.30 0.30 V

0.10 0.10 0.10 0.10 0.10 V

0.0150 0.0129 0.0113 0.0100 0.0100

0.1050 0.0900 0.0788 0.0700 0.0700

0.0150 0.0129 0.0113 0.0100 0.0100

DDR4-

1866

VDDQ + 0.24 VDDQ+0.24 V

DDR4-

2133

DDR4-

2400

DDR4-

2666

DDR4-

2933

DDR4-

3200

Uni

Vns

Rev. 1.5 / Jun.2018 27

Data, Strobe and Mask Overshoot and Undershoot Definition

Page 28

Slew Rate Definitions

Delta TRdiff

Delta TFdiff

IHdiffmin

ILdiffmax

Differential Input Voltage(i,e, CK_t - CK_c)

Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Figure below.

Differential Input Slew Rate Definition

Description Defined by

Differential input slew rate for rising edge(CK_t -

CK_c)

Differential input slew rate for falling edge(CK_t -

CK_c)

NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

from to

ILdiffmaxVIHdiffmin

IHdiffminVILdiffmax

[

IHdiffmin - VILdiffmax

[

IHdiffmin - VILdiffmax

] / DeltaTR-

diff

] / DeltaTF-

diff

Differential Input Slew Rate Definition for CK_t, CK_c

Rev. 1.5 / Jun.2018 28

Page 29

Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

Delta TRsingle

Delta TFsingle

IHCA(AC) Min

IHCA(DC) Min

VREFCA(DC)

ILCA(DC) Max

ILCA(AC) Max

Single-ended Input Slew Rate definition for CMD and ADD

NOTE :

1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single

2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single

3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope

Rev. 1.5 / Jun.2018 29

Page 30

Differential Input Cross Point Voltage

Vix

CK_t

VDD/2

VSS

VDD

CK_c

Vix

VSEL

VSEH

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

Vix Definition (CK)

Cross point voltage for differential input signals (CK)

Symbol Parameter

- Area of VSEH, VSEL

VSEL =<

VDD/2 - 145mV

min max

Differential Input Cross

VlX(CK)

Point Voltage relative to

-120mV

VDD/2 for CK_t, CK_c

Rev. 1.5 / Jun.2018 30

DDR4-1600/1866/2133

VDD/2 -

145mV =<

VSEL =< VDD/

2 - 100mV

- (VDD/2 -

VSEL) + 25mV

VDD/2 + 100mV

=< VSEH =<

VDD/2 + 145mV

(VSEH - VDD/2)

- 25mV

VDD/2 +

145mV =<

VSEH

120mV

Page 31

Symbol Parameter

- Area of VSEH, VSEL

Differential Input Cross

VlX(CK)

Point Voltage relative to

VDD/2 for CK_t, CK_c

VSEL =<

VDD/2 - 145mV

-120mV

DDR4-2400/2666/3200

min max

VDD/2 -

145mV =<

VSEL =< VDD/

2 - 100mV

- (VDD/2 -

VSEL) + 25mV

VDD/2 + 100mV

=< VSEH =<

VDD/2 + 145mV

(VSEH - VDD/2)

- 25mV

VDD/2 +

145mV =<

VSEH

120mV

Rev. 1.5 / Jun.2018 31

Page 32

CMOS rail to rail Input Levels

0.8*VDD

TR_RESET

tPW_RESET

0.7*VDD

0.3*VDD

0.2*VDD

CMOS rail to rail Input Levels for RESET_n

Parameter Symbol Min Max Unit NOTE

AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6

DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2

DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD

AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD

Rising time TR_RESET - 1.0 us 4

RESET pulse width tPW_RESET 1.0 - us 3,5

NOTE :

1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,

otherwise, SDRAM may not be reset.

2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM

operation will not be guaranteed until it is reset asserting RESET_n signal LOW.

3. RESET is destructive to data contents.

4. No slope reversal(ringback) requirement during its level transition from Low to High.

5. This definition is applied only “Reset Procedure at Power Stable”.

6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.

7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings

V 1

V 7

RESET_n Input Slew Rate Definition

Rev. 1.5 / Jun.2018 32

Page 33

AC and DC Logic Input Levels for DQS Signals Differential signal definition

Definition of differential DQS Signal AC-swing Level

Differential swing requirements for DQS (DQS_t - DQS_c)

Differential AC and DC Input Levels for DQS

Symbol Parameter

VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 160 Note2 140 Note2 mV 1

VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 Note2 -160 Note2 -140 mV 1

NOTE :

1. Used to define a differential signal slew-rate.

2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended signals.

Rev. 1.5 / Jun.2018 33

DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200

Min Max Min Max Min Max

Unit Note

Page 34

Peak voltage calculation method

The peak voltage of Differential DQS signals are calculated in a following equation.

VIH.DIFF.Peak Voltage = Max(f(t)) VIL.DIFF.Peak Voltage = Min(f(t)) f(t) = VDQS_t - VDQS_c

The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.

Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling

Rev. 1.5 / Jun.2018 34

Page 35

Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.

VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.

A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ringback’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.

Vix Definition (DQS)

Rev. 1.5 / Jun.2018 35

Page 36

Cross point voltage for differential input signals

DDR4-

Symbol Parameter

Vix_DOS_ ratio

VDQSmid_to_ Vcent

NOTE :

1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the

difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest

horizontal tangent below VDQSmid of the transitioning DQS signals.

2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs

drivers and paths are matched.

3. Teh maximum limite shall not exceed the smaller of VIHdiff minimum limit or 50mV.

4. VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and

high-z states are not applicable conditions.

5. The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a

system.

DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings

VDQSmid offset relative to Vcent_DQ(midpoint)

1600,1866,2133,2400

Min Max Min Max

-25-25%1,2

min(VIH-

diff, 50)

DDR4-

2666,2933,3200

min(VIH-

diff, 50)

Unit Note

mV 3,4,5



Rev. 1.5 / Jun.2018 36

Page 37

Differential Input Slew Rate Definition

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure below.

NOTE :

1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.

2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.

Differential Input Slew Rate Definition for DQS_t, DQS_c

Description Defined by

Differential input slew rate for rising edge(DQS_t - DQS_c)

Differential input slew rate for falling edge(DQS_t - DQS_c)

Rev. 1.5 / Jun.2018 37

From To

VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff

VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff

Page 38

Symbol Parameter

VIHDiff_DQS

VILDiff_DQS

Differential Input High

Differential Input Low

Differential Input Level for DQS_t, DQS_c

DDR4-

1600,1866,

2133

Min Max Min Max Min Max Min Max Min Max

136 - 130 - 130 - 115 - 110 -

- -136 - -130 - -130 - -115 - -110

DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Differential Input Slew Rate for DQS_t, DQS_c

Symbol Parameter

Differential

SRIdiff

Input Slew Rate

DDR4-

1600,1866,21

Min Max Min Max Min Max Min Max Min Max

3 18 3 18 2.5 18 2.5 18 2.5 18

DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

V/ ns

Rev. 1.5 / Jun.2018 38

Page 39

AC and DC output Measurement levels

Single-ended AC & DC Output Levels

Single-ended AC & DC output levels

Symbol Parameter

(DC) DC output high measurement level (for IV curve linearity) 1.1 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.8 x V

(DC) DC output low measurement level (for IV curve linearity) 0.5 x V

(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x V

(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x V

DDR4-1600/1866/2133/

2400/2666/3200

DDQ

NOTE :

1. The swing of ± 0.15 × V

is based on approximately 50% of the static single-ended output peak-to-

DDQ

peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to V

Differential AC & DC Output Levels

Differential AC & DC output levels

Symbol Parameter

(AC) AC differential output high measurement level (for output SR) +0.3 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.3 x V

OLdiff

NOTE :

1. The swing of ± 0.3 × V

a driver impedance of RZQ/7Ω and an effective test load of 50Ω to V

is based on approximately 50% of the static differential output peak-to-peak swing with

DDQ

DDR4-1600/1866/

2133/2400/2666/3200

= V

at each of the differential outputs.

DDQ

= V

Units NOTE

DDQ

Units NOTE

Rev. 1.5 / Jun.2018 39

Page 40

Single-ended Output Slew Rate

OH(AC)

OL(AC)

delta TRsedelta TFse

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

OL(AC)

and V

for single ended signals as shown in Table and Figure below.

OH(AC)

Single-ended output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

Measured

From To

(AC) VOH(AC)

(AC) VOL(AC)

Defined by

(AC)-VOL(AC)] /

Delta TRse

(AC)-VOL(AC)] /

Delta TFse

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Single-ended Output Slew Rate Definition

Single-ended output slew rate

Parameter Symbol

Single ended output slew rate SRQse49494949494949V/ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Units

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting

NOTE:

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies

Rev. 1.5 / Jun.2018 40

Page 41

Differential Output Slew Rate

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure below.

Differential output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OLdiff

(AC)

OHdiff

Defined by

(AC)-V

OLdiff

Delta TRdiff

(AC)-V

OLdiff

Delta TFdiff

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Differential Output Slew Rate Definition

Differential output slew rate

(AC)] /

Parameter Symbol

Differential output slew rate SRQdiff818818818818818818818V/ns

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max Min Max

Units

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting

Rev. 1.5 / Jun.2018 41

Page 42

Single-ended AC & DC Output Levels of Connectivity Test Mode

VOH(AC)

TR_output_CT

VTT 0.5 * VDDQ

VOL(AC)

TF_output_CT

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.

Single-ended AC & DC output levels of Connectivity Test Mode

Symbol Parameter

(DC) DC output high measurement level (for IV curve linearity) 1.1 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.8 x V

(DC) DC output low measurement level (for IV curve linearity) 0.5 x V

(DC) DC output below measurement level (for IV curve linearity) 0.2 x V

(AC) AC output high measurement level (for output SR) VTT + (0.1 x V

(AC) AC output below measurement level (for output SR) VTT - (0.1 x V

DDR4-1600/1866/2133/

2400/2666/3200

NOTE :

1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.

Differential Output Slew Rate Definition of Connectivity Test Mode

Unit Note

DDQ

)V1

DDQ

)V1

DDQ

Single-ended output slew rate of Connectivity Test Mode

Parameter Symbol

Output signal Falling time TF_output_CT - 10 ns/V

Output signal Rising time TR_output_CT - 10 ns/V

Rev. 1.5 / Jun.2018 42

DDR4-1600/1866/2133/2400/2666/3200

Min Max

Unit Note

Page 43

Standard Speed Bins

DDR4-1600 Speed Bins and Operations

Speed Bin DDR4-1600K

Unit NOTECL-nRCD-nRP 11-11-11

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write

delay time

tAA

tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 12

tRCD

PRE command period tRP

ACT to PRE command period tRAS 35 9 x tREFI ns 12

ACT to ACT or REF command

period

tRC

Normal Read DBI

CL = 11

CWL = 9

CL = 9

(Optional)

tCK(AVG) 1.5 1.6 ns

CL = 10 CL = 12 tCK(AVG) Reserved ns

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

CWL =

9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3

Supported CL Settings (9),11,12 nCK 13,14

Supported CL Settings with read DBI (11),13,14 nCK 13

Supported CWL Settings 9,11 nCK

13.75

(13.50)

13.75

(13.50)

13.75

(13.50)

48.75

(48.50)

5,12

18.00 ns 12

- ns 12

1,2,3,4,

11, 14

1,2,3,4,

Rev. 1.5 / Jun.2018 43

Page 44

DDR4-1866 Speed Bins and Operations

Speed Bin DDR4-1866M

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write

delay time

PRE command period tRP

ACT to PRE command period tRAS

ACT to ACT or REF command

period

Normal Read DBI

CL = 9

CWL = 9

CL = 11

(Optional)

CL = 10 CL = 12 tCK(AVG)

CWL =

9,11

CL = 11 CL = 13 tCK(AVG)

CL = 12 CL = 14 tCK(AVG)

CWL =

10,12

CL = 13 CL = 15 tCK(AVG)

CL = 14 CL = 16 tCK(AVG)

Supported CL Settings

Supported CL Settings with read DBI

Supported CWL Settings

tAA

tAA_DBI

tRCD

tRC

tCK(AVG)

Unit NOTECL-nRCD-nRP 13-13-13

13.92

5,12

(13.50)

tAA(min) + 2nCK tAA(max) +2nCK ns

13.92

5,12

(13.50)

13.92

5,12

(13.50)

34 9 x tREFI ns

47.92

5,12

(47.50)

1.5

Reserved ns

1.25 <1.5 ns

Reserved ns

1.071 <1.25 ns

9,11,12,13,14 nCK

11,13,14 15,16 nCK

9,10,11,12 nCK

18.00 ns

- ns

1.6

1,2,3,4,

11, 14

1,2,3,4,

1,2,3,6

1,2,3,4

1,2,3

13,14

Rev. 1.5 / Jun.2018 44

Page 45

DDR4-2133 Speed Bins and Operations

Speed Bin DDR4-2133P

Unit NOTECL-nRCD-nRP 15-15-15

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write delay

time

tAA

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12

tRCD

PRE command period tRP

ACT to PRE command period tRAS 33 9 x tREFI ns 12

ACT to ACT or REF command

period

tRC

Normal Read DBI

CWL = 9

CWL = 9,11

CWL =

10,12

CWL =

11, 14

CL = 9 CL = 11

CL = 10 CL = 12

CL = 11 CL = 13

CL = 12 CL = 14

CL = 13 CL = 15

CL = 14 CL = 16

CL = 14 CL = 17

CL = 15 CL = 18

CL = 16 CL = 19

tCK(AVG) 1.5 1.6 ns

tCK(AVG) Reserved ns 1,2,3,11

tCK(AVG) 1.25 <1.5 ns

tCK(AVG) 1.25 <1.5 ns 1,2,3,7

tCK(AVG) 1.071 <1.25 ns

tCK(AVG) 1.071 <1.25 ns 1,2,3,7

tCK(AVG) Reserved ns 1,2,3,4

tCK(AVG) 0.937 <1.071 ns 1,2,3,4

tCK(AVG) 0.937 <1.071 ns 1,2,3

Supported CL Settings (9),(11),12,(13),14,15,16 nCK 13,14

Supported CL Settings with read DBI (11),(13),14,(15),16,18,19 nCK

Supported CWL Settings 9,10,11,12,14 ns 12

14.06

(13.50)

14.06

(13.50)

14.06

(13.50)

47.06

(46.50)

5,12

18.00 ns 12

- ns 12

1,2,3,4,

11, 14

1,2,3,4,

Rev. 1.5 / Jun.2018 45

Page 46

DDR4-2400 Speed Bins and Operations

Speed Bin DDR4-2400T

Unit NOTECL-nRCD-nRP 17-17-17

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write

delay time

tAA

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12

tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 12

ACT to ACT or REF command

period

tRC

Normal Read DBI

CL = 11

(Optional)

tCK(AVG)

tCK(AVG) Reserved ns 4

tCK(AVG) 1.25 <1.5 ns 1,2,3,4,8

tCK(AVG) 1.25 <1.5 ns 1,2,3,8

tCK(AVG) Reserved ns 4

tCK(AVG) 1.071 <1.25 ns 1,2,3,4,8

tCK(AVG) 1.071 <1.25 ns 1,2,3,8

tCK(AVG) Reserved ns 4

tCK(AVG) 0.937 <1.071 ns 1,2,3,4,8

tCK(AVG) 0.937 <1.071 ns 1,2,3,8

tCK(AVG) Reserved ns 1,2,3,4

tCK(AVG) 0.833 <0.937

tCK(AVG) 0.833 <0.937 ns 1,2,3

CWL = 9

CWL = 9,11

CWL =

10,12

CWL =

11, 14

CWL =

12,16

CL = 9

CL = 10 CL = 12

CL = 11 CL = 13

CL = 12 CL = 14

CL = 13 CL = 15

CL = 14 CL = 16

CL = 14 CL = 17

CL = 15 CL = 18

CL = 16 CL = 19

CL = 15 CL = 18

CL = 16 CL = 19

CL = 17 CL = 20

CL = 18 CL = 21

Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 13

Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK

Supported CWL Settings 9,10,11,12,14,16 nCK

14.16

(13.75)

14.16

(13.75)

14.16

(13.75)

46.16

(45.75)

5,12

Reserved ns

18.00 ns 12

- ns 12

-ns 12

1,2,3,4,11

1.5 1.6 ns 1,2,3,4,11

Rev. 1.5 / Jun.2018 46

Page 47

DDR4-2666 Speed Bins and Operations

Speed Bin DDR4-2666V

Unit NOTECL-nRCD-nRP 19-19-19

Parameter Symbol min max

Internal read command to

first data

tAA

Internal read command to

first data with read DBI

tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 12

enabled

ACT to internal read or write

delay time

PRE command period

ACT to PRE command

period

ACT to ACT or REF com-

mand period

tRCD

tRP

tRAS 32 9 x tREFI ns 12

tRC

Normal Read DBI

CWL = 9 CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,11

CWL =

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,9

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

CWL =

10,12

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,9

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9

CWL =

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

11, 14

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,9

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9

CWL =

12.16

CL = 15 CL = 18 tCK(AVG) Reserved ns 4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,9

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,9

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

CWL =

14,18

CL = 17 CL = 20 tCK(AVG) Reserved ns 1,2,3,4

CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3

Supported CL Settings 10,(11),12,(13),14,(15),16,(17),18,19,20 nCK 13

Supported CL Settings with read DBI 12,(13),14,(15),17,(18),19,(20),21,22,23 nCK

Supported CWL Settings 9,10,11,12,14,16,18 nCK

14.25

(13.75)

14.25

(13.75)

14.25

(13.75)

46.25

(45.75)

5,12

18.00 ns 12

-ns 12

Rev. 1.5 / Jun.2018 47

Page 48

DDR4-2933 Speed Bins and Operations

Speed Bin DDR4-2933Y

Parameter Symbol min max

Internal read command to

first data

tAA

14.32

(13.75)

5,12

Internal read command to

first data with read DBI

tAA_DBI tAA(min) + 4nCK tAA(max) + 4nCK ns 12

enabled

ACT to internal read or write

delay time

PRE command period tRP

ACT to PRE command

period

ACT to ACT or REF com-

mand period

Read

DBI

CWL =

9,11

Normal

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,11

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,13

tRCD

tRAS 32 9 x tREFI ns 12

tRC

14.32

(13.75)

14.32

(13.75)

46.32

(45.75)

5,12

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,15

CWL =

10,12

CL = 12 CL = 14 tCK(AVG) Reserved ns 1,2,3,4

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,15

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,15

CWL =

11, 14

CL = 14 CL = 17 tCK(AVG) Reserved ns 1,2,3,4

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,15

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,15

CWL =

12.16

CL = 15 CL = 18 tCK(AVG) Reserved ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,15

CL = 17 CL = 20 tCK(AVG) 0.833 0.937 ns 1,2,3,4,15

CL = 18 CL = 21 tCK(AVG) 0.833 0.937 ns 1,2,3,15

CWL =

14,18

CL = 17 CL = 20 tCK(AVG) Reserved ns 1,2,3,4

CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4,15

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4,15

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3,15

CWL =

16,20

CL = 19 CL = 23 tCK(AVG) Reserved ns 1,2,3,4

CL = 20 CL = 24 tCK(AVG) Reserved ns 1,2,3,4

CL = 21 CL = 26 tCK(AVG) 0.682 <0.75 ns 1,2,3,4

CL = 22 CL = 26 tCK(AVG) 0.682 <0.75 ns 1,2,3

Supported CL Settings 10,(11),12,(13),14,(15),16,(17),18,(19),20,

21,22

Supported CL Settings with read DBI 12,(13),14,(15),16,(18),19,(20),21,(22),23,

25,26

Supported CWL Settings 9,10,11,12,14,15,16,18,20 nCK

18.00 ns 12

-ns 12

Unit NOTECL-nRCD-nRP 21-21-21

nCK 13



Rev. 1.5 / Jun.2018 48

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DDR4-3200 Speed Bins and Operations

Speed Bin DDR4-3200AA

Unit NOTECL-nRCD-nRP 22-22-22

Parameter Symbol min max

Internal read command to

first data

Internal read command to

first data with read DBI

enabled

ACT to internal read or

write delay time

PRE command period tRP 13.75 - ns 12

ACT to PRE command

period

ACT to ACT or REF com-

mand period

Normal

CWL =

10,12

CWL =

11, 14

CWL =

12.16

CWL =

14,18

CWL =

16,20

Supported CL Settings with read DBI 12,13,14,15,16,18, 19,20,21,22,23,24,

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,11

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,11

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,10

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,10

CL = 12 CL = 14 tCK(AVG) Reserved ns 1,2,3,4

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,10

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,10

CL = 14 CL = 17 tCK(AVG) Reserved ns 1,2,3,4

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,10

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,10

CL = 15 CL = 18 tCK(AVG) Reserved ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,10

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3,10

CL = 17 CL = 20 tCK(AVG) Reserved ns 1,2,3,4

CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4,10

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3,10

CL = 20 CL = 24 tCK(AVG) Reserved ns 1,2,3,4

CL = 22 CL = 26 tCK(AVG) 0.625 <0.75 ns 1,2,3,4

CL = 24 CL = 28 tCK(AVG) 0.625 <0.75 ns 1,2,3

Supported CL Settings 10,11,12,13,14,15, 16,17,18,19,20,22,

Supported CWL Settings 9,10,11,12,14,16,

Read

DBI

tAA 13.75 18.00 ns 12

tAA_DBI

tRCD 13.75 - ns 12

tRAS 32 9 x tREFI ns 12

tRC 45.75 - ns 12

tAA(min)

+ 4nCK

26, 28

18,20

tAA(max) + 4nCK ns 12

nCK 13

nCK

 

Rev. 1.5 / Jun.2018 49

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Speed Bin Table Note

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133, 2400, 2933 and 3200 Speed Bin Tables are valid only when Geardown Mode is

disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL

- all possible intermediate frequencies may not be guaranteed. CL in clock cycle is calculated from tAA following rounding algorithm defined in

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.937 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

10. Any DDR4-3200 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

11. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

12. DDR4-2400,2666,2933 and 3200Mbps speed bin support CL=10 if DRAM operate at 1333MT/s data rate.

13. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

14. CL number in parentheses, it means that these numbers are optional.

15. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

16. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

Section 13.5.

Rev. 1.5 / Jun.2018 50

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IDD and IDDQ Specification Parameters and Test Conditions

IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure shows the setup and test load for IDD, IPP and IDDQ measurements.

• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur rents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

• “0” and “LOW” is defined as VIN <= VILAC(max).

• “1” and “HIGH” is defined as VIN >= VIHAC(min).

• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.

• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.

• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.

• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.

• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting  RON = RZQ/7 (34 Ohm in MR1);  RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; Qoff = 0B (Output Buffer enabled) in MR1;

TDQS_t disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR5;

Gear down mode disabled in MR3 Read/Write DBI disabled in MR5; DM disabled in MR5

• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed.

• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply invert of BG/BA changes when directed above.

Rev. 1.5 / Jun.2018 51

Page 52

NOTE:

RESET CK_t/CK_c

CKE CS

ACT,RAS,CAS,WE

A,BG,BA

ODT

DQS_t/DQS_c

DDR4 SDRAM

SSQ

DDQ

Application specific

memory channel

environment

Channel

IO Powe

Simulatin

Channel IO Power

Number

IDDQ

TestLad

IDDQ

Simuaion

IDDQ

Measurement

Correlation

1. DIMM level Output test load condition may be different from above

Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ

Measurement

Rev. 1.5 / Jun.2018 52

Page 53

Table 1-Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns

Symbol

tCK 1.25

CL 11 13 15 17 19 21 22 nCK

CWL 11 12 14 16 18 20 20 nCK

nRCD 11 13 15 17 19 21 22 nCK

nRC 39 45 51 56 62 68 74 nCK

nRAS 28 32 36 39 43 47 52 nCK

nRP 11 13 15 17 19 21 22 nCK

nFAW

nRRDS

nRRDL

tCCD_S 4 4 4 4 4 4 4 nCK

tCCD_L5566788nCK

tWTR_S 2 3 3 3 4 4 4 nCK

tWTR_L 6 7 8 9 10 11 12 nCK

nRFC 2Gb 128 150 171 193 214 235 256 nCK

nRFC 4Gb 208 243 278 313 347 382 416 nCK

nRFC 8Gb 280 327 374 421 467 514 560 nCK

nRFC 16Gb 440 514 587 661 734 807 880 nCK

TBD nCK

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200

11-11- 11 13-13-13 15-15-15 17-17-17 19-19-19 21-21-21 22-22-22

1.071 0.937 0.833 0.75 0.682 0.625 ns

x4 16 16 16 16 16 16 16 nCK

x8 20 22 23 26 28 31 34 nCK

x16 28 28 32 36 40 44 48 nCK

x4 4 4 4 4 4 4 4 nCK

x8 4 4 4 4 4 4 4 nCK

x165567889nCK

x4 5 5 6 6 7 8 8 nCK

x8 5 5 6 6 7 8 8 nCK

x16 6 6 7 8 9 10 11 nCK

Unit

Rev. 1.5 / Jun.2018 53

Page 54

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

Operating One Bank Active-Precharge Current (AL=0)

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High

IDD0

IDD0A

IPP0

IDD1

IDD1A

IPP1

IDD2N

IDD2NA

IPP2N

IDD2NT

IDDQ2NT

(Optional)

IDD2NL

IDD2NG

IDD2ND

between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Regis-

; ODT Signal: stable at 0; Pattern Details: see Table 3

ters

Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0

Operating One Bank Active-Precharge IPP Current Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0) CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8

between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 4

Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1

Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1

Precharge Standby Current (AL=0) CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 5

Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N

Precharge Standby IPP Current Same condition with IDD2N

Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

Same definition like for IDD2N, CAL enabled

Precharge Standby Current with Gear Down mode enabled

Same definition like for IDD2N, Gear Down mode enabled

3,5

Precharge Standby Current with DLL disabled

Same definition like for IDD2N, DLL disabled

; AL: 0; CS_n: High

Rev. 1.5 / Jun.2018 54

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IDD2N_par

IDD2P

IPP2P

IDD2Q

IDD3N

IDD3NA

IPP3N

IDD3P

IPP3P

IDD4R

IDD4RA

IDD4RB

IPP4R

IDDQ4R

(Optional)

IDDQ4RB

(Optional)

Precharge Standby Current with CA parity enabled

Same definition like for IDD2N, CA parity enabled

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:

Enabled in Mode Registers

; ODT Signal: stable at 0

Precharge Power-Down IPP Current Same condition with IDD2P

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; AL: 0; CS_n: stable at 1; Command,

; ODT

Signal: stable at 0

Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 5

Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N

Active Standby IPP Current Same condition with IDD3N

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0

Active Power-Down IPP Current Same condition with IDD3P

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal:

stable at 0; Pattern Details: see Table 7

Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R

Operating Burst Read Current with Read DBI Read DBI enabled

, Other conditions: see IDD4R

Operating Burst Read IPP Current Same condition with IDD4R

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Rev. 1.5 / Jun.2018 55

Page 56

IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4W_par

IPP4W

IDD5B

IPP5B

IDD5F2

IPP5F2

IDD5F4

IPP5F4

IDD6N

IPP6N

IDD6E

IPP6E

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8

; AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless write data burst with different data between one burst and the next one according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal:

stable at HIGH; Pattern Details: see Table 8

Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W

Operating Burst Write Current with Write DBI Write DBI enabled

Operating Burst Write Current with Write CRC Write CRC enabled

Operating Burst Write Current with CA Parity CA Parity enabled

, Other conditions: see IDD4W

Operating Burst Write IPP Current Same condition with IDD4W

Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8

; AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9); Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see

Table 9

Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B

Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2

Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4

Self Refresh Current: Normal Temperature Range

: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:

CASE

Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N

Self-Refresh Current: Extended Temperature Range

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:

CASE

Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 8

; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

)

; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E

Rev. 1.5 / Jun.2018 56

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IDD6R

IPP6R

IDD6A

IPP6A

IDD7

IPP7

IDD8

IPP8

Self-Refresh Current: Reduced Temperature Range

: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;

CASE

External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 8

; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2;

ODT Signal: MID-LEVEL

Self Refresh IPP Current: Reduced Temperature Range Same condition with IDD6R

Auto Self-Refresh Current

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External clock: Off;

CASE

CK_t and CK_c#: LOW; CL: see Table 1; BL: 8 Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh

operation; Output Buffer and RTT: Enabled in Mode Registers

; AL: 0; CS_n#, Command, Address, Bank Group

; ODT Signal: MID-LEVEL

Auto Self-Refresh IPP Current Same condition with IDD6A

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 8

; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 10

Operating Bank Interleave Read IPP Current Same condition with IDD7

Maximum Power Down Current TBD

Maximum Power Down IPP Current Same condition with IDD8

Rev. 1.5 / Jun.2018 57

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NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7 RTT_Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6 RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2 RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s 010] : 1866MT/s, 2133MT/s 011] : 2400MT/s Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate DLL disabled : set MR1 [A0 = 0] CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s 010] : 2400MT/s Read DBI enabled : set MR5 [A12 = 1] Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal 01] : Reduced Temperature range 10] : Extended Temperature range 11] : Auto Self Refresh

5. IDD2NG should be measured after sync pulse(NOP) input.

Rev. 1.5 / Jun.2018 58

Page 59

Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern

CKE

Sub-Loop

CK_t /CK_c

Cycle

Number

Command

00 ACT 000000000000000 -

1,2 D, D 100000000000000 -

3,4

D_#,

D_#

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 010100000000000 -

... repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC

2*nRC

3*nRC

4*nRC

5*nRC

toggling

6*nRC

7*nRC

8*nRC

9*nRC

10*nRC

11*nRC

12*nRC

13*nRC

14*nRC

15*nRC

Static High

NOTE:

1 .DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

repeat Sub-Loop 0, use BG[1:0]

CS_n

ACT_n

CAS_n/ A15

RAS_n/ A16

1111100

ODT

WE_n/ A14

C[2:0]

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

BA[1:0]

BG[1:0]

30007F0 -

A12/BC_n

Data

A[9:7]

A[6:3]

A[2:0]

A[17,13,11]

A[10]/AP

For x4 and x8

only

Rev. 1.5 / Jun.2018 59

Page 60

A[17,13,11]

A[9:7]

A[10]/AP

A[6:3]

A[2:0]

Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

0 0 WR 011001000000000D0=00, D1=FF

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

1 D 100001000000000-

2,3 D#, D# 1111110

30007F 0 -

1 4 WR 0110010110007 F0 D0=FF, D1=00

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

5 D 100001000000000-

30007F 0 -

For x4 and x8 only

toggling

6,7 D#, D# 1111110

28-11

3 12-15

4 16-19

5 20-23

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

Static High

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

NOTE:

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

Data

Rev. 1.5 / Jun.2018 60

Page 61

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P

Measurement-Loop Pattern1

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

00 D, D 1000000000000000

1 D, D 1000000000000000

2D#,

3D#,

14-7

28-11

312-15

416-19

520-23

toggling

624-27

Static High

728-31

832-35

936-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]

CS_n

Command

ACT_n

CAS_n/A15

RAS_n/A16

1111100

ODT

WE_n/A14

C[2:0]

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 1 instead

= 0, BA[1:0] = 3 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 0 instead

BA[1:0]

BG[1:0]

3 0007F00

A[9:7]

A12/BC_n

A[10]/AP

A[17,13,11]

A[6:3]

Data

A[2:0]

Rev. 1.5 / Jun.2018 61

Page 62

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

00 D, D 100000000000000-

1 D, D 1000 00000000000-

2 D#, D# 1111100

3 D#, D# 1111100

14-7

28-11

3 12-15

4 16-19

5 20-23

6 24-27

toggling

7 28-31

Static High

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

BA[1:0]

BG[1:0]

3 0007F0-

= 1, BA[1:0] = 1 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 3 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 0 instead

Data

A[9:7]

A[6:3]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

For x4

and x8

only

Rev. 1.5 / Jun.2018 62

Page 63

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

00 RD 011010000000000 D0=00, D1=FF

1 D 100000000000000-

2,3 D#, D# 1111100

14 RD 0110100110007F0 D0=FF, D1=00

5 D 100000000000000-

6,7 D#, D# 1111100

28-11

312-15

416-19

toggling

Static High

520-23

624-27

728-31

832-35

936-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Read Command.

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 2 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 2, BA[1:0] = 3 instead

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

3 0007F0-

A[10]/AP

A[17,13,11]

A[2:0]

Data

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

For x4 and x8 only

Rev. 1.5 / Jun.2018 63

Page 64

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

ODT

WE_n/A14

C[2:0]

00 WR 011011000000000 D0=00, D1=FF

1 D 100001000000000-

2,3 D#, D# 1111110

14 WR 0110110110007F0 D0=FF, D1=00

5 D 100001000000000-

6,7 D#, D# 1111110

28-11

312-15

416-19

toggling

Static High

520-23

624-27

728-31

832-35

936-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 2 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 2, BA[1:0] = 3 instead

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

3 0007F0-

Data

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

For x4 and x8 only

Rev. 1.5 / Jun.2018 64

Page 65

Table 9 - IDD4WC Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

00 WR 011011000000000 D0=00, D1=FF

1,2 D, D 100001000000000-

3,4 D#, D#1111110

5 WR 0110110110007F0 D0=FF, D1=00

6,7 D, D 100001000000000-

8,9 D#, D#1111110

2 10-14

3 15-19

toggling

4 20-24

Static High

5 25-29

6 30-34

7 35-39

8 40-44

9 45-49

10 50-54

11 55-59

12 60-64

13 65-69

14 70-74

15 75-79

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat Sub-Loop 0, use BG[1:0]

repeat Sub-Loop 1, use BG[1:0]

ODT

WE_n/A14

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 0, BA[1:0] = 3 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 1 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

A[9:7]

A[6:3]

C[2:0]

BG[1:0]

BA[1:0]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D8=CRC

3 0007F0-

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

D8=CRC

3 0007F0-

For x4 and x8 only

Data

Rev. 1.5 / Jun.2018 65

Page 66

Table 10 - IDD5B Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

00 REF 100000000000000-

11 D 100000000000000-

2 D 100000000000000-

3 D#, D#1111100

4 D#, D#1111100

toggling

Static High

4-7

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

repeat pattern 1...4, use BG[1:0]

repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]

repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead

repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead

repeat pattern 1...4, use BG[1:0]

repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]

repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead

repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead

repeat pattern 1...4, use BG[1:0]

2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. DQ signals are VDDQ.

CS_n

Command

ACT_n

RAS_n/A16

WE_n/A14

CAS_n/A15

ODT

C[2:0]

= 1, BA[1:0] = 1 instead

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

= 1, BA[1:0] = 2 instead

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 3 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

3 0007F0-

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

Data

For x4 and x8

only

Rev. 1.5 / Jun.2018 66

Page 67

Table 11 - IDD7 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

00 ACT 000000000000000 -

1 RDA 011010 00001000 D0=00, D1=FF

2 D 1000000000000003 D# 1111100

... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

1 nRRD ACT 000000011000000 -

nRRD + 1 RDA 011010 11001000 D0=FF, D1=00

... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary

2 2*nRRD 3 3*nRRD

repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0]

4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary

CS_n

Command

ACT_n

RAS_n/A16

WE_n/A14

CAS_n/A15

ODT

C[2:0]

= 0, BA[1:0] = 2 instead

= 1, BA[1:0] = 3 instead

BA[1:0]

BG[1:0]

A12/BC_n

3 0007F0-

Data

A[9:7]

A[6:3]

A[10]/AP

A[17,13,11]

A[2:0]

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

= 0, BA[1:0] = 1 instead

= 1, BA[1:0] = 2 instead

= 0, BA[1:0] = 3 instead

= 1, BA[1:0] = 0 instead

toggling

5nFAW 6 nFAW + nRRD 7 nFAW + 2*nRRD

Static High

8 nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0] repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0]

9 nFAW + 4*nRRD repeat Sub-Loop 4

10 2*nFAW 11 2*nFAW + nRRD 12 2*nFAW + 2*nRRD 13 2*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0] repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0]

= 2, BA[1:0] = 0 instead

= 3, BA[1:0] = 1 instead

= 2, BA[1:0] = 2 instead

= 3, BA[1:0] = 3 instead

14 2*nFAW + 4*nRRD repeat Sub-Loop 4

15 3*nFAW 16 3*nFAW + nRRD 17 3*nFAW + 2*nRRD 18 3*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0] repeat Sub-Loop 0, use BG[1:0] repeat Sub-Loop 1, use BG[1:0]

= 2, BA[1:0] = 1 instead

= 3, BA[1:0] = 2 instead

= 2, BA[1:0] = 3 instead

= 3, BA[1:0] = 0 instead

19 3*nFAW + 4*nRRD repeat Sub-Loop 4

20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ

For x4 and x8

only

Rev. 1.5 / Jun.2018 67

Page 68

IDD Specifications (Tcase: 0 to 95oC)

4GB, 512Mx 64 SO-DIMM: HMA851S6CJR6N

IDD

Symbol 2400 2666 2933 3200 Symbol 2400 2666 2933 3200

IDD0 176 180 TBD TBD mA IPP0 38 38 TBD TBD mA

IDD0A 176 184 TBD TBD mA

IDD1 236 244 TBD TBD mA IDD1A 248 256 TBD TBD mA IPP2P 13 13 TBD TBD mA IDD2N 108 112 TBD TBD mA

IDD2NA 108 112 TBD TBD mA IDD2NT 128 132 TBD TBD mA IPP4R 88 88 TBD TBD mA

IDD2NL 80 84 TBD TBD mA IDD2NG 108 112 TBD TBD mA IDD2ND 104 108 TBD TBD mA IPP5F2 160 164 TBD TBD mA IDD2NP 108 112 TBD TBD mA

IDD2P 76 80 TBD TBD mA

IDD2Q 100 100 TBD TBD mA IPP6E 28 28 TBD TBD mA

IDD3N 148 152 TBD TBD mA

IDD3NA 148 152 TBD TBD mA

IDD3P 120 124 TBD TBD mA IPP7 92 96 TBD TBD mA

IDD4R 736 800 TBD TBD mA IDD4RA 756 816 TBD TBD mA IDD4RB 756 812 TBD TBD mA

IDD4W 588 640 TBD TBD mA IDD4WA 608 664 TBD TBD mA IDD4WB 560 604 TBD TBD mA IDD4WC 580 628 TBD TBD mA IDD4WP 648 708 TBD TBD mA

IDD5B 784 788 TBD TBD mA IDD5F2 568 576 TBD TBD mA IDD5F4 508 516 TBD TBD mA

IDD6N 84 84 TBD TBD mA

IDD6E 112 112 TBD TBD mA

IDD6R 56 56 TBD TBD mA

IDD6A 112 112 TBD TBD mA

IDD7 736 756 TBD TBD mA IDD8 48 48 TBD TBD mA

unitnot

IPP1 42 42 TBD TBD mA

IPP2N 13 13 TBD TBD mA

IPP3N 64 64 TBD TBD mA

IPP3P 64 64 TBD TBD mA

IPP4W 88 88 TBD TBD mA

IPP5B 252 252 TBD TBD mA

IPP5F4 140 140 TBD TBD mA

IPP6N 20 20 TBD TBD mA

IPP6R 16 20 TBD TBD mA IPP6A 28 28 TBD TBD mA

IPP8 13 13 TBD TBD mA

IPP

unitno

Rev. 1.5 / Jun.2018 68

Page 69

8GB, 1Gx 64 SO-DIMM: HMA81GS6CJR8N

IDD

Symbol 2400 2666 2933 3200 Symbol 2400 2666 2933 3200

IDD0 288 296 TBD TBD mA

IDD0A 288 304 TBD TBD mA

IDD1 360 376 TBD TBD mA IDD1A 384 400 TBD TBD mA IDD2N 216 224 TBD TBD mA

IDD2NA 216 224 TBD TBD mA IDD2NT 256 264 TBD TBD mA

IDD2NL 160 168 TBD TBD mA IDD2NG 216 224 TBD TBD mA IDD2ND 208 216 TBD TBD mA

IDD2NP 216 224 TBD TBD mA

IDD2P 152 160 TBD TBD mA IDD2Q 200 200 TBD TBD mA IPP6E 56 56 TBD TBD mA IDD3N 296 304 TBD TBD mA

IDD3NA 296 304 TBD TBD mA

IDD3P 240 248 TBD TBD mA IPP7 136 144 TBD TBD mA IDD4R 928 1008 TBD TBD mA

IDD4RA 952 1032 TBD TBD mA IDD4RB 952 1024 TBD TBD mA

IDD4W 800 864 TBD TBD mA IDD4WA 824 896 TBD TBD mA IDD4WB 760 816 TBD TBD mA IDD4WC 784 848 TBD TBD mA IDD4WP 920 1000 TBD TBD mA

IDD5B 1568 1576 TBD TBD mA IDD5F2 1136 1152 TBD TBD mA IDD5F4 1016 1032 TBD TBD mA

IDD6N 168 168 TBD TBD mA

IDD6E 224 224 TBD TBD mA IDD6R 112 112 TBD TBD mA IDD6A 224 224 TBD TBD mA

IDD7 1120 1168 TBD TBD mA IDD8 96 96 TBD TBD mA

unitnot

IPP0 44 44 TBD TBD mA IPP1 52 52 TBD TBD mA

IPP2N 26 26 TBD TBD mA

IPP2P 26 26 TBD TBD mA

IPP3N 128 128 TBD TBD mA

IPP3P 128 128 TBD TBD mA IPP4R 152 152 TBD TBD mA

IPP4W 152 152 TBD TBD mA

IPP5B 504 504 TBD TBD mA IPP5F2 320 328 TBD TBD mA IPP5F4 280 280 TBD TBD mA

IPP6N 40 40 TBD TBD mA

IPP6R 33 33 TBD TBD mA

IPP6A 56 56 TBD TBD mA

IPP8 26 26 TBD TBD mA

IPP

unitno

Rev. 1.5 / Jun.2018 69

Page 70

8GB, 1Gx 72 SO-DIMM: HMA81GS7CJR8N

IDD

Symbol 2400 2666 Symbol 2400 2666

IDD0 324 333 mA

IDD0A 324 342 mA

IDD1 405 423 mA IDD1A 432 450 mA IDD2N 243 252 mA

IDD2NA 243 252 mA IDD2NT 288 297 mA

IDD2NL 180 189 mA IDD2NG 243 252 mA IDD2ND 234 243 mA IDD2NP 243 252 mA

IDD2P 171 180 mA IDD2Q 225 225 mA IPP6E 63 63 mA IDD3N 333 342 mA

IDD3NA 333 342 mA

IDD3P 270 279 mA IPP7 153 162 mA IDD4R 1044 1134 mA

IDD4RA 1071 1161 mA IDD4RB 1071 1152 mA

IDD4W 900 972 mA IDD4WA 927 1008 mA IDD4WB 855 918 mA IDD4WC 882 954 mA IDD4WP 1035 1125 mA

IDD5B 1764 1773 mA IDD5F2 1278 1296 mA IDD5F4 1143 1161 mA

IDD6N 189 189 mA

IDD6E 252 252 mA

IDD6R 126 126 mA

IDD6A 252 252 mA

IDD7 1260 1314 mA IDD8 108 108 mA

unit note

IPP0 50 50 mA

IPP1 59 59 mA IPP2N 29 29 mA IPP2P 29 29 mA IPP3N 144 144 mA IPP3P 144 144 mA IPP4R 171 171 mA

IPP4W 171 171 mA

IPP5B 567 567 mA

IPP5F2 360 369 mA IPP5F4 315 315 mA

IPP6N 45 45 mA

IPP6R 37 37 mA IPP6A 63 63 mA

IPP8 29 29 mA

IPP

unit note

Rev. 1.5 / Jun.2018 70

Page 71

16GB, 2Gx 64 SO-DIMM: HMA82GS6CJR8N

IDD

Symbol 2400 2666 2933 3200 Symbol 2400 2666 2933 3200

IDD0 504 520 TBD TBD mA

IDD0A 504 528 TBD TBD mA

IDD1 576 600 TBD TBD mA

IDD1A 600 624 TBD TBD mA

IDD2N 432 448 TBD TBD mA IDD2NA 432 448 TBD TBD mA IDD2NT 512 528 TBD TBD mA IDD2NL 320 336 TBD TBD mA

IDD2NG 432 448 TBD TBD mA IDD2ND 416 432 TBD TBD mA

IDD2NP 432 448 TBD TBD mA

IDD2P 304 320 TBD TBD mA IDD2Q 400 400 TBD TBD mA IPP6E 112 112 TBD TBD mA IDD3N 592 608 TBD TBD mA

IDD3NA 592 608 TBD TBD mA

IDD3P 480 496 TBD TBD mA IPP7 162 170 TBD TBD mA

IDD4R 1144 1232 TBD TBD mA

IDD4RA 1168 1256 TBD TBD mA IDD4RB 1168 1248 TBD TBD mA

IDD4W 1016 1088 TBD TBD mA

IDD4WA 1040 1120 TBD TBD mA

IDD4WB 976 1040 TBD TBD mA

IDD4WC 1000 1072 TBD TBD mA

IDD4WP 1136 1224 TBD TBD mA

IDD5B 1784 1800 TBD TBD mA

IDD5F2 1352 1376 TBD TBD mA IDD5F4 1232 1256 TBD TBD mA

IDD6N 336 336 TBD TBD mA

IDD6E 448 448 TBD TBD mA

IDD6R 224 224 TBD TBD mA

IDD6A 448 448 TBD TBD mA

IDD7 1336 1392 TBD TBD mA IDD8 192 192 TBD TBD mA

unitnot

IPP0 70 70 TBD TBD mA

IPP1 78 78 TBD TBD mA IPP2N 51 51 TBD TBD mA IPP2P 51 51 TBD TBD mA IPP3N 256 256 TBD TBD mA IPP3P 256 256 TBD TBD mA IPP4R 178 178 TBD TBD mA

IPP4W 178 178 TBD TBD mA

IPP5B 530 530 TBD TBD mA

IPP5F2 346 354 TBD TBD mA IPP5F4 306 306 TBD TBD mA

IPP6N 80 80 TBD TBD mA

IPP6R 66 66 TBD TBD mA IPP6A 112 112 TBD TBD mA

IPP8 51 51 TBD TBD mA

IPP

unitno

Rev. 1.5 / Jun.2018 71

Page 72

16GB, 2Gx 72 SO-DIMM: HMA82GS7CJR8N

IDD

Symbol 2400 2666 Symbol 2400 2666

IDD0 567 585 mA

IDD0A 567 594 mA

IDD1 648 675 mA IDD1A 675 702 mA IDD2N 486 504 mA

IDD2NA 486 504 mA IDD2NT 576 594 mA

IDD2NL 360 378 mA IDD2NG 486 504 mA IDD2ND 468 486 mA IDD2NP 486 504 mA

IDD2P 342 360 mA IDD2Q 450 450 mA IPP6E 126 126 mA IDD3N 666 684 mA

IDD3NA 666 684 mA

IDD3P 540 558 mA IPP7 182 191 mA

IDD4R 1287 1386 mA IDD4RA 1314 1413 mA IDD4RB 1314 1404 mA

IDD4W 1143 1224 mA IDD4WA 1170 1260 mA IDD4WB 1098 1170 mA IDD4WC 1125 1206 mA

IDD4WP 1278 1377 mA

IDD5B 2007 2025 mA IDD5F2 1521 1548 mA IDD5F4 1386 1413 mA

IDD6N 378 378 mA

IDD6E 504 504 mA

IDD6R 252 252 mA

IDD6A 504 504 mA

IDD7 1503 1566 mA IDD8 216 216 mA

unit note

IPP0 78 78 mA

IPP1 87 87 mA IPP2N 58 58 mA IPP2P 58 58 mA IPP3N 288 288 mA IPP3P 288 288 mA IPP4R 200 200 mA

IPP4W 200 200 mA

IPP5B 596 596 mA

IPP5F2 389 398 mA IPP5F4 344 344 mA

IPP6N 90 90 mA

IPP6R 74 74 mA IPP6A 126 126 mA

IPP8 58 58 mA

IPP

unit note

Rev. 1.5 / Jun.2018 72

Page 73

Module Dimensions

Front

Back

30.00

69.60mm

20.00

18.00

1.75

35.50 28.50

1.425

2.50

pin 1

pin 260

Detail-A

4.00 0.10

1.80 0.102



Side

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

3.5mm max

6.00

1.675

1.00 ±0.05

0.20±0.15

4.00±.010

Detail - A

2.55

0.50

0.35±0.03

Note-metalized

Max 0.25

keep out area Max 0.30

1.20±0.10

SPD

512Mx64 - HMA851S6CJR6N

Rev. 1.5 / Jun.2018 73

Page 74

1Gx64 - HMA81GS6CJR8N

Front

Back

30.00

69.60mm

20.00

18.00

1.75

35.50 28.50

1.425

2.50

pin 1

pin 260

Detail-A

4.00 0.10

1.80 0.102



Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

6.00

1.675

1.00 ±0.05

0.20±0.15

4.00±.010

Detail - A

2.55

0.50

0.35±0.03

Note-metalized

Max 0.25

keep out area Max 0.30

Detail - A

Side

3.7mm max

1.20±0.10

SPD

Rev. 1.5 / Jun.2018 74

Page 75

1Gx72 - HMA81GS7CJR8N

Front

Back

30.00

69.60mm

20.00

18.00

1.75

35.50 28.50

1.425

2.50

pin 1

pin 260

Detail-A

4.00 0.10

1.80 0.102



Side

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

3.7mm max

6.00

1.675

1.20±0.10

SPD/TS

1.00 ±0.05

0.20±0.15

4.00±.010

2.55

0.50

0.35±0.03

Note-metalized

Max 0.25

keep out area Max 0.30

Detail - A

Rev. 1.5 / Jun.2018 75

Page 76

2Gx64 - HMA82GS6CJR8N

Front

Back

30.00

69.60mm

20.00

18.00

1.75

35.50 28.50

1.425

2.50

pin 1

pin 260

Detail-A

4.00 0.10

1.80 0.102



Side

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

3.7mm max

6.00

1.675

1.20±0.10

1.00 ±0.05

0.20±0.15

4.00±.010

2.55

0.50

0.35±0.03

Note-metalized

Max 0.25

keep out area Max 0.30

Detail - A

SPD

Rev. 1.5 / Jun.2018 76

Page 77

2Gx72 - HMA82GS7CJR8N

Front

Back

30.00

69.60mm

20.00

18.00

1.75

35.50 28.50

1.425

2.50

pin 1

pin 260

Detail-A

4.00 0.10

1.80 0.102



Side

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

3.7mm max

6.00

1.675

1.20±0.10

SPD/TS

1.00 ±0.05

0.20±0.15

4.00±.010

2.55

0.50

0.35±0.03

Note-metalized

Max 0.25

keep out area Max 0.30

Detail - A

Rev. 1.5 / Jun.2018 77