SK hynix HMA451R7AFR8N, HMA41GR7AFR8N, HMA41GR7AFR4N, HMA42GR7AFR4N User Manual

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288pin DDR4 SDRAM Registered DIMM

DDR4 SDRAM Registered DIMM

Based on 4Gb A-die

HMA451R7AFR8N HMA41GR7AFR8N HMA41GR7AFR4N HMA42GR7AFR4N

*SK hynix reserves the right to change products or specifications without notice.

Rev. 1.7 / Jun.2016 1

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Revision History

Revision No. History Draft Date Remark

0.1 Initial Release Dec.2014

1.0 IDD Specification update May.2015

1.1 Module dimension update(PCB) Jun.2015

1.2 Corrected IDD value of HMA41GR7AFR8N Jul.2015

1.3 Corrected Pin Assignments Jul.2015

1.4 Changed Module Dimension Oct.2015

1.5 Updated JEDEC Specification Changed Speed Bin : 2666Mbps CL9(VK)

1.6 Updated 2133Mbps (tCK(min) : 0.938ns -> 0.937ns)

Updated JEDEC Specification

1.7 Corrected typo : page number Jun.2016

Dec.2015

Mar.2016

Rev. 1.7 / Jun.2016 2

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Description

SK hynix Registered DDR4 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations.

Features

• Power Supply: VDD=1.2V (1.14V to 1.26V)

• VDDQ = 1.2V (1.14V to 1.26V)

• VPP - 2.5V (2.375V to 2.75V)

• VDDSPD=2.25V to 2.75V

• Functionality and operations comply with the DDR4 SDRAM datasheet

• 16 internal banks

• Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available

• Data transfer rates: PC4-2666, PC4-2400, PC4-2133

• Bi-Directional Differential Data Strobe

• 8 bit pre-fetch

• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)

• Supports ECC error correction and detection

• On-Die Termination (ODT)

• Temperature sensor with integrated SPD

• This product is in compliance with the RoHS directive.

• Per DRAM Addressability is supported

• Internal Vref DQ level generation is available

• Write CRC is supported at all speed grades

• DBI (Data Bus Inversion) is supported(x8)

• CA parity (Command/Address Parity) mode is supported

Ordering Information

Part Number Density Organization Component Composition

HMA451R7AFR8N-TF/UH/VK 4GB 512Mx72 512Mx8(H5AN4G8NAFR)*9 1

HMA41GR7AFR8N-TF/UH/VK 8GB 1Gx72 512Mx8(H5AN4G8NAFR)*18 2

HMA41GR7AFR4N-TF/UH/VK 8GB 1Gx72 1Gx4(H5AN4G4NAFR)*18 1

HMA42GR7AFR4N-TF/UH/VK 16GB 2Gx72 1Gx4(H5AN4G4NAFR)*36 2

Rev. 1.7 / Jun.2016 3

# of

ranks

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Key Parameters

MT/s Grade

DDR4-1600 -PB 1.25 11

DDR4-1866 -RD 1.071 13

DDR4-2133 -TF 0.937 15

DDR4-2400 -UH 0.833 17

DDR4-2666 -VK 0.75 19

*SK hynix DRAM devices support optional downbinning to CL17, CL15, CL13 and CL11. SPD setting is programmed to match.

tCK

(ns)

CAS

Latency

(tCK)

tRCD

(ns)

13.75

(13.50)*

13.92

(13.50)*

14.06

(13.50)*

14.16

(13.75)*

14.25

(13.75)*

tRP

(ns)

13.75

(13.50)*

13.92

(13.50)*

14.06

(13.50)*

14.16

(13.75)*

14.25

(13.75)*

tRAS

(ns)

tRC

(ns)

48.75

(48.50)*

47.92

(47.50)*

47.06

(46.50)*

46.16

(45.75)*

46.25

(45.75)*

CL-tRCD-tRP

11-11-11

13-13-13

15-15-15

17-17-17

19-19-19

Address Table

4GB(1Rx8) 8GB(2Rx8) 8GB(1Rx4) 16GB(2Rx4)

# of Bank Groups 4 4 4 4

Bank Address

BG Address BG0~BG1 BG0~BG1 BG0~BG1 BG0~BG1

Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A14 A0~A14 A0~A15 A0~A15 Column Address A0~ A9 A0~ A9 A0~ A9 A0~ A9 Page size 1 KB 1 KB 512MB 512MB

Rev. 1.7 / Jun.2016 4

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Pin Descriptions

Pin Name Description Pin Name Description

A0-A17

BA0, BA1 Regisiter bank select input SDA

BG0, BG1 Regisiter bank group select input SA0-SA2

RAS_n

CAS_n

WE_n

CS0_n, CS1_n,

CS2_n, CS3_n

DIMM Rank Select Lines input 12V

CKE0, CEK1 Register clock enable lines input VREFCA

ODT0, ODT1

VSS Power supply return (ground)

I2C serial bus clock for SPD-TSE and register

I2C serial data line for SPD-TSE and register

I2C slave address select for SPD-TSE and register

Optional Power Supply on socket but not used on RDIMM

SDRAM command/address reference supply

ACT_n Register input for activate input VDDSPD Serial SPD/TS positive power supply

DQ0-DQ63 DIMM memory data bus ALERT_n Register ALERT_n output

CB0-CB7 DIMM ECC check bits VPP SDRAM Supply

TDQS9_t-TDQS17_t

TDQS9_c-TDQS17_c

DQS0_t-DQS17_t

DQS0_c-DQS17_c

DBI0_n-DBI8_n Data Bus Inversion EVENT_n

CK0_t, CK1_t

CK0_c, CK1_c

Dummy loads for mixed populations of x4 based and x8 based RDIMMs.

Data Buffer data strobes

(positive line of differential pair)

Data Buffer data strobes

(negative line of differential pair)

DM0_n-DM8_n Data Mask

RESET_n

Set Register and SDRAMs to a Known State

SPD signals a thermal event has occurred

VTT SDRAM I/O termination supply

RFU Reserved for future use

1. Address A17 is only valid for 16Gbx4 based SDRAMs.

2. RAS_n is a multiplexed function with A16.

3. CAS_n is a multiplexed function with A15.

4. WE_n is a multiplexed function with A14.

Rev. 1.7 / Jun.2016 5

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Input/Output Functional Descriptions

Symbol Type Function

CK0_t, CK0_c,

CK1_t, CK1_c

CKE0, CKE1 Input

CS0_n, CS1_n,

CS2_n, CS3_n

C0, C1, C2

ODT0, ODT1

ACT_n

RAS_n/A16, CAS_n/A15,

WE_n/A14

Input

Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals and device input buffers and output drivers. Taking CKE LOW provides Precharge PowerDown and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t, CK_c, ODT and CKE, are disabled during power-down. Input buffers, excluding CKE, are disabled during SelfRefresh.

Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection. CS_n is considered part of the command code.

Chip ID: Chip ID is only used for 3DS for 2,4,8 high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code.

On-Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c, TDQS_t, and TDQS_c signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.

Activation Command Input: ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as Row Address A16, A15, and A14.

Command Inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the command being entered. Those pins are multi-function. For example, for activation with ACT_n Low, these are Addresses like A16, A15, and A14, but for non-activation command with ACT_n High, these are Command pins for Read, Write, and other commands defined in command truth table.

Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read, Write, or

BG0 - BG1

BA0 - BA1

A0 - A17

Rev. 1.7 / Jun.2016 6

Input

Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle.

Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write, or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.

Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions. See other rows. The address inputs also provide the op-code during Mode Register Set commands. A17 is only defined for 16Gb x4 SDRAM configurations.

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Symbol Type Function

Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write

A10 / AP

Input

operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if

A12 / BC_n

Input

burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.

RESET_n

CMOS

Input

Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.

Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register, then

Input / Output

CRC code is added at the end of Data Burst. Any DQ from DQ0-DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. Refer to vendor specific data sheets to determine which DQ is used.

Data Strobe: output with read data, input with write data. Edge-aligned with read data, DQS0_t-DQS17_t, DQS0_c-DQS17_c

Input / Output

centered in write data. The data strobe DQS_t is paired with differential signals DQS_c,

respectively, to provide differential pair signaling to the system during reads and writes.

DDR4 SDRAM supports differential data strobe only and does not support single-ended.

TDQS9_t-TDQS17_t, TDQS9_c-TDQS17_c

DBI0_n-DBI8_n

DM0_n-DM8_n

PAR

ALERT_n

RFU

VDD

VSS

Input

Input/

Output

Input

Output (Input)

Supply

Provides a dummy load for x8 based RDIMMs where mixed populations of x4 and x8

based RDIMMs are present.

Provides for data bus inversion. Only possible for x8 based RDIMMs and where only x8

based RDIMMs are on a channel.

Provides for masking of a byte on WRITE commands to the SDRAMs. Only Possible x8

based RDIMMs and where only x8 based RDIMMs are on a channel.

Command and Address Parity Input : DDR4 Supports Even Parity check in SDRAMs with

MR setting. Once it’s enabled via Register in MR5, then SDRAM calculates Parity with

ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity

should be maintained at the rising edge of the clock and at the same time as command

& address, with CS_n LOW.

Alert: Is multi functions, such as CRC error flag or Command and Address Parity error

flag, as on Output signal. If there is an error in the CRC, then ALERT_n goes LOW for the

period time interval and goes back HIGH. If there is an error in the Command Address

Parity Check, then ALERT_n goes LOW for a relatively long period until on going SDRAM

internal recovery transaction is complete. During Connectivity Test mode, this pin

functions as an input.

Using this signal or not is dependent on the system.

Reserved for Future Use: No on-DIMM electrical connection is present.

No Connect: No on-DIMM electrical connection is present.

Power Supply: 1.2 V ± 0.06 V

Ground

Rev. 1.7 / Jun.2016 7

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Symbol Type Function

VTT

12V

VPP

VDDSPD

VREFCA

Supply

Power Supply for termination of Address, Command and Control, VDD/2.

12V supply not used on RDIMMs.

SDRAM Activating Power Supply: 2.5V (2.375V min , 2.75V max)

Power supply used to power the I2C bus on the SPD-TSE and register.

Reference voltage for CA

Note: For PC4, VDD is 1.2V. For PC4L, VDD is TBD.

Rev. 1.7 / Jun.2016 8

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Pin Assignments

1 NC 145

3 DQ4 147 VSS 76 VDD 220 VDD

4 VSS 148

6 VSS 150 DQ1

9 VSS 153 DQS0_t 80 VDD 224 BA1

10 DQ6 154

12 DQ2 156 VSS 83 VDD 227 RFU

13 VSS 157

15 VSS 159 DQ13 86 CAS_n/A15 230 NC

16 DQ8 160

19 TDQS10_c, DQS10_c 163

21 DQ14 165 VSS 92 VDD 236 VDD

22 VSS 166

24 VSS 168 DQ11 95 DQ36 239 VSS

25 DQ20 169

27 DQ16 171 VSS 98 VSS 242 DQ33

28 VSS 172

30 TDQS11_c, DQS11_c 174 DQS2_c 101 VSS 245 DQS4_t

31 VSS 175

33 VSS 177 DQ23 104 DQ34 248 VSS

34 DQ18 178

36 DQ28 180 VSS 107 VSS 251 DQ45

Front Side

Pin Label

VSS

DQ0

TDQS9_t, DQS9_t,

DM0_n, DBI0_n

TDQS9_C, DQS9_

VSS

DQ12

VSS

TDQS10_t, DQS10_t,

DM1_n, DBI1_n

VSS

DQ10

VSS

TDQS11_t, DQS11_t,

DM2_n, DBI2_n

DQ22

VSS

146 VREFCA 75 CK0_c 219 CK1_c

149 VSS

151

152 DQS0_c 79 A0 223 VDD

155 DQ7 82 RAS_n/A16 226 VDD

158 VSS 85 VDD 229 VDD

161 DQ9 88 VDD 232 A13

162 VSS 89 CS1_n, NC 233 VDD

164 DQS1_t 91

167 VSS 94

170 DQ21 97

173 VSS 100

176 VSS 103

179 DQ19 106

Back Side

Pin Label

DQ5

VSS

DQ3

VSS

DQS1

_c 90 VDD 234

DQ15

VSS

DQ17

DQS2_t

VSS

74 CK0_t 218 CK1_t

77 VTT 221 VTT

78 EVENT_n 222 PARITY

81 BA0 225 A10/AP

84 CS0_n 228 WE_n/A14

87 ODT0 231 VDD

93 C0, CS2_n, NC 237

96 VSS 240

102 DQ38 246

105 VSS 249

Front Side

Pin Label

ODT1, NC

VSS

DQ32

TDQS13_t, DQS13_t,

DM4_n, DBI4_n

TDQS13_C, DQS13_C244 DQS4_c

VSS

DQ44

KEY

235 NC, C2

238 SA2

241 VSS

243

247 DQ39

250 VSS

Back Side

Pin Label

A17

NC, CS3_n, C1

DQ37

VSS

DQ35

Rev. 1.7 / Jun.2016 9

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37 VSS 181

39 VSS 183 DQ25 110

42 VSS 186 DQS3_t 113 DQ46 257 VSS

43 DQ30 187

45 DQ26 189 VSS 116 VSS 260 DQ43

46 VSS 190

48 VSS 192 CB5 119 DQ48 263 VSS

49 CB0 193 VSS 120 VSS 264 DQ49

50 VSS 194 CB1 121

52 TDQS17_c, DQS17_c 196 DQS8_c 123 VSS 267

53 VSS 197 DQS8_t 124

54 CB6 198 VSS 125 VSS 269 DQ55

55 VSS 199 CB7 126 DQ50 270

56 CB2 200 VSS 127

57 VSS 201 CB3 128 DQ60 272 VSS

58 RESET_n 202 VSS 129 VSS 273 DQ61

59 VDD 203 CKE1, NC 130

60 CKE0 204 VDD 131 VSS 275 DQ57

61 VDD 205 RFU 132

62 ACT_n 206 VDD 133 TDQS16_t, DQS16_c 277 DQS7_c

63 BG0 207 BG1 134 VSS 278 DQS7_t

64 VDD 208 ALERT_n 135 DQ62 279 VSS

65 A12/BC_n 209 VDD 136 VSS 280 DQ63

66 A9 210 A11 137 DQ58 281 VSS

67 VDD 211 A7 138 VSS 282 DQ59

68 A8 212 VDD 139 SA0 283 VSS

69 A6 213 A5 140 SA1 284 VDDSPD

70 VDD 214 A4 141 SCL 285 SDA

71 A3 215 VDD 142 VPP 286 VPP

72 A1 216 A2 143 VPP 287 VPP

73 VDD 217 VDD 144 RFU 288 VPP

Front Side

Pin Label

DQ24

TDQS12_t, DQS12_t,

DM3_n, DBI3_n

TDQS12_C, DQS12_C185 DQS3_c 112

VSS

CB4

TDQS17_t, DQS17_t,

DM8_n, DBI8_n

182 VSS 109

184

188 DQ31 115

191 VSS 118

195 VSS 122 TDQS15_c, DQS15_c 266 DQS6_c

Back Side

Pin Label

DQ29

VSS

DQ27

108 DQ40 252

111 TDQS14_c, DQS14_c 255

114 VSS 258

117 DQ52 261

Front Side

Pin Label

VSS

TDQS14_t, DQS14_t,

DM5_n, DBI5_n

VSS

DQ42

VSS

TDQS15_t, DQS15_t,

DM6_n, DBI6_n

DQ54

VSS

DQ56

TDQS16_t, DQS16_t,

DM7_n, DBI7_n

253 DQ41

254 VSS

256 DQS5_t

259 VSS

262 DQ53

265 VSS

268 VSS

271 DQ51

274

276 VSS

Back Side

Pin Label

VSS

DQS5_

DQ47

VSS

DQS6_t

VSS

Rev. 1.7 / Jun.2016 10

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Functional Block Diagram

CS0B_n

ODT0B

CKE0B

DQS0_t

DQS0_c

DQ [7:0]

DQS1_t

DQS1_c

DQ [15:8]

DQS2_t

DQS2_c

DQ [23:16]

DQS3_t

DQS3_c

DQ [31:24]

DQS8_t

DQS8_c

CB [0:7]

DQS_t DQS_c DQ [7:0]

DQS5_t

DQS5_c

DQ [47:40]

DQS6_t

DQS6_c

DQ [55:48]

DQS7_t

DQS7_c

DQ [63:56]

DQS_t DQS_c DQ [7:0]

D0–D8

DDSPD

D0–D8

VREFCA

SPD

D0–D8

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. The TEN pin on the SDRAMs are tied to VSS.

5. VDD and VDDSPD also connect with the register.

DQS4_t

DQS4_c

DQ [39:32]

CKE ODT CS_n VSS

VSS

CKE ODT CS_n

CS0A_n

ODT0A

CKE0A

SA0

Serial PD with Thermal sensor

SA1

SA0 SA1

SCL

EVENT_n

SA2

EVENT_n

SCL

SDA

SA0 SA1

SA0

SA1

BFUNC

SA2

VSS

SCL

SDA

Ω

RCD

DBI0_n/DM0_n DBI_n/DM_n DBI4_n/DM4_n DBI_n/DM_n

DBI1_n/DM1_n DBI_n/DM_n DBI5_n/DM5_n DBI_n/DM_n

DBI2_n/DM2_n DBI_n/DM_n DBI6_n/DM6_n DBI_n/DM_n

DBI3_n/DM3_n DBI_n/DM_n

DBI8_n/DM8_n DBI_n/DM_n

DBI7_n/DM7_n DBI_n/DM_n

4GB, 512Mx72 Module(1Rank of x8) - page1

Rev. 1.7 / Jun.2016 11

Page 12

4GB, 512Mx72 Module(1Rank of x8) - page2

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs

BG[1:0]

BA[1:0]

A[16:0]

PARITY, ACT_n

CKE0

ODT0

CS0_n

CK0_t

CK0_c

BG[1:0]A -> BG[1:0]: SDRAMs D[4:0] BG[1:0]B -> BG[1:0]: SDRAMs D[8:5]

CKE0B -> CKE: SDRAMs D[8:5]

A[16:0]B -> A[16:0]: SDRAMs D[8:5]

A[16:0]A -> A[16:0]: SDRAMs D[4:0]

CKE0A -> CKE: SDRAMs D[4:0]

ODT0B -> ODT: SDRAMs D[8:5]

ODT0A -> ODT: SDRAMs D[4:0]

CS0B_n -> CS_n: SDRAMs D[8:5]

CS0A_n -> CS_n: SDRAMs D[4:0]

Y1(_t, _c) -> CK1(_t, _c): SDRAMs D[4:0]

Y0(_t, _c) -> CK0(_t, _c): SDRAMs D[8:5]

RESET_n QRESET_n -> RESET_n: All SDRAMs

R E

I S T E R

PARB -> PAR, ACT_n: SDRAMs D[8:5]

PARA -> PAR, ACT_n: SDRAMs D[4:0]

BA[1:0]A -> BA[1:0]: SDRAMs D[4:0] BA[1:0]B -> BA[1:0]: SDRAMs D[8:5]

CK1_t

CK1_c

Note:

1. CK0_t, CK0_c terminated with 120Ω±5% resistor.

2. CK1_t, CK1_c terminated with 120

Ω±5% resistor but not used.

3. Unless otherwise noted resistors are 22

Ω±5%.

4. Register inputs CS1_n, CS2_n/C0 and CS3_n/C1 are tied to VDD. Register inputs CS, ODT1 and CKE1 are tied to VSS.

Rev. 1.7 / Jun.2016 12

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8GB, 1Gx72 Module(2Rank of x8) - page1

CKE1A

ODT1A

CS1A_n

CKE0A

ODT0A

CS0A_n

CKE1B

ODT1B

CS1B_n

CKE0B

ODT0B

CS0B_n

DQS8_t DQS8_c

CB [7:0]

DQS3_t DQS3_c

DQ [31:24]

DQS2_t DQS2_c

DQ [23:16]

DQS‘_t

DQS‘_c

DQ [15:8]

DQS_t DQS_c DQ [7:0]

D0–D17

DDSPD

D0–D17

VREFCA

RCD, Serial PD

D0–D17

D0–D17, RCD, Serial PD

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. The TEN pin on the SDRAMs are tied to Vss.

5. VDD and VDDSPD also connect to the RCD

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [7:0]

D13

DQS_t DQS_c DQ [7:0]

D12

DQS_t DQS_c DQ [7:0]

D11

DQS_t DQS_c DQ [7:0]

D10

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS4_t

DQS4_c

DQ [39:32]

DQS5_t

DQS5_c

DQ [47:40]

DQS6_t

DQS6_c

DQ [55:48]

DQS7_t

DQS7_c

DQ [59:56]

DQS_t DQS_c DQ [7:0]

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [7:0]

D14

DQS_t DQS_c DQ [7:0]

D15

DQS_t DQS_c DQ [7:0]

D16

DQS_t DQS_c DQ [7:0]

D17

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS0_t DQS0_c

DQ [7:0]

DQS_t DQS_c DQ [7:0]

ZQ VSS

DQS_t DQS_c DQ [7:0]

ZQ VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

DBI8_n/DM8_n DBI_n/DM_n DBI_n/DM_n DBI4_n/DM4_n DBI_n/DM_n DBI_n/DM_n

DBI3_n/DM3_n DBI_n/DM_n DBI_n/DM_n DBI5_n/DM5_n DBI_n/DM_n DBI_n/DM_n

DBI2_n/DM2_n DBI_n/DM_n DBI_n/DM_n DBI6_n/DM6_n DBI_n/DM_n DBI_n/DM_n

DBI1_n/DM1_n DBI_n/DM_n DBI_n/DM_n DBI7_n/DM7_n DBI_n/DM_n DBI_n/DM_n

DBI0_n/DM0_n DBI_n/DM_n DBI_n/DM_n

SA0

Serial PD with Thermal sensor

SA1

SA0 SA1

SCL

EVENT_n

SA2

EVENT_n

SCL

SDA

SA0 SA1

SA0

SA1

BFUNC

SA2

VSS

SCL

SDA

Ω

RCD

Rev. 1.7 / Jun.2016 13

Page 14

8GB, 1Gx72 Module(2Rank of x8) - page2

CKE1

CKE1B -> CKE: SDRAMs D[17:14]

CKE1A -> CKE: SDRAMs D[13:9]

ODT1

ODT1B -> ODT: SDRAMs D[17:14]

ODT1A -> ODT: SDRAMs D[13:9]

CS1_n

CS1B_n -> CS_n: SDRAMs D[17:14]

CS1A_n -> CS_n: SDRAMs D[13:9]

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs

ACT_n

BG[1:0]

BA[1:0]

A[17:0]

PARITY

CKE0

ODT0

CS0_n

CK0_t

CK0_c

BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[13:9] BG[1:0]B -> BG[1:0]: SDRAMs D[8:5], D[17:14]

CKE0B -> CKE: SDRAMs D[8:5]

A[17:0]B -> A[17:0]: SDRAMs D[8:5], D[12:9]

A[17:0]A -> A[17:0]: SDRAMs D[4:0], D[17:13]

CKE0A -> CKE: SDRAMs D[4:0]

ODT0B -> ODT: SDRAMs D[8:5]

ODT0A -> ODT: SDRAMs D[4:0]

CS0B_n -> CS_n: SDRAMs D[8:5]

CS0A_n -> CS_n: SDRAMs D[4:0]

Y2_t -> CK_C: SDRAMs D[17:14]

Y0_t -> CK_t: SDRAMs D[8:5]

RESET_n QRST_n -> RESET_n: All SDRAMs

T E

PARB -> PAR: SDRAMs D[8:5], D[17:14]

PARA -> PAR: SDRAMs D[4:0], D[13:9]

BA[1:0]A -> BA[1:0]: SDRAMs D[4:0], D[13:9] BA[1:0]A -> BA[1:0]: SDRAMs D[8:5], D[17:14]

CK1_t

CK1_c

Note:

1. CK0_t, CK0_c terminated with 120Ω±5% resistor.

2. CK1_t, CK1_c terminated with 120

Ω±5% resistor but not used.

3. Unless otherwise noted resistors are 22

Ω±5%.

ACTB_n -> ACT_n: SDRAMs D[8:5], D[17:14]

ACTA_n -> ACT_n: SDRAMs D[4:0], D[13:9]

I S

Y1_t -> CK_t: SDRAMs D[4:0]

Y3_t -> CK_C: SDRAMs D[13:9]

Y2_c -> CK_C: SDRAMs D[17:14]

Y0_c -> CK_t: SDRAMs D[8:5] Y1_c-> CK_t: SDRAMs D[4:0]

Y3_c -> CK_C: SDRAMs D[13:9]

Rev. 1.7 / Jun.2016 14

Page 15

8GB, 1Gx72 Module(1Rank of x4) - page1

CS0B_n

ODT0B

CKE0B

DQS9_t

DQS9_c

DQ [9:4]

DQS10_t

DQS10_c

DQ [15:12]

DQS11_t

DQS11_c

DQ [23:20]

DQS12_t

DQS12_c

DQ [31:28]

DQS_t DQS_c DQ [3:0]

D0–D17

DDSPD

D0–D17

VREFCA

SPD

D0–D17

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. VDD and VDDSPD also connect to the register. TEN pi n of SDRAMs is tied to VSS.

CKE

ODT

CS_n

VSS

CS0A_n

ODT0A

CKE0A

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS0_t

DQS0_c

DQ [3:0]

DQS1_t

DQS1_c

DQ [11:8]

DQS2_t

DQS2_c

DQ [19:16]

DQS3_t

DQS3_c

DQ [27:24]

DQS_t DQS_c DQ [3:0]

D17

DQS_t DQS_c DQ [3:0]

D16

DQS_t DQS_c DQ [3:0]

D15

DQS_t DQS_c DQ [3:0]

D14

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS4_t

DQS4_c

DQ [35:32]

DQS5_t

DQS5_c

DQ [43:40]

DQS6_t

DQS6_c

DQ [51:48]

DQS7_t

DQS7_c

DQ [59:56]

DQS_t DQS_c DQ [3:0]

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS13_t DQS13_c

DQ [39:36]

DQS14_t DQS14_c

DQ [47:44]

DQS15_t DQS15_c

DQ [55:52]

DQS16_t DQS16_c

DQ [63:60]

DQS_t DQS_c DQ [3:0]

D10

DQS_t DQS_c DQ [3:0]

D11

DQS_t DQS_c DQ [3:0]

D12

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS17_t DQS17_c

CB [7:4]

DQS_t DQS_c DQ [3:0]

ZQ VSS

CKE

ODT

CS_n

DQS8_t DQS8_c

CB [3:0]

DQS_t DQS_c DQ [3:0]

D13

ZQ VSS

CKE

ODT

CS_n

SA0

Serial PD with Thermal sensor

SA1

SA0 SA1

SCL

EVENT_n

SA2

EVENT_n

SCL

SDA

SA0 SA1

SA0

SA1

BFUNC

SA2

VSS

SCL

SDA

Ω

RCD

Rev. 1.7 / Jun.2016 15

Page 16

8GB, 1Gx72 Module(1Rank of x4) - page2

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs

C[2:0]

ACT_n

BG[1:0]

BA[1:0]

A[17:0]

PARITY

CKE0

ODT0

CS0_n

CK0_t

CK0_c

BG[1:0]A -> BG[1:0]: SDRAMs D[4:0], D[17:13] BG[1:0]B -> BG[1:0]: SDRAMs D[8:5], D[12:9]

CKE0B -> CKE: SDRAMs D[8:5], D[12:9]

A[17:0]B -> A[17:0]: SDRAMs D[8:5], D[12:9]

A[17:0]A -> A[17:0]: SDRAMs D[4:0], D[17:13]

CKE0A -> CKE: SDRAMs D[4:0], D[17:13]

ODT0B -> ODT: SDRAMs D[8:5], D[12:9]

ODT0A -> ODT: SDRAMs D[4:0], D[17:13]

CS0B_n -> CS_n: SDRAMs D[8:5], D[12:9]

CS0A_n -> CS_n: SDRAMs D[4:0], D[17:13]

Y0_C -> CK_C: SDRAMs D[8:5], D[12:9]

Y0_t -> CK_t: SDRAMs D[8:5], D[12:9]

RESET_n QRST_n -> RESET_n: All SDRAMs

T E

PARB -> PAR: SDRAMs D[8:5], D[12:9]

PARA -> PAR: SDRAMs D[4:0], D[17:13]

BA[1:0]A -> BA[1:0]: SDRAMs D[4:0], D[17:13] BA[1:0]A -> BA[1:0]: SDRAMs D[8:5], D[12:9]

CK1_t

CK1_c

Note:

1. CK0_t, CK0_c terminated with 120Ω±5% resistor.

2. CK1_t, CK1_c terminated with 120

Ω±5% resistor but not used.

3. Unless otherwise noted resistors are 22

Ω±5%.

4. Register input CS1_n is tied to VDD. Register inputs ODT1 and CKE1 are tied to VSS.

ACTB_n -> ACT_n: SDRAMs D[8:5], D[12:9]

ACTA_n -> ACT_n: SDRAMs D[4:0], D[17:13]

I S

Y1_t -> CK_t: SDRAMs D[4:0], D[17:13]

Y1_C -> CK_C: SDRAMs D[4:0], D[17:13]

C[2:0]B -> C[2:0]: SDRAMs D[8:5], D[12:9]

C[2:0]A -> C[2:0]: SDRAMs D[4:0], D[17:13]

Rev. 1.7 / Jun.2016 16

Page 17

DQS0_t

DQS0_c

DQ [3:0]

DQS1_t

DQS1_c

DQ [11:8]

DQS2_t

DQS2_c

DQ [19:16]

DQS3_t

DQS3_c

DQ [27:24]

DQS8_t

DQS8_c

CB [3:0]

DQS_t DQS_c DQ [3:0]

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. DRAM TEN pin need to be tied to VSS.

CKE

ODT

CS_n

VSS

QACS1_n

QAODT1

QACKE1

DQS_t DQS_c DQ [3:0]

D15

DQS_t DQS_c DQ [3:0]

D16

DQS_t DQS_c DQ [3:0]

D17

DQS_t DQS_c DQ [3:0]

D18

DQS_t DQS_c DQ [3:0]

D19

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS9_t

DQS9_c

DQ [7:4]

DQS10_t

DQS10_c

DQ [15:12]

DQS11_t

DQS11_c

DQ [23:20]

DQS12_t

DQS12_c

DQ [31:28]

DQS17_t

DQS17_c

CB [7:4]

DQS_t DQS_c DQ [3:0]

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [3:0]

D10

DQS_t DQS_c DQ [3:0]

D11

DQS_t DQS_c DQ [3:0]

D12

DQS_t DQS_c DQ [3:0]

D13

DQS_t DQS_c DQ [3:0]

D14

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

QACS0_n

QAODT0

QACKE0

16GB, 2Gx72 Module(2Rank of x4) - TF page1

Rev. 1.7 / Jun.2016 17

Page 18

DQS4_t

DQS4_c

DQ [35:32]

DQS5_t

DQS5_c

DQ [43:40]

DQS6_t

DQS6_c

DQ [51:48]

DQS7_t

DQS7_c

DQ [59:56]

DQS_t DQS_c DQ [3:0]

D14

DQS_t DQS_c DQ [3:0]

D25

DQS_t DQS_c DQ [3:0]

D26

DQS_t DQS_c DQ [3:0]

D27

D0–D35

DDSPD

D0–D35

VREFCA

SPD

D0–D35

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. DRAM TEN pin need to be tied to VSS.

CKE

ODT

CS_n

VSS

QBCS1_n

QBODT1

QBCKE1

DQS_t DQS_c DQ [3:0]

D32

DQS_t DQS_c DQ [3:0]

D33

DQS_t DQS_c DQ [3:0]

D34

DQS_t DQS_c DQ [3:0]

D35

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS13_t

DQS13_c

DQ [39:36]

DQS14_t

DQS14_c

DQ [47:44]

DQS15_t

DQS15_c

DQ [55:52]

DQS16_t

DQS16_c

DQ [63:60]

DQS_t DQS_c DQ [3:0]

D20

DQS_t DQS_c DQ [3:0]

D21

DQS_t DQS_c DQ [3:0]

D22

DQS_t DQS_c DQ [3:0]

D23

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [3:0]

D28

DQS_t DQS_c DQ [3:0]

D29

DQS_t DQS_c DQ [3:0]

D30

DQS_t DQS_c DQ [3:0]

D31

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

QBCS0_n

QBODT0

QBCKE0

SA0

Serial PD with Thermal sensor

SA1

SA0 SA1

SCL

EVENT_n

SA2

EVENT_n

SCL

SDA

SA0 SA1

SA0

SA1

BFUNC

SA2

VSS

SCL

SDA

Ω

RCD

16GB, 2Gx72 Module(2Rank of x4) - TF page2

Rev. 1.7 / Jun.2016 18

Page 19

16GB, 2Gx72 Module(2Rank of x4) - TF page3

ACT_n

QBACT_n -> ACT_n: SDRAMs D[35:20]

QAACT_n -> ACT_n: SDRAMs D[19:0]

C[2:0]

QBC[2:0] -> C[2:0]: SDRAMs D[35:20]

QAC[2:0] -> C[2:0]: SDRAMs D[19:0]

CKE1

QBCKE1 -> CKE: SDRAMs D[35:28]

QACKE1 -> CKE: SDRAMs D[19:10]

ODT1

QBODT1 -> ODT: SDRAMs D[35:28]

QAODT1 -> ODT: SDRAMs D[19:10]

CS1_n

QBCS1_n -> CS1_n: SDRAMs D[35:28]

QACS1_n -> CS1_n: SDRAMs D[19:10]

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs

BG[1:0]

BA[1:0]

A[17:0]

PARITY

CKE0

ODT0

CS0_n

CK0_t

CK0_c

QABG[1:0] -> BG[1:0]: SDRAMs D[19:0] QBBG[1:0] -> BG[1:0]: SDRAMs D[35:20]

QBCKE0 -> CKE: SDRAMs D[27:20]

QBA[17:0] -> A[17:0]: SDRAMs D[35:20]

QAA[17:0] -> A[17:0]: SDRAMs D[19:0]

QACKE0 -> CKE: SDRAMs D[9:0]

QBODT0 -> ODT: SDRAMs D[27:20]

QAODT0 -> ODT: SDRAMs D[9:0]

QBCS0_n -> CS0_n: SDRAMs D[27:20]

QACS0_n -> CS_n: SDRAMs D[9:0]

Y0_t -> CK_t: SDRAMs D[23:20], D[31:28]

RESET_n QRST_n -> RESET_n: All SDRAMs

R E

I S T E R

QBPAR -> PAR: SDRAMs D[35:20]

QAPAR -> PAR: SDRAMs D[19:0]

QABA[1:0] -> BA[1:0]: SDRAMs D[19:0] QBBA[1:0] -> BA[1:0]: SDRAMs D[35:20]

CK1_t

CK1_c

Note:

1. CK0_t, CK0_c terminated with 120Ω±5% resistor.

2. CK1_t, CK1_c terminated with 120

Ω±5% resistor but not used.

3. Unless otherwise noted resistors are 22

Ω±5%.

Y1_t -> CK_t: SDRAMs D[4:0],D[14:10] Y2_t -> CK_t: SDRAMs D[27:24], D[35:32] Y3_t -> CK_t: SDRAMs D[9:5], D[19:15]

Y0_c -> CK_c: SDRAMs D[23:20], D[31:28] Y1_c -> CK_c: SDRAMs D[4:0],D[14:10] Y2_c -> CK_c: SDRAMs D[27:24], D[35:32] Y3_c -> CK_c: SDRAMs D[9:5], D[19:15]

Rev. 1.7 / Jun.2016 19

Page 20

DQS0_t

DQS0_c

DQ [3:0]

DQS1_t

DQS1_c

DQ [11:8]

DQS2_t

DQS2_c

DQ [19:16]

DQS3_t

DQS3_c

DQ [27:24]

DQS8_t

DQS8_c

CB [3:0]

DQS_t DQS_c DQ [3:0]

D10

DQS_t DQS_c DQ [3:0]

D11

DQS_t DQS_c DQ [3:0]

D12

DQS_t DQS_c DQ [3:0]

D17

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. DRAM TEN pin need to be tied to VSS.

5. VDDSPD also connects to the register (RCD).

6. VREFCA from the edge connector only connects with the register (RCD). The RCD sources a separate VREFCA to all the SDRAMs.

CKE

ODT

CS_n

VSS

QACS1_n

QAODT1

QACKE1

DQS_t DQS_c DQ [3:0]

D27

DQS_t DQS_c DQ [3:0]

D28

DQS_t DQS_c DQ [3:0]

D29

DQS_t DQS_c DQ [3:0]

D30

DQS_t DQS_c DQ [3:0]

D35

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS9_t

DQS9_c

DQ [7:4]

DQS10_t

DQS10_c

DQ [15:12]

DQS11_t

DQS11_c

DQ [23:20]

DQS12_t

DQS12_c

DQ [31:28]

DQS17_t

DQS17_c

CB [7:4]

DQS_t DQS_c DQ [3:0]

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [3:0]

D18

DQS_t DQS_c DQ [3:0]

D19

DQS_t DQS_c DQ [3:0]

D20

DQS_t DQS_c DQ [3:0]

D21

DQS_t DQS_c DQ [3:0]

D26

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

QACS0_n

QAODT0

QACKE0

16GB, 2Gx72 Module(2Rank of x4) - UH page1

Rev. 1.7 / Jun.2016 20

Page 21

DQS4_t

DQS4_c

DQ [35:32]

DQS5_t

DQS5_c

DQ [43:40]

DQS6_t

DQS6_c

DQ [51:48]

DQS7_t

DQS7_c

DQ [59:56]

DQS_t DQS_c DQ [3:0]

D13

DQS_t DQS_c DQ [3:0]

D14

DQS_t DQS_c DQ [3:0]

D15

DQS_t DQS_c DQ [3:0]

D16

D0–D35

DDSPD

D0–D35

VREFCA

SPD

D0–D35

Note:

1. Unless otherwize noted, resistor values are 15Ω±5%.

2. See the Net Structure diagrams for all resistor associated with the command, address and control bus.

3. ZQ resistors are 240

Ω±1%.For all other resistor values refer to the appropriate wiring diagram.

4. DRAM TEN pin need to be tied to VSS.

5. VDDSPD also connects to the register (RCD).

6. VREFCA from the edge connector only connects with the register (RCD). The RCD sources a separate VREFCA to all the SDRAMs.

CKE

ODT

CS_n

VSS

QBCS1_n

QBODT1

QBCKE1

DQS_t DQS_c DQ [3:0]

D31

DQS_t DQS_c DQ [3:0]

D32

DQS_t DQS_c DQ [3:0]

D33

DQS_t DQS_c DQ [3:0]

D34

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

DQS13_t

DQS13_c

DQ [39:36]

DQS14_t

DQS14_c

DQ [47:44]

DQS15_t

DQS15_c

DQ [55:52]

DQS16_t

DQS16_c

DQ [63:60]

DQS_t DQS_c DQ [3:0]

CKE

ODT

CS_n

VSS

DQS_t DQS_c DQ [3:0]

D22

DQS_t DQS_c DQ [3:0]

D23

DQS_t DQS_c DQ [3:0]

D24

DQS_t DQS_c DQ [3:0]

D25

CKE

ODT

CS_n

VSS

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

CKE

ODT

CS_n

QBCS0_n

QBODT0

QBCKE0

SA0

Serial PD with Thermal sensor

SA1

SA0 SA1

SCL

EVENT_n

SA2

EVENT_n

SCL

SDA

SA0 SA1

SA0

SA1

BFUNC

SA2

VSS

SCL

SDA

Ω

RCD

16GB, 2Gx72 Module(2Rank of x4) - UH page2

Rev. 1.7 / Jun.2016 21

Page 22

16GB, 2Gx72 Module(2Rank of x4) - UH page3

ACT_n

QBACT_n -> ACT_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

QAACT_n -> ACT_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

C[2:0]

QBC[2:0] -> C[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

QAC[2:0] -> C[2:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

CKE1

QBCKE1 -> CKE: SDRAMs D[25:22], D[34:31]

QACKE1 -> CKE: SDRAMs D[21:18], D[30:26], D35

ODT1

QBODT1 -> ODT: SDRAMs D[25:22], D[34:31]

QAODT1 -> ODT: SDRAMs D[21:18], D[30:26], D35

CS1_n

QBCS1_n -> CS_n: SDRAMs D[25:22], D[34:31]

QACS1_n -> CS_n: SDRAMs D[21:18], D[30:26], D35

ALERT_n ERROR_IN_n <- ALERT_n: All SDRAMs

BG[1:0]

BA[1:0]

A[17:0]

PARITY

CKE0

ODT0

CS0_n

CK0_t

CK0_c

QABG[1:0] -> BG[1:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 QBBG[1:0] -> BG[1:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

QBCKE0 -> CKE: SDRAMs D[7:4], D[16:13]

QBA[17:0] -> A[17:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

QAA[17:0] -> A[17:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

QACKE0 -> CKE: SDRAMs D[3:0], D[12:8], D17

QBODT0 -> ODT: SDRAMs D[7:4], D[16:13]

QAODT0 -> ODT: SDRAMs D[3:0], D[12:8], D17

QBCS0_n -> CS_n: SDRAMs D[7:4], D[16:13]

QACS0_n -> CS_n: SDRAMs D[3:0], D[12:8], D17

Y0_t -> CK_t: SDRAMs D[7:4], D[25:22]

RESET_n QRST_n -> RESET_n: All SDRAMs

R E

I S T E R

QBPAR -> PAR: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

QAPAR -> PAR: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35

QABA[1:0] -> BA[1:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 QBBA[1:0] -> BA[1:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

CK1_t

CK1_c

Note:

1. CK0_t, CK0_c terminated with 120Ω±5% resistor.

2. CK1_t, CK1_c terminated with 120

Ω±5% resistor but not used.

3. Unless otherwise noted resistors are 22

Ω±5%.

Y1_t -> CK_t: SDRAMs D[3:0], D8, D[21:18], D26 Y2_t -> CK_t: SDRAMs D[16:13], D[34:31] Y3_t -> CK_t: SDRAMs D[12:9], D17, D[30:27], D35

Y0_c -> CK_c: SDRAMs D[7:4], D[25:22] Y1_c -> CK_c: SDRAMs D[3:0], D8, D[21:18], D26 Y2_c -> CK_c: SDRAMs D[16:13], D[34:31] Y3_c -> CK_c: SDRAMs D[12:9], D17, D[30:27], D35

Rev. 1.7 / Jun.2016 22

Page 23

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol Parameter Rating Units NOTE

VDD

VDDQ

VPP

IN, VOUT

STG

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV

4. VPP must be equal or greater than VDD/VDDQ at all times

5. Overshoot area above 1.5V is specified in DDR4 Device Operation.

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VPP pin relative to Vss

Voltage on any pin except VREFCA relative to Vss

Storage Temperature

-0.3 ~ 1.5 V 1,3

-0.3 ~ 3.0 V 4

-0.3 ~ 1.5 V 1,3,5

-55 to +100 °C 1,2

DRAM Component Operating Temperature Range

Temperature Range

Symbol Parameter Rating Units Notes

OPER

Notes:

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:

Normal Operating Temperature Range

Extended Temperature Range

a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is

also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability

0 to 85

85 to 95

C under all operating conditions.

b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use

the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

C 1,2

C1,3

C and 95oC

Rev. 1.7 / Jun.2016 23

Page 24

AC & DC Operating Conditions

Recommended DC Operating Conditions

Symbol Parameter

VDD Supply Voltage 1.14 1.2 1.26 V 1,2,3

VDDQ Supply Voltage for Output 1.14 1.2 1.26 V 1,2,3

VPP Supply Voltage for DRAM Activating 2.375 2.5 2.75 V 3

NOTE:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. DC bandwidth is limited to 20MHz.

Min. Typ. Max.

Rating

Unit NOTE

Rev. 1.7 / Jun.2016 24

Page 25

AC & DC Input Measurement Levels

AC & DC Logic input levels for single-ended signals

Single-ended AC & DC input levels for Command and Address

DDR4-1600/1866/2133/

Symbol Parameter

2400

Min. Max. Min. Max.

IH.CA

IL.CA

IH.CA

IL.CA

REFCA

(DC75)

(AC100)

(DC)

DC input logic high

DC input logic low VSS

AC input logic high

AC input logic low Note 2

Reference Voltage for

ADD, CMD inputs

REFCA

0.075

VDD TBD TBD V

REFCA

0.075

REF

+ 0.1

Note 2 TBD TBD V 1

- 0.1

REF

0.49*VDD 0.51*VDD TBD TBD V 2,3

NOTE :

1. See “Overshoot and Undershoot Specifications”

2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

3. For reference : approx. VDD/2 ± 12mV

DDR4-2666/3200

Unit NOTE

TBD TBD V

TBD TBD V 1

Rev. 1.7 / Jun.2016 25

Page 26

AC and DC Input Measurement Levels: V

voltage

time

Tolerances

REF

The DC-tolerance limits and ac-noise limits for the reference voltages V It shows a valid reference voltage V

(DC) is the linear average of V

REF

meet the min/max requirement in Table X. Furthermore V no more than ± 1% V

(t) as a function of time. (V

REF

(t) over a very long period of time (e.g. 1 sec). This average has to

REF

(t) may temporarily deviate from V

is illustrated in Figure below.

REFCA

stands for V

REFCA

REF

(DC) by

Illustration of V

(DC) tolerance and V

REF

AC-noise limits

REF

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on V

" shall be understood as V

REF

This clarifies, that DC-variations of V

REF

(DC), as defined in Figure above.

REF

affect the absolute voltage a signal has to reach to achieve a valid

REF

high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V

(DC) deviations from the optimum position within the data-eye of the

REF

input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V

ified limit (+/-1% of V

AC-noise. Timing and voltage effects due to AC-noise on V

REF

) are included in DRAM timings and their associated deratings.

up to the spec-

REF

Rev. 1.7 / Jun.2016 26

Page 27

AC and DC Logic Input Levels for Differential Signals

0.0

tDVAC

.DIFF.MIN

half cycle

Differential Input Voltage (CK-CK)

time

tDVAC

VIH.DIFF.AC.MIN

.DIFF.MAX

.DIFF.AC.MAX

(CK_t - CK_c)

Differential signal definition

NOTE:

1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.

2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.

Definition of differential ac-swing and “time above ac-level” t

DVAC

Rev. 1.7 / Jun.2016 27

Page 28

Differential swing requirements for clock (CK_t - CK_c)

Differential AC and DC Input Levels

Symbol Parameter

IHdiff

ILdiff

IHdiff

ILdiff

differential input high +0.150 NOTE 3 TBD NOTE 3 V 1

differential input low NOTE 3 -0.150 NOTE 3 TBD V 1

(AC)

differential input high ac

(AC)

differential input low ac NOTE 3

DDR4 -1600,1866,2133 DDR4 -2400,2666 & 3200

min max min max

2 x (V

REF

(AC) -

)

NOTE 3

2 x (VIL(AC) -

)

REF

2 x (V

(AC) -

REF

NOTE 3

)

NOTE 3 V 2

2 x (VIL(AC) -

REF

)

unit NOTE

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK_t - CK_c use V

IH.CA/VIL.CA

(AC) of ADD/CMD and V

REFCA

;

3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (V

(DC) max, V

IH.CA

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.

IL.CA

Allowed time before ringback (tDVAC) for CK_t - CK_c

Slew Rate [V/ns]

tDVAC [ps] @ |V

min max min max

> 4.0 120 - TBD -

4.0 115 - TBD -

3.0 110 - TBD -

2.0 105 - TBD -

1.8 100 - TBD -

1.6 95 - TBD -

1.4 90 - TBD -

1.2 85 - TBD -

1.0 80 - TBD -

< 1.0 80 - TBD -

(AC)| = 200mV tDVAC [ps] @ |V

IH/Ldiff

(AC)| = TBDmV

IH/Ldiff

Rev. 1.7 / Jun.2016 28

Page 29

Single-ended requirements for differential signals

VDD or V

DDQ

SEH

min

/2 or V

DDQ

SEL

max

SEH

VSS or V

SSQ

SEL

time

Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.

CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.

Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c

Single-ended requirement for differential signals

Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

Rev. 1.7 / Jun.2016 29

Page 30

Single-ended levels for CK_t, CK_c

Symbol Parameter

SEH

SEL

Single-ended high-level for

CK_t , CK_c

Single-ended low-level for

CK_t , CK_c

DDR4-1600/1866/2133 DDR4-2400/2666/3200

Min Max Min Max

(VDD/2)

+0.100

NOTE3

NOTE3 TBD NOTE3 V 1, 2

(VDD/2)-

0.100

NOTE3 TBD V 1, 2

Unit NOTE

NOTE :

1. For CK_t - CK_c use V

2. V

(AC)/VIL(AC) for ADD/CMD is based on V

IH.CA/VIL.CA

(AC) of ADD/CMD;

;

REFCA

3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits

(DC) max, V

IH.CA

(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.

IL.CA

Rev. 1.7 / Jun.2016 30

Page 31

Address and Control Overshoot and Undershoot specifications

Overshoot Area Between

Undershoot Area below VSS

VDD Absolute Max

Volts

(V)

1 tCK

VDD Absolute Max and VDD Max

Overshoot Area above VDD Absolute Max

AC overshoot/undershoot specification for Address, Command and Control pins

Specification

Parameter

Maximum peak amplitude above VDD Absolute Max allowed for overshoot area

Delta value between VDD Absolute Max and VDD Max allowed for overshoot area

Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBD V-ns

Maximum overshoot area per 1tCK Above Absolute Max

Maximum overshoot area per 1tCK Between Absolute Max

Maximum undershoot area per 1tCK Below VSS 0.2644 0.2265 0.1984 0.1762 TBD V-ns

(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)

DDR4-

1600

0.06 0.06 0.06 0.06 TBD V

0.24 0.24 0.24 0.24 TBD V

0.0083 0.0071 0.0062 0.0055 TBD V-ns

0.2550 0.2185 0.1914 0.1699 TBD V-ns

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

Unit

Address,Command and Control Overshoot and Undershoot Definition

Rev. 1.7 / Jun.2016 31

Page 32

Clock Overshoot and Undershoot Specifications

Overshoot Area Between

Undershoot Area below VSS

VDD Absolute Max

Volts

(V)

1 UI

VDD Absolute Max and VDD Max

Overshoot Area above VDD Absolute Max

AC overshoot/undershoot specification for Clock

Specification

Parameter

Maximum peak amplitude above VDD Absolute Max allowed for overshoot area

Delta value between VDD Absolute Max and VDD Max allowed for overshoot area

Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBD V

Maximum overshoot area per 1UI Above Absolute Max 0.0038 0.0032 0.0028 0.0025 TBD V-ns

Maximum overshoot area per 1UI Between Absolute Max

Maximum undershoot area per 1UI Below VSS 0.1144 0.0980 0.0858 0.0762 TBD V-ns

DDR4-

1600

0.06 0.06 0.06 0.06 TBD V

0.24 0.24 0.24 0.24 TBD V

0.1125 0.0964 0.0844 0.0750 TBD V-ns

(CK_t, Ck_c)

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

Unit

Clock Overshoot and Undershoot Definition

Rev. 1.7 / Jun.2016 32

Page 33

Data, Strobe and Mask Overshoot and Undershoot Specifications

Overshoot Area Between

VDDQ

Undershoot Area below Min absolute level of Vin, Vout

Max absolute level of Vin,Vout

VSSQ

Volts

(V)

1 UI

Max absolute level of Vin,Vout and VDDQ

Overshoot Area above Max absolute level of Vin,Vout

Undershoot Area Between Min absolute level of Vin,Vout and VSSQ

Min absolute level of Vin,Vout

AC overshoot/undershoot specification for Data, Strobe and Mask

Specification

Parameter

Maximum peak amplitude above Max absolute level of Vin,Vout

Overshoot area Between Max Absolute level of Vin, Vout and VDDQ Max

Undershoot area Between Min absolute level of Vin,Vout and VDDQ

Maximum peak amplitude below Min absolute level of Vin,Vout

Maximum overshoot area per 1UI Above Max absolute level of Vin,Vout

Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max

Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ

Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout

(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)

DDR4-

1600

0.16 0.16 0.16 0.16 TBD V

0.24 0.24 0.24 0.24 TBD V

0.30 0.30 0.30 0.30 TBD V

0.10 0.10 0.10 0.10 TBD V

0.0150 0.0129 0.0113 0.0100 TBD V-ns

0.1050 0.0900 0.0788 0.0700 TBD V-ns

0.0150 0.0129 0.0113 0.0100 TBD V-ns

DDR4-

1866

DDR4-

2133

DDR4-

2400

DDR4-

2666

Unit

Rev. 1.7 / Jun.2016 33

Data, Strobe and Mask Overshoot and Undershoot Definition

Page 34

Slew Rate Definitions

Delta TRdiff

Delta TFdiff

IHdiffmin

ILdiffmax

Differential Input Voltage(i,e, CK_t - CK_c)

Slew Rate Definitions for Differential Input Signals (CK)

Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table and Figure below.

Differential Input Slew Rate Definition

Description Defined by

Differential input slew rate for rising edge(CK_t - CK_c)

Differential input slew rate for falling edge(CK_t - CK_c)

NOTE: The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.

from to

ILdiffmax

IHdiffmin

ILdiffmax

[

IHdiffmin - VILdiffmax

[

IHdiffmin - VILdiffmax

] / DeltaTRdiff

] / DeltaTFdiff

Differential Input Slew Rate Definition for CK_t, CK_c

Rev. 1.7 / Jun.2016 34

Page 35

Slew Rate Definition for Single-ended Input Signals (CMD/ADD)

Delta TRsingle

Delta TFsingle

IHCA(AC) Min

IHCA(DC) Min

VREFCA(DC)

ILCA(DC) Max

ILCA(AC) Max

Single-ended Input Slew Rate definition for CMD and ADD

NOTE :

1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single

2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single

3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.

4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope

Rev. 1.7 / Jun.2016 35

Page 36

Differential Input Cross Point Voltage

Vix

CK_t

VDD/2

VSS

VDD

CK_c

Vix

VSEL

VSEH

To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS.

Vix Definition (CK)

Cross point voltage for differential input signals (CK)

Symbol Parameter

-Area of VSEH, VSEL

Differential Input Cross Point

VlX(CK)

Symbol Parameter

VlX(CK)

Rev. 1.7 / Jun.2016 36

Voltage relative to VDD/2 for

CK_t, CK_c

- Area of VSEH, VSEL TBD TBD TBD TBD

Differential Input Cross Point Voltage relative to VDD/2 for

CK_t, CK_c

VSEL =<

VDD/2 - 145mV

-120mV

TBD TBD TBD TBD

DDR4-1600/1866/2133

min max

VDD/2 - 145mV

=< VSEL =<

VDD/2 - 100mV

- (VDD/2 - VSEL) + 25mV

DDR4-2400/2666/3200

min max

VDD/2 + 100mV

=< VSEH =<

VDD/2 + 145mV

(VSEH - VDD/2)

- 25mV

VDD/2 + 145mV

=< VSEH

120mV

Page 37

CMOS rail to rail Input Levels

0.8*VDD

TR_RESET

tPW_RESET

0.7*VDD

0.3*VDD

0.2*VDD

CMOS rail to rail Input Levels for RESET_n

Parameter Symbol Min Max Unit NOTE

AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6

DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2

DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1

AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7

Rising time TR_RESET - 1.0 us 4

RESET pulse width tPW_RESET 1.0 - us 3,5

NOTE :

1. After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET,

otherwise, SDRAM may not be reset.

2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM

operation will not be guaranteed until it is reset asserting RESET_n signal LOW.

3. RESET is destructive to data contents.

4. No slope reversal(ringback) requirement during its level transition from Low to High.

5. This definition is applied only “Reset Procedure at Power Stable”.

6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.

7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings

RESET_n Input Slew Rate Definition

Rev. 1.7 / Jun.2016 37

Page 38

AC and DC Logic Input Levels for DQS Signals Differential signal definition

Definition of differential DQS Signal AC-swing Level

Differential swing requirements for DQS (DQS_t - DQS_c)

Differential AC and DC Input Levels for DQS

Symbol Parameter

VIHDiffPeak VIH.DIFF.Peak Voltage 186 Note2 TBD TBD TBD TBD mV 1

VILDiffPeak VIL.DIFF.Peak Voltage Note2 -186 TBD TBD TBD TBD mV 1

NOTE :

1. Used to define a differential signal slew-rate.

2. These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended signals.

Rev. 1.7 / Jun.2016 38

DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200

Min Max Min Max Min Max

Unit Note

Page 39

Peak voltage calculation method

The peak voltage of Differential DQS signals are calculated in a following equation.

VIH.DIFF.Peak Voltage = Max(f(t)) VIL.DIFF.Peak Voltage = Min(f(t)) f(t) = VDQS_t - VDQS_c

The Max(f(t)) or Min(f(t)) used t o determine the midpoint which to reference the +/-35% window of the exempt non-monotonic signaling shall be the samllest peak voltage observed in all ui’s.

Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling

Rev. 1.7 / Jun.2016 39

Page 40

Differential Input Cross Point Voltage

To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Tabel below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) ins measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid fo the DQS_t and DQS_c signals.

VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.

A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provieded the said ledge occurs within +/- 30% of the midpoint of either VID.DIFF.Peak Voltage (DQS_t rising) of VIL.DIFF.Peak Voltage (DQS_c rising), refer to Furure Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. Thath is, a falling transition’s horizontal tangent is derived from its negative slope to zero slope transition (point A in Fugure bloew) and a ringback’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure below) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point C in Figure below) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in Figure below) is not a valid horizontal tangent.

Vix Definition (DQS)

Rev. 1.7 / Jun.2016 40

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Cross point voltage for differential input signals

DDR4-

Symbol Parameter

Vix_DOS_ ratio

NOTE :

1. Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the

difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest

horizontal tangent below VDQSmid of the transitioning DQS signals.

2. VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs

drivers and paths are matched.

DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings

1600,1866,2133,2400

Min Max Min Max

-25TBDTBD%1,2

DDR4-2666,2933,3200

Unit Note



Rev. 1.7 / Jun.2016 41

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Differential Input Slew Rate Definition

Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure below.

NOTE :

1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.

2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.

Differential Input Slew Rate Definition for DQS_t, DQS_c

Description Defined by

Differential input slew rate for rising edge(DQS_t - DQS_c)

Differential input slew rate for falling edge(DQS_t - DQS_c)

From To

VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff

VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff

Differential Input Level for DQS_t, DQS_c

Symbol Parameter

VIHDiff_DQS Differential Input High 136 - 130 - TBD TBD mV

VILDiff_DQS Differential Input Low - -136 - -130 TBD TBD mV

Rev. 1.7 / Jun.2016 42

DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200

Min Max Min Max Min Max

Unit Note

Page 43

Differential Input Slew Rate for DQS_t, DQS_c

Symbol Parameter

SRIdiff

Differential Input Slew Rate

DDR4-1600,1866,2133 DDR4-2400 DDR4-2666,3200

Min Max Min Max Min Max

318318TBDTBDV/ns

Unit Note

Rev. 1.7 / Jun.2016 43

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AC and DC output Measurement levels

Single-ended AC & DC Output Levels

Single-ended AC & DC output levels

Symbol Parameter

(DC) DC output high measurement level (for IV curve linearity) 1.1 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.8 x V

(DC) DC output low measurement level (for IV curve linearity) 0.5 x V

(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x V

(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x V

DDR4-1600/1866/2133/

2400/2666/3200

NOTE :

1. The swing of ± 0.15 × V

is based on approximately 50% of the static single-ended output peak-to-peak swing

DDQ

with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = V

Differential AC & DC Output Levels

Differential AC & DC output levels

Symbol Parameter

(AC) AC differential output high measurement level (for output SR) +0.3 x V

OHdiff

(AC) AC differential output low measurement level (for output SR) -0.3 x V

OLdiff

NOTE :

1. The swing of ± 0.3 × V

a driver impedance of RZQ/7Ω and an effective test load of 50Ω to V

is based on approximately 50% of the static differential output peak-to-peak swing with

DDQ

= V

DDR4-1600/1866/

2133/2400/2666/3200

at each of the differential outputs.

DDQ

Units NOTE

DDQ

Units NOTE

DDQ

Rev. 1.7 / Jun.2016 44

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Single-ended Output Slew Rate

OH(AC)

OL(AC)

delta TRsedelta TFse

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V

OL(AC)

and V

for single ended signals as shown in Table and Figure below.

OH(AC)

Single-ended output slew rate definition

Description

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

Measured

From To

(AC) VOH(AC)

(AC) VOL(AC)

Defined by

(AC)-VOL(AC)] /

Delta TRse

(AC)-VOL(AC)] /

Delta TFse

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Single-ended Output Slew Rate Definition

Single-ended output slew rate

Parameter Symbol

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max

Units

Single ended output slew rate SRQse49494949TBDTBDTBDTBDV/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting

NOTE:

1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.

-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).

-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies

Rev. 1.7 / Jun.2016 45

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Differential Output Slew Rate

OHdiff

(AC)

OLdiff

(AC)

delta TRdiffdelta TFdiff

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table and Figure below.

Differential output slew rate definition

Description

Differential output slew rate for rising edge

Differential output slew rate for falling edge

Measured

From To

(AC) V

OLdiff

(AC) V

OHdiff

OLdiff

(AC)

OHdiff

Defined by

(AC)-V

OLdiff

Delta TRdiff

(AC)-V

OLdiff

Delta TFdiff

NOTE :

1. Output slew rate is verified by design and characterization, and may not be subject to production test.

Differential Output Slew Rate Definition

Differential output slew rate

(AC)] /

Parameter Symbol

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-3200

Min Max Min Max Min Max Min Max Min Max Min Max

Units

Differential output slew rate SRQdiff818818818818TBDTBDTBDTBDV/ns

Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting

Rev. 1.7 / Jun.2016 46

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Single-ended AC & DC Output Levels of Connectivity Test Mode

VOH(AC)

TR_output_CT

VTT 0.5 * VDDQ

VOL(AC)

TF_output_CT

Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.

Single-ended AC & DC output levels of Connectivity Test Mode

Symbol Parameter

(DC) DC output high measurement level (for IV curve linearity) 1.1 x V

(DC) DC output mid measurement level (for IV curve linearity) 0.8 x V

(DC) DC output low measurement level (for IV curve linearity) 0.5 x V

(DC) DC output below measurement level (for IV curve linearity) 0.2 x V

(AC) AC output high measurement level (for output SR) VTT + (0.1 x V

(AC) AC output below measurement level (for output SR) VTT - (0.1 x V

DDR4-1600/1866/2133/

2400/2666/3200

NOTE :

1. The effective test load is 50 terminated by VTT = 0.5 * VDDQ.

Differential Output Slew Rate Definition of Connectivity Test Mode

Unit Note

DDQ

)V1

DDQ

)V1

DDQ

Single-ended output slew rate of Connectivity Test Mode

Parameter Symbol

Output signal Falling time TF_output_CT - 10 ns/V

Output signal Rising time TR_output_CT - 10 ns/V

Rev. 1.7 / Jun.2016 47

DDR4-1600/1866/2133/2400/2666/3200

Min Max

Unit Note

Page 48

Standard Speed Bins

DDR4-1600 Speed Bins and Operations

Speed Bin DDR4-1600K

Unit NOTECL-nRCD-nRP 11-11-11

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write

delay time

tAA

tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

tRCD

PRE command period tRP

ACT to PRE command period tRAS 35 9 x tREFI ns 11

ACT to ACT or REF command

period

tRC

Normal Read DBI

CWL = 9

CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4

CWL = 9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3

Supported CL Settings 9,11,12 nCK 12,13

Supported CL Settings with read DBI 11,13,14 nCK 12

Supported CWL Settings 9,11 nCK

13.75

(13.50)

13.75

(13.50)

13.75

(13.50)

48.75

(48.50)

5,11

18.00 ns 11

- ns 11

1,2,3,4,10

,13

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DDR4-1866 Speed Bins and Operations

Speed Bin DDR4-1866M

Unit NOTECL-nRCD-nRP 13-13-13

Parameter Symbol min max

Internal read command to first

data

Internal read command to first

data with read DBI enabled

ACT to internal read or write delay

time

tAA

tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 11

tRCD

PRE command period tRP

ACT to PRE command period tRAS 34 9 x tREFI ns 11

ACT to ACT or REF command

period

tRC

Normal Read DBI

CWL = 9

CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CWL = 9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,6

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6

CL = 12 CL = 14 tCK(AVG) Reserved ns 1,2,3,4

CWL = 10,12

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3

Supported CL Settings 9,11,12,13,14 nCK 12,13

Supported CL Settings with read DBI 11,13,14 ,15,16 nCK 13

Supported CWL Settings 9,10,11,12 nCK

13.92

(13.50)

13.92

(13.50)

13.92

(13.50)

47.92

(47.50)

5,11

18.00 ns 11

- ns 11

1,2,3,4,10

,11

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DDR4-2133 Speed Bins and Operations

Speed Bin DDR4-2133P

Unit NOTECL-nRCD-nRP 15-15-15

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data

with read DBI enabled

ACT to internal read or write delay

time

tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 11

tRCD

PRE command period tRP

ACT to PRE command period tRAS 33 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CL = 9 CL = 11 tCK(AVG) 1.5 1.6 ns

CL = 10 CL = 12 tCK(AVG) Reserved ns 1,2,3,10

CWL = 9,11

CWL = 10,12

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,7

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,7

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7

CL = 14 CL = 17 tCK(AVG) Reserved ns 1,2,3,4

CWL = 11,14

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3

Supported CL Settings 9,11,12,13,14,15,16 nCK 12,13

Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK

Supported CWL Settings 9,10,11,12,14 nCK

14.06

(13.50)

14.06

(13.50)

14.06

(13.50)

47.06

(46.50)

5,11

18.00 ns 11

- ns 11

1,2,3,4,10,

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DDR4-2400 Speed Bins and Operations

Speed Bin DDR4-2400T

Unit NOTECL-nRCD-nRP 17-17-17

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data

with read DBI enabled

ACT to internal read or write delay

time

tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 11

tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 11

ACT to ACT or REF command period tRC

Normal Read DBI

CWL = 9

CL = 9

CL = 11

tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CWL = 9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,8

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,8

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CWL = 10,12

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,8

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,8

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CWL = 11,14

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,8

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,8

CL = 15 CL = 18 tCK(AVG) Reserved ns 1,2,3,4

CWL = 12,16

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK 12

Supported CL Settings with read DBI 12,14,16,18,19,20,21 nCK

Supported CWL Settings 9,10,11,12,14,16 nCK

14.16

(13.75)

14.16

(13.75)

14.16

(13.75)

46.16

(45.75)

5,11

18.00 ns 11

- ns 11

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DDR4-2666 Speed Bins and Operations

Speed Bin DDR4-2666V

Unit NOTECL-nRCD-nRP 19-19-19

Parameter Symbol min max

Internal read command to first data tAA

Internal read command to first data

with read DBI enabled

ACT to internal read or write delay

time

tAA_DBI tAA(min)+3nCK tAA(max)+3nCK ns 11

tRCD

PRE command period tRP

ACT to PRE command period tRAS 32 9 x tREFI ns 11

14.25

(13.75)

14.25

(13.75)

14.25

(13.75)

5,11

18.00 ns 11

- ns 11

ACT to ACT or REF command period tRC

46.25

(45.75)

5,11

- ns 11

Normal Read DBI

CWL = 9

CL = 9 CL = 11 tCK(AVG) Reserved ns 1,2,3,4,10

CL = 10 CL = 12 tCK(AVG) 1.5 1.6 ns 1,2,3,10

CL = 10 CL = 12 tCK(AVG) Reserved ns 4

CWL = 9,11

CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,9

CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,9

CL = 12 CL = 14 tCK(AVG) Reserved ns 4

CWL = 10,12

CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,9

CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,9

CL = 14 CL = 17 tCK(AVG) Reserved ns 4

CWL = 11,14

CL = 15 CL = 18 tCK(AVG) 0.937 <1.071 ns 1,2,3,4,9

CL = 16 CL = 19 tCK(AVG) 0.937 <1.071 ns 1,2,3,9

CL = 15 CL = 18 tCK(AVG) Reserved ns 4

CWL = 12,16

CL = 16 CL = 19 tCK(AVG) Reserved ns 1,2,3,4,9

CL = 17 CL = 20 tCK(AVG) 0.833 <0.937 ns 1,2,3,4,9

CL = 18 CL = 21 tCK(AVG) 0.833 <0.937 ns 1,2,3

CL = 17 CL = 20 tCK(AVG) Reserved ns 1,2,3,4

CWL = 14,18

CL = 18 CL = 21 tCK(AVG) Reserved ns 1,2,3,4

CL = 19 CL = 22 tCK(AVG) 0.75 <0.833 ns 1,2,3,4

CL = 20 CL = 23 tCK(AVG) 0.75 <0.833 ns 1,2,3

Supported CL Settings 10,11,12,13,14,15,16,17,18,19,20 nCK 12

Supported CL Settings with read DBI 12,13,14,15,17,18,19,20,21,22,23 nCK

Supported CWL Settings 9,10,11,12,14,16,18 nCK

Rev. 1.7 / Jun.2016 52

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Speed Bin Table Notes

Absolute Specification

- VDDQ = VDD = 1.20V +/- 0.06 V

- VPP = 2.5V +0.25/-0.125 V

- The values defined with above-mentioned table are DLL ON case.

- DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled.

1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as require ments from CWL setting.

2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next ‘Supported CL’, where tAA = 12.5ns and tCK(avg) = 1.3 ns should only be used for CL = 10 calculation.

3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported.

6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

10. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate.

11. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables.

12. CL number in parentheses, it means that these numbers are optional.

13. DDR4 SDRAM supports CL=9 as long as a system meets tAA(min).

14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.

Rev. 1.7 / Jun.2016 53

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IDD and IDDQ Specification Parameters and Test Conditions

IDD, IPP and IDDQ Measurement Conditions

In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure shows the setup and test load for IDD, IPP and IDDQ measurements.

• IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.

• IPP currents have the same definition as IDD except that the current on the VPP supply is measured.

• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ cur rents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.

For IDD, IPP and IDDQ measurements, the following definitions apply:

• “0” and “LOW” is defined as VIN <= VILAC(max).

• “1” and “HIGH” is defined as VIN >= VIHAC(min).

• “MID-LEVEL” is defined as inputs are VREF = VDD / 2.

• Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 1.

• Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 2.

• Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 11.

• IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting  RON = RZQ/7 (34 Ohm in MR1);  RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; Qoff = 0B (Output Buffer enabled) in MR1;

TDQS_t disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR5;

Gear down mode disabled in MR3 Read/Write DBI disabled in MR5; DM disabled in MR5

• Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.

• Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed.

• Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} ; apply invert of BG/BA changes when directed above.

Rev. 1.7 / Jun.2016 54

Page 55

NOTE:

RESET CK_t/CK_c

CKE CS

ACT,RAS,CAS,WE

A,BG,BA

ODT ZQ

DQS_t/DQS_c

DDR4 SDRAM

SSQ

DDQ

Application specific

memory channel

environment

Channel IO Powe

Simulatin

Channel IO Power

Number

IDDQ

TestLad

IDDQ

Simuaion

IDDQ

Measurement

Correlation

1. DIMM level Output test load condition may be different from above

Figure 1 - Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements

Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ

Measurement

Rev. 1.7 / Jun.2016 55

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Table 1 -Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns

Symbol

tCK 1.25 1.071 0.937 0.833 ns

CL 11 13 15 17 nCK

CWL 11 12 14 17 nCK

nRCD 11 13 15 17 nCK

nRC 39 45 51 56 nCK

nRAS 28 32 36 39 nCK

nRP 11 13 15 17 nCK

x4 16 16 16 16 nCK

nFAW

nRRDS

nRRDL

nRFC 2Gb 128 150 171 193 nCK

nRFC 4Gb 208 243 278 313 nCK

nRFC 8Gb 280 327 374 421 nCK

nRFC 16Gb TBD TBD TBD TBD nCK

x8 20 22 23 26 nCK

x16 28 28 32 36 nCK

x4 4 4 4 4 nCK

x8 4 4 4 4 nCK

x16 5 5 6 7 nCK

x4 5 5 6 6 nCK

x8 5 5 6 6 nCK

x16 6 6 7 8 nCK

tCCD_S 4 4 4 4 nCK

tCCD_L 5 5 6 6 nCK

tWTR_S 2 3 3 3 nCK

tWTR_L 6 7 8 9 nCK

DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400

11-11-11 13-13-13 15-15-15 17-17-17

Unit

Rev. 1.7 / Jun.2016 56

Page 57

Table 2 -Basic IDD, IPP and IDDQ Measurement Conditions

Symbol Description

Operating One Bank Active-Precharge Current (AL=0) CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 81; AL: 0; CS_n: High

IDD0

IDD0A

IPP0

IDD1

IDD1A

IPP1

IDD2N

IDD2NA

IPP2N

IDD2NT

IDDQ2NT

(Optional)

IDD2NL

IDD2NG

IDD2ND

between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode

Registers

; ODT Signal: stable at 0; Pattern Details: see Table 3

Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0

Operating One Bank Active-Precharge IPP Current Same condition with IDD0

Operating One Bank Active-Read-Precharge Current (AL=0) CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 81; AL: 0; CS_n: High

between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling according to Table 4; DM_n: stable at 1; Bank Activity: Cycling with one

bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and RTT: Enabled in Mode

Registers

; ODT Signal: stable at 0; Pattern Details: see Table 4

Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1

Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1

Precharge Standby Current (AL=0) CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 5

Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N

Precharge Standby IPP Current Same condition with IDD2N

Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 6; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: toggling according to Table 6; Pattern Details: see Table 6

Precharge Standby ODT IDDQ Current

Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current

Precharge Standby Current with CAL enabled

Same definition like for IDD2N, CAL enabled

Precharge Standby Current with Gear Down mode enabled

Same definition like for IDD2N, Gear Down mode enabled

Precharge Standby Current with DLL disabled

Same definition like for IDD2N, DLL disabled

Rev. 1.7 / Jun.2016 57

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IDD2N_par

IDD2P

IPP2P

IDD2Q

IDD3N

IDD3NA

IPP3N

IDD3P

IPP3P

IDD4R

IDD4RA

IDD4RB

IPP4R

IDDQ4R

(Optional)

IDDQ4RB

(Optional)

Precharge Standby Current with CA parity enabled

Same definition like for IDD2N, CA parity enabled

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:

Enabled in Mode Registers

; ODT Signal: stable at 0

Precharge Power-Down IPP Current Same condition with IDD2P

Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

; ODT

Signal: stable at 0 Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in

Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 5

Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N

Active Standby IPP Current Same condition with IDD3N

Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal:

stable at 0

Active Power-Down IPP Current Same condition with IDD3P

Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Tab l e 7 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal :

stable at 0; Pattern Details: see Table 7

Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R

Operating Burst Read Current with Read DBI Read DBI enabled3, Other conditions: see IDD4R

Operating Burst Read IPP Current Same condition with IDD4R

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

Rev. 1.7 / Jun.2016 58

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IDD4W

IDD4WA

IDD4WB

IDD4WC

IDD4W_par

IPP4W

IDD5B

IPP5B

IDD5F2

IPP5F2

IDD5F4

IPP5F4

IDD6N

IPP6N

IDD6E

IPP6E

Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Tab l e 8 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 8; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 8); Output Buffer and RTT: Enabled in Mode Registers stable at

HIGH; Pattern Details: see Table 8

; ODT Signal :

Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W

Operating Burst Write Current with Write DBI Write DBI enabled3, Other conditions: see IDD4W

Operating Burst Write Current with Write CRC Write CRC enabled3, Other conditions: see IDD4W

Operating Burst Write Current with CA Parity CA Parity enabled3, Other conditions: see IDD4W

Operating Burst Write IPP Current Same condition with IDD4W

Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 81; AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Tab l e 9 ; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 9); Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see

Tab l e 9

Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B

Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B

Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2

Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B

Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4

Self Refresh Current: Normal Temperature Range

: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock:

CASE

Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 8 Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; AL: 0; CS_n#, Command, Address, Bank Group

; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N

Self-Refresh Current: Extended Temperature Range

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock:

CASE

)

Off; CK_t and CK_c: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: MID-LEVEL

Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E

Rev. 1.7 / Jun.2016 59

Page 60

IDD6R

IPP6R

IDD6A

IPP6A

IDD7

IPP7

IDD8

IPP8

Self-Refresh Current: Reduced Temperature Range

: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low;

CASE

External clock: Off; CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity:

Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers

;

ODT Signal: MID-LEVEL Self Refresh IPP Current: Reduced Temperature Range

Same condition with IDD6R Auto Self-Refresh Current

: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4; CKE: Low; External c lock : Off;

CASE

CK_t and CK_c#: LOW; CL: see Table 1; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh

operation; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: MID-LEVEL

Auto Self-Refresh IPP Current Same condition with IDD6A

Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 1; BL: 81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 10; Data IO: read data bursts with different data between

one burst and the next one according to Table 10; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 10; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern Details: see Table 10

Operating Bank Interleave Read IPP Current Same condition with IDD7

Maximum Power Down Current TBD

Maximum Power Down IPP Current Same condition with IDD8

Rev. 1.7 / Jun.2016 60

Page 61

NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7

RTT_Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s

010] : 1866MT/s, 2133MT/s 011] : 2400MT/s Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate DLL disabled : set MR1 [A0 = 0] CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s 010] : 2400MT/s Read DBI enabled : set MR5 [A12 = 1] Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal

01] : Reduced Temperature range 10] : Extended Temperature range 11] : Auto Self Refresh

5. IDD2NG should be measured after sync pulse(NOP) input.

Rev. 1.7 / Jun.2016 61

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Table 3 - IDD0, IDD0A and IPP0 Measurement-Loop Pattern

CK_t /CK_c

CKE

Sub-Loop

Cycle

Number

Command

0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

1,2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

3,4

D_#,

D_#

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -

... repeat pattern 1...4 until nRC - 1, truncate if necessary

1*nRC

2*nRC

3*nRC

4*nRC

5*nRC

toggling

6*nRC

7*nRC

8*nRC

9*nRC

10*nRC

11*nRC

12*nRC

13*nRC

14*nRC

15*nRC

Static High

NOTE:

1 .DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead

CS_n

ACT_n

CAS_n/ A15

RAS_n/ A16

1 1 1 1 1 0 0

ODT

C[2:0]

WE_n/ A14

BA[1:0]

BG[1:0]

A12/BC_n

3 0 0 0 7 F 0 -

Data

A[9:7]

A[6:3]

A[2:0]

A[17,13,11]

A[10]/AP

For x4 and x8

only

Rev. 1.7 / Jun.2016 62

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Table 4 - IDD1, IDD1A and IPP1 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Command

CS_n

ACT_n

RAS_n/A16

CAS_n/A15

Cycle

Number

WE_n/A14

ODT

C[2:0]

BA[1:0]

BG[1:0]

A[9:7]

A12/BC_n

A[10]/AP

A[17,13,11]

A[6:3]

0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3, 4 D#, D# 1 1 1 1 1 0 0

3 0 0 0 7 F 0 -

... repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary nRCD -AL RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF

... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ... repeat pattern 1...4 until nRC - 1, truncate if necessary

1 1*nRC + 0 ACT 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 -

1*nRC + 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1*nRC + 3, 4 D#, D# 1 1 1 1 1 0 0

3 0 0 0 7 F 0 -

3 ... repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary 1*nRC + nRCD

RD 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 D0=FF, D1=00

- AL

... repeat pattern 1...4 until nRAS - 1, truncate if necessary

toggling

NOTE:

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4.Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ.

1*nRC + nRAS PRE 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 -

Static High

... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary

2 2*nRC

3 3*nRC

4 4*nRC

5 5*nRC

6 6*nRC

8 7*nRC

9 9*nRC

10 10*nRC

11 11*nRC

12 12*nRC

13 13*nRC

14 14*nRC

15 15*nRC

16 16*nRC

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead

Data

A[2:0]

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

For x4 and x8 only

Rev. 1.7 / Jun.2016 63

Page 64

Table 5 - IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P

Measurement-Loop Pattern1

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

CS_n

Command

ACT_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ODT

C[2:0]

BG[1:0]

BA[1:0]

A[9:7]

A12/BC_n

A[10]/AP

A[17,13,11]

A[6:3]

0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2 D#, D#1 1 1 1 1 0 0

3 0 0 0 7 F 0 0

Data

A[2:0]

3 D#, D#1 1 1 1 1 0 0

1 4-7

2 8-11

3 12-15

4 16-19

5 20-23

toggling

6 24-27

Static High

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

3 0 0 0 7 F 0 0

Rev. 1.7 / Jun.2016 64

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Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern1

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

0 0 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

1 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

2 D#, D# 1 1 1 1 1 0 0

3 D#, D# 1 1 1 1 1 0 0

1 4-7

2 8-11

3 12-15

4 16-19

5 20-23

6 24-27

toggling

7 28-31

Static High

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. DQ signals are VDDQ.

repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 1 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 0 instead

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

WE_n/A14

ODT

C[2:0]

BA[1:0]

BG[1:0]

3 0 0 0 7 F 0 -

Data

A[9:7]

A[6:3]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

For x4 and x8

only

Rev. 1.7 / Jun.2016 65

Page 66

Table 7 - IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

WE_n/A14

ODT

C[2:0]

0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF

1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

2,3 D#, D# 1 1 1 1 1 0 0

1 4 RD 0 1 1 0 1 0 0 1 1 0 0 0 7 F 0 D0=FF, D1=00

5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

6,7 D#, D# 1 1 1 1 1 0 0

2 8-11

3 12-15

4 16-19

toggling

Static High

5 20-23

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Read Command.

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

3 0 0 0 7 F 0 -

Data

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

For x4 and x8 only

Rev. 1.7 / Jun.2016 66

Page 67

Table 8 - IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

Cycle

Number

WE_n/A14

ODT

C[2:0]

0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF

1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -

2,3 D#, D# 1 1 1 1 1 1 0

1 4 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00

5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -

6,7 D#, D# 1 1 1 1 1 1 0

2 8-11

3 12-15

4 16-19

toggling

Static High

5 20-23

6 24-27

7 28-31

8 32-35

9 36-39

10 40-43

11 44-47

12 48-51

13 52-55

14 56-59

15 60-63

NOTE :

1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ.

2. BG1 is don’t care for x16 device

3. C[2:0] are used only for 3DS device

4. Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

A[9:7]

A[6:3]

BA[1:0]

BG[1:0]

A12/BC_n

A[10]/AP

A[17,13,11]

A[2:0]

3 0 0 0 7 F 0 -

Data

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

For x4 and x8 only

Rev. 1.7 / Jun.2016 67

Page 68

Table 9 - IDD4WC Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

0 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF

1,2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -

3,4 D#, D# 1 1 1 1 1 1 0 5 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00

6,7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 -

8,9 D#, D# 1 1 1 1 1 1 0

2 10-14

3 15-19

toggling

4 20-24

Static High

5 25-29

6 30-34

7 35-39

8 40-44

9 45-49

10 50-54

11 55-59

12 60-64

13 65-69

14 70-74

15 75-79

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Write Command.

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

ODT

WE_n/A14

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

3 0 0 0 7 F 0 -

A[10]/AP

A[9:7]

A[6:3]

A[2:0]

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

D8=CRC

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

D8=CRC

For x4 and x8 only

Data

Rev. 1.7 / Jun.2016 68

Page 69

Table 10 - IDD5B Measurement-Loop Patt ern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

0 0 REF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

3 D#, D# 1 1 1 1 1 0 0

4 D#, D# 1 1 1 1 1 0 0

toggling

Static High

4-7

8-11

12-15

16-19

20-23

24-27

28-31

32-35

36-39

40-43

44-47

48-51

52-55

56-59

60-63

repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 1 instead repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead

2 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. DQ signals are VDDQ.

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

WE_n/A14

ODT

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

3 0 0 0 7 F 0 - 3 0 0 0 7 F 0 -

A[10]/AP

A[9:7]

A[6:3]

Data

A[2:0]

For x4 and x8

only

Rev. 1.7 / Jun.2016 69

Page 70

Table 11 - IDD7 Measurement-Loop Pattern

CKE

CK_t, CK_c

Sub-Loop

Cycle

Number

0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -

1 RDA 0 1 1 0 1 0 0 0 0 0 1 0 0 0 D0=00, D1=FF

2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 D# 1 1 1 1 1 0 0

... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary

1 nRRD ACT 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 -

nRRD + 1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 D0=FF, D1=00

... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary

2 2*nRRD 3 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead

4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary

Command

CS_n

ACT_n

CAS_n/A15

RAS_n/A16

WE_n/A14

ODT

C[2:0]

BA[1:0]

BG[1:0]

A12/BC_n

A[17,13,11]

A[10]/AP

A[9:7]

A[6:3]

Data

A[2:0]

D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF

3 0 0 0 7 F 0 -

D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00

toggling

Static High

5 nFAW 6 nFAW + nRRD 7 nFAW + 2*nRRD 8 nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead

9 nFAW + 4*nRRD repeat Sub-Loop 4

10 2*nFAW 11 2*nFAW + nRRD 12 2*nFAW + 2*nRRD 13 2*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead

14 2*nFAW + 4*nRRD repeat Sub-Loop 4

15 3*nFAW 16 3*nFAW + nRRD 17 3*nFAW + 2*nRRD 18 3*nFAW + 3*nRRD

repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead

19 3*nFAW + 4*nRRD repeat Sub-Loop 4

20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary

NOTE :

1. DQS_t, DQS_c are VDDQ.

2. BG1 is don’t care for x16 device.

3. C[2:0] are used only for 3DS device.

4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ

For x4 and x8

only

Rev. 1.7 / Jun.2016 70

Page 71

IDD Specifications

Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power. The actual measurements may vary according to DQ loading cap.

4GB, 512M x 72 R-DIMM: HMA451R7AFR8N

Symbol

IDD0 6221564316mA

IDD0A 622 15 645 16 mA

IDD17161274513mA IDD1A 720 12 749 13 mA IDD2N49965136mA

IDD2NA54875717mA

IDD2NT53565576mA

IDD2NL 458 6 471 6 mA IDD2NG50265186mA IDD2ND49165046mA

IDD2NP 499 6 513 6 mA

IDD2P 301 6 313 6 mA IDD2Q49565096mA IDD3N59786218mA

IDD3NA59886218mA

IDD3P 383 8 400 8 mA

IDD4R1165812638mA IDD4RA1183812838mA IDD4RB1170812688mA

IDD4W1221813258mA IDD4WA1243813508mA IDD4WB1221813258mA IDD4WC1130812248mA IDD4WP1221813258mA

IDD5B 2014 286 2020 286 mA IDD5F2 2173 317 2178 320 mA IDD5F4 1728 229 1733 231 mA

IDD6N91159115mA

IDD6E 114 16 114 16 mA

IDD6R74117411mA

IDD6A 125 22 125 22 mA

IDD7 1502 87 1543 87 mA IDD8 39 16 39 16 mA

IDD IPP IDD IPP

2133 2400

unit note

Rev. 1.7 / Jun.2016 71

Page 72

8GB, 1G x 72 R-DIMM: HMA41GR7AFR8N

Symbol

IDD0 7452177422mA

IDD0A 795 22 835 23 mA

IDD18391887719mA IDD1A 893 19 939 19 mA IDD2N 622 12 645 12 mA

IDD2NA7211376113mA

IDD2NT6941273212mA

IDD2NL5401256112mA IDD2NG6291265512mA IDD2ND6071262612mA

IDD2NP6221264512mA

IDD2P 381 12 402 12 mA IDD2Q 614 12 637 12 mA IDD3N 819 16 860 16 mA

IDD3NA8201686116mA

IDD3P 545 16 576 16 mA

IDD4R128814139414mA IDD4RA 1356 15 1473 15 mA IDD4RB 1293 14 1400 14 mA

IDD4W134414145714mA IDD4WA 1416 15 1540 15 mA IDD4WB 1344 14 1457 14 mA IDD4WC 1254 14 1356 14 mA IDD4WP 1344 14 1457 14 mA

IDD5B 2137 292 2152 292 mA IDD5F2 2296 323 2310 326 mA IDD5F4 1851 235 1865 237 mA

IDD6N 177 30 177 30 mA

IDD6E 223 33 223 33 mA

IDD6R 142 22 142 22 mA

IDD6A 245 45 245 45 mA

IDD7 1626 93 1675 93 mA IDD8 73 32 73 32 mA

IDD IPP IDD IPP

2133 2400

unit note

Rev. 1.7 / Jun.2016 72

Page 73

8GB, 1G x 72 R-DIMM: HMA41GR7AFR4N

Symbol

IDD0 838 33 904 35 mA

IDD0A 838 33 909 34 mA

IDD1 964 27 1062 24 mA IDD1A 971 28 1076 29 mA IDD2N 622 13 645 13 mA

IDD2NA 721 15 761 15 mA

IDD2NT 694 13 732 13 mA

IDD2NL 540 14 561 14 mA IDD2NG 629 13 655 13 mA IDD2ND 607 14 626 14 mA

IDD2NP 622 13 645 13 mA

IDD2P 381 13 402 13 mA IDD2Q 614 13 637 13 mA IDD3N 819 18 860 18 mA

IDD3NA 820 18 861 18 mA

IDD3P 545 19 576 19 mA

IDD4R158818209718mA IDD4RA 1630 18 2138 18 mA IDD4RB 1637 18 2109 18 mA

IDD4W161219222319mA IDD4WA 1660 19 2272 19 mA IDD4WB 1658 19 2207 19 mA IDD4WC 1507 19 2020 19 mA IDD4WP 1612 19 2223 19 mA

IDD5B 3653 571 3658 571 mA IDD5F2 3970 634 3976 639 mA IDD5F4 3080 457 3085 461 mA

IDD6N 177 30 177 30 mA

IDD6E 223 33 223 33 mA

IDD6R 142 22 142 22 mA

IDD6A 245 45 245 45 mA

IDD7 2416 155 2832 200 mA IDD8 87 31 73 32 mA

IDD IPP IDD IPP

2133 2400

unit note

Rev. 1.7 / Jun.2016 73

Page 74

16GB, 2G x 72 R-DIMM: HMA42GR7AFR4N

Symbol

IDD0 1085 47 1168 48 mA

IDD0A118448128949mA

IDD1 1210 41 1326 41 mA IDD1A131643145744mA IDD2N 868 27 908 27 mA

IDD2NA 1067 30 1142 31 mA

IDD2NT 1013 26 1082 26 mA

IDD2NL 705 27 740 27 mA IDD2NG 883 27 929 27 mA IDD2ND 838 27 872 27 mA

IDD2NP 868 27 908 27 mA

IDD2P 542 27 579 27 mA IDD2Q 853 26 892 26 mA IDD3N126237133937mA

IDD3NA 1264 37 1340 37 mA

IDD3P 870 37 927 38 mA

IDD4R183432236132mA IDD4RA 1976 34 2518 34 mA IDD4RB 1883 32 2372 32 mA

IDD4W185832248632mA IDD4WA 2006 34 2652 34 mA IDD4WB 1904 32 2471 32 mA IDD4WC 1753 32 2284 32 mA IDD4WP 1858 32 2486 32 mA

IDD5B 3899 585 3922 585 mA IDD5F2 4216 647 4239 653 mA IDD5F4 3326 471 3349 475 mA

IDD6N 350 59 350 59 mA

IDD6E 440 66 440 66 mA

IDD6R 279 43 279 43 mA

IDD6A 485 89 485 89 mA

IDD7 2663 169 3095 213 mA IDD8 169 62 141 63 mA

IDD IPP IDD IPP

2133 2400

unit note

Rev. 1.7 / Jun.2016 74

Page 75

Module Dimensions

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pin 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

2.60

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

Registering

Clock Driver

SPD/TS

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

31.25

0.15

Detail F

512Mx72 - HMA451R7AFR8N

Rev. 1.7 / Jun.2016 75

Page 76

1Gx72 - HMA41GR7AFR8N-TF

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pin 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 76

Page 77

1Gx72 - HMA41GR7AFR8N-UH

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pin 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 77

Page 78

1Gx72 - HMA41GR7AFR4N-TF

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pin 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 78

Page 79

1Gx72 - HMA41GR7AFR4N-UH

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pin 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 79

Page 80

2Gx72 - HMA42GR7AFR4N-TF

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pi n 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 80

Page 81

2Gx72 - HMA42GR7AFR4N-UH

3.35

Detail E

2.10

64.60

56.10

2.70

0.15

Front

30.75

17.10

Back

133.35

129.55

1.40±0.1mm

Side

max

3.98mm max

Detail A

Note:

1. tolerance on all dimensions unless otherwise stated.

0.13

Units: millimeters

2x R0.60 Max

14.10

3.00

Pin 35 Pin 47

Pin 1

Pin 105 Pin 117

Detail B Detail D Detail C

8.00

11.00

Registering

Clock Driver

SPD/TS

0.85

0.60± 0.03

Detail of Contacts A, F

1.50 ±0.05

0.2

0.15

0.20 ±0.15

5.95

3.85

0.1

4.30

Detail of Contacts E

2.10

2.60

9.35

10.20

Detail of Contacts B

Pin 35 Pi n 47

2.10

2.60

9.35

10.20

Detail of Contacts C

Pin 117Pin 105

2.10

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

0.85

0.60± 0.03

Detail of Contacts D

Non-matarized keep out area

Max 0.30

Max 0.35

Max 0.25

31.25

0.15

Detail F

Rev. 1.7 / Jun.2016 81