C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are fully integrated mixed-signal System-on-a-Chip MCUs.
Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
•High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
•Internal low-frequency oscillator for additional pow
•Up to 64 kB of on-chip Flash memory
•Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
•External Memory Interface (EMIF) available on 48-pin versions.
•SMBus/I2C, up to 2 UARTs, and Enhanced SPI ser
•Four general-purpose 16-bit timers
•Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
tion
func
•On-chip Power-On Reset, V
•Up to 40 Port I/O (5 V tolerant)
Monitor, and Missing Clock Detector
DD
t flexible endpoint pipes, integrated trans-
C with analog multiplexer
er savings
ial interfaces implemented in hardware
With on-chip Power-On Reset,
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are truly stand-alone System-on-a-Chip solutions. The
Flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field
upgrades of the 8051 firmware. User software has comp lete contr ol of all perip he rals, and ma y in dividually
shut down any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) D
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
or voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for
F
USB com
4/5/6/7/8/9/A/B/C/D devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See
Table 1.1, “Product Selection Guide,” on page 18 for feature and package choices.
munication. The Port I/O and
VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
evelopment Interface allows non-intrusive (uses no on-chip
RST pins are tolerant of input signals up to 5 V. C8051F340/1/2/3/
Ambient temperature under bias–55125°C
Storage Temperature–65150°C
Voltage on any Port I/O Pin or RST
respect to GND
Voltage on V
Maximum Total current through V
GND
Maximum output current sunk by RST
Port pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to GND–0.34.2V
DD
DD
with
and
or any
–0.35.8V
500mA
100mA
24Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
3.Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
ParameterConditionsMinTypMaxUnits
Digital Supply Voltage
1
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)
2
C8051F340/1/2/3/A/B/C/D
C8051F344/5/6/7/8/9
Specified Operating
Temperature Range
Digital Supply Current - CPU Active (Normal Mode, accessing Flash)
I
DD
3
VDD = 3.3 V, SYSCLK = 48 MHz
= 3.3 V, SYSCLK = 24 MHz
V
DD
= 3.3 V, SYSCLK = 1 MHz
V
DD
= 3.3 V, SYSCLK = 80 kHz
V
DD
VRST3.33.6V
–40+85°C
1.5V
0
0
25.9
13.9
0.69
55
48
25
.5
28
15.7
MHz
mA
mA
mA
µA
= 3.6 V, SYSCLK = 48 MHz
V
DD
= 3.6 V, SYSCLK = 24 MHz
V
DD
Supply Sensitivity
I
DD
3,4
SYSCLK = 1 MHz,
relative to V
= 3.3 V
DD
SYSCLK = 24 MHz,
= 3.3 V
DD
Frequency Sensitivity
I
DD
3,5
relative to V
VDD = 3.3 V, SYSCLK < 30 MHz,
T = 25 ºC
= 3.3 V, SYSCLK > 30 MHz,
V
DD
T = 25 ºC
= 3.6 V, SYSCLK < 30 MHz,
V
DD
T = 25 ºC
= 3.6 V, SYSCLK > 30 MHz,
V
DD
T = 25 ºC
Digital Supply Current - CPU Inactive (Idle Mode, not accessing Flash)
3
I
DD
Supply Sensitivity
I
DD
3,4
VDD = 3.3 V, SYSCLK = 48 MHz
= 3.3 V, SYSCLK = 24 MHz
V
DD
= 3.3 V, SYSCLK = 1 MHz
V
DD
= 3.3 V, SYSCLK = 80 kHz
V
DD
= 3.6 V, SYSCLK = 48 MHz
V
DD
= 3.6 V, SYSCLK = 24 MHz
V
DD
SYSCLK = 1 MHz,
relative to V
= 3.3 V
DD
SYSCLK = 24 MHz,
relative to V
= 3.3 V
DD
29.7
15.9
47
46
0.69
0.44
0.80
0.50
16.6
8.25
0.44
35
18.6
9.26
41
39
32.3
18
18
9.34
20.9
10.5
.75
mA
mA
%/V
%/V
MHz
mA/
mA/MHz
mA/MHz
mA/MHz
mA
mA
mA
µA
mA
mA
%/V
%/V
Rev. 1.325
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 3.1. Global DC Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
ParameterConditionsMinTypMaxUnits
Frequency Sensitivity
I
DD
3,6
VDD = 3.3 V, SYSCLK < 1 MHz,
T = 25 ºC
= 3.3 V, SYSCLK > 1 MHz,
V
DD
T = 25 ºC
0.44
0.32
MHz
mA/
mA/MHz
= 3.6 V, SYSCLK < 1 MHz,
V
DD
0.49
mA/MHz
T = 25 ºC
= 3.6 V, SYSCLK > 1 MHz,
V
DD
0.36
mA/MHz
T = 25 ºC
Digital Supply Current (Stop
Mode, shutdown)
Digital Supply Current for USB
Module (USB Active Mode)
Digital Supply Current for USB
Module (USB Suspend Mode)
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on
4. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD
Supply Sensitivity. For example, if the VDD is 3.0 V instead of 3.3 V at 24 MHz: IDD = 13.9 mA typical at 3.3 V
and SYSCLK = 24 MHz. From this, I
= 24 MHz.
5. IDD can be estimated for frequencies < 30 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate I
be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.3 V; SYSCLK = 35 MHz, IDD = 13.9 mA – (24 MHz – 35 MHz) x 0.44 mA/MHz =
18.74 mA.
le IDD can be estimated for frequencies < 1 MHz by multiplying the frequency of interest by the frequency
6. Id
sensitivity number for that range. When using these numbers to estimate Idle IDD for > 1 MHz, the estimate
should be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency
sensitivity number. For example: V
0.32 mA/MHz = 2.17 mA.
device characterization of data; Not production tested.
Oscillator not running,
monitor disabled
V
DD
= 3.3 V, USB Clock = 48 MHz
V
DD
= 3.6 V, USB Clock = 48 MHz
V
DD
Oscillator not running
monitor disabled
V
DD
= 13.9 mA + 0.46 x (3.0 V – 3.3 V) = 13.76 mA at 3.0 V and SYSCLK
DD
= 3.3 V; SYSCLK = 5 MHz, Idle IDD = 8.25 mA – (24 MHz – 5 MHz) x
DD
< 0.1µA
8.69
9.59
< 0.1µA
for > 30 MHz, the estimate should
DD
mA
mA
Other electrical characteristics tables are fo und in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in
26Rev. 1.3
Table 3.2.
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 3.2. Index to Electrical Characteristics Tables
Table TitlePage No.
ADC0 Electrical Characteristics56
Voltage Reference Electrical Char
Comparator Electrical Characteristics68
Voltage Regulator Electrical Specifications69
Reset Electrical Characteristics106
Flash Electrical Ch
AC Parameters for Exter
Oscillator Electrical Characteristics141
Port I/O DC Electrical Characteristics158
USB Transceiver Electrical Characteristics187
aracteristics109
nal Memory Interface130
acteristics58
Rev. 1.327
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
4.Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Name
V
DD
GND73Ground.
RST/
C2CK
C2D14—D I/OBi-directional data signal for the C2 Debug Interface.
P3.0 /
C2D
REGIN117Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
VBUS128D InVBUS Sense Input. This pin should be connected to the
Pin Numbers
TypeDescription
48-pin 32-pin
106Power In
Power
Out
139D I/O
D I/O
—10D I/O
D I/O
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 11.
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 15 for a complete description of Port
3.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS signal
cates a USB network connection.
of a USB network. A 5 V signal on this pin indi-
D+84D I/OUSB D+.
D-95D I/OUSB D–.
P0.062D I/O or
A In
P0.151D I/O or
A In
P0.2432D I/O or
A In
P0.3331D I/O or
A In
P0.4230D I/O or
A In
P0.5129D I/O or
A In
P0.64828D I/O or
A In
P0.74727D I/O or
A In
Port 0.0. See Section 15 for a complete description of Port
0.
Port 0.1.
Port 0.2.
Port 0.3.
Port 0.4.
Port 0.5.
Port 0.6.
Port 0.7.
28Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued)
Name
P1.04626D I/O or
P1.14525D I/O or
P1.24424D I/O or
P1.34323D I/O or
P1.44222D I/O or
P1.54121D I/O or
P1.64020D I/O or
P1.73919D I/O or
P2.03818D I/O or
P2.13717D I/O or
Pin Numbers
TypeDescription
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 1.0. See Section 15 for a complete description of Port
1.
Port 1.1.
Port 1.2.
Port 1.3.
Port 1.4.
Port 1.5.
Port 1.6.
Port 1.7.
Port 2.0. See Section 15 for a complete description of Port
2.
Port 2.1.
P2.23616D I/O or
A In
P2.33515D I/O or
A In
P2.43414D I/O or
A In
P2.53313D I/O or
A In
P2.63212D I/O or
A In
P2.73111D I/O or
A In
P3.030—D I/O or
A In
P3.129—D I/O or
A In
P3.228—D I/O or
A In
Port 2.2.
Port 2.3.
Port 2.4.
Port 2.5.
Port 2.6.
Port 2.7.
Port 3.0. See Section 15 for a complete description of Port
3.
Port 3.1.
Port 3.2.
Rev. 1.329
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued)
Name
P3.327—D I/O or
P3.426—D I/O or
P3.525—D I/O or
P3.624—D I/O or
P3.723—D I/O or
P4.022—D I/O or
P4.121—D I/O or
P4.220—D I/O or
P4.319—D I/O or
P4.418—D I/O or
Pin Numbers
TypeDescription
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 3.3.
Port 3.4.
Port 3.5.
Port 3.6.
Port 3.7.
Port 4.0. See Section 15 for a complete description of Port
4.
Port 4.1.
Port 4.2.
Port 4.3.
Port 4.4.
P4.517—D I/O or
A In
P4.616—D I/O or
A In
P4.715—D I/O or
A In
Port 4.5.
Port 4.6.
Port 4.7.
30Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
VBUS
P2.2
P2.0
P1.7
P1.6
P1.2
P2.4
P2.3
P3.5
P3.4
P3.2
P3.1
P2.1
P0.6
P3.3
P0.7
P0.2
D-
REGIN
P0.3
P3.0
P1.4
P1.5
P0.5
P1.1
P1.0
P0.4
P1.3
13
14
15
16
17
18
19
20
21
22
23
24
P2.6
P2.5
C8051F340/1/4/5/8/C-GQ
Top View
GND
D+
P0.1
P0.0
VDD
P2.7
P3.6
P4.1
P4.0
P3.7
P4.2
P4.5
P4.4
P4.3
P4.6
RST / C2CK
C2D
P4.7
Figure 4.1. TQFP-48 Pinout Diagram (Top View)
Rev. 1.331
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.2. TQFP-48 Package Diagram
Table 4.2. TQFP-48 Package Dimensions
DimensionMinNomMax
A——1.20
A10.05—0.15
A20.951.001.05
b0.170.220.27
c0.09—0.20
D9.00 BSC
D17.00 BSC
e0.50 BSC
E9.00 BSC
E17.00 BSC
L0.450.600.75
aaa0.20
bbb0.20
ccc0.08
ddd0.08
0°3.5°7°
Notes:
1. All dimen
2. Dimensi
3. Thi
4. The
specification for Small Body Components.
sions shown are in millimeters (mm) unless otherwise noted.
oning and Tolerancing per ANSI Y14.5M-1994.
s drawing conforms to JEDEC outline MS-026, variation ABC.
recommended card reflow profile is per the JEDEC/IPC J-STD-020
32Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.3. TQFP-48 Recommended PCB Land Pattern
Table 4.3. TQFP-48 PCB Land Pattern Dimensions
DimensionMinMax
C18.308.40
C
28.308.40
E0.50 BSC
X10.200.30
Y11.401.50
Notes:
General:
1. All dimensions shown
his Land Pattern Design is based on the IPC-7351 guidelines.
2. T
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
ainless steel, laser-cut and electro-polished stencil with trapezoidal walls
4. A st
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
he ratio of stencil aperture to land pad size should be 1:1 for all pads.
6. T
Card Assembly:
7. A No-Cle
8. T
he recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
an, Type-3 solder paste is recommended.
are in millimeters (mm) unless otherwise noted.
Rev. 1.333
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
1
VBUS
P1.2
P1.7
P1.4
P1.3
P1.5D+
D-
GND
P0.1
P0.0
P2.0
P2.1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
P1.6
C8051F342/3/6/7/9/A/B/D-GQ
Top View
VDD
REGIN
RST / C2CK
P3.0 / C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P1.1
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
Figure 4.4. LQFP-32 Pinout Diagram (Top View)
34Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.5. LQFP-32 Package Diagram
Table 4.4. LQFP-32 Package Dimensions
DimensionMinNomMax
A——1.60
A10.05—0.15
A21.351.401.45
b0.300.370.45
Notes:
1. All dimen
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. Thi
4. The
c0.09—0.20
D9.00 BSC
D17.00 BSC
e0.80 BSC
E9.00 BSC
E17.00 BSC
L0.450.600.75
aaa0.20
bbb0.20
ccc0.10
ddd0.20
0°3.5°7°
sions shown are in millimeters (mm) unless otherwise noted.
s drawing conforms to JEDEC outline MS-026, variation BBA.
recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.335
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.6. LQFP-32 Recommended PCB Land Pattern
Table 4.5. LQFP-32 PCB Land Pattern Dimensions
DimensionMinMax
C18.408.50
C
28.408.50
E0.80 BSC
X10.400.50
Y11.251.35
Notes:
General:
1. All dimensions shown
his Land Pattern Design is based on the IPC-7351 guidelines.
2. T
Solder Mask Design:
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between
the solder mask and the metal pad is to be 60 µm minimum, all the way around
the pad.
Stencil Design:
ainless steel, laser-cut and electro-polished stencil with trapezoidal walls
4. A st
should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
he ratio of stencil aperture to land pad size should be 1:1 for all pads.
6. T
Card Assembly:
7. A No-Cle
8. T
he recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
an, Type-3 solder paste is recommended.
are in millimeters (mm) unless otherwise noted.
36Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
25P1.1
17P2.1
16P2.2
8VBUS
32
31
30
29
28
27
26
1
2
3
4
5
6
7
9
10
11
12
13
14
15
24
23
22
21
20
19
18
GND (optional)
C8051F342/3/6/7/9/A/B-GM
Top View
P1.0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
GND
D+
D-
VDD
REGIN
RST / C2CK
P3.0 / C2D
P2.7
P2.6
P2.5
P2.4
P2.3
P2.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
Figure 4.7. QFN-32 Pinout Diagram (Top View)
Rev. 1.337
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.8. QFN-32 Package Drawing
Table 4.6. QFN-32 Package Dimensions
DimensionMinNomMax
A0.800.91.00
A10.000.020.05
b0.180.250.30
D5.00 BSC
D23.203.303.40
e0.50 BSC
E5.00 BSC
E23.203.303.40
L0.300.400.50
Notes:
1. All dimensions shown
mensioning and T o lerancing per ANSI Y14.5M-1994.
2. Di
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
variation VHHD except for custom features D2, E2, and L which are
toleranced per supplier designation.
commended card reflow profile is per the JEDEC/IPC J-STD-020
4. Re
specification for Small Body Components.
are in millimeters (mm) unless otherwise noted.
38Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 4.6. QFN-32 Package Dimensions (Continued)
DimensionMinNomMax
L10.00—0.15
aaa——0.15
bb
b——0.10
ddd——0.05
eee——0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220,
variation VHHD except for custom features D2, E2, and L which are
toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Rev. 1.339
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Figure 4.9. QFN-32 Recommended PCB Land Pattern
Table 4.7. QFN-32 PCB Land Pattern Dimesions
DimensionMinMaxDimensionMinMax
C14.804.90X23.203.40
C24.804.90Y10.750.85
E0.50 BSCY23.203.40
X10.200.30
Notes:
General:
l dimensions shown are in millimeters (mm) unless otherwise noted.
1. Al
his Land Pattern Design is based on the IPC-7351 guidelines.
2. T
Solder Mask Design:
l metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
3. Al
mask and the metal pad is to be 60m minimum, all the way around the pad.
Stencil Design:
4. A st
5. Th
6. T
7. A
Card Assembly:
8. A No-Cl
9. T
ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
e stencil thickness should be 0.125 mm (5 mils).
he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
3x3 array of 1.0 mm openings on a 1.2mm pitch should be used for the center pad to assure
the proper paste volume.
ean, Type-3 solder paste is recommended.
he recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
The ADC0 subsystem for the C8051F34x devices consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated
ck-and-hold and programmable window detector. The AMUX0, data conversion modes, and window
tra
detector are all configured und er software control via the Special Function Regi sters shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages
t port pins, the Temperature Sensor output, or V
a
tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN
system is in low power shutdown when
this bit is logic 0.
with respect to a port pin, VREF, or GND. The connec-
DD
) is set to logic 1. The ADC0 sub-
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.341
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
5.1.Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be conn ected to
individual Port pins, the on-chip temperature sensor, or the positive power supply (V
input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the neg-
ative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential
Mo
de. The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Definition 5.1 and SFR Definition 5.2.
). The negative
DD
The conversion code format differs between Single-en
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left- justified , depending o n the setting of the AD0 LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10- bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
Input Voltage
Single-Ended)
(
VREF x 1023/10240x03FF0xFFC0
VREF x 512/10240x02000x8000
VREF x 256/10240x01000x4000
00x00000x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
uts are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus-
Inp
tified and left-justified data. For right-justified data, the
data word. For left-justified data, the unused LSBs in the ADC0L regi ster are set to ‘0’.
Input Voltage
(Differential)
VREF x 511/5120x01FF0x7FC0
VREF x 256/5120x01000x4000
00x00000x0000
–VREF x 256/5120xFF000xC000
–VREF 0xFE000x8000
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
ded and Differential modes. The registers ADC0H
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
unused MSBs of ADC0H are a sign-extension of the
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
Important Note About ADC0 Input Configuration: Por
ured as analog inputs, and should be skipped by the Dig
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See Section “15. Port Input/
Output” on page 142 for more Port I/O co
42Rev. 1.3
nfiguration details.
t pins selected as ADC0 inputs should be config-
ital Crossbar. To configure a Port pin for analog
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Temperature
Voltage
V
TEMP
= (Gain x TempC) + Offset
Offset (V at 0 Celsius)
Gain (V / deg C)
Temp
C
= (V
TEMP
- Offset) / Gain
5.2.Temperature Sensor
The temperature sensor transfer function is shown in Figure 5.2. The outp ut volt age (V
ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the
fset and Slope parameters can be found in Table 5.1.
Of
) is the positive
TEMP
Figure 5.2. Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extreme
surements (see Table 5.1 for linearity specifications). For absolute tem
or gain calibration is recommended. Typically a 1-point (of
Step 1. Control/measure the ambient temperatur
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the positive input
and GND selected as the negative input.
Step 4. Calculate the o ffset characteristics, and store this value in non-volatile memory for use
with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error
parameters which affect ADC measurement, in particular the voltage reference value, will also
ffect temperature measurement.
a
ly linear and suitable for relative temperature mea-
perature measurements, offset and/
fset) calibration includes the following steps:
e (this temperature must be known).
assuming a 1-point calibration at 25 °C. Note that
Rev. 1.343
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
-40.00-20.00
0.0
0
20.0
0
40.0
0
60.0
0
80.0
0
Temperature (degrees C)
Error (degrees C)
-5.00
-4.00
-3.00
-2.00
-1.00
0.0
0
1.0
0
2.0
0
3.0
0
4.0
0
5.0
0
-5.00
-4.00
-3.00
-2.00
-1.00
0.0
0
1.0
0
2.0
0
3.0
0
4.0
0
5.0
0
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
44Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
5.3.Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC + 1) for 0 AD0SC 31).
5.3.1. Starting a Conversion
A conversion can be initiated in one of five way s, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in registe r ADC0CN. Conversions may be initia ted by one of the following:
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed co
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
ntinuous conversions)
Writing a ‘1’ to AD0BUSY provides software contro
"on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is complete. The falling edge of A
interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag
(AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when
bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low
Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit
mode. See Section “21. Timers” on pag e 235 for timer configuration.
Important Note About Using CNVSTR: The
CNVSTR input is used as the ADC0 conversion source, the associated Port pin should be skipped by the
Digital Crossbar. To configure the Crossbar to skip a pin, se t the correspondin g bit in the PnSKIP regis ter
to ‘1’. See Section “15. Port Input/Output” on page 142 for details on Port I/O configuration.
D0BUSY triggers an interrupt (when enabled) and sets the ADC0
CNVSTR input pin also functions as a Port pin. When the
l of ADC0 whereby conversions are performed
Rev. 1.345
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
AD0TM=1
TrackConvertLow Power Mode
AD0TM=0
Track or
Convert
ConvertTrack
Low Po wer
or Convert
SAR Clocks
123456789101112
123456789
SAR Clocks
B. ADC0 Timing for Internal Trigger Source
123456789
CNVSTR
(AD0CM[2:0]=100)
AD0TM=1
A. ADC0 Timing for External Trigger Source
SAR Clocks
Track or ConvertConvertTrackAD0TM=0
TrackConvert
Low Po wer
Mode
Low Power
or Convert
10 11
13 14
10
11
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion s
ate conversions in low-power tracking mode, ADC0 trac
on the rising edge of CNVSTR (see Figure 5.4). Tr acking can also be disabled (shut down) when the device
is in low power standby or sleep mod
es. Low-power track-and-hold mode is also useful when AMUX set-
tings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling
Time Requirements” on page 47.
ignal). When the CNVSTR signal is used to initi-
ks only when CNVSTR is low; conversion begins
46Rev. 1.3
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
t
2
n
SA
------ -
R
TOTALCSAMPLE
ln=
R
MUX
= 5k
RC
Input
= R
MUX
* C
SAMPLE
R
MUX
= 5k
C
SAMPLE
= 5pF
C
SAMPLE
= 5pF
MUX
Select
MUX Select
Differential Mode
Px.x
Px.x
R
MUX
= 5k
C
SAMPLE
= 5pF
RC
Input
= R
MUX
* C
SAMPLE
MUX Select
Single-Ended Mode
Px.x
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. Note that in low-powe
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the minimum tracking time requirements.
r tracking mode, three SAR clocks are used for
Figure 5.5 shows the equivalent ADC0 input circu its for b
that the equivalent time constant for both input circuit
oth Differential and Single-ended modes. Notice
s is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or
V
with respect to GND, R
DD
reduces to R
TOTAL
. See Table 5.1 for ADC0 minimum
MUX
settling time requirements.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the
t is the r
R
TOTAL
n is the AD
settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
equired settling time in seconds
is the sum of the AMUX0 resistance and any external source resistance.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirement s
are given in Table 5.1.
Bit2:AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
AD0SC4AD0SC3AD0SC2AD0SC1AD0SC0 AD0LJST--11111000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xBC
AD0SC
SYSCLK
CLK
SAR
----------------------
1–=
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xBE
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xBD
SFR Definition 5.3. ADC0CF: ADC0 Configuration
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
50Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3:AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
Bits7–0: High byte of ADC0 Greater-Than Data Word.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
11111111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC4
Bits7–0: Low byte of ADC0 Greater-Than Data Word.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
11111111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC3
5.4.Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 conversion results to
user-programmed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (A
in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be progra mmed to indicate when measured data is inside or outside of the user-program
Less-Than and ADC0 Greater-Than registers.
D0WINT in register ADC0CN) can also be used
med limits, depending on the contents of the ADC0
The Window Detector registers must be written with the same
as that of the current ADC configuration (left/right justified, single-ended/differential).
format (left/right justified, signed/unsigned)
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
52Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits7–0: High byte of ADC0 Less-Than Data Word.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC6
Bits7–0: Low byte of ADC0 Less-Than Data Word.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC5
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
Rev. 1.353
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x03FF
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0G TL = 0x0040 (64d). In single-ended mode,
input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
the
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
will be generated
ADC0LT registers (if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an example using left-justified data with equivale
if the ADC0 conversion word is outside of the range defined by the ADC0GT and
nt ADC0GT and ADC0LT register settings.
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
54Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x01FF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
0x8000
-VREF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0GTH:ADC0GTL
AD0WINT=1
AD0WINT=1
ADC0H:ADC0LADC0H:ADC0L
ADC0LTH:ADC0LTL
5.4.2. Window Detector In Differential Mode
Figure 5.8 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the
asurable voltage between the input pins is between -VREF a nd VREF*(511/512). Output codes are rep-
me
resented as 10-bit 2’s complement s
erated if the ADC0 conversion word
and ADC0LTH:ADC0LTL (if 0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the rig
AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the
ADC0GT and ADC0LT registers (if ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)).
Figure 5.9 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.
igned integers. In the left example, an AD0WINT interrupt will be gen(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL
ht example, an
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
Rev. 1.355
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified
ParameterConditionsMinTypMaxUnits
DC Accuracy
Resolution10bits
Integral Nonlinearity±0.5±1LSB
Differential NonlinearityGuaranteed Monotonic±0.5±1LSB
Offset Error–150+15LSB
Full Scale Error–15–1+15LSB
Offset Temperature Coefficient10ppm/°C
Dynamic Performance (10 kHz sine-wave Single-en
Signal-to-Noise Plus Distortion5152.5dB
Total Harmonic Distortion
Up to the 5
th
harmonic
Spurious-Free Dynamic Range78dB
Conversion Rate
SAR Conversion Clock3MHz
Conversion Time in SAR Clocks10clocks
Track/Hold Acquisition Time300ns
Throughput Rate200ksps
Analog Inputs
ADC Input Voltage RangeSingle Ended (AIN+ – GND)
Differential (AIN+ – AIN–)
Absolute Pin V oltage with respect
to G
ND
Single Ended or Differential0
Input Capacitance5pF
Temperature Sensor
Linearity
1
Gain2.86mV/°C
Gain Error
Offset
Offset Error
2
1
2
(Temp = 0 °C)776mV
Power Specifications
Power Supply Current (V
plied to ADC0)
DD
sup-
Operating Mode, 200 ksps400900µA
Power Supply Rejection±0.3mV/V
ded input, 1 dB below Full Scale, 200 ksps)
–67dB
0
–VREF
VREF
VREF
V
DD
V
V
V
±0.1°C
±33.5µV/ºC
±8.51mV
Notes:
1. Includes ADC offset, gain, and linearity variations.
The Voltage reference MUX on C8051F34x devices is configurable to use an externally conn ected vo ltage
reference, the on-chip reference voltage generator, or the power supply voltage V
REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal refe rence or an external source, REFSL should be set to ‘0’; For V
as the reference source, REFSL should
DD
be set to ‘1’.
(see Figure 6.1). The
DD
The BIASE bit enables the internal ADC bias
generator, which is used by the ADC and Internal Oscillator.
This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias
generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see SFR Definition 6.1 for REF0CN register details. The Re
Voltage Reference, Temperature Sensor, and Clock Multiplier
ference bias generator (see Figure 6.1) is used by the Internal
. The Reference bias is automatically
enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the voltage reference and bias circuits are given in Table 6.1.
Important Note About the VREF Pin: T
he VREF pin, when not using the on-chip voltage reference or an
external precision reference, ca n be co n fig ur ed a s a G P IO Po rt p in. Wh en u sin g an e xte r na l vo ltage ref erence or the on-chip reference, the VREF pin
should be configured as analog pin and skipped by the Digital
Crossbar. To configure the VREF pin for analog mode, set the corresponding bit in the PnMDIN register to
‘0’. To configure the Crossbar to skip the VREF pin, set the corresponding bit in register PnSKIP to ‘1’.
Refer to Section “15. Port Input/Output” on page 142 for complete Port I/O configuration details.
The temperature sensor connects to the ADC0 positive input multiplexe r (see Section “5.1. Analog Multi-
plexer” on page 42 for details). The TEMPE bit in register REF0CN enables/disables the temperature
sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meanin gless data.
Figure 6.1. Voltage Reference Functional Block Diagram
Rev. 1.357
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3:REFSL: Voltage Referenc e Sele ct .
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: V
DD
used as voltage reference.
Bit2:TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1:BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0:REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
----REFSLTEMPEBIASEREFBE00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xD1
SFR Definition 6.1. REF0CN: Reference Control
Table 6.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C Unless Otherwise Specified
ParameterConditionsMinTypMaxUnits
Internal Reference (REFBE = 1)
Output Voltage25 °C ambient2.382.442.50V
VREF Short-Circuit Current10mA
VREF Temperature Coeffi-
cient
Load RegulationLoad = 0 to 200 µA to GND1.5ppm/µA
VREF Turn-on Time 1
VREF Turn-on Time 20.1 µF ceramic bypass20µs
VREF Turn-on Time 3no bypass cap10µs
Power Supply Rejection140ppm/V
C8051F34x devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically with the following excep tions: (1) Their input sele ctions differ, and (2) Comparator0 can be
sed as a reset source. For input selection details, refer to SFR Definition 7.2 and SFR Definition 7.5.
u
Each Comparator offers pro grammable re sponse time a nd hysteresis, an an alog input multip lexer, and two
utputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
o
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “15.2. Port I/O Initialization” on page 147). Comparator0 may also be used as a
reset source (see Section “11.5. Comparator0 Reset” on page 103).
The Comparator0 inputs are se lected in the CPT0 MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 7.5). The
CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the
mparator1 negative input.
Co
CMX0N0 bits select the Comparator0 negative
Important Note About Comparator Inputs: Th
figured as analog inputs in their associated Po rt configur
Crossbar (for details on Port configuration, see Section “15.3. General Purpose Port I/O” on page 150).
e Port pins selected as Comparator inputs should be con-
ation register , a nd config ured to be skipped by th e
Rev. 1.359
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
VDD
CPTnCN
Reset Decision Tree
(Comprator 0 Only)
+
-
Crossbar
Interrupt
Logic
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CPn +
CPn -
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
CPn
CPnA
CPn
Rising-edge
CPn
Falling-edge
CPn
Interrupt
CPnRIE
CPnFIE
CPTnMX
CMXnN1
CMXnN0
CMXnP1
CMXnP0
CMXnN2
CMXnP2
Port I/O connection options vary with
package (32-pin or 48-pin)
Comparator outputs can be polled in software, used as an interr upt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When disabled, the Comparator output (if assigned to a Port I/O pin via th
and supply current falls to less than 100 nA. See Section “15.1. Priority Crossbar Decoder” on
page 144 for details on configuring Comparator outputs via the dig
externally driven from –0.25 V to (V
trical specifications are given in Table 7.1.
Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition
7.3 and SFR Definition 7.6). Selecting a longer response time reduce
Table 7.1 for complete timing and supply current specifications.
60Rev. 1.3
Figure 7.1. Comparator Functional Block Diagram
) + 0.25 V without damage or upset. The complete Comparator elec-
DD
e Crossbar) defaults to the logic low state,
ital Crossbar . Comparator inputs can be
s the Comparator supply current. See
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Posi t ive Hystere sis Voltag e
(Programmed with CP0HYP Bits)
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CP0+
CP0-
CP0
VIN+
VIN-
OUT
V
OH
Posi t ive Hystere sis
Disabled
Maximum
Posi tive Hysteresis
Negative Hysteresis
Disabled
Maximum
Negative Hysteresis
OUTPUT
V
OL
Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hyster
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a sim
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on
rupt enable and priority control, see Section “9.3. Interrupt Handler” on page 88.) The CPnFIF flag is set
to ‘1’ upon a Comparator falling-edge,
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
Figure 7.2. Comparator Hysteresis Plot
ilar way, the amount of positive hysteresis is
both rising-edge and falling-edge output transitions. (For Inter-
and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
esis voltage is determined by
Rev. 1.361
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:CP0EN: Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6:CP0OUT: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5:CP0RIF: Comparator0 Rising-Edge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4:CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
68Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
8.Voltage Regulator (REG0)
C8051F34x devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the
pin and can be used to power external devi ces. REG0 can be en abled/disa bled by software using bit
V
DD
REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics.
Note that the VBUS signal must be connected to the VBUS pin
when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powere d
function. REG0 configuration options are shown in Figure 8.1–Figure 8.4.
8.1.Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynami c performa nce (respo nse time) is
degraded. See Table 8.1 for normal and low power mode supply cu
selection is controlled via the REGMOD
bit in register REG0CN.
rrent specifications. The REG0 mode
8.2.VBUS Detection
When the USB Function Controller is used (see section Section “16. Universal Serial Bus Controller
(USB0)” on page 159), the VBUS signal should be connected to the VBUS pin.
REG0CN) indicates the current logic level of the VBUS s
ignal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The
VBUS
interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be
active as long as the VBUS signal matc hes the polarity selected by VBPOL. See Table 8.1 for VBUS input
parameters.
Important Note: When USB is
selected as a reset source, a system reset will be generated when the
VBUS signal matches the polarity selected by the VBPOL bit. See Section “11. Reset Sources” on
page 100 for details on selecting USB as a reset source
The VBSTAT bit (register
Table 8.1. Voltage Regulator Electrical Specifications
–40 to +85 °C unless otherwise specified.
ParameterConditionsMinTypMaxUnits
Input Voltage Range
Output Voltage (V
Output Current
1
2
)
DD
2
Output Current = 1 to 100 mA3.03.33.6V
VBUS Detection Input Low Voltage1.0V
VBUS Detection Input High Voltage3.0V
Bias Current
3
Dropout Voltage (V
Notes:
1. Inpu
2. Output cu
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.
t range specified for regulation. When an external regulator is used, should be tied to VDD.
)
DO
rrent is total regulator output, including any current required by the C8051F34x.
Normal Mode (REGMOD = ‘0’)
Low Power Mode (REGMOD = ‘1’)
Rev. 1.369
2.75.25V
100mA
65
35
111
61
µA
1mV/mA
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Voltage Regulator (REG0)5 V In
3 V Out
VBUS Sense
REGIN
VBUS
From VBUS
To 3 V
Power Net
Device
Power Net
VDD
Voltage Regulator (REG0)5 V In
3 V Out
VBUS Sense
REGIN
VBUS
To 3 V
Power Net
Device
Power Net
VDD
From 5 V
Power Net
From VBUS
Figure 8.1. REG0 Configuration: USB Bus-Powered
Figure 8.2. REG0 Configuration: USB Self-Powered
70Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Voltage Regulator (REG0)5 V In
3 V Out
VBUS Sense
REGIN
VBUS
From 3 V
Power Net
Device
Power Net
VDD
From VBUS
Voltage Regulator (REG0)5 V In
3 V Out
VBUS Sense
REGIN
VBUS
To 3 V
Power Net
Device
Power Net
VDD
From 5 V
Power Net
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
Figure 8.4. REG0 Configuration: No USB Connection
Rev. 1.371
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:REGDIS: Voltage Regulator Disable.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
Bit6:VBSTAT: VBUS Signal Status.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
Bit5: VBPOL: VBUS Interrupt Polarity Select.
This bit selects the VBUS interrupt polarity.
0: VBUS interrupt active when VBUS is low.
1: VBUS interrupt active when VBUS is high.
Bit4:REGMOD: Voltage Regulator Mode Select.
This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regulator operates in low power (suspend) mode.
0: USB0 Voltage Regulator in normal mode.
1: USB0 Voltage Regulator in low power mode.
Bits3–0: Reserved. Read = 0000b. Must Write = 0000b.
SFR Definition 8.1. REG0CN: Voltage Regulator Control
72Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
- Fully Compatible with MCS-51 Instruction
Set
- 0 to 48 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 25 Port I/O
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
TMP1TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
D8
STACK POINTER
D8
9.CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
r 16-bit counter/timers (see description in Section 21), an enhanced full-duplex UART (see description
fou
in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Sec-
tion 15). The CIP-51 also includes on-chip debug hardware (see description in Se ction 23 ), and interf aces
directly with the analog and digit
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional c
ustom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
al subsystems providing a complete data acquisition or control-system
Figure 9.1. CIP-51 Block Diagram
Rev. 1.373
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Performance
The CIP-51 employs a pipelined architecture that gre a tly increases its instruction throughput over the stan dard 8051 architecture. In a standard 8051, all inst
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core exec
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
total of 109 instructions. The table below shows the total number of instructions that for execution time.
a
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is ac
mable Flash can also be read and changed a single byte
MOVC and MOVX instructions. T his feat ure allows progra m me mory to be us ed for no n-volatile data storage as well as updating program code under software control.
utes 70% of its instructions in one or two system clock cycles, with no instructions taking more
Clocks to Execute122/433/5454/668
Number of Instructions2650510752121
complished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program-
ructions except for MUL and DIV take 12 or 24 system
at a time by the application software using the
The on-chip Silicon Labs 2-Wire (C2) D
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. C2 details can be found in Section “23. C2 Interface” on page 271.
The CIP-51 is supported by devel
vides an integrated development environment (IDE) including editor, debugger, and programmer. The
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient
IDE's
in-system device programming and debugging. An 8051 assembler, linker and evaluation ‘C’ compiler are
included in the Development Kit. Many third party macro assemblers and C compilers are also available,
which can be used directly with the IDE.
opment tools from Silicon Labs and third party vendors. Silicon Labs pro-
evelopment Interface allows non-intrusive (uses no on-chip
9.1.Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
structions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
in
addressing modes and effect on PSW flags. However, instruction timing is different than that of the standard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most in
cycles as there are program bytes in the instruction. Conditional branch instructions take two fewer clock
cycles to complete when the branch is not taken as opposed to when the branch is taken. Table 9.1 is the
CIP-51 Instruction Set Summary, which includes the mn
cycles for each instruction.
74Rev. 1.3
structions execute in the same number of clo ck
emonic, number of bytes, and number of clock
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
9.1.2. MOVX Instruction and Program Memory
In the CIP-51, the MOVX instruction serves th ree purposes: accessing on-chip XRAM, accessing off-chip
data XRAM (only on C8051F340/1/4/5/8 devices), and accessing on-chip program Flash memory. The
Flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data storage (see Section “12. Flash Memory” on page 107). The
External Memory Interface (only on C8051F340/1/4/5/8 devices) provides a fast access interface to
f-chip data XRAM (or memory-mapped peripherals) via the MOVX instruction. Refer to Section
of
“13. External Data Memory Inter face and On-Chip XRAM” on
Table 9.1. CIP-51 Instruction Set Summary
page 114. for details.
MnemonicDescriptionBytes
Arithmetic Operations
ADD A, RnAdd register to A11
ADD A, directAdd direct byte to A22
ADD A, @RiAdd indirect RAM to A12
ADD A, #dataAdd immediate to A22
ADDC A, RnAdd register to A with carry11
ADDC A, directAdd direct byte to A with carry22
ADDC A, @RiAdd indirect RAM to A with carry12
ADDC A, #dataAdd immediate to A with carry22
SUBB A, RnSubtract register fro m A with bo rr ow11
SUBB A, directSubtract direct byte from A with borrow22
SUBB A, @RiSubtract indirect RAM from A with borrow12
SUBB A, #dataSubtract imm e dia te fro m A with bo rr ow22
INC AIncrement A11
INC RnIncrement register11
INC directIncrement direct byte22
INC @RiIncrement indirect RAM12
DEC ADecrement A11
DEC RnDecrement register11
DEC directDecrement direct byte22
DEC @RiDecrement indirect RAM12
INC DPTRIncrement Data Pointer11
MUL ABMultiply A and B14
DIV ABDivide A by B18
DA ADecimal adjust A11
Logical Operations
ANL A, RnAND Register to A11
ANL A, directAND direct byte to A22
ANL A, @RiAND indirect RAM to A12
ANL A, #dataAND immediate to A22
ANL direct, AAND A to direct byte22
ANL direct, #dataAND immediate to direct byte33
ORL A, RnOR Register to A11
ORL A, directOR direct byte to A22
ORL A, @RiOR indirect RAM to A1
Clock
Cycles
2
Rev. 1.375
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.1. CIP-51 Instruction Set Summary (Continued)
MnemonicDescriptionBytes
ORL A, #dataOR immediate to A22
ORL direct, AOR A to direct byte22
ORL direct, #dataOR immediate to direct byte33
XRL A, RnExclusive-OR Register to A11
XRL A, directExclusive-OR direct byte to A22
XRL A, @RiExclusive-OR indirect RAM to A12
XRL A, #dataExclusive-OR immediate to A22
XRL direct, AExclusive-OR A to direct byte22
XRL direct, #dataExclusive-OR immediate to direct byte33
CLR AClear A11
CPL AComplement A11
RL ARotate A left11
RLC ARotate A left through Carry11
RR ARotate A right11
RRC ARotate A right through Carry11
SWAP ASwap nibbles of A11
Data Transfer
MOV A, RnMove Register to A11
MOV A, directMove direct byte to A22
MOV A, @RiMove indirect RAM to A12
MOV A, #dataMove immediate to A22
MOV Rn, AMove A to Register11
MOV Rn, directMove direct byte to Register22
MOV Rn, #dataMove immediate to Register22
MOV direct, AMove A to direct byte22
MOV direct, RnMove Register to direct byte22
MOV direct, directMove direct byte to direct byte33
MOV direct, @RiMove indirect RAM to direct byte22
MOV direct, #dataMove immediate to direct byte33
MOV @Ri, AMove A to indirect RAM12
MOV @Ri, directMove direct byte to indirect RAM22
MOV @Ri, #dataMove immediate to indirect RAM22
MOV DPTR, #data16Load DPTR with 16-bit constant33
MOVC A, @A+DPTRMove code byte relative DPTR to A13
MOVC A, @A+PCMove code byte relative PC to A
MOVX A, @RiMove external data (8-bit address) to A13
MOVX @Ri, AMove A to external data (8-bit address)13
MOVX A, @DPTRMove external data (16-bit address) to A13
MOVX @DPTR, AMove A to external data (16-bit address)13
PUSH directPush direct byte onto stack22
POP directPop direct byte from stack22
XCH A, RnExchange Register with A11
XCH A, directExchange direct byte with A22
XCH A, @RiExchange indirect RAM with A12
XCHD A, @RiExchange low nibble of indirect RAM with A12
13
Clock
Cycles
76Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.1. CIP-51 Instruction Set Summary (Continued)
MnemonicDescriptionBytes
Boolean Manipulation
CLR CClear Carry11
CLR bitClear direct bit22
SETB CSet Carry11
SETB bitSet direct bit22
CPL CComplement Carry11
CPL bitComplement direct bit22
ANL C, bitAND direct bit to Carry22
ANL C, /bitAND complement of direct bit to Carry22
ORL C, bitOR direct bit to carry22
ORL C, /bitOR complement of direct bit to Carry22
MOV C, bitMove direct bit to Carry22
MOV bit, CMove Carry to direct bit22
JC relJump if Carry is set22/4
JNC relJump if Carry is not set22/4
JB bit, relJump if direct bit is set33/5
JNB bit, relJump if direct bit is not set33/5
JBC bit, relJump if direct bit is set and clear bit33/5
Program Branching
ACALL addr11Absolute subroutine call24
LCALL addr16Long subroutine call35
RETReturn from subroutine16
RETIReturn from interrupt16
AJMP addr11Absolute jump24
LJMP addr16Long jump35
SJMP relShort jump (relative address)24
JMP @A+DPTRJump indirect relative to DPTR14
JZ relJump if A equals zero22/4
JNZ relJump if A does not equal zero22/4
CJNE A, direct, relCompare direct byte to A and jump if not equal33/5
CJNE A, #data, relCompare immediate to A and jump if not equal33/5
CJNE Rn, #data, relCompare immediate to Register and jump if not equal33/5
CJNE @Ri, #data, relCompare immediate to indirect and jump if not equal34/6
DJNZ Rn, relDecrement Register and jump if not zero22/4
DJNZ direct, relDecrement direct byte and jump if not zero33/5
NOP
No operation11
Clock
Cycles
Rev. 1.377
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Notes on Registers, Operands and Addressing Modes:
Rn - Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset r elative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location
(0x00-0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywher e within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in Figure 9.2 and Figure 9.3.
Figure 9.2. On-Chip Memory Map for 64 kB Devices
Rev. 1.379
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF
Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F
Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
XRAM - 2048 Bytes
(Accessable using MOVX
instruction)
0x0000
0x07FF
Off-Chip XRAM
(Available only on devices
with EMIF)
0x0400
0xFFFF
FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x7FFF
USB FIFOs
1024 Bytes
0x07FF
0x0800
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F34x implements 64k or 32k bytes of
this program memory space as in-system, re-programmable Flash memory. Note that on the 64k versions
of the C8051F34x, addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only.
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature provides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile dat
80Rev. 1.3
Figure 9.3. On-Chip Memory Map for 32 kB Devices
a storage. Refer to Section “12. Flash Memory” on page 107 for further details.
However , th e CIP-51 can wr ite to pro gram m emory
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
9.2.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory.
r direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations
Eithe
x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
0
eight byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as
tes or as 128 bit locations accessible with the direct addressing mode.
by
The upper 128 bytes of data memory are accessible only by i ndir
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. In
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 9.2 illustrates the data memory organization
ect addressing. This region occupies the
structions that use
of the CIP-51.
9.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight b
one of these banks may be enabled at a time. Two bits in the program st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 9.4). This allows
fast context switching when entering subroutines and inte
use registers R0 and R1 as index registers.
yte-wide registers designated R0 through R7. Only
rrupt service routines. Indirect addressing modes
9.2.4. Bit Addressable Locations
In addition to direct access to data memory or ganize d as bytes, the sixteen d ata memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the by te at 0x20 has b it address
0x
x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
0
the type of instruction used (bit source or destination operands as opposed to a byte source or destination).
The MCS-51™ assembly language allows an alternate no
XX is the byte address and B is the bit position within the byte. For example, the instruction:
tation for bit addressing of the form XX.B where
MOVC, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
9.2.5. Stack
A programmer's stack can be located anywhe re in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR.
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the fir st value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of registe r bank 1. Th us, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack de pth can exte nd up
to 256 bytes.
The SP will point to the last location used. The next value
Rev. 1.381
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.2. Special Function Register (SFR) Memory Map
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 list
mented in the CIP-51 System Controller.
s the SFRs imple-
The SFR registers are accessed anyt ime the dire ct addr
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are
bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the cor responding p a ges of the dat asheet, as indicated in Table 9.3,
for a detailed description of each register.
essing mode is used to access memory locations
82Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
RegisterAddressDescriptionPage
ACC0xE0Accumulator87
ADC0CF0xBCADC0 Configuration50
ADC0CN0xE8ADC0 Control51
ADC0GTH0xC4ADC0 Gr ea te r- Th a n Co mpare High52
ADC0GTL0xC3ADC0 Greater-Th a n Co mpare Low52
ADC0H0xBEADC0 High50
ADC0L0xBDADC0 Low50
ADC0LTH0xC6ADC0 Less-Than Compare Word High53
ADC0LTL0xC5ADC0 Less-Than Compare Word Low53
AMX0N0xBAAMUX0 Negative Channel Select49
AMX0P0xBBAMUX0 Positive Channel Select48
B0xF0B Register88
CKCON0x8EClock Control241
CLKMUL0xB9Clock Multiplier138
CLKSEL0xA9Clock Select140
CPT0CN0x9BComparator0 Control62
CPT0MD0x9DComparator0 Mode Selection64
CPT0MX0x9FComparator0 MUX Selection63
CPT1CN0x9AComparator1 Control65
CPT1MD0x9CComparator1 Mode Selection67
CPT1MX0x9EComparator1 MUX Selection66
DPH0x83Data Pointer High86
DPL0x82Data Pointer Low86
EIE10xE6Extended Interrupt Enable 193
EIE20xE7Extended Interrupt Enable 295
EIP10xF6Extended Interrupt Priority 194
EIP20xF7Extended Interrupt Priority 295
EMI0CN0xAAExternal Memory Interface Control117
EMI0CF0x85External Memory Interface Configuration118
EMI0TC0x84External Memory Interface Timing123
FLKEY0xB7Flash Lock and Key 112
FLSCL0xB6Flash Scale113
IE0xA8Interrupt Enable91
IP
IT01CF0xE4INT0/INT1 Configuration96
OSCICL0xB3Internal Oscillator Calibration133
OSCICN0xB2Internal Oscillator Control132
OSCLCN0x86Internal Low-Frequency
OSCXCN0xB1External Oscillator Control137
P00x80Port 0 Latch150
P0MDIN0xF1Port 0 Input Mo de Con fig ur at ion150
P0MDOUT0xA4Port 0 Output Mode Configuration151
P0SKIP0xD4Port 0 Skip151
P10x90Port 1 Latch152
0xB8Interrupt Priority92
Oscillator Control134
Rev. 1.383
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
RegisterAddressDescriptionPage
P1MDIN0xF2Port 1 Input Mo de Con fig ur at ion152
P1MDOUT0xA5Port 1 Output Mode Configuration152
P1SKIP0xD5Port 1 Skip153
P20xA0Port 2 Latch153
P2MDIN0xF3Port 2 Input Mo de Con fig ur at ion153
P2MDOUT0xA6Port 2 Output Mode Configuration154
P2SKIP0xD6Port 2 Skip 154
P30xB0Port 3 Latch155
P3MDIN0xF4Port 3 Input Mo de Con fig ur at ion155
P3MDOUT0xA7Port 3 Output Mode Configuration155
P3SKIP0xDFPort 3Skip 156
P40xC7Port 4 Latch156
P4MDIN0xF5Port 4 Input Mo de Con fig ur at ion157
P4MDOUT0xAEPort 4 Output Mode Configuration157
PCA0CN0xD8PCA Control266
PCA0CPH00xFCPCA Capture 0 High270
PCA0CPH10xEAPCA Capture 1 High270
PCA0CPH20xECPCA Capture 2 High270
PCA0CPH30xEEPCA Capture 3High270
PCA0CPH40xFEPCA Capture 4 High270
PCA0CPL00xFBPCA Capture 0 Low269
PCA0CPL10xE9PCA Capture 1 Low269
PCA0CPL20xEBPCA Capture 2 Lo w269
PCA0CPL30xEDPCA Capture 3 Low269
PCA0CPL40xFDPCA Captur e 4 Lo w269
PCA0CPM0 0xDAPCA Module 0 Mode Register268
PCA0CPM1 0xDBPCA Module 1 Mode Register268
PCA0CPM2 0xDCPCA Module 2 Mode Register268
PCA0CPM3 0xDDPCA Module 3 Mode Register268
PCA0CPM4 0xDEPCA Module 4 Mode Register268
PCA0H0xFAPCA Counter High269
PCA0L0xF9PCA Counter Low269
PCA0MD0xD9PCA Mode 267
PCON0x87Power Control
PFE0CN0xAFPrefetch Engine Control99
PSCTL0x8FProgram Store R/W Control112
PSW0xD0Program Status Word87
REF0CN0xD1Voltage Reference Control58
REG0CN0xC9Voltage Regulator Control72
RSTSRC0xEFReset Source Configuration/Status105
SBCON10xACUART1 Baud Rate Generator Control220
SBRLH10xB5UART1 Baud Rate Generator High221
SBRLL10xB4UART1 Baud Rate Generator Low221
SBUF10xD3UART1 Data Buffer220
SCON10xD2UART1 Control218
98
84Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
VDM0CN0xFF
USB0ADR0x96USB0 Indirect Address Register163
USB0DAT0x97USB0 Data Register164
USB0XCN0xD7USB0 Transceiver Control161
XBR00xE1Port I/O Crossbar Control 0148
XBR10xE2Port I/O Crossbar Control 1149
XBR2
All Other AddressesReserved
0xE3Port I/O Crossbar Control 2149
Monitor Control
DD
102
Rev. 1.385
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
R/WR/WR/WR/WR/WR/WR/WR/WR eset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0x82
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0x83
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 afte r reset.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0x81
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller . Reserved bit s
should not be set to logic l. Future product versions may use these bits to implement new features in which
the reset value of the bit will be logic 0, selecting the feature's default st
case
the remaining SFRs are included in the sections of the datasheet associated with their corresponding system function.
SFR Definition 9.1. DPL: Data Pointer Low Byte
ate. Detailed descriptions of
SFR Definition 9.2. DPH: Data Pointer High Byte
SFR Definition 9.3. SP: Stack Pointer
86Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6:AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by a ll other arithmetic oper ations.
Bit5:F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software contr ol.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
Bit2:OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255) .
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1:F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software contr ol.
Bit0:PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
This register is the accumulator for arithmetic operations.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
ACC.7ACC.6ACC.5ACC.4ACC.3ACC.2ACC.1ACC.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
0xE0
SFR Definition 9.4. PSW: Program Status Word
SFR Definition 9.5. ACC: Accumulator
Rev. 1.387
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
B.7B.6B.5B.4B.3B.2B.1B.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
0xF0
SFR Definition 9.6. B: B Register
9.3.Interrupt Handler
The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority
levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a periph
tion, the associated interrupt-pending flag
is set to logic 1.
eral or external source meets a valid interrupt condi-
If interrupts are enabled for the source, an interrupt request
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a predetermined address to begin execution of an interrupt service ro
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not en abled, the inter rupt-pending flag is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1 regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or di
enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are re cogn
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared
However, most are not cle ared by the hardwar e and must be cleared by so f tware befo re returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
is generated when the interrupt-pending flag is
utine (ISR). Each ISR must end with an RETI
sabled through the use of an associated interrupt
ized. Setting the EA bit to logic 0 disables
by the hardware when the CPU vectors to the ISR.
9.3.1. MCU Interrupt Sources and Vectors
The MCU supports multiple interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag,
the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources,
associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 90. Refer
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
terrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
in
an interrupt request will be generated and
9.3.2. External Interrupts
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (
active low; the IT0 and IT1 bits in TCON (Section “21.1. Timer 0 and Timer 1” on page 235) select level
or edge sensitive. The following table list
88Rev. 1.3
INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
INT0 and INT1 are assigned to Port pins as defined in the IT01CF reg ister (see SFR Definition 9.13). Note
INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
that
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar . To assign a Port pin only to
This is accomplished by setting the associated bit in register XBR0 (se e Section “15.1. Priority Crossbar
Decoder” on page 144 for complete details on configuring the Crossbar
external interrupt pin should be skipped in the crossbar and configured as open-drain with the pin latch set
to '1'.
Active low, edge sensitive10Active low, edge sensitive
INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
). In the typical configuration, the
IE0 (TCON.1) and IE1 (TCON.3) serve as the in
rupts, respectively. If an
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the inter rupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
INT0 or INT1 external interrupt is configured as edge-sensitive, the correspondin g
terrupt-pending flags for the INT0 and INT1 external inter-
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are re cognized simult aneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 9.4.
by a high priority interrupt. A high priority interrupt cannot be
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU whe n the in terr upt occur s. Pending inter rupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1 clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
ISR.
is made to service the pending interrup t. Th eref ore, the maxim um r espo nse time for an inter rupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20 system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
les to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR. If the CPU is
cyc
ecuting an ISR for an interrupt with equal or higher priority , the new interrupt will not be serviced until the
ex
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write/e
Section “13.2. Accessing USB FIFO Sp ac e” on page 115). Interrupt service latency
interrupts occurring while the CPU is st
standard interrupt service procedure (as described above) and the amount of time the CPU is stalled.
alled. The latency for these situations will be determined by the
The SFRs used to enable the interrupt sources and set their pr iority le vel are de scri bed below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrup t
conditions for the peripheral and the behavio r of its interrupt-p en ding flag (s) .
90Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6:ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Bit5:ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4:ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3:ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2:EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the INT1
input.
Bit1:ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0:EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Bit5:PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4:PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3:PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2:PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1:PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
Bit0:PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
-PSPI0PT2PS0PT1PX1PT0PX010000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
0xB8
SFR Definition 9.8. IP: Interrupt Priority
92Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bit7:ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Bit6:ECP1: Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Bit5:ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Bit1:EUSB0: Enable USB0 Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
Bit0:ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit1:PUSB0: USB0 Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
These bits select which Port pin is assigned to INT1
. Note that this pin assignment is inde-
pendent of the Crossbar; INT1
will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
Bit3:IN0PL: INT0
Polarity
0: INT0
interrupt is active low.
1: INT0
interrupt is active high.
Bits2–0: INT0SL2–0: INT0
Port Pin Selection Bits
These bits select which Port pin is assigned to INT0
. Note that this pin assignment is inde-
pendent of the Crossbar. INT0
will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the
the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of p
Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON )
used to control the CIP-51's power management modes.
internal oscillator is stopped (analog peripherals remain in their selected states;
eripherals left in active mode before entering
Although the CIP-51 has Idle and Stop modes built in (
management of the entire MCU is better accomplished through system clock and individual peripheral
management. Each analog peripheral can be disabled when not in use and placed in low power mode.
Digital peripherals, such as timers or serial buses, draw little power when they are not in us e. Turning off
the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
The internal oscillator can be
Suspend mode, the internal
signal matches the polarity selected by the VBPOL bit in register REG0CN (SFR Definition 8.1).
placed in Suspend mode (see Section “14. Oscillators” on page 131). In
oscillator is stopped until a non-idle USB event is detected, or the VBUS input
as with any standard 8051 architecture), power
9.4.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an
nate the Idle mode. This feature protects the system from an unintended per manent shutdown in the event
f an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
o
software prior to entering the Idle mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional power savings, allow
nitely, waiting for an external stimulus to wake up the system. Refer to Section “11.6. PCA Watchdog
Timer Reset ” on page 103 for more information on the use and configuration of the WDT.
interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
internal watchdog reset and thereby termi-
ing the system to remain in the Idle mode indefi-
9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In S
als are stopped; the state of
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
the external oscillator circuit is not affected. Each analog peripheral (including
top mode the internal oscillator, CPU, and all digita l peripher-
an internal reset and thereby terminate the Stop mode.
Rev. 1.397
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1:STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0:IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
GF5GF4GF3GF2GF1GF0STOPIDLE00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0x87
SFR Definition 9.14. PCON: Power Control
98Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5:PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0:FLBWE: FLASH Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of two.
RRR/WRRRRR/WReset Value
PFENFLBWE00100000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
SFR Address: 0xAF
10. Prefetch Engine
The 48 MHz versions of the C8051F34x family of devices incorporate a 2-byte prefetch engine. Because
the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the
refetch engine is necessary for full-speed code exec ution. Instr uctions are re ad from FLASH m emory two
p
bytes at a time by the prefetc h engine, and given to the CIP-51 processor core to execute. When running
linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed
at full speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the
next set of code bytes is retrieved from FLASH memory. The FLRT bit (FLSCL.4) determines how many
clock cycles are used to read each set of two code bytes from FLASH. When operating from a system
clock of 25 MHz or less, the FLRT bit should be set to ‘0’ so that the
cycle for each read. When operating with a system clock of greater than 25 MHz (up to 48 MHz), the FLRT
it should be set to ‘1’, so that each prefetch code read lasts for two clock cycles.
b
SFR Definition 10.1. PFE0CN: Prefetch Engine Control
prefetch engine takes only one clock
Rev. 1.399
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
PCA
WDT
Missing
Clock
Detector
(oneshot)
Software Reset (SWRSF)
System Reset
Reset
Funnel
Px.x
Px.x
EN
System
Clock
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
Clock Select
EN
WDT
Enable
MCD
Enable
Errant
FLASH
Operation
+
-
Comparator 0
C0RSEF
RST
(wired-OR)
Power On
Reset
+
-
VDD
Supply
Monitor
Enable
'0'
Internal HF
Oscillator
XTAL1
XTAL2
External
Oscillator
Drive
Clock
Multiplier
USB
Controller
VBUS
Transition
Enable
Internal LF
Oscillator
11. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•CIP-51 halts program execution
•Special Function Registers (SFRs) are initialized to their defined reset values
•External Port pins are forced to a known state
•Interrupts and timers are disabled.
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
ata memory are unaffected during a reset; any previously stored data is preserved. However, since the
d
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones)
ing and after the reset. For V
Monitor and Power-On Resets, the RST pin is driven low until the device
DD
in open-drain mode. Weak pull-ups are enabled dur-
exits the reset state.
On exit from the reset state, the program counter (PC) is
reset, and the system clock defaults to the internal oscillator. Refer to Sectio n “14. Oscillators” on page 131 for information on selecting and configuring
the system clock source. The Watchdog Timer is enabled with the system clock divide
d by 12 as its clock
source (Section “22.3. Watchdog Timer Mode” on page 264 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
Figure 1 1.1. Reset Sources
100Rev. 1.3
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