Silicon Laboratories C8051F347 User Manual
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
ANALOG
PERIPHERALS
10-bit
200 ksps
ADC
64/32 kB
ISP FLASH
4/2 kB RAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(48/25 MIPS)
DIGITAL I/O
PRECISION INTERNAL
OSCILLATORS
HIGH-SPEED CONTROLLER CORE
A
M
U
X
CROSSBAR
+
-
WDT
+
-
USB Controller /
Transceiver
Port 0
Port 1
Port 2
Port 3
TEMP
SENSOR
VREG
VREF
Port 4
Ext. Memory I/F
48 Pin Only
UART0
SMBus
PCA
4 Timers
SPI
UART1*
C8051F340/1/2/34/5/6/7/A/B Only * C8051F340/1/4/5/8/A/B/C Only
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only)
• Up to 200 ksps
• Built-in analog multiplexer with single-ended and
differential mode
• VREF from external pin, internal reference, or V
• Built-in temperature sensor
• External conversion start input option
DD
- Two comparators
- Internal voltage reference
(C8051F340/1/2/3/4/5/6/7/A/B only)
- Brown-out detector and POR Circuitry
USB Function Controller
-
USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
-
Voltages from 3.6 to 5.25 V supported using On-Chip
Voltage Regulator
HIgh Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
Instructions in 1 or 2 system clocks
- 48 MIPS and 25 MIPS versions available.
- Expanded interrupt handler
Memory
-
4352 or 2304 Bytes RAM
- 64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
-
40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, SMBus™, and one or two
enhanced UART serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
-
Internal Oscillator: ±0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
-
48-pin TQFP (C8051F340/1/4/5/8/C)
- 32-pin LQFP (C8051F342/3/6/7/9/A/B/D)
- 5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)
Temperature Range: –40 to +85 °C
Rev. 1.4 9/09 Copyright © 2009 by Silicon Laboratories C8051F34x
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
2 Rev. 1.4
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table of Contents
1. System Overview.................................................................................................... 17
2. Absolute Maximum Ratings .................................................................................. 24
3. Global DC Electrical Characteristics.................................................................... 25
4. Pinout and Package Definitions............................................................................ 28
5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)........................................ 41
5.1. Analog Multiplexer ............................................................................................ 42
5.2. Temperature Sensor......................................................................................... 43
5.3. Modes of Operation .......................................................................................... 45
5.3.1. Starting a Conversion............................................................................... 45
5.3.2. Tracking Modes . ....................................................................................... 46
5.3.3. Settling Time Requirements..................................................................... 47
5.4. Programmable Window Detector...................................................................... 52
5.4.1. Window Detector In Single-Ended Mode ................................................. 54
5.4.2. Window Detector In Differential Mode...................................................... 55
6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)....................................... 57
7. Comparators........................................................................................................... 59
8. Voltage Regulator (REG0)...................................................................................... 69
8.1. Regulator Mode Selection................................................................................. 69
8.2. VBUS Detection................................................................................................ 69
9. CIP-51 Microcontroller........................................................................................... 73
9.1. Instruction Set................................................................................................... 74
9.1.1. Instruction and CPU Timing ..................................................................... 74
9.1.2. MOVX Instruction and Program Memory ................................................. 75
9.2. Memory Organization........................................................................................ 79
9.2.1. Program Memory...................................................................................... 80
9.2.2. Data Memory............................................................................................ 81
9.2.3. General Purpose Registers...................................................................... 81
9.2.4. Bit Addressable Locations........................................................................ 81
9.2.5. Stack ....................................................................................................... 81
9.2.6. Special Function Registers....................................................................... 82
9.2.7. Register Descriptions............................................................................... 86
9.3. Interrupt Handler............................................................................................... 88
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 88
9.3.2. External Interrupts.................................................................................... 88
9.3.3. Interrupt Priorities..................................................................................... 89
9.3.4. Interrupt Latency ......................................................................................
9.3.5. Interrupt Register Descriptions................................................................. 90
9.4. Power Management Modes.............................................................................. 97
9.4.1. Idle Mode.................................................................................................. 97
9.4.2. Stop Mode................................................................................................ 97
10.Prefetch Engine ...................................................................................................... 99
11.Reset Sources....................................................................................................... 100
11.1.Power-On Reset............................................................................................. 101
89
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11.2.Power-Fail Reset / VDD Monitor .................................................................... 102
11.3.External Reset................................................................................................ 103
11.4.Missing Clock Detector Reset ........................................................................ 103
11.5.Comparator0 Reset........................................................................................ 103
11.6.PCA Watchdog Timer Reset .......................................................................... 103
11.7.Flash Error Reset ........................................................................................... 103
11.8.Software Reset............................................................................................... 104
11.9.USB Reset . ..................................................................................................... 104
12.Flash Memory ....................................................................................................... 107
12.1.Programming The Flash Memory................................................................... 107
12.1.1.Flash Lock and Key Functions............................................................... 107
12.1.2.Flash Erase Procedure .......................................................................... 107
12.1.3.Flash Write Procedure ........................................................................... 108
12.2.Non-Volatile Data Storage.............................................................................. 109
12.3.Security Options............................................................................................. 109
13.External Data Memory Interface and On-Chip XRAM........................................ 114
13.1.Accessing XRAM............................................................................................ 114
13.1.1.16-Bit MOVX Example........................................................................... 114
13.1.2.8-Bit MOVX Example............................................................................. 114
13.2.Accessing USB FIFO Space .......................................................................... 115
13.3.Configuring the External Memory Interface.................................................... 116
13.4.Port Configuration........................................................................................... 116
13.5.Multiplexed and Non-multiplexed Selection.................................................... 119
13.5.1.Multiplexed Configuration....................................................................... 119
13.5.2.Non-multiplexed Configuration............................................................... 120
13.6.Memory Mode Selection................................................................................. 120
13.6.1.Internal XRAM Only ............................................................................... 121
13.6.2.Split Mode without Bank Select.............................................................. 121
13.6.3.Split Mode with Bank Select................................................................... 122
13.6.4.External Only.......................................................................................... 122
13.7.Timing .......................................................................................................... 122
13.7.1.Non-multiplexed Mode........................................................................... 124
13.7.2.Multiplexed Mode................................................................................... 127
14.Oscillators............................................................................................................. 131
14.1.Programmable Internal High-F
14.1.1.Internal H-F Oscillator Suspend Mode................................................... 132
14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 133
14.2.1.Calibrating the Internal L-F Oscillator..................................................... 133
14.3.External Oscillator Drive Circuit...................................................................... 135
14.3.1.Clocking Timers Directly Through the External Oscillator...................... 135
14.3.2.External Crystal Example....................................................................... 135
14.3.3.External RC Example............................................................................. 136
14.3.4.External Capacitor Example................................................................... 136
14.4.4x Clock Multiplier .......................................................................................... 138
14.5.System and USB Clock Selection .................................................................. 139
requency (H-F) Oscillator............................... 132
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14.5.1.System Clock Selection ......................................................................... 139
14.5.2.USB Clock Selection.............................................................................. 139
15.Port Input/Output.................................................................................................. 142
15.1.Priority Crossbar Decoder.............................................................................. 144
15.2.Port I/O Initialization ....................................................................................... 147
15.3.General Purpose Port I/O............................................................................... 150
16.Universal Serial Bus Controller (USB0).............................................................. 159
16.1.Endpoint Addressing ...................................................................................... 160
16.2.USB Transceiver ............................................................................................ 160
16.3.USB Register Access..................................................................................... 162
16.4.USB Clock Configuration................................................................................ 166
16.5.FIFO Management ......................................................................................... 167
16.5.1.FIFO Split Mode..................................................................................... 167
16.5.2.FIFO Double Buffering........................................................................... 168
16.5.3.FIFO Access .......................................................................................... 168
16.6.Function Addressing....................................................................................... 169
16.7.Function Configuration and Control................................................................ 169
16.8.Interrupts ........................................................................................................ 172
16.9.The Serial Interface Engine............................................................................ 176
16.10.Endpoint0 ..................................................................................................... 176
16.10.1.Endpoint0 SETUP Transactions .......................................................... 177
16.10.2.Endpoint0 IN Transactions................................................................... 177
16.10.3.Endpoint0 OUT Transactions............................................................... 178
16.11.Configuring Endpoints1-3............................................................................. 180
16.12.Controlling Endpoints1-3 IN.......................................................................... 180
16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 180
16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 181
16.13.Controlling Endpoints1-3 OUT...................................................................... 183
16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 183
16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 184
17.SMBus ................................................................................................................... 188
17.1.Supporting Documents................................................................................... 189
17.2.SMBus Configuration...................................................................................... 189
17.3.SMBus Operation...........................................................................................
17.3.1.Arbitration............................................................................................... 190
17.3.2.Clock Low Extension.............................................................................. 191
17.3.3.SCL Low Timeout................................................................................... 191
17.3.4.SCL High (SMBus Free) Timeout .......................................................... 191
17.4.Using the SMBus............................................................................................ 191
17.4.1.SMBus Configuration Register............................................................... 192
17.4.2.SMB0CN Control Register..................................................................... 195
17.4.3.Data Register......................................................................................... 198
17.5.SMBus Transfer Modes.................................................................................. 198
17.5.1.Master Transmitter Mode....................................................................... 198
17.5.2.Master Receiver Mode........................................................................... 200
189
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17.5.3.Slave Receiver Mode............................................................................. 201
17.5.4.Slave Transmitter Mode......................................................................... 202
17.6.SMBus Status Decoding................................................................................. 202
18.UART0.................................................................................................................... 205
18.1.Enhanced Baud Rate Generation................................................................... 206
18.2.Operational Modes......................................................................................... 206
18.2.1.8-Bit UART............................................................................................. 207
18.2.2.9-Bit UART............................................................................................. 208
18.3.Multiprocessor Communications .................................................................... 208
19.UART1 (C8051F340/1/4/5/8/A/B/C Only).............................................................. 213
19.1.Baud Rate Generator ..................................................................................... 214
19.2.Data Format.................................................................................................... 215
19.3.Configuration and Operation .......................................................................... 216
19.3.1.Data Transmission................................................................................. 216
19.3.2.Data Reception ...................................................................................... 216
19.3.3.Multiprocessor Communications............................................................ 217
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 222
20.1.Signal Descriptions......................................................................................... 223
20.1.1.Master Out, Slave In (MOSI).................................................................. 223
20.1.2.Master In, Slave Out (MISO).................................................................. 223
20.1.3.Serial Clock (SCK)................................................................................. 223
20.1.4.Slave Select (NSS) ................................................................................ 223
20.2.SPI0 Master Mode Operation......................................................................... 224
20.3.SPI0 Slave Mode Operation........................................................................... 226
20.4.SPI0 Interrupt Sources................................................................................... 226
20.5.Serial Clock Timing......................................................................................... 227
20.6.SPI Special Function Registers...................................................................... 229
21.Timers.................................................................................................................... 235
21.1.Timer 0 and Timer 1....................................................................................... 235
21.1.1.Mode 0: 13-bit Counter/Timer................................................................ 235
21.1.2.Mode 1: 16-bit Counter/Timer................................................................ 236
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 237
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 238
21.2.Timer 2 ..........................................................................................................
21.2.1.16-bit Timer with Auto-Reload................................................................ 243
21.2.2.8-bit Timers with Auto-Reload................................................................ 244
21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge...... 245
21.3.Timer 3 .......................................................................................................... 249
21.3.1.16-bit Timer with Auto-Reload................................................................ 249
21.3.2.8-bit Timers with Auto-Reload................................................................ 250
21.3.3.USB Start-of-Frame Capture.................................................................. 251
22.Programmable Counter Array (PCA0)................................................................ 255
22.1.PCA Counter/Timer........................................................................................ 256
22.2.Capture/Compare Modules ............................................................................ 257
22.2.1.Edge-triggered Capture Mode................................................................ 258
243
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22.2.2.Software Timer (Compare) Mode........................................................... 259
22.2.3.High Speed Output Mode....................................................................... 260
22.2.4.Frequency Output Mode ........................................................................ 261
22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 262
22.2.6.16-Bit Pulse Width Modulator Mode....................................................... 263
22.3.Watchdog Timer Mode................................................................................... 264
22.3.1.Watchdog Timer Operation.................................................................... 264
22.3.2.Watchdog Timer Usage ......................................................................... 265
22.4.Register Descriptions for PCA........................................................................ 266
23.C2 Interface........................................................................................................... 271
23.1.C2 Interface Registers.................................................................................... 271
23.2.C2 Pin Sharing ............................................................................................... 273
Document Change List............................................................................................. 274
Contact Information.................................................................................................. 276
Rev. 1.3 7
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
List of Figures
1. System Overview
Figure 1.1. C8051F340/1/4/5 Block Diagram........................................................... 19
Figure 1.2. C8051F342/3/6/7 Block Diagram........................................................... 20
Figure 1.3. C8051F348/C Block Diagram................................................................. 21
Figure 1.4. C8051F349/D Block Diagram................................................................. 22
Figure 1.5. C8051F34A/B Block Diagram ................................................................ 23
4. Pinout and Package Definitions
Figure 4.1. TQFP-48 Pinout Diagram (Top View) .................................................... 31
Figure 4.2. TQFP-48 Package Diagram................................................................... 32
Figure 4.3. TQFP-48 Recommended PCB Land Pattern......................................... 33
Figure 4.4. LQFP-32 Pinout Diagram (Top View)..................................................... 34
Figure 4.5. LQFP-32 Package Diagram................................................................... 35
Figure 4.6. LQFP-32 Recommended PCB Land Pattern ......................................... 36
Figure 4.7. QFN-32 Pinout Diagram (Top View) ...................................................... 37
5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 41
Figure 5.2. Temperature Sensor Transfer Function................................................. 43
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 44
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 46
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 47
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data... 54
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data...... 54
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data........ 55
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 55
6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
Figure 6.1. Voltage Reference Functional Block Diagram........................................ 57
7. Comparators
Figure 7.1. Comparator Functional Block Diagram .................................................. 60
Figure 7.2. Comparator Hysteresis Plot ................................................................... 61
8. Voltage Regulator (REG0)
Figure 8.1. REG0 Configuration: USB Bus-Powered............................................... 70
Figure 8.2. REG0 Configuration: USB Self-Powered............................................... 70
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled............... 71
Figure 8.4. REG0 Configuration: No USB Connection............................................. 71
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 73
Figure 9.2. On-Chip Memory Map for 64 kB Devices............................................... 79
Figure 9.3. On-Chip Memory Map for 32 kB Devices............................................... 80
11. Reset Sources
Figure 11.1. Reset Sources.................................................................................... 100
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 101
8 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
12. Flash Memory
Figure 12.1. Flash Program Memory Map and Security Byte................................. 110
13. External Data Memory Interface and On-Chip XRAM
Figure 13.1. USB FIFO Space and XRAM Memory Map
with USBFAE set to ‘1’...................................................................................... 115
Figure 13.2. Multiplexed Configuration Example.................................................... 119
Figure 13.3. Non-multiplexed Configuration Example............................................ 120
Figure 13.4. EMIF Operating Modes...................................................................... 120
Figure 13.5. Non-multiplexed 16-bit MOVX Timing................................................ 124
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 125
Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 126
Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 127
Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing......................... 128
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing............................ 129
14. Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 131
15. Port Input/Output
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)................ 142
Figure 15.2. Port I/O Cell Block Diagram ............................................................... 143
Figure 15.3. Peripheral Availability on Port I/O Pins............................................... 144
Figure 15.4. Crossbar Priority Decoder in Example Configuration
(No Pins Skipped)............................................................................................. 145
Figure 15.5. Crossbar Priority Decoder in
Example Configuration (3 Pins Skipped) .......................................................... 146
16. Universal Serial Bus Controller (USB0)
Figure 16.1. USB0 Block Diagram.......................................................................... 159
Figure 16.2. USB0 Register Access Scheme......................................................... 162
Figure 16.3. USB FIFO Allocation.......................................................................... 167
17. SMBus
Figure 17.1. SMBus Block Diagram ....................................................................... 188
Figure 17.2. Typical SMBus Configuration............................................................. 189
Figure 17.3. SMBus Transaction............................................................................ 190
Figure 17.4. Typical SMBus SCL Generation......................................................... 193
Figure 17.5. Typical Master Transmitter Sequence................................................ 199
Figure 17.6. Typical Master Receiver Sequence.................................................... 200
Figure 17.7. Typical Slave Receiver Sequence...................................................... 201
Figure 17.8. Typical Slave Transmitter Sequence.................................................. 202
18. UART0
Figure 18.1. UART0 Block Diagram....................................................................... 205
Figure 18.2. UART0 Baud Rate Logic.................................................................... 206
Figure 18.3. UART Interconnect Diagram.............................................................. 207
Figure 18.4. 8-Bit UART Timing Diagram............................................................... 207
Figure 18.5. 9-Bit UART Timing Diagram............................................................... 208
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram.......................... 209
19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
Rev. 1.3 9
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Figure 19.1. UART1 Block Diagram....................................................................... 213
Figure 19.2. UART1 Timing Without Parity or Extra Bit.......................................... 215
Figure 19.3. UART1 Timing With Parity ................................................................. 215
Figure 19.4. UART1 Timing With Extra Bit............................................................. 215
Figure 19.5. Typical UART Interconnect Diagram.................................................. 216
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram.......................... 218
20. Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram............................................................................. 222
Figure 20.2. Multiple-Master Mode Connection Diagram....................................... 225
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 225
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram... 225
Figure 20.5. Master Mode Data/Clock Timing........................................................ 227
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 228
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 228
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 232
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 232
Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 233
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 233
21. Timers
Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 236
Figure 21.2. T0 Mode 2 Block Diagram.................................................................. 237
Figure 21.3. T0 Mode 3 Block Diagram.................................................................. 238
Figure 21.4. Timer 2 16-Bit Mode Block Diagram .................................................. 243
Figure 21.5. Timer 2 8-Bit Mode Block Diagram .................................................... 244
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’).............................................. 245
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’).............................................. 246
Figure 21.8. Timer 3 16-Bit Mode Block Diagram .................................................. 249
Figure 21.9. Timer 3 8-Bit Mode Block Diagram .................................................... 250
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)............................................ 251
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)............................................ 252
22. Programmable Counter Array (PCA0)
Figure 22.1. PCA Block Diagram............................................................................ 255
Figure 22.2. PCA Counter/Timer Block Diagram.................................................... 256
Figure 22.3. PCA Interrupt Block Diagram............................................................. 257
Figure 22.4. PCA Capture Mode Diagram.............................................................. 258
Figure 22.5. PCA Software Timer Mode Diagram.................................................. 259
Figure 22.6. PCA High Speed Output Mode Diagram............................................ 260
Figure 22.7. PCA Frequency Output Mode............................................................ 261
Figure 22.8. PCA 8-Bit PWM Mode Diagram......................................................... 262
Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 263
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled................................. 264
23. C2 Interface
Figure 23.1. Typical C2 Pin Sharing
....................................................................... 273
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List of Tables
1. System Overview
Table 1.1. Product Selection Guide ......................................................................... 18
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings* .................................................................. 24
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics ....................................................... 25
Table 3.2. Index to Electrical Characteristics Tables ............................................... 27
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D ................. 28
Table 4.2. TQFP-48 Package Dimensions .............................................................. 32
Table 4.3. TQFP-48 PCB Land Pattern Dimensions ............................................... 33
Table 4.4. LQFP-32 Package Dimensions .............................................................. 35
Table 4.5. LQFP-32 PCB Land Pattern Dimensions ............................................... 36
5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only)
Table 5.1. ADC0 Electrical Characteristics .............................................................. 56
6. Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only)
Table 6.1. Voltage Reference Electrical Characteristics ......................................... 58
7. Comparators
Table 7.1. Comparator Electrical Characteristics .................................................... 68
8. Voltage Regulator (REG0)
Table 8.1. Voltage Regulator Electrical Specifications ............................................ 69
9. CIP-51 Microcontroller
Table 9.1. CIP-51 Instruction Set Summary ............................................................ 75
Table 9.2. Special Function Register (SFR) Memory Map ...................................... 82
Table 9.3. Special Function Registers ..................................................................... 83
Table 9.4. Interrupt Summary .................................................................................. 90
11. Reset Sources
Table 11.1. Reset Electrical Characteristics .......................................................... 106
12. Flash Memory
Table 12.1. Flash Electrical Characteristics .......................................................... 109
13. External Data Memory Interface and On-Chip XRAM
Table 13.1. AC Parameters for External Memory Interface ................................... 130
14. Oscillators
Table 14.1. Oscillator Electrical Characteristics .................................................... 141
15. Port Input/Output
Table 15.1. Port I/O DC Electrical Characteristics ................................................. 158
16. Universal Serial Bus Controller (USB0)
Table 16.1. Endpoint Addressing Scheme ............................................................ 160
Table 16.2. USB0 Controller Registers ................................................................. 165
Table 16.3. FIFO Configurations ........................................................................... 168
Table 16.4. USB Transceiver Electrical Characteristics ........................................ 187
17. SMBus
Table 17.1. SMBus Clock Source Selection .......................................................... 192
Rev. 1.3 11
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Table 17.2. Minimum SDA Setup and Hold Times ................................................ 193
Table 17.3. Sources for Hardware Changes to SMB0CN ..................................... 197
Table 17.4. SMBus Status Decoding ..................................................................... 203
18. UART0
Table 18.1. Timer Settings for Standard Baud Rates
Using the Internal Oscillator ............................................................... 212
19. UART1 (C8051F340/1/4/5/8/A/B/C Only)
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates ................... 214
20. Enhanced Serial Peripheral Interface (SPI0)
Table 20.1. SPI Slave Timing Parameters ............................................................ 234
22. Programmable Counter Array (PCA0)
Table 22.1. PCA Timebase Input Options ............................................................. 256
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules .... 257
Table 22.3. Watchdog Timer Timeout Intervals1 ................................................... 265
12 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 52
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 52
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 53
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 53
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 72
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 96
SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SFR Definition 10.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 11.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 102
SFR Definition 11.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SFR Definition 12.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 12.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 12.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SFR Definition 13.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 117
SFR Definition 13.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 118
SFR Definition 13.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 123
SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 132
SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 133
Rev. 1.3 13
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 134
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 137
SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 138
SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 148
SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 149
SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 149
SFR Definition 15.4. P0: Port0 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFR Definition 15.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 15.7. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SFR Definition 15.8. P1: Port1 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 15.9. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 15.10. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 15.11. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.12. P2: Port2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.13. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.14. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.15. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.16. P3: Port3 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.17. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.18. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.19. P3SKIP: Port3 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.20. P4: Port4 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.21. P4MDIN: Port4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.22. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 16.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 161
SFR Definition 16.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 163
SFR Definition 16.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
USB Register Definition 16.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 165
USB Register Definition 16.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 166
USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 168
USB Register Definition 16.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 169
USB Register Definition 16.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 171
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 172
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 172
USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 173
USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 173
USB Register Definition 16.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 174
USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 175
USB Register Definition 16.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 175
USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 176
USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 179
USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 180
14 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 182
USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 183
USB Register Definition 16.21. EOUTCSRL: USB0 OUT
Endpoint Control Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
USB Register Definition 16.22. EOUTCSRH: USB0 OUT
Endpoint Control High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 186
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 186
SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 194
SFR Definition 17.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
SFR Definition 17.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
SFR Definition 18.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 210
SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 211
SFR Definition 19.1. SCON1: UART1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
SFR Definition 19.2. SMOD1: UART1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
SFR Definition 19.3. SBUF1: UART1 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control . . . . . . . . . . . 220
SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte . . . . . . . . . . 221
SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte . . . . . . . . . . . 221
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 229
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
SFR Definition 21.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
SFR Definition 21.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
SFR Definition 21.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
SFR Definition 21.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SFR Definition 21.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SFR Definition 21.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SFR Definition 21.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SFR Definition 21.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 248
SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 248
SFR Definition 21.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 21.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 21.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 254
SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 254
SFR Definition 21.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
SFR Definition 21.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
SFR Definition 22.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
SFR Definition 22.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 268
SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 269
SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 269
Rev. 1.3 15
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 269
SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 270
C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 271
C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 272
C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 272
C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 272
16 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
1. System Overview
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are fully integrated mixed-signal System-on-a-Chip MCUs.
Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
• High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• Universal Serial Bus (USB) Function Controller with eigh
ceiver, and 1 kB FIFO RAM
• Supply Voltage Regulator
• True 10-bit 200 ksps differential / single-ended AD
• On-chip Voltage Reference and Temperature Sensor
• On-chip Voltage Comparators (2)
• Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier
• Internal low-frequency oscillator for additional pow
• Up to 64 kB of on-chip Flash memory
• Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
• External Memory Interface (EMIF) available on 48-pin versions.
• SMBus/I2C, up to 2 UARTs, and Enhanced SPI ser
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
tion
func
• On-chip Power-On Reset, V
• Up to 40 Port I/O (5 V tolerant)
Monitor, and Missing Clock Detector
DD
t flexible endpoint pipes, integrated trans-
C with analog multiplexer
er savings
ial interfaces implemented in hardware
With on-chip Power-On Reset,
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are truly stand-alone System-on-a-Chip solutions. The
Flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field
upgrades of the 8051 firmware. User software has comp lete contr ol of all perip he rals, and ma y in dividually
shut down any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) D
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
or voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for
F
USB com
4/5/6/7/8/9/A/B/C/D devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See
Table 1.1, “Product Selection Guide,” on page 18 for feature and package choices.
munication. The Port I/O and
VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
evelopment Interface allows non-intrusive (uses no on-chip
RST pins are tolerant of input signals up to 5 V. C8051F340/1/2/3/
Rev. 1.3 17
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 1.1. Product Selection Guide
Ordering Part Number
C8051F340-GQ 48 64k 4352
C8051F341-GQ 48 32k 2304 24 40 2TQFP48
C8051F342-GQ 48 64k 4352 14 25 — 2LQFP32
C8051F342-GM 48 64k 4352
C8051F343-GQ 48 32k 2304 14 25 — 2LQFP32
C8051F343-GM 48 32k 2304 14 25 — 2QFN32
C8051F344-GQ 25 64k 4352
C8051F345-GQ 25 32k 2304 24 40 2TQFP48
C8051F346-GQ 25 64k 4352 — 14 25 — 2LQFP32
C8051F346-GM 25 64k 4352
C8051F347-GQ 25 32k 2304 — 14 25 — 2LQFP32
C8051F347-GM 25 32k 2304 — 14 25 — 2QFN32
C8051F348-GQ 25 32k 2304
MIPS (Peak)
Flash Memory (Bytes)
RAM
Calibrated Internal Oscillator
Low Frequency Oscillator
USB with 1k Endpoint RAM
Supply Voltage Regulator
—
SMBus/I2C
Enhanced SPI
UARTs
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
2440
1425 —
2440
1425 —
2440
External Memory Interface (EMIF)
10-bit 200 ksps ADC
Temperature Sensor
Voltage Reference
Analog Comparators
2TQFP48
— — — 2 TQFP48
2QFN32
2TQFP48
2QFN32
Package
C8051F349-GQ 25 32k 2304 14 25
C8051F349-GM 25 32k 2304 14 25 ————2 QFN32
C8051F34A-GQ 48 64k 4352
C8051F34A-GM 48 64k 4352 24 25
C8051F34B-GQ 48 32k 2304 24 25
C8051F34B-GM 48 32k 2304
C8051F34C-GQ 48 64k 4352 24 40 — — — 2 TQFP48
C8051F34D-GQ 48 64k 4352 14 25 — — — — 2 LQFP32
18 Rev. 1.3
2425 —
2425 —
— — — — 2 LQFP32
—
2QFN32
—
2LQFP32
2LQFP32
2QFN32
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Analog Peripherals
10-bit
200ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN19
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
UART1
SPI
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator
Clock
Multiplier
Clock
Recovery
USB Peripheral
Controller
1k Byte
RAM
Full / Low
Speed
Transceiver
External Memory
Interface
Control
Address
Data
P1
P2 / P3
P4
SFR
Bus
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
C2D
CIP-51 8051
Controller Core
64/32k Byte ISP FLASH
Program Memory
256 Byte RAM
4/2k Byte XRAM
Figure 1.1. C8051F340/1/4/5 Block Diagram
Rev. 1.3 19
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Analog Peripherals
10-bit
200 ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN20
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
SPI
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator*
Clock
Multiplier
Clock
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Low
Speed
Transceiver
SFR
Bus
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
*Low Frequency Oscillator option not available on C8051F346/7
20 Rev. 1.3
Figure 1.2. C8051F342/3/6/7 Block Diagram
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Debug / Programming
Hardware
Port 0
Drivers
P0.0
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
UART1
SPI
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator
Clock
Multiplier
Clock
Recovery
USB Peripheral
Controller
1k Byte
RAM
Full / Low
Speed
Transceiver
External Memory
Interface
Control
Address
Data
P1
P2 / P3
P4
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
C2D
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
Analog Peripherals
2 Comparators
+
-
CP0
+
-
CP1
SFR
Bus
Figure 1.3. C8051F348/C Block Diagram
Rev. 1.3 21
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Debug / Programming
Hardware
Port 0
Drivers
P0.0
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
SPI
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator
Clock
Multiplier
Clock
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Low
Speed
Transceiver
SFR
Bus
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
CIP-51 8051
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
Analog Peripherals
2 Comparators
+
-
CP0
+
-
CP1
Figure 1.4. C8051F349/D Block Diagram
22 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Analog Peripherals
10-bit
200 ksps
ADC
A
M
U
X
Temp
Sensor
2 Comparators
+
-
VREFVDD
CP0
VDD
+
-
CP1
VREF
Debug / Programming
Hardware
Port 0
Drivers
P0.0
AIN0 - AIN20
Port I/O Configuration
Digital Peripherals
Priority
Crossbar
Decoder
Crossbar Control
Power-On
Reset
Power
Net
UART0
Timers 0, 1,
2, 3
PCA/WDT
SMBus
SPI
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Supply
Monitor
System Clock Setup
External
Oscillator
Internal
Oscillator
XTAL1
XTAL2
Low Freq.
Oscillator*
Clock
Multip lier
Clock
Recovery
USB Peripheral
Controller
1 kB RAM
Full / Lo w
Speed
Transceiver
SFR
Bus
Voltage
Regulator
D+
D-
VBUS
VDD
VREG
GND
C2CK/RST
Reset
CIP-51 8051
Controller Core
64/32 k B IS P FLA SH
Program Memory
256 Byte RAM
4/2 kB XRAM
C2D
UART1
Figure 1.5. C8051F34A/B Block Diagram
Rev. 1.3 23
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or RST
respect to GND
Voltage on V
Maximum Total current through V
GND
Maximum output current sunk by RST
Port pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to GND –0.3 4.2 V
DD
DD
with
and
or any
–0.3 5.8 V
500 mA
100 mA
24 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage
1
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)
2
C8051F340/1/2/3/A/B/C/D
C8051F344/5/6/7/8/9
Specified Operating
Temperature Range
Digital Supply Current - CPU Active (Normal Mode, accessing Flash)
I
DD
3
VDD = 3.3 V, SYSCLK = 48 MHz
= 3.3 V, SYSCLK = 24 MHz
V
DD
= 3.3 V, SYSCLK = 1 MHz
V
DD
= 3.3 V, SYSCLK = 80 kHz
V
DD
VRST 3.3 3.6 V
–40 +85 °C
1.5 V
0
0
25.9
13.9
0.69
55
48
25
.5
28
15.7
MHz
mA
mA
mA
µA
= 3.6 V, SYSCLK = 48 MHz
V
DD
= 3.6 V, SYSCLK = 24 MHz
V
DD
Supply Sensitivity
I
DD
3,4
SYSCLK = 1 MHz,
relative to V
= 3.3 V
DD
SYSCLK = 24 MHz,
= 3.3 V
DD
Frequency Sensitivity
I
DD
3,5
relative to V
VDD = 3.3 V, SYSCLK < 30 MHz,
T = 25 ºC
= 3.3 V, SYSCLK > 30 MHz,
V
DD
T = 25 ºC
= 3.6 V, SYSCLK < 30 MHz,
V
DD
T = 25 ºC
= 3.6 V, SYSCLK > 30 MHz,
V
DD
T = 25 ºC
Digital Supply Current - CPU Inactive (Idle Mode, not accessing Flash)
3
I
DD
Supply Sensitivity
I
DD
3,4
VDD = 3.3 V, SYSCLK = 48 MHz
= 3.3 V, SYSCLK = 24 MHz
V
DD
= 3.3 V, SYSCLK = 1 MHz
V
DD
= 3.3 V, SYSCLK = 80 kHz
V
DD
= 3.6 V, SYSCLK = 48 MHz
V
DD
= 3.6 V, SYSCLK = 24 MHz
V
DD
SYSCLK = 1 MHz,
relative to V
= 3.3 V
DD
SYSCLK = 24 MHz,
relative to V
= 3.3 V
DD
29.7
15.9
47
46
0.69
0.44
0.80
0.50
16.6
8.25
0.44
35
18.6
9.26
41
39
32.3
18
18
9.34
20.9
10.5
.75
mA
mA
%/V
%/V
MHz
mA/
mA/MHz
mA/MHz
mA/MHz
mA
mA
mA
µA
mA
mA
%/V
%/V
Rev. 1.3 25
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 3.1. Global DC Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Frequency Sensitivity
I
DD
3,6
VDD = 3.3 V, SYSCLK < 1 MHz,
T = 25 ºC
= 3.3 V, SYSCLK > 1 MHz,
V
DD
T = 25 ºC
0.44
0.32
MHz
mA/
mA/MHz
= 3.6 V, SYSCLK < 1 MHz,
V
DD
0.49
mA/MHz
T = 25 ºC
= 3.6 V, SYSCLK > 1 MHz,
V
DD
0.36
mA/MHz
T = 25 ºC
Digital Supply Current (Stop
Mode, shutdown)
Digital Supply Current for USB
Module (USB Active Mode)
Digital Supply Current for USB
Module (USB Suspend Mode)
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Based on
4. Active and Inactive IDD at voltages and frequencies other than those specified can be calculated using the IDD
Supply Sensitivity. For example, if the VDD is 3.0 V instead of 3.3 V at 24 MHz: IDD = 13.9 mA typical at 3.3 V
and SYSCLK = 24 MHz. From this, I
= 24 MHz.
5. IDD can be estimated for frequencies < 30 MHz by multiplying the frequency of interest by the frequency
sensitivity number for that range. When using these numbers to estimate I
be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.3 V; SYSCLK = 35 MHz, IDD = 13.9 mA – (24 MHz – 35 MHz) x 0.44 mA/MHz =
18.74 mA.
le IDD can be estimated for frequencies < 1 MHz by multiplying the frequency of interest by the frequency
6. Id
sensitivity number for that range. When using these numbers to estimate Idle IDD for > 1 MHz, the estimate
should be the current at 24 MHz (or 48 MHz) minus the difference in current indicated by the frequency
sensitivity number. For example: V
0.32 mA/MHz = 2.17 mA.
device characterization of data; Not production tested.
Oscillator not running,
monitor disabled
V
DD
= 3.3 V, USB Clock = 48 MHz
V
DD
= 3.6 V, USB Clock = 48 MHz
V
DD
Oscillator not running
monitor disabled
V
DD
= 13.9 mA + 0.46 x (3.0 V – 3.3 V) = 13.76 mA at 3.0 V and SYSCLK
DD
= 3.3 V; SYSCLK = 5 MHz, Idle IDD = 8.25 mA – (24 MHz – 5 MHz) x
DD
< 0.1 µA
8.69
9.59
< 0.1 µA
for > 30 MHz, the estimate should
DD
mA
mA
Other electrical characteristics tables are fo und in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in
26 Rev. 1.3
Table 3.2.
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 3.2. Index to Electrical Characteristics Tables
Table Title Page No.
ADC0 Electrical Characteristics 56
Voltage Reference Electrical Char
Comparator Electrical Characteristics 68
Voltage Regulator Electrical Specifications 69
Reset Electrical Characteristics 106
Flash Electrical Ch
AC Parameters for Exter
Oscillator Electrical Characteristics 141
Port I/O DC Electrical Characteristics 158
USB Transceiver Electrical Characteristics 187
aracteristics 109
nal Memory Interface 130
acteristics 58
Rev. 1.3 27
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Name
V
DD
GND 7 3 Ground.
RST/
C2CK
C2D 14 — D I/O Bi-directional data signal for the C2 Debug Interface.
P3.0 /
C2D
REGIN 11 7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
VBUS 12 8 D In VBUS Sense Input. This pin should be connected to the
Pin Numbers
Type Description
48-pin 32-pin
10 6 Power In
Power
Out
13 9 D I/O
D I/O
— 10 D I/O
D I/O
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 11.
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 15 for a complete description of Port
3.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS signal
cates a USB network connection.
of a USB network. A 5 V signal on this pin indi-
D+ 8 4 D I/O USB D+.
D- 9 5 D I/O USB D–.
P0.0 6 2 D I/O or
A In
P0.1 5 1 D I/O or
A In
P0.2 4 32 D I/O or
A In
P0.3 3 31 D I/O or
A In
P0.4 2 30 D I/O or
A In
P0.5 1 29 D I/O or
A In
P0.6 48 28 D I/O or
A In
P0.7 47 27 D I/O or
A In
Port 0.0. See Section 15 for a complete description of Port
0.
Port 0.1.
Port 0.2.
Port 0.3.
Port 0.4.
Port 0.5.
Port 0.6.
Port 0.7.
28 Rev. 1.3
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued)
Name
P1.0 46 26 D I/O or
P1.1 45 25 D I/O or
P1.2 44 24 D I/O or
P1.3 43 23 D I/O or
P1.4 42 22 D I/O or
P1.5 41 21 D I/O or
P1.6 40 20 D I/O or
P1.7 39 19 D I/O or
P2.0 38 18 D I/O or
P2.1 37 17 D I/O or
Pin Numbers
Type Description
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 1.0. See Section 15 for a complete description of Port
1.
Port 1.1.
Port 1.2.
Port 1.3.
Port 1.4.
Port 1.5.
Port 1.6.
Port 1.7.
Port 2.0. See Section 15 for a complete description of Port
2.
Port 2.1.
P2.2 36 16 D I/O or
A In
P2.3 35 15 D I/O or
A In
P2.4 34 14 D I/O or
A In
P2.5 33 13 D I/O or
A In
P2.6 32 12 D I/O or
A In
P2.7 31 11 D I/O or
A In
P3.0 30 — D I/O or
A In
P3.1 29 — D I/O or
A In
P3.2 28 — D I/O or
A In
Port 2.2.
Port 2.3.
Port 2.4.
Port 2.5.
Port 2.6.
Port 2.7.
Port 3.0. See Section 15 for a complete description of Port
3.
Port 3.1.
Port 3.2.
Rev. 1.3 29
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D (Continued)
Name
P3.3 27 — D I/O or
P3.4 26 — D I/O or
P3.5 25 — D I/O or
P3.6 24 — D I/O or
P3.7 23 — D I/O or
P4.0 22 — D I/O or
P4.1 21 — D I/O or
P4.2 20 — D I/O or
P4.3 19 — D I/O or
P4.4 18 — D I/O or
Pin Numbers
Type Description
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 3.3.
Port 3.4.
Port 3.5.
Port 3.6.
Port 3.7.
Port 4.0. See Section 15 for a complete description of Port
4.
Port 4.1.
Port 4.2.
Port 4.3.
Port 4.4.
P4.5 17 — D I/O or
A In
P4.6 16 — D I/O or
A In
P4.7 15 — D I/O or
A In
Port 4.5.
Port 4.6.
Port 4.7.
30 Rev. 1.3
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