Silicon Laboratories C8051F347, C8051F341, C8051F345, C8051F344, C8051F340 User Manual
...
C8051F340/1/2/3/4/5/6/7
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC
• Up to 200 ksps
• Built-in analog multiplexer with single-ended and
differential mode
• VREF from external pin, internal reference, or V
• Built-in temperature sensor
• External conversion start input option
DD
- Two comparators
- Internal voltage reference
- Brown-out detector and POR Circuitry
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 3.6 to 5.25 V supported using On-Chip
Voltage Regulator
HIgh Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
Instructions in 1 or 2
system clocks
- 48 MIPS and 25 MIPS versions available.
- Expanded interrupt handler
Memory
- 4352 or 2304 Bytes RAM
- 64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, SMBus™, and one or two
enhanced UART serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: 0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F340/1/4/5)
- 32-pin LQFP (C8051F342/3/6/7)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
TEMP
SENSOR
10-bit
200 ksps
ADC
PRECISION INTERNAL
OSCILLATORS
+
+
-
-
VREGVREF
DIGITAL I/O
UART0
UART1
SPI
SMBus
PCA
4 Timers
48 Pin Only
USB Controller /
CROSSBAR
Transceiver
Ext. Memory I/F
Port 0
Port 1
Port 2
Port 3
Port 4
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 0.5 1/06 Copyright © 2006 by Silicon Laboratories C8051F34x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
8051 CPU
(48/25 MIPS)
DEBUG
CIRCUITRY
4/2 kB RAM
POR
WDT
C8051F340/1/2/3/4/5/6/7
NOTES:
2 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table Of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 21
1.1.1. Fully 8051 Compatible.............................................................................. 21
1.1.2. Improved Throughput............................................................................... 21
1.1.3. Additional Features .................................................................................. 21
1.2. On-Chip Memory............................................................................................... 23
1.3. Universal Serial Bus Controller......................................................................... 24
1.4. Voltage Regulator............................................................................................. 25
1.5. On-Chip Debug Circuitry................................................................................... 25
1.6. Programmable Digital I/O and Crossbar........................................................... 26
1.7. Serial Ports ....................................................................................................... 27
1.8. Programmable Counter Array........................................................................... 27
1.9. 10-Bit Analog to Digital Converter..................................................................... 28
1.10.Comparators..................................................................................................... 29
2. Absolute Maximum Ratings .................................................................................. 30
3. Global DC Electrical Characteristics.................................................................... 31
4. Pinout and Package Definitions............................................................................ 33
5. 10-Bit ADC (ADC0).................................................................................................. 41
5.1. Analog Multiplexer ............................................................................................ 42
5.2. Temperature Sensor......................................................................................... 43
5.3. Modes of Operation .......................................................................................... 45
5.3.1. Starting a Conversion............................................................................... 45
5.3.2. Tracking Modes . ....................................................................................... 46
5.3.3. Settling Time Requirements..................................................................... 47
5.4. Programmable Window Detector...................................................................... 52
5.4.1. Window Detector In Single-Ended Mode ................................................. 54
5.4.2. Window Detector In Differential Mode...................................................... 55
6. Voltage Reference.................................................................................................. 57
7. Comparators........................................................................................................... 59
8. Voltage Regulator (REG0)...................................................................................... 69
8.1. Regulator Mode Selection................................................................................. 69
8.2. VBUS Detection................................................................................................ 69
9. CIP-51 Microcontroller........................................................................................... 73
9.1. Instruction Set................................................................................................... 74
9.1.1. Instruction and CPU Timing ..................................................................... 74
9.1.2. MOVX Instruction and Program Memory ................................................. 75
9.2. Memory Organization........................................................................................ 79
9.2.1. Program Memory...................................................................................... 79
9.2.2. Data Memory............................................................................................ 80
9.2.3. General Purpose Registers...................................................................... 80
9.2.4. Bit Addressable Locations........................................................................ 80
9.2.5. Stack ....................................................................................................... 80
9.2.6. Special Function Registers....................................................................... 81
9.2.7. Register Descriptions............................................................................... 85
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9.3. Interrupt Handler............................................................................................... 87
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87
9.3.2. External Interrupts.................................................................................... 87
9.3.3. Interrupt Priorities..................................................................................... 88
9.3.4. Interrupt Latency ...................................................................................... 88
9.3.5. Interrupt Register Descriptions................................................................. 89
9.4. Power Management Modes.............................................................................. 96
9.4.1. Idle Mode.................................................................................................. 96
9.4.2. Stop Mode................................................................................................ 96
10.Prefetch Engine ...................................................................................................... 99
11.Reset Sources....................................................................................................... 101
11.1.Power-On Reset............................................................................................. 102
11.2.Power-Fail Reset / VDD Monitor .................................................................... 103
11.3.External Reset................................................................................................ 104
11.4.Missing Clock Detector Reset ........................................................................ 104
11.5.Comparator0 Reset........................................................................................ 104
11.6.PCA Watchdog Timer Reset .......................................................................... 104
11.7.Flash Error Reset ........................................................................................... 104
11.8.Software Reset............................................................................................... 105
11.9.USB Reset . ..................................................................................................... 105
12.Flash Memory ....................................................................................................... 109
12.1.Programming The Flash Memory................................................................... 109
12.1.1.Flash Lock and Key Functions............................................................... 109
12.1.2.Flash Erase Procedure .......................................................................... 109
12.1.3.Flash Write Procedure ........................................................................... 110
12.2.Non-volatile Data Storage .............................................................................. 111
12.3.Security Options............................................................................................. 111
13.External Data Memory Interface and On-Chip XRAM........................................ 117
13.1.Accessing XRAM............................................................................................ 117
13.1.1.16-Bit MOVX Example........................................................................... 117
13.1.2.8-Bit MOVX Example............................................................................. 117
13.2.Accessing USB FIFO Space .......................................................................... 118
13.3.Configuring the External Memory Interface.................................................... 119
13.4.Port Configuration........................................................................................... 119
13.5.Multiplexed and Non-multiplexed Selection.................................................... 122
13.5.1.Multiplexed Configuration....................................................................... 122
13.5.2.Non-multiplexed Configuration............................................................... 123
13.6.Memory Mode Selection................................................................................. 123
13.6.1.Internal XRAM Only ............................................................................... 124
13.6.2.Split Mode without Bank Select.............................................................. 124
13.6.3.Split Mode with Bank Select................................................................... 125
13.6.4.External Only.......................................................................................... 125
13.7.Timing .......................................................................................................... 125
13.7.1.Non-multiplexed Mode........................................................................... 127
13.7.2.Multiplexed Mode................................................................................... 130
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14.Oscillators............................................................................................................. 135
14.1.Programmable Internal High-Frequency (H-F) Oscillator............................... 136
14.1.1.Internal H-F Oscillator Suspend Mode................................................... 136
14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 137
14.2.1.Calibrating the Internal L-F Oscillator..................................................... 137
14.3.External Oscillator Drive Circuit...................................................................... 139
14.3.1.Clocking Timers Directly Through the External Oscillator...................... 139
14.3.2.External Crystal Example....................................................................... 139
14.3.3.External RC Example............................................................................. 140
14.3.4.External Capacitor Example................................................................... 140
14.4.4x Clock Multiplier .......................................................................................... 142
14.5.System and USB Clock Selection .................................................................. 143
14.5.1.System Clock Selection ......................................................................... 143
14.5.2.USB Clock Selection.............................................................................. 143
15.Port Input/Output.................................................................................................. 147
15.1.Priority Crossbar Decoder.............................................................................. 149
15.2.Port I/O Initialization ....................................................................................... 151
15.3.General Purpose Port I/O............................................................................... 154
16.Universal Serial Bus Controller (USB0).............................................................. 163
16.1.Endpoint Addressing ...................................................................................... 164
16.2.USB Transceiver ............................................................................................ 164
16.3.USB Register Access..................................................................................... 166
16.4.USB Clock Configuration................................................................................ 170
16.5.FIFO Management ......................................................................................... 171
16.5.1.FIFO Split Mode..................................................................................... 171
16.5.2.FIFO Double Buffering........................................................................... 172
16.5.3.FIFO Access .......................................................................................... 172
16.6.Function Addressing....................................................................................... 173
16.7.Function Configuration and Control................................................................ 173
16.8.Interrupts ........................................................................................................ 176
16.9.The Serial Interface Engine............................................................................ 180
16.10.Endpoint0 ..................................................................................................... 180
16.10.1.Endpoint0 SETUP Transactions .......................................................... 181
16.10.2.Endpoint0 IN Transactions................................................................... 181
16.10.3.Endpoint0 OUT Transactions............................................................... 182
16.11.Configuring Endpoints1-3............................................................................. 184
16.12.Controlling Endpoints1-3 IN.......................................................................... 184
16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 184
16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 185
16.13.Controlling Endpoints1-3 OUT...................................................................... 187
16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 187
16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 188
17.SMBus ................................................................................................................... 193
17.1.Supporting Documents................................................................................... 194
17.2.SMBus Configuration...................................................................................... 194
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17.3.SMBus Operation........................................................................................... 194
17.3.1.Arbitration............................................................................................... 195
17.3.2.Clock Low Extension.............................................................................. 196
17.3.3.SCL Low Timeout................................................................................... 196
17.3.4.SCL High (SMBus Free) Timeout .......................................................... 196
17.4.Using the SMBus............................................................................................ 196
17.4.1.SMBus Configuration Register............................................................... 198
17.4.2.SMB0CN Control Register..................................................................... 201
17.4.3.Data Register......................................................................................... 204
17.5.SMBus Transfer Modes.................................................................................. 204
17.5.1.Master Transmitter Mode....................................................................... 204
17.5.2.Master Receiver Mode........................................................................... 206
17.5.3.Slave Receiver Mode............................................................................. 207
17.5.4.Slave Transmitter Mode......................................................................... 208
17.6.SMBus Status Decoding................................................................................. 208
18.UART0.................................................................................................................... 211
18.1.Enhanced Baud Rate Generation................................................................... 212
18.2.Operational Modes......................................................................................... 212
18.2.1.8-Bit UART............................................................................................. 213
18.2.2.9-Bit UART............................................................................................. 214
18.3.Multiprocessor Communications .................................................................... 214
19.UART1 (C8051F340/1/4/5 Only) ........................................................................... 219
19.1.Baud Rate Generator ..................................................................................... 220
19.2.Data Format.................................................................................................... 221
19.3.Configuration and Operation .......................................................................... 222
19.3.1.Data Transmission................................................................................. 222
19.3.2.Data Reception ...................................................................................... 222
19.3.3.Multiprocessor Communications............................................................ 223
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 229
20.1.Signal Descriptions......................................................................................... 230
20.1.1.Master Out, Slave In (MOSI).................................................................. 230
20.1.2.Master In, Slave Out (MISO).................................................................. 230
20.1.3.Serial Clock (SCK)................................................................................. 230
20.1.4.Slave Select (NSS) ................................................................................ 230
20.2.SPI0 Master Mode Operation......................................................................... 231
20.3.SPI0 Slave Mode Operation........................................................................... 233
20.4.SPI0 Interrupt Sources................................................................................... 233
20.5.Serial Clock Timing......................................................................................... 234
20.6.SPI Special Function Registers...................................................................... 236
21.Timers.................................................................................................................... 243
21.1.Timer 0 and Timer 1....................................................................................... 243
21.1.1.Mode 0: 13-bit Counter/Timer................................................................ 243
21.1.2.Mode 1: 16-bit Counter/Timer................................................................ 244
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 245
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 246
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21.2.Timer 2 .......................................................................................................... 251
21.2.1.16-bit Timer with Auto-Reload................................................................ 251
21.2.2.8-bit Timers with Auto-Reload................................................................ 252
21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge...... 253
21.3.Timer 3 .......................................................................................................... 257
21.3.1.16-bit Timer with Auto-Reload................................................................ 257
21.3.2.8-bit Timers with Auto-Reload................................................................ 258
21.3.3.USB Start-of-Frame Capture.................................................................. 259
22.Programmable Counter Array (PCA0)................................................................ 263
22.1.PCA Counter/Timer........................................................................................ 264
22.2.Capture/Compare Modules ............................................................................ 265
22.2.1.Edge-triggered Capture Mode................................................................ 266
22.2.2.Software Timer (Compare) Mode........................................................... 267
22.2.3.High Speed Output Mode....................................................................... 268
22.2.4.Frequency Output Mode ........................................................................ 269
22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 270
22.2.6.16-Bit Pulse Width Modulator Mode....................................................... 271
22.3.Watchdog Timer Mode................................................................................... 272
22.3.1.Watchdog Timer Operation.................................................................... 272
22.3.2.Watchdog Timer Usage ......................................................................... 273
22.4.Register Descriptions for PCA........................................................................ 274
23.C2 Interface........................................................................................................... 279
23.1.C2 Interface Registers.................................................................................... 279
23.2.C2 Pin Sharing ............................................................................................... 281
Contact Information.................................................................................................. 282
Rev. 0.5 7
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NOTES:
8 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
List of Figures and Tables
1. System Overview
Table 1.1. Product Selection Guide........................................................................ 18
Figure 1.1. C8051F340/1/4/5 Block Diagram........................................................... 19
Figure 1.2. C8051F342/3/6/7 Block Diagram........................................................... 20
Figure 1.3. On-Chip Clock and Reset ...................................................................... 22
Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6) ................ 23
Figure 1.5. USB Controller Block Diagram............................................................... 24
Figure 1.6. Digital Crossbar Diagram....................................................................... 26
Figure 1.7. PCA Block Diagram ............................................................................... 27
Figure 1.8. PCA Block Diagram ............................................................................... 27
Figure 1.9. 10-Bit ADC Block Diagram..................................................................... 28
Figure 1.10. Comparator0 Block Diagram................................................................ 29
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings................................................................... 30
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics...................................................... 31
Table 3.2. Index to Electrical Characteristics Tables.............................................. 32
4. Pinout and Package Definitions
Table 4.1. Pin Definitions fo r the C8051F340/1/2/3/4/5/6/7.................................... 33
Figure 4.1. TQFP-48 Pinout Diagram (Top View) .................................................... 36
Table 4.2. TQFP-48 Package Dimensions.............................................................. 37
Figure 4.2. TQFP-48 Package Diagram................................................................... 37
Figure 4.3. LQFP-32 Pinout Diagram (Top View) .................................................... 38
Table 4.3. LQFP-32 Package Dimensions.............................................................. 39
Figure 4.4. LQFP-32 Package Diagram................................................................... 39
5. 10-Bit ADC (ADC0)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 41
Figure 5.2. Temperature Sensor Transfer Function................................................. 43
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 44
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 46
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 47
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data... 54
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 54
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 55
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 55
Table 5.1. ADC0 Electrical Characteristics............................................................. 56
6. Voltage Reference
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 57
Table 6.1. Voltage Reference Electrical Characteristics......................................... 58
7. Comparators
Figure 7.1. Comparator Functional Block Diagram .................................................. 60
Figure 7.2. Comparator Hysteresis Plot ................................................................... 61
Table 7.1. Comparator Electrical Characteristics.................................................... 68
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8. Voltage Regulator (REG0)
Table 8.1. Voltage Regulator Electrical Specifications............................................ 69
Figure 8.1. REG0 Configuration: USB Bus-Powered............................................... 70
Figure 8.2. REG0 Configuration: USB Self-Powered............................................... 70
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 71
Figure 8.4. REG0 Configuration: No USB Connection............................................. 71
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 73
Table 9.1. CIP-51 Instruction Set Summary............................................................ 75
Figure 9.2. Memory Map .......................................................................................... 79
Table 9.2. Special Function Register (SFR) Memory Map...................................... 81
Table 9.3. Special Function Registers .................................................................... 82
Table 9.4. Interrupt Summary ................................................................................. 89
10.Prefetch Engine
11.Reset Sources
Figure 11.1. Reset Sources.................................................................................... 101
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 102
Table 11.1. Reset Electrical Characteristics........................................................... 107
12.Flash Memory
Table 12.1. Flash Electrical Characteristics ........................................................... 111
Figure 12.1. Flash Program Memory Map and Security Byte................................. 112
13.External Data Memory Interface and On-Chip XRAM
Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’.. 118
Figure 13.2. Multiplexed Configuration Example.................................................... 122
Figure 13.3. Non-multiplexed Configuration Example............................................ 123
Figure 13.4. EMIF Operating Modes...................................................................... 123
Figure 13.5. Non-multiplexed 16-bit MOVX Timing................................................ 127
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 128
Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 129
Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 130
Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing......................... 131
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing............................ 132
Table 13.1. AC Parameters for External Memory Interface.................................... 133
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 135
Table 14.1. Oscillator Electrical Characteristics..................................................... 145
15.Port Input/Output
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)................ 147
Figure 15.2. Port I/O Cell Block Diagram ............................................................... 148
Figure 15.3. Crossbar Priority Decoder with No Pins Skipped............................... 149
Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 150
Table 15.1. Port I/O DC Electrical Characteristics.................................................. 162
16.Universal Serial Bus Controller (USB0)
Figure 16.1. USB0 Block Diagram.......................................................................... 163
Table 16.1. Endpoint Addressing Scheme............................................................. 164
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Figure 16.2. USB0 Register Access Scheme......................................................... 166
Table 16.2. USB0 Controller Registers .................................................................. 169
Figure 16.3. USB FIFO Allocation.......................................................................... 171
Table 16.3. FIFO Configurations............................................................................ 172
Table 16.4. USB Transceiver Electrical Characteristics......................................... 191
17.SMBus
Figure 17.1. SMBus Block Diagram ....................................................................... 193
Figure 17.2. Typical SMBus Configuration............................................................. 194
Figure 17.3. SMBus Transaction............................................................................ 195
Table 17.1. SMBus Clock Source Selection........................................................... 198
Figure 17.4. Typical SMBus SCL Generation......................................................... 199
Table 17.2. Minimum SDA Setup and Hold Times................................................. 199
Table 17.3. Sources for Hardware Changes to SMB0CN...................................... 203
Figure 17.5. Typical Master Transmitter Sequence................................................ 205
Figure 17.6. Typical Master Receiver Sequence.................................................... 206
Figure 17.7. Typical Slave Receiver Sequence...................................................... 207
Figure 17.8. Typical Slave Transmitter Sequence.................................................. 208
Table 17.4. SMBus Status Decoding...................................................................... 209
18.UART0
Figure 18.1. UART0 Block Diagram....................................................................... 211
Figure 18.2. UART0 Baud Rate Logic.................................................................... 212
Figure 18.3. UART Interconnect Diagram.............................................................. 213
Figure 18.4. 8-Bit UART Timing Diagram............................................................... 213
Figure 18.5. 9-Bit UART Timing Diagram............................................................... 214
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram.......................... 215
Table 18.1. Timer Settings for Standard Baud Rates
Using The Internal Oscillator ............................................................... 218
19.UART1 (C8051F340/1/4/5 Only)
Figure 19.1. UART1 Block Diagram....................................................................... 219
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates.................... 220
Figure 19.2. UART1 Timing Without Parity or Extra Bit.......................................... 221
Figure 19.3. UART1 Timing With Parity ................................................................. 221
Figure 19.4. UART1 Timing With Extra Bit............................................................. 221
Figure 19.5. Typical UART Interconnect Diagram.................................................. 222
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram.......................... 223
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram............................................................................. 229
Figure 20.2. Multiple-Master Mode Connection Diagram....................................... 232
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 232
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram... 232
Figure 20.5. Master Mode Data/Clock Timing........................................................ 234
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 235
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 235
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 239
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 239
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Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 240
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 240
Table 20.1. SPI Slave Timing Parameters ............................................................. 241
21.Timers
Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 244
Figure 21.2. T0 Mode 2 Block Diagram.................................................................. 245
Figure 21.3. T0 Mode 3 Block Diagram.................................................................. 246
Figure 21.4. Timer 2 16-Bit Mode Block Diagram .................................................. 251
Figure 21.5. Timer 2 8-Bit Mode Block Diagram .................................................... 252
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’).............................................. 253
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’).............................................. 254
Figure 21.8. Timer 3 16-Bit Mode Block Diagram .................................................. 257
Figure 21.9. Timer 3 8-Bit Mode Block Diagram .................................................... 258
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)............................................ 259
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)............................................ 260
22.Programmable Counter Array (PCA0)
Figure 22.1. PCA Block Diagram............................................................................ 263
Table 22.1. PCA Timebase Input Options.............................................................. 264
Figure 22.2. PCA Counter/Timer Block Diagram.................................................... 264
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..... 265
Figure 22.3. PCA Interrupt Block Diagram............................................................. 265
Figure 22.4. PCA Capture Mode Diagram.............................................................. 266
Figure 22.5. PCA Software Timer Mode Diagram.................................................. 267
Figure 22.6. PCA High Speed Output Mode Diagram............................................ 268
Figure 22.7. PCA Frequency Output Mode............................................................ 269
Figure 22.8. PCA 8-Bit PWM Mode Diagram......................................................... 270
Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 271
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled................................. 272
Table 22.3. Watchdog Timer Timeout Intervals1.................................................... 273
23.C2 Interface
Figure 23.1. Typical C2 Pin Sharing....................................................................... 281
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List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 52
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 52
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 53
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 53
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 72
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 10.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 11.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 11.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 12.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 12.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 12.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SFR Definition 13.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 120
SFR Definition 13.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 121
SFR Definition 13.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 126
SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 137
Rev. 0.5 13
C8051F340/1/2/3/4/5/6/7
SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.4. P0: Port0 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.7. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.8. P1: Port1 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.9. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.10. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.11. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.12. P2: Port2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.13. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.14. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 15.15. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 15.16. P3: Port3 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.17. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.18. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.19. P3SKIP: Port3 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 15.20. P4: Port4 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 15.21. P4MDIN: Port4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 15.22. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 16.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 165
SFR Definition 16.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
USB Register Definition 16.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 169
USB Register Definition 16.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 170
USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 172
USB Register Definition 16.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 173
USB Register Definition 16.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 175
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 176
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 176
USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 177
USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 177
USB Register Definition 16.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 178
USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 179
USB Register Definition 16.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 179
USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 180
USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 183
USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 184
USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 186
14 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187
USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189
USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 190
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 190
SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 200
SFR Definition 17.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SFR Definition 17.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SFR Definition 18.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 217
SFR Definition 19.1. SCON1: UART1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 19.2. SMOD1: UART1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 19.3. SBUF1: UART1 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control . . . . . . . . . . . 226
SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte . . . . . . . . . . 227
SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte . . . . . . . . . . . 227
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 21.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
SFR Definition 21.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 21.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 21.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 256
SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 256
SFR Definition 21.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 21.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 21.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 262
SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 262
SFR Definition 21.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SFR Definition 21.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SFR Definition 22.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
SFR Definition 22.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 276
SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 277
SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 277
SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 277
SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 278
C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Rev. 0.5 15
C8051F340/1/2/3/4/5/6/7
C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279
C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 280
C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 280
C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 280
16 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1. System Overview
C8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed- signal System-on-a-Chip MCUs. Highlighted
features are listed below. Refer to
• High-speed pipelined 8051-compa tible microcontroller core (up to 48 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1 kB FIFO RAM
• Supply Voltage Regulator
• True 10-bit 200 ksps differential / single-ended ADC with analog multiplexer
• On-chip Voltage Reference and Temperature Sensor
• On-chip Voltage Comparators (2)
• Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier
• Internal low-frequency oscillator for additional power savings
• Up to 64 kB of on-chip Flash memory
• Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
• External Memory Interface (EMIF) available on 48-pin versions.
• SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
• On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
• Up to 40 Port I/O (5 V tolerant)
Table 1.1 for specific product feature selection.
With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F340/1/2/3/4/5/6/7 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6
USB communication. The Port I/O and /RST pins are tolerant of input signals up to 5
4/5/6/7 are available in a 48-pin TQFP or a 32-pin LQFP package.
V, the on-chip Vo ltage Regulator must be used. A minimum of 3.0 V is required for
V. C8051F340/1/2/3/
-
Rev. 0.5 17
C8051F340/1/2/3/4/5/6/7
Table 1.1. Product Selection Guide
Ordering Part Number
C8051F340-GQ 48 64k 4352 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F341-GQ 48 32k 2304 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F342-GQ 48 64k 4352 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F343-GQ 48 32k 2304 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F344-GQ 25 64k 4352 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F345-GQ 25 32k 2304 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F346-GQ 25 64k 4352 3 - 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F347-GQ 25 32k 2304 3 - 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
MIPS (Peak)
Flash Memory (Bytes)
RAM
Calibrated Internal Oscillator
Low Frequency Oscillator
USB with 1k Endpoint RAM
Supply Voltage Regulator
SMBus/I2C
Enhanced SPI
UARTs
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
External Memory Interface (EMIF)
10-bit 200ksps ADC
Temperature Sensor
Voltage Reference
Analog Comparators
Package
18 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
C2D
C2CK/RST
VDD
VREG
GND
VBUS
Debug / Programming
Hardware
Reset
CIP-51 8051
Power-On
Reset
Supply
Monitor
Voltage
Regulator
Power
Net
Controller Core
64/32k Byte ISP FLASH
Program Memory
256 Byte RAM
4/2k Byte XRAM
SFR
Bus
XTAL1
XTAL2
System Clock Setup
External
Oscillator
Internal
Oscillator
Clock
Recovery
Clock
Multiplier
Low Freq.
Oscillator
USB Peripheral
D+
D-
Full / Low
Speed
Transceiver
Controller
1k Byte
RAM
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0, 1,
2, 3
Crossbar
PCA/WDT
Decoder
SMBus
SPI
Crossbar Control
External Memory
Interface
Control
Address
Data
Analog Peripherals
VREF
VREFVDD
2 Comparators
10-bit
200ksps
ADC
A
M
U
X
Priority
CP0
CP1
VDD
Temp
Sensor
P2 / P3
+
-
+
-
P1
P4
AIN0 - AIN19
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Figure 1.1. C8051F340/1/4/5 Block Diagram
Rev. 0.5 19
C8051F340/1/2/3/4/5/6/7
C2CK/RST
VDD
VREG
GND
VBUS
C2D
Debug / Programming
Hardware
Reset
CIP-51 8051
Power-On
Reset
Supply
Monitor
Voltage
Regulator
Power
Net
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
System Clock Setup
XTAL1
XTAL2
External
Oscillator
Internal
Oscillator
Clock
Recovery
Clock
Multiplier
Low Freq.
Oscillator*
USB Peripheral
D+
D-
Full / Low
Speed
Transceiver
*Low Frequency Oscillator option not available on C8051F346/7
Controller
1 kB RAM
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0, 1,
2, 3
PCA/WDT
Crossbar
Decoder
SMBus
SPI
Crossbar Control
Analog Peripherals
VREF
VREFVDD
2 Comparators
10-bit
200 ksps
ADC
A
M
U
X
Priority
CP0
CP1
VDD
Temp
Sensor
+
-
+
-
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
AIN0 - AIN20
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Figure 1.2. C8051F342/3/6/7 Block Diagram
20 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x asse mblers and c ompil
ers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard
8052, including four 16-bit counter/timers, two full-duplex UARTs with extended baud rate configuration, an
enhanced SPI port, up to 4352
space, and up to 40 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions listed by
the required execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
Bytes of on-chip RAM, 128 byte Special Function Register (SFR) address
MHz. By contrast, the CIP-51 core exe-
-
1.1.3. Additional Features
The C8051F340/1/2/3/4/5/6/7 SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sour ces into the CIP-51 (as opp osed to 7 for the st andard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below V
(USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detec-
tion from Comparator0, a forced software reset, an exte rnal reset pin, and an erran t Flash read/wr ite protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software. The WDT may be permanently enabled in software after a power-on reset during
MCU initialization.
The high-speed internal oscillator is factory calibrated to 12 MHz ±1.5%. A clock recovery mechanism
allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed
mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscil
lators may also be used with the 4x Clock Multiplier. An internal low-frequency oscillator is also included to
aid applications where power savings are critical. Also included is an external oscillator drive circuit, which
allows an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system
clock. The system clock may be configured to use ether of the internal oscillators, an external oscillator, or
the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly
between oscillator sources. The low-frequency internal oscillator or an external oscillator can be useful in
low power applications, allowing the MCU to run from a slow (power saving) external clock source, while
periodically switching to a higher-speed clock source when fast throughput is necessary.
as given in Table 11.1 on page 107), the USB controller
RST
-
Rev. 0.5 21
C8051F340/1/2/3/4/5/6/7
VDD
Comparator 0
System
Clock
Clock Select
+
-
C0RSEF
Missing
Clock
Detector
(one-
shot)
EN
MCD
WDT
Enable
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
PCA
XTAL1
XTAL2
Internal LF
Oscillator
Internal HF
Oscillator
Clock
Multiplier
External
Oscillator
Drive
Px.x
Px.x
EN
WDT
Enable
Supply
Monitor
+
-
System Reset
Enable
Power On
Reset
Software Reset (SWRSF)
Errant
FLASH
Operation
'0'
USB
Controller
(wired-OR)
Enable
Reset
Funnel
VBUS
Transition
/RST
Figure 1.3. On-Chip Clock and Reset
22 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four b anks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addr essable.
Program memory consists of 64 k (C8051F340/2/4/6) or 32 k (C8051F341/3/5/7) bytes of Flash. This
memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip program
ming voltage. On-chip XRAM is also included for the entire device family. The 64 k FLASH devices
(C8051F340/2/4/6) have 4
XRAM space. A separate 1
k of XRAM space. The 32 k Flash devices (C8051F341/3/5/7) have 2 k of
k Bytes of USB FIFO RAM is also included on all devices. See Figure 1.4 for
the MCU system memory map of the 64k Flash devices. Note that on the 64k devices, 1024 bytes at locations 0xFC00 to 0xFFFF are reserved.
-
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-Chip XRAM
(Available only on devices
with EMIF)
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
0x0000
USB FIFOs
1024 Bytes
Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6)
Rev. 0.5 23
0x07FF
0x0400
C8051F340/1/2/3/4/5/6/7
1.3. Universal Serial Bus Controller
The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k Byte block of RAM is used for USB FIFO space. This FIFO space is distributed among Endpoints0-3;
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum
FIFO size is 512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The
pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the
software-selected speed setting (Full or Low Speed).
D+
Transceiver Serial Interface Engine (SIE)
VDD
Data
Transfer
Control
D-
Endpoint0
IN/OUT
Endpoint1
Endpoint2
Endpoint3
IN OUT
IN OUT
IN OUT
USB FIFOs
(1k RAM)
USB
Control,
Status, and
Interrupt
Registers
CIP-51 Core
Figure 1.5. USB Controller Block Diagram
24 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.4. Voltage Regulator
C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output
appears on the V
abled by software.
1.5. On-Chip Debug Circuitry
The C8051F340/1/2/3/4/5/6/7 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the USB, ADC, and
gle stepping, or at a breakpoint in order to keep them synchronized.
The C8051F340DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F340/1/2/3/4/5/6/7 M CUs. The kit includes software with a developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a
debug adapter. It also has a target application board with the C8051F340 MCU installed, the necessary
cables for connection to a PC, and a wall-mount po wer sup ply. The development kit contents may also be
used to program and debug the device on the production PCB using the appropriate connections fo r the
programming pins.
pin, and can also be used to power other external devices. REG0 can be enabled/dis-
DD
SMBus) are stalled when the MCU is halted, during sin-
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Rev. 0.5 25
C8051F340/1/2/3/4/5/6/7
1.6. Programmable Digital I/O and Crossbar
C8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7 devices include 25
I/O pins (three byte-wide Ports, and a 1-bit- wide Port ). The C8051F340 /1/2/3/4/5/6/7 Port s behave like typ
ical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital
I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. Th e
“weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings
capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.6).
On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the
controller can be configured to appear on the Port I/O pin s specified in the Crossbar Control reg isters. This
allows the user to select the exact mix of general purpose Po rt I/O and digit al resour ces needed for the end
application.
-
Highest
Priority
Lowest
Priority
UART0
SMBus
Outputs
Outputs
SYSCLK
(Internal Digital Signals)
T0, T1
UART1*
P0
P1
P2
(Port Latches)
P3
SPI
CP0
CP1
PCA
2
4
2
2
2
6
2
2
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7*)
XBR0, XBR1, XBR2,
PnSKIP Registers
Priority
Decoder
Digital
Crossbar
PnMDOUT,
PnMDIN Registers
P0
8
I/O
Cells
P1
8
I/O
Cells
P2
8
I/O
Cells
P3
8
I/O
Cells
*Note: P3.1-P3.7 and UART1 only
available on 48-pin package
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7*
Figure 1.6. Digital Crossbar Diagram
26 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.7. Serial Ports
The C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an
Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in add ition to the fou r 1 6-bit g enera l pu rpose counter/timers. The PCA consists of a dedicated 16 -bit cou nter /time r time base with five prog ra mmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, a dedicated External Clock Input (ECI), the sys
tem clock, or the external oscillator clock source divided by 8. The external clock source selection is useful
for real-time clock functionality, where the PCA may be clocked by an external source while the internal
oscillator drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Ti mer, High Speed Output, 8- or 16-bit Pulse Wid t h Modu lator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
-
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
ECI
CEX0
PCA
CLOCK
MUX
Capture/Compare
Module 1
CEX1
16-Bit Counter/Timer
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4 / WDT
CEX4
Crossbar
Port I/O
Figure 1.8. PCA Block Diagram
Rev. 0.5 27
C8051F340/1/2/3/4/5/6/7
1.9. 10-Bit Analog to Digital Converter
The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-b it SAR ADC with a true d if fe rential inpu t mul tiplexer. With a ma ximum throughput of 200 ksp s, the ADC of fer s true 10-bit linear ity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Twenty (48-pin package) or twenty-one (32-pin package) of the Port I/O pins can be used as analog
inputs to the ADC. Additionally, the on-chip Temperature Sensor output and the power supply voltage
(V
) are available as ADC inputs. User firmware may shut down the ADC to save power.
DD
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC output data can be con figur ed to inter rupt the contr oller whe n ADC
data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in
background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
* 21 Selections on 32-pin package
20 Selections on 48-pin package
Port I/O
Pins*
VDD
Temp
Sensor
Port I/O
Pins*
VREF
GND
Configuration, Control, and Data Registers
Positive
Input
(AIN+)
AMUX
(+)
10-Bit
SAR
(-)
Negative
Input
(AIN-)
AMUX
Figure 1.9. 10-Bit ADC Block Diagram
ADC
End of
Conversion
Interrupt
Start
Conversion
16
Window Compare
000 AD0BUSY (W)
001
010
011
100
101
Logic
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
ADC Data
Registers
Window
Compare
Interrupt
28 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.10. Comparators
C8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled and
configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux.
Two comp arator output s may b e routed to a Po rt pin if desired: a latched output and/o r an unlatched (asyn
chronous) output. Comparator response time is programmable, allowing the user to select between
high-speed and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.10 shows the Comparator0 block diagram.
CPnEN
CPnOUT
CMXnN2
CMXnN1
CMXnN0
CPTnMX
CMXnP2
CMXnP1
CMXnP0
CPnRIF
CPnFIF
CPnHYP1
CPTnCN
CPnHYP0
CPnHYN1
CPnHYN0
VDD
CPn
Rising-edge
CPn
Interrupt
CPn
Falling-edge
-
Port I/O connection options vary with
package (32-pin or 48-pin)
Figure 1.10. Comparator0 Block Diagram
CPn +
CPn -
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
Interrupt
Logic
+
-
GND
SET
SET
D
D
Q
Q
CLR
CLR
Q
Q
(SYNCHRONIZER)
Reset Decision Tree
(Comprator 0 Only)
Crossbar
CPnRIE
CPnFIE
CPn
CPnA
Rev. 0.5 29
C8051F340/1/2/3/4/5/6/7
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or /RST with
respect to GND
Voltage on V
Maximum Total current through V
GND
Maximum output current sunk by /RST or any
Port pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to GND –0.3 4.2 V
DD
and
DD
–0.3 5.8 V
500 mA
100 mA
30 Rev. 0.5
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