USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 186
14Rev. 0.5
C8051F340/1/2/3/4/5/6/7
USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187
USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189
USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 190
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 190
•Internal low-frequency oscillator for additional power savings
•Up to 64 kB of on-chip Flash memory
•Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
•External Memory Interface (EMIF) available on 48-pin versions.
•SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
•Four general-purpose 16-bit timers
•Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
•On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
•Up to 40 Port I/O (5 V tolerant)
Table 1.1 for specific product feature selection.
With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F340/1/2/3/4/5/6/7 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6
USB communication. The Port I/O and /RST pins are tolerant of input signals up to 5
4/5/6/7 are available in a 48-pin TQFP or a 32-pin LQFP package.
V, the on-chip Vo ltage Regulator must be used. A minimum of 3.0 V is required for
The C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x asse mblers and c ompil
ers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard
8052, including four 16-bit counter/timers, two full-duplex UARTs with extended baud rate configuration, an
enhanced SPI port, up to 4352
space, and up to 40 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions listed by
the required execution time.
Clocks to Execute122/333/444/558
Number of Instructions265051473121
Bytes of on-chip RAM, 128 byte Special Function Register (SFR) address
MHz. By contrast, the CIP-51 core exe-
-
1.1.3. Additional Features
The C8051F340/1/2/3/4/5/6/7 SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sour ces into the CIP-51 (as opp osed to 7 for the st andard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below V
(USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detec-
tion from Comparator0, a forced software reset, an exte rnal reset pin, and an erran t Flash read/wr ite protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software. The WDT may be permanently enabled in software after a power-on reset during
MCU initialization.
The high-speed internal oscillator is factory calibrated to 12 MHz ±1.5%. A clock recovery mechanism
allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed
mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscil
lators may also be used with the 4x Clock Multiplier. An internal low-frequency oscillator is also included to
aid applications where power savings are critical. Also included is an external oscillator drive circuit, which
allows an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system
clock. The system clock may be configured to use ether of the internal oscillators, an external oscillator, or
the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly
between oscillator sources. The low-frequency internal oscillator or an external oscillator can be useful in
low power applications, allowing the MCU to run from a slow (power saving) external clock source, while
periodically switching to a higher-speed clock source when fast throughput is necessary.
as given in Table 11.1 on page 107), the USB controller
RST
-
Rev. 0.521
C8051F340/1/2/3/4/5/6/7
VDD
Comparator 0
System
Clock
Clock Select
+
-
C0RSEF
Missing
Clock
Detector
(one-
shot)
EN
MCD
WDT
Enable
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
PCA
XTAL1
XTAL2
Internal LF
Oscillator
Internal HF
Oscillator
Clock
Multiplier
External
Oscillator
Drive
Px.x
Px.x
EN
WDT
Enable
Supply
Monitor
+
-
System Reset
Enable
Power On
Reset
Software Reset (SWRSF)
Errant
FLASH
Operation
'0'
USB
Controller
(wired-OR)
Enable
Reset
Funnel
VBUS
Transition
/RST
Figure 1.3. On-Chip Clock and Reset
22Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.2.On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four b anks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addr essable.
Program memory consists of 64 k (C8051F340/2/4/6) or 32 k (C8051F341/3/5/7) bytes of Flash. This
memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip program
ming voltage. On-chip XRAM is also included for the entire device family. The 64 k FLASH devices
(C8051F340/2/4/6) have 4
XRAM space. A separate 1
k of XRAM space. The 32 k Flash devices (C8051F341/3/5/7) have 2 k of
k Bytes of USB FIFO RAM is also included on all devices. See Figure 1.4 for
the MCU system memory map of the 64k Flash devices. Note that on the 64k devices, 1024 bytes at locations 0xFC00 to 0xFFFF are reserved.
-
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-Chip XRAM
(Available only on devices
with EMIF)
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
0x0000
USB FIFOs
1024 Bytes
Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6)
Rev. 0.523
0x07FF
0x0400
C8051F340/1/2/3/4/5/6/7
1.3.Universal Serial Bus Controller
The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k Byte block of RAM is used for USB FIFO space. This FIFO space is distributed among Endpoints0-3;
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum
FIFO size is 512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The
pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the
software-selected speed setting (Full or Low Speed).
D+
TransceiverSerial Interface Engine (SIE)
VDD
Data
Transfer
Control
D-
Endpoint0
IN/OUT
Endpoint1
Endpoint2
Endpoint3
INOUT
INOUT
INOUT
USB FIFOs
(1k RAM)
USB
Control,
Status, and
Interrupt
Registers
CIP-51 Core
Figure 1.5. USB Controller Block Diagram
24Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.4.Voltage Regulator
C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output
appears on the V
abled by software.
1.5.On-Chip Debug Circuitry
The C8051F340/1/2/3/4/5/6/7 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the USB, ADC, and
gle stepping, or at a breakpoint in order to keep them synchronized.
The C8051F340DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F340/1/2/3/4/5/6/7 M CUs. The kit includes software with a developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a
debug adapter. It also has a target application board with the C8051F340 MCU installed, the necessary
cables for connection to a PC, and a wall-mount po wer sup ply. The development kit contents may also be
used to program and debug the device on the production PCB using the appropriate connections fo r the
programming pins.
pin, and can also be used to power other external devices. REG0 can be enabled/dis-
DD
SMBus) are stalled when the MCU is halted, during sin-
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Rev. 0.525
C8051F340/1/2/3/4/5/6/7
1.6.Programmable Digital I/O and Crossbar
C8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7 devices include 25
I/O pins (three byte-wide Ports, and a 1-bit- wide Port ). The C8051F340 /1/2/3/4/5/6/7 Port s behave like typ
ical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital
I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. Th e
“weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings
capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.6).
On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the
controller can be configured to appear on the Port I/O pin s specified in the Crossbar Control reg isters. This
allows the user to select the exact mix of general purpose Po rt I/O and digit al resour ces needed for the end
application.
-
Highest
Priority
Lowest
Priority
UART0
SMBus
Outputs
Outputs
SYSCLK
(Internal Digital Signals)
T0, T1
UART1*
P0
P1
P2
(Port Latches)
P3
SPI
CP0
CP1
PCA
2
4
2
2
2
6
2
2
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7*)
XBR0, XBR1, XBR2,
PnSKIP Registers
Priority
Decoder
Digital
Crossbar
PnMDOUT,
PnMDIN Registers
P0
8
I/O
Cells
P1
8
I/O
Cells
P2
8
I/O
Cells
P3
8
I/O
Cells
*Note: P3.1-P3.7 and UART1 only
available on 48-pin package
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7*
Figure 1.6. Digital Crossbar Diagram
26Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.7.Serial Ports
The C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an
Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8.Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in add ition to the fou r 1 6-bit g enera l pu rpose counter/timers. The PCA consists of a dedicated 16 -bit cou nter /time r time base with five prog ra mmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, a dedicated External Clock Input (ECI), the sys
tem clock, or the external oscillator clock source divided by 8. The external clock source selection is useful
for real-time clock functionality, where the PCA may be clocked by an external source while the internal
oscillator drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Ti mer, High Speed Output, 8- or 16-bit Pulse Wid t h Modu lator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
-
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
ECI
CEX0
PCA
CLOCK
MUX
Capture/Compare
Module 1
CEX1
16-Bit Counter/Timer
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4 / WDT
CEX4
Crossbar
Port I/O
Figure 1.8. PCA Block Diagram
Rev. 0.527
C8051F340/1/2/3/4/5/6/7
1.9.10-Bit Analog to Digital Converter
The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-b it SAR ADC with a true d if fe rential inpu t mul tiplexer. With a ma ximum throughput of 200 ksp s, the ADC of fer s true 10-bit linear ity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Twenty (48-pin package) or twenty-one (32-pin package) of the Port I/O pins can be used as analog
inputs to the ADC. Additionally, the on-chip Temperature Sensor output and the power supply voltage
(V
) are available as ADC inputs. User firmware may shut down the ADC to save power.
DD
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC output data can be con figur ed to inter rupt the contr oller whe n ADC
data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in
background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
* 21 Selections on 32-pin package
20 Selections on 48-pin package
C8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled and
configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux.
Two comp arator output s may b e routed to a Po rt pin if desired: a latched output and/o r an unlatched (asyn
chronous) output. Comparator response time is programmable, allowing the user to select between
high-speed and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.10 shows the Comparator0 block diagram.
CPnEN
CPnOUT
CMXnN2
CMXnN1
CMXnN0
CPTnMX
CMXnP2
CMXnP1
CMXnP0
CPnRIF
CPnFIF
CPnHYP1
CPTnCN
CPnHYP0
CPnHYN1
CPnHYN0
VDD
CPn
Rising-edge
CPn
Interrupt
CPn
Falling-edge
-
Port I/O connection options vary with
package (32-pin or 48-pin)
Figure 1.10. Comparator0 Block Diagram
CPn +
CPn -
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
Interrupt
Logic
+
-
GND
SET
SET
D
D
Q
Q
CLR
CLR
Q
Q
(SYNCHRONIZER)
Reset Decision Tree
(Comprator 0 Only)
Crossbar
CPnRIE
CPnFIE
CPn
CPnA
Rev. 0.529
C8051F340/1/2/3/4/5/6/7
2.Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
ParameterConditionsMinTypMaxUnits
Ambient temperature under bias–55125°C
Storage Temperature–65150°C
Voltage on any Port I/O Pin or /RST with
respect to GND
Voltage on V
Maximum Total current through V
GND
Maximum output current sunk by /RST or any
Port pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to GND–0.34.2V
DD
and
DD
–0.35.8V
500mA
100mA
30Rev. 0.5
C8051F340/1/2/3/4/5/6/7
3.Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
ParameterConditionsMinTypMaxUnits
Digital Supply Voltage
Digital Supply Current with CPU
active
Digital Supply Current with CPU
active and USB active (Full or
Low Speed)
Digital Supply Current with CPU
inactive (not accessing Flash)
Digital Supply Current (suspend
1
= 3.3 V, Clock = 24 MHz
V
DD
V
= 3.3 V, Clock = 1 MHz
DD
= 3.3 V, Clock = 32 kHz
V
DD
V
= 3.3 V, Clock = 24 MHz
DD
V
= 3.3 V, Clock = 6 MHz
DD
= 3.3 V, Clock = 24 MHz
V
DD
= 3.3 V, Clock = 1 MHz
V
DD
V
= 3.3 V, Clock = 32 kHz
DD
Oscillator not running< 0.1µA
mode or shutdown mode)
Digital Supply RAM Data Reten-
tion Voltage
SYSCLK (System Clock)
2
C8051F340/1/2/3
C8051F344/5/6/7
T
(SYSCLK High Time)C8051F340/1/2/3 @ 50 MHz
SYSH
C8051F344/5/6/7
2.73.33.6V
15
0.7
74
TBD
TBD
9
0.5
74
mA
mA
µA
mA
mA
mA
mA
µA
1.5V
0
0
9
48
25
MHz
ns
18
(SYSCLK Low Time)C8051F340/1/2/3 @ 50 MHz
T
SYSL
C8051F344/5/6/7
Specified Operating Temperature Range
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
9
ns
18
-40+85°C
Other electrical characteristics tables are foun d in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in
Table 3.2.
Rev. 0.531
C8051F340/1/2/3/4/5/6/7
Table 3.2. Index to Electrical Characteristics Tables
Table Title
ADC0 Electrical Characteristics56
Voltage Reference Electrical Characteristics58
Comparator Electrical Characteristics68
Voltage Regulator Electrical Specifications69
Reset Electrical Characteristics107
Flash Electrical Characteristics111
AC Parameters for External Memory Interface133
Oscillator Electrical Characteristics145
Port I/O DC Electrical Characteristics162
USB Transceiver Electrical Characteristics191
Page
No.
32Rev. 0.5
4.Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7
C8051F340/1/2/3/4/5/6/7
Name
V
DD
GND73Ground.
/RST/
C2CK
C2D14-D I/OBi-directional data signal for the C2 Debug Interface.
P3.0 /
C2D
REGIN117Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
VBUS128D InVBUS Sense Input. This pin should be connected to the
Pin Numbers
TypeDescription
48-pin 32-pin
106Power In
Power
Out
139D I/O
D I/O
-10D I/O
D I/O
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 15 for a complete description of Port
3.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS signal of a USB network. A 5
cates a USB network connection.
µs. See Section 11.
V signal on this pin indi-
D+84D I/OUSB D+.
D-95D I/OUSB D–.
P0.062D I/O or
A In
P0.151D I/O or
A In
P0.2432D I/O or
A In
P0.3331D I/O or
A In
P0.4230D I/O or
A In
P0.5129D I/O or
A In
P0.64828D I/O or
A In
P0.74727D I/O or
A In
Port 0.0. See Section 15 for a complete description of Port
0.
Port 0.1.
Port 0.2.
Port 0.3.
Port 0.4.
Port 0.5.
Port 0.6.
Port 0.7.
Rev. 0.533
C8051F340/1/2/3/4/5/6/7
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued)
Name
P1.04626D I/O or
P1.14525D I/O or
P1.24424D I/O or
P1.34323D I/O or
P1.44222D I/O or
P1.54121D I/O or
P1.64020D I/O or
P1.73919D I/O or
P2.03818D I/O or
P2.13717D I/O or
Pin Numbers
TypeDescription
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 1.0. See Section 15 for a complete description of Port
1.
Port 1.1.
Port 1.2.
Port 1.3.
Port 1.4.
Port 1.5.
Port 1.6.
Port 1.7.
Port 2.0. See Section 15 for a complete description of Port
2.
Port 2.1.
P2.23616D I/O or
A In
P2.33515D I/O or
A In
P2.43414D I/O or
A In
P2.53313D I/O or
A In
P2.63212D I/O or
A In
P2.73111D I/O or
A In
P3.030-D I/O or
A In
P3.129-D I/O or
A In
P3.228-D I/O or
A In
Port 2.2.
Port 2.3.
Port 2.4.
Port 2.5.
Port 2.6.
Port 2.7.
Port 3.0. See Section 15 for a complete description of Port
3.
Port 3.1.
Port 3.2.
34Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued)
Name
P3.327-D I/O or
P3.426-D I/O or
P3.525-D I/O or
P3.624-D I/O or
P3.723-D I/O or
P4.022-D I/O or
P4.121-D I/O or
P4.220-D I/O or
P4.319-D I/O or
P4.418-D I/O or
Pin Numbers
TypeDescription
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 3.3.
Port 3.4.
Port 3.5.
Port 3.6.
Port 3.7.
Port 4.0. See Section 15 for a complete description of Port
The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window
detector are all configured und er software control via the Special Function Reg isters shown in
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages
at port pins, the Temperature Sensor output, or V
with respect to a port pin, VREF, or GND. The connec-
DD
tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 5.1.
Port I/O
Pins*
VDD
Temp
Sensor
Port I/O
Pins*
VREF
GND
* 21 Selections on 32-pin package
20 Selections on 48-pin package
AMUX0 selects the positive and negative inputs to the ADC. Th e positive input (AIN+) can be connecte d to
individual Port pins, the on-chip temperature sensor, or the positive power supply (V
input (AIN-) can be connected to individual Port pins, VREF, or GND.
ative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential
The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Mode.
Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left- justified , depending o n the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justi
fied and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When GND is selected as the neg-
). The negative
DD
-
Input Voltage
(Single-Ended)
VREF x 1023/10240x03FF0xFFC0
VREF x 512/10240x02000x8000
VREF x 256/10240x01000x4000
00x00000x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus
tified and left-justified data. For right-justified data, the unused MSBs of ADC0 H ar e a sign-e xtension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Input Voltage
(Differential)
VREF x 511/5120x01FF0x7FC0
VREF x 256/5120x01000x4000
00x00000x0000
–VREF x 256/5120xFF000xC000
–VREF 0xFE000x8000
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See
Output” on page 147 for more Port I/O configuration details.
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
Section “15. Port Input/
-
42Rev. 0.5
5.2.Temperature Sensor
C8051F340/1/2/3/4/5/6/7
The temperature sensor transfer function is shown in Figure 5.2. The outp ut volt age (V
ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the
Offset and Slope parameters can be found in
V
= (Slope x TempC) + Offset
TEMP
Temp
= (V
C
Voltage
Table 5.1.
- Offset) / Slope
TEMP
Slope (V / deg C)
Offset (V at 0 Celsius)
) is the positive
TEMP
Temperature
Figure 5.2. Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset and/
or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
Step 1. Control/m easure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the po sitive input
and GND selected as the negative input.
Step 4. Calculate the o ffset characteristics, and store this value in non-volatile memory for use
with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
Rev. 0.543
C8051F340/1/2/3/4/5/6/7
5.0
0
4.0
0
3.0
0
2.0
0
1.0
0
0.0
0
-40.00-20.00
-1.00
Error (degrees C)
-2.00
-3.00
-4.00
-5.00
0.0
0
20.0
0
Temperature (degrees C)
40.0
0
60.0
0
80.0
0
5.0
0
4.0
0
3.0
0
2.0
0
1.0
0
0.0
0
-1.00
-2.00
-3.00
-4.00
-5.00
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
44Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.3.Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC
5.3.1. Starting a Conversion
A conversion can be initiated in on e of five ways, d epending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Con versions may be initiate d by one of th e fol
lowing:
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed
"on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when th e conver
sion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0
interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag
(AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when
bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low
Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit
mode. See
+ 1) for 0 ≤ AD0SC ≤ 31).
-
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
-
Section “21. Timer s” on page 243 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port pin. When the
CNVSTR input is used as the ADC0 conversion source,
Digital Crossbar. To configure the Crossbar to skip a pin, set th e corresponding bit in the PnSKIP register
to ‘1’. See
Section “15. Port Input/Output” on page 147 for details on Port I/O configuration.
the associated Port pin should be skipped by the
Rev. 0.545
C8051F340/1/2/3/4/5/6/7
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mod e. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR (see
is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling
Time Requirements” on page 47.
CNVSTR
(AD0CM[2:0]=100)
Figure 5.4). Tracking can also be disabled (shut down) when th e device
A. ADC0 Timing for External Trigger Source
-
SAR Clocks
AD0TM=1
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
SAR Clocks
AD0TM=1
SAR Clocks
AD0TM=0
Low Power
or Convert
Track or ConvertConvertTrackAD0TM=0
123456789
TrackConvert
10 11
Low Po wer
B. ADC0 Timing for Internal Trigger Source
Low Po wer
or Convert
Track or
Convert
123456789101112
TrackConvertLow Power Mode
123456789
ConvertTrack
10
13 14
11
Mode
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
46Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu
racy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the mini
mum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by
Sensor output or VDD with respect to GND, R
TOTAL
settling time requirements.
n
2
⎛⎞
t
------ -
×ln=
⎝⎠
SA
R
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
is the sum of the AMUX0 resistance and any external source resistance.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirement s
are given in Table 5.1.
SYSCLK
AD0SC
Bit2:AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
----------------------
CLK
SAR
1–=
0xBC
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6:AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4:AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3:AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match h as not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
0xE8
Rev. 0.551
C8051F340/1/2/3/4/5/6/7
5.4.Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 conversion results to
user-programmed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster sys
tem response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used
in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag ca n be programmed to indicate when mea
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
The Window Detector registers must be written with the same format (left/right justified, signed/unsigned)
as that of the current ADC configuration (left/right justified, single-ended/differential).
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
11111111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC4
-
-
Bits7–0: High byte of ADC0 Greater-Than Data Word.
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: Low byte of ADC0 Greater-Than Data Word.
11111111
0xC3
52Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: High byte of ADC0 Less-Than Data Word.
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
0xC6
0xC5
Bits7–0: Low byte of ADC0 Less-Than Data Word.
Rev. 0.553
C8051F340/1/2/3/4/5/6/7
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if
ple using left-justified data with equivalent ADC0GT and ADC0LT register settings.
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an exam-
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - GND)
0x03FF
VREF x (1023/1024)
0x03FF
VREF x (128/1024)
VREF x (64/1024)
0
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
VREF x (128/1024)
VREF x (64/1024)
0
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
AD0WINT=1
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
54Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.4.2. Window Detector In Differential Mode
Figure 5.8 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the
measurable voltage between the input pins is between -VREF a nd VREF*(511/512). Output codes are rep
resented as 10-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL
and ADC0LTH:ADC0LTL (if
0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an
AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the
ADC0GT and ADC0LT registers (if
ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)).
Figure 5.9 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
0x01FF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
0x01FF
-
VREF x (64/512)
VREF x (-1/512)
-VREF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
VREF x (64/512)
VREF x (-1/512)
-VREF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
Input Voltage
(Px.x - Px.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
-VREF
0x8000
AD0WINT
not affected
-VREF
0x8000
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
Rev. 0.555
C8051F340/1/2/3/4/5/6/7
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified
ParameterConditionsMinTypMaxUnits
DC Accuracy
Resolution10bits
Integral Nonlinearity±0.5±1LSB
Differential NonlinearityGuaranteed Monotonic±0.5±1LSB
Offset Error0LSB
Full Scale Error-1LSB
Offset Temperature Coefficient10ppm/°C
Dynamic Performance (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion5152.5dB
Total Harmonic Distortion
Spurious-Free Dynamic Range78dB
SAR Conversion Clock3MHz
Conversion Time in SAR Clocks10clocks
Track/Hold Acquisition Time300ns
Throughput Rate200ksps
ADC Input Voltage RangeSingle Ended (AIN+ – GND)
Absolute Pin V oltage with respect
to GND
Input Capacitance5pF
Linearity
Slope
Offset
Power Supply Current (VDD supplied to ADC0)
Power Supply Rejection±0.3mV/V
1
2
1,2
Up to the 5th harmonic
Conversion Rate
Analog Inputs
0
Differential (AIN+ – AIN–)
Single Ended or Differential0
Temperature Sensor
(Temp = 0 °C)
Power Specifications
Operating Mode, 200 ksps400900µA
–VREF
–67dB
VREF
VREF
V
DD
±0.1°C
TBD
±TBD
TBD
±TBD
mV / °C
V
V
V
mV
Notes:
1. Includes ADC offset, gain, and linearity variations.
2. Represents mean ± one standard deviation.
56Rev. 0.5
C8051F340/1/2/3/4/5/6/7
6.Voltage Reference
The Voltage reference MUX on C8051F340/1/2/3/4/5/6/7 devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage VDD (see
Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For
the internal reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source,
REFSL should be set to ‘1’.
The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator.
This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias
generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
tion 6.1 for REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal
Voltage Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically
enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the volt
age reference and bias circuits are given in Table 6.1.
Important Note About the VREF Pin: The VREF pin, when not using the on-chip voltage reference or an
external precision reference, ca n be co n fig ur ed a s a G PIO Port pin. When using an exte r na l vo ltage ref er
ence or the on-chip reference, the VREF pin sh ould be con figured as analog p in and ski pped by the Digital
Crossbar. To configure the VREF pin for analog mode, set the corresponding bit in the PnMDIN register to
‘0’. To configure the Crossbar to skip the VREF pin, set the corresponding bit in register PnSKIP to ‘1’.
Refer to
Section “15. Port Input/Output” on page 147 for complete Port I/O configuration details.
SFR Defini-
-
-
The temperature sensor connects to the ADC0 po sitive inp ut multiplexer (see Section “5.1. Analog Multi-
plexer” on page 42 for details). The TEMPE bit in register REF0CN enables/disables the temperature
sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data.
REF0CN
BIASE
REFSL
REFBE
TEMPE
AD0EN
To ADC,
Internal Oscillator
To Analog Mux
VREF
(to ADC)
To Clock Multiplier,
Temp Sensor
VDD
GND
R1
External
Voltage
Reference
Circuit
VREF
VDD
0
1
TEMPE
IOSCEN
CLKMUL
Enable
REFBE
EN
EN
EN
ADC Bias
Temp Sensor
Reference
Bias
EN
Internal
Reference
Figure 6.1. Voltage Reference Functional Block Diagram
C8051F340/1/2/3/4/5/6/7 devices include two on-chip programma ble voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two
Comparators operate identically with the following exceptions: (1) Their input selections differ, and (2)
Comparator0 can be used as a reset source. For input selection details, refer to
SFR Definition 7.5.
Each Comparator offers pro grammable resp onse time a nd hysteresis, an an alog input multip lexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see
reset source (see Section “11.5. Comparator0 Reset” on page 104).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (
CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the
Comparator1 negative input.
Section “15.2. Port I/O Initialization” on page 151). Comparator0 may also be used as a
SFR Definition 7.2 and
SFR Definition 7.5). The
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port co nfigur ation reg ister, and configured to be skipped by the
Crossbar (for details on Port configuration, see
Section “15.3. General Purpose Port I/O” on page 154).
Rev. 0.559
C8051F340/1/2/3/4/5/6/7
CPnEN
CPnOUT
CPnRIF
CMXnN2
CMXnN1
CMXnN0
CPTnMX
CMXnP2
CMXnP1
CMXnP0
CPnFIF
CPnHYP1
CPTnCN
CPnHYP0
CPnHYN1
CPnHYN0
VDD
CPn
Rising-edge
CPn
Interrupt
CPn
Falling-edge
CPnRIE
CPnFIE
CPn
CPnA
Port I/O connection options vary with
package (32-pin or 48-pin)
CPn +
CPn -
CPnRIE
CPnFIE
Interrupt
Logic
+
-
GND
SET
SET
Q
D
(SYNCHRONIZER)
Q
D
CLR
CLR
Q
Q
Reset Decision Tree
(Comprator 0 Only)
Crossbar
CPTnMD
CPnMD1
CPnMD0
Figure 7.1. Comparator Functional Block Diagram
Comparator outputs can be polled in software, used as an inte rrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100
page 149 for details on configuring Comparator outputs via the dig ital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1.
nA. See Section “15.1. Priority Crossbar Decoder” on
-
Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition
7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current. See
Table 7.1 for complete timing and supply current specifications.
60Rev. 0.5
C8051F340/1/2/3/4/5/6/7
CP0+
VIN+
CP0-
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
VIN+
OUTPUT
V
OL
Positive Hysteresis
Disabled
Figure 7.2. Comparator Hysteresis Plot
+
CP0
_
V
OH
OUT
Maximum
Posi tive Hysteresis
Negative Hysteresis
Disabled
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis
Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in
SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “ 9.3. Interrupt Handler” on page 87.) The CPnFIF flag is set
to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
68Rev. 0.5
C8051F340/1/2/3/4/5/6/7
8.Voltage Regulator (REG0)
C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output
appears on the V
software using bit REGEN in register REG0CN. See
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powere d
function. REG0 configuration options are shown in
8.1.Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynami c performa nce (respo nse time) is
degraded. See
selection is controlled via the REGMOD bit in register REG0CN.
8.2.VBUS Detection
When the USB Function Controller is used (see section Section “16. Universal Serial Bus Controller
(USB0)” on page 163), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The
VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be
active as long as the VBUS signal matc hes the polarity selected by VBPOL. See
parameters.
pin and can be used to po wer external devices. REG0 can be enabled/disabled by
DD
Table 8.1 for REG0 electrical characteristics.
Figure 8.1–Figure 8.4.
Table 8.1 for normal and low power mode supply current specifications. The REG0 mode
Table 8.1 for VBUS input
Important Note: When USB is selected as a reset source, a system reset will be generated when the
VBUS signal matches the polarity selected by the VBPOL bit. See
page 101 for details on selecting USB as a reset source
Section “11. Reset Sources” on
Table 8.1. Voltage Regulator Electrical Specifications
–40 to +85 °C unless otherwise specified.
ParameterConditionsMinTypMaxUnits
Input Voltage Range
Output Voltage (VDD)
Output Current
VBUS Detection Input Threshold1.01.84.0V
Bias Current
Dropout Voltage (VDO)
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to VDD.
2. Output current is total regulator output, including any current required by the C8051F34x.
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.
1
2
2
3
Output Current = 1 to 100 mA3.03.33.6V
Normal Mode (REGMOD = ‘0’)
Low Power Mode (REGMOD = ‘1’)
IDD = 1 mA
IDD = 100 mA
2.75.25V
100mA
90
60
100
TBD
TBD
1
µA
mV/mA
Rev. 0.569
C8051F340/1/2/3/4/5/6/7
VBUS
From VBUS
To 3 V
Power Net
From VBUS
VBUS Sense
REGIN
VDD
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.1. REG0 Configuration: USB Bus-Powered
VBUS
VBUS Sense
Device
Power Net
From 5 V
Power Net
To 3 V
Power Net
REGIN
VDD
Figure 8.2. REG0 Configuration: USB Self-Powered
70Rev. 0.5
Voltage Regulator (REG0)5 V In
3 V Out
Device
Power Net
C8051F340/1/2/3/4/5/6/7
From VBUS
From 3 V
Power Net
VBUS
REGIN
VDD
VBUS Sense
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
VBUS
Device
Power Net
From 5 V
Power Net
To 3 V
Power Net
VBUS Sense
REGIN
VDD
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.4. REG0 Configuration: No USB Connection
Device
Power Net
Rev. 0.571
C8051F340/1/2/3/4/5/6/7
SFR Definition 8.1. REG0CN: Voltage Regulator Control
1: Voltage Regulator Disabled.
Bit6:VBSTAT: VBUS Signal Status.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
Bit5: VBPOL: VBUS Interrupt Polarity Select.
This bit selects the VBUS interrupt polarity.
0: VBUS interrupt active when VBUS is low.
1: VBUS interrupt active when VBUS is high.
Bit4:REGMOD: Voltage Regulator Mode Select.
This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regu-
lator operates in low power (suspend) mode.
0: USB0 Voltage Regulator in normal mode.
1: USB0 Voltage Regulator in low power mode.
Bits3–0: Reserved. Read = 0000b. Must Write = 0000b.
0xC9
72Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9.CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Sec-
tion 15). The CIP-51 also includes on-chip debug hardware (see descr iption in Sectio n 23), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see
The CIP-51 includes the following features:
Section 21), an enhanced full-duplex UART (see description
Figure 9.1 for a block diagram).
-
- Fully Compatible with MCS-51 Instruction
Set
- 0 to 48 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 25 Port I/O
DATA BUS
RESET
CLOCK
STOP
IDLE
D8
ACCUMULATOR
PSW
D8
BUFFER
DATA POINTER
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
CONTROL
LOGIC
POWER CONTROL
REGISTER
D8
TMP1TMP2
ALU
PIPELINE
DATA BUS
D8
D8
DATA BUS
D8
D8
D8
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
B REGISTER
ADDRESS
REGISTER
D8
INTERFACE
D8
A16
INTERFACE
D8
INTERRUPT
INTERFACE
D8
D8
SRAM
D8
SFR
BUS
MEMORY
D8
STACK POINTER
SRAM
(256 X 8)
D8
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEM_WRITE_DATA
MEM_READ_DATA
SYSTEM_IRQs
EMULATION_IRQ
Figure 9.1. CIP-51 Block Diagram
Rev. 0.573
C8051F340/1/2/3/4/5/6/7
Performance
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12
core executes 70% of its instructions in one or two system clock cycles, with no instruct ions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that for execution time.
Clocks to Execute122/433/5454/668
Number of Instructions2650510752121
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. T his featur e allows progra m memo ry to b e used for non -volatile data stor
age as well as updating program code under software control.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins. C2 details can be found in Section “23. C2 Interface” on page 279.
MHz. By contrast, the CIP-51
-
-
-
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger, and programmer. The
IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient
in-system device programming and debugging. An 8051 assembler, linker and evaluation ‘C’ compiler are
included in the Development Kit. Many third party macro assemblers and C compilers are also available,
which can be used directly with the IDE.
9.1.Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan
dard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken a s opposed to wh en the branch is taken.
Table 9.1 is the
-
74Rev. 0.5
C8051F340/1/2/3/4/5/6/7
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
9.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F340/1/2/3/4/5/6/
7 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to
accesses external RAM (XRAM) and the on-chip program memory space implemented as re-progr amma
ble Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program
code and use the program memory space for non-vo latile dat a storage. Refer to
ory” on page 109 for further details.
Table 9.1. CIP-51 Instruction Set Summary
Section “12. Flash Mem-
-
MnemonicDescriptionBytes
Arithmetic Operations
ADD A, RnAdd register to A11
ADD A, directAdd direct byte to A22
ADD A, @RiAdd indirect RAM to A12
ADD A, #dataAdd immediate to A22
ADDC A, RnAdd register to A with carry11
ADDC A, directAdd direct byte to A with carry22
ADDC A, @RiAdd indirect RAM to A with carry12
ADDC A, #dataAdd immediate to A with carry22
SUBB A, RnSubtract register from A with borrow11
SUBB A, directSubtract direct byte from A with borrow22
SUBB A, @RiSubtract indirect RAM from A with borrow12
SUBB A, #dataSubtract imme dia te fro m A with borr ow22
INC AIncrement A11
INC RnIncrement register11
INC directIncrement direct byte22
INC @RiIncrement indirect RAM12
DEC ADecrement A11
DEC RnDecrement register11
DEC directDecrement dir ec t byt e22
DEC @RiDecrement indirect RAM12
INC DPTRIncrement Data Pointer11
MUL ABMultiply A and B14
DIV ABDivide A by B18
DA ADecimal adjust A11
Logical Operations
ANL A, RnAND Register to A11
ANL A, directAND direct byte to A22
ANL A, @RiAND indirect RAM to A12
ANL A, #dataAND immediate to A22
ANL direct, AAND A to direct byte22
ANL direct, #dataAND immediate to direct byte33
ORL A, RnOR Register to A11
Clock
Cycles
Rev. 0.575
C8051F340/1/2/3/4/5/6/7
Table 9.1. CIP-51 Instruction Set Summary (Continued)
MnemonicDescriptionBytes
ORL A, directOR direct byte to A22
ORL A, @RiOR indirect RAM to A12
ORL A, #dataOR immediate to A22
ORL direct, AOR A to direct byte22
ORL direct, #dataOR immediate to direct byte33
XRL A, RnExclusive-OR Register to A11
XRL A, directExclusive-OR direct byte to A22
XRL A, @RiExclusive-OR indirect RAM to A12
XRL A, #dataExclusive-OR immediate to A22
XRL direct, AExclusive-OR A to direct byte22
XRL direct, #dataExclusive-OR immediate to direct byte33
CLR AClear A11
CPL AComplement A11
RL ARotate A left11
RLC ARotate A left through Carry11
RR ARotate A right11
RRC ARotate A right through Carry11
SWAP ASwap nibbles of A11
Data Transfer
MOV A, RnMove Register to A11
MOV A, directMove direct byte to A22
MOV A, @RiMove indirect RAM to A12
MOV A, #dataMove immediate to A22
MOV Rn, AMove A to Register11
MOV Rn, directMove direct byte to Register22
MOV Rn, #dataMove immediate to Register22
MOV direct, AMove A to direct byte22
MOV direct, RnMove Register to direct byte22
MOV direct, directMove direct byte to direct byte33
MOV direct, @RiMove indirect RAM to direct byte22
MOV direct, #dataMove immediate to direct byte33
MOV @Ri, AMove A to indirect RAM12
MOV @Ri, directMove direct byte to indirect RAM22
MOV @Ri, #dataMove immediate to indirect RAM22
MOV DPTR, #data16Load DPTR with 16-bit constant33
MOVC A, @A+DPTRMove code byte relative DPTR to A13
MOVC A, @A+PCMove code byte relative PC to A13
MOVX A, @RiMove external data (8-bit address) to A13
MOVX @Ri, AMove A to external data (8-bit address)13
MOVX A, @DPTRMove external data (16-bit address) to A13
MOVX @DPTR, AMove A to external data (16-bit address)13
PUSH directPush direct byte onto stack22
POP directPop direct byte from stack22
XCH A, RnExchange Register with A11
XCH A, directExchange direct byte with A22
Clock
Cycles
76Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 9.1. CIP-51 Instruction Set Summary (Continued)
MnemonicDescriptionBytes
XCH A, @RiExchange indirect RAM with A12
XCHD A, @RiExchange low nibble of indirect RAM with A12
Boolean Manipulation
CLR CClear Carry11
CLR bitClear direct bit22
SETB CSet Carry11
SETB bitSet direct bit22
CPL CComplement Carry11
CPL bitComplement direct bit22
ANL C, bitAND direct bit to Carry22
ANL C, /bitAND complement of direct bit to Carry22
ORL C, bitOR direct bit to carry22
ORL C, /bitOR complement of direct bit to Carry22
MOV C, bitMove direct bit to Carry22
MOV bit, CMove Carry to direct bit22
JC relJump if Carry is set22/4
JNC relJump if Carry is not set22/4
JB bit, relJump if direct bit is set33/5
JNB bit, relJump if direct bit is not set33/5
JBC bit, relJump if direct bit is set and clear bit33/5
Program Branching
ACALL addr11Absolute subroutine call24
LCALL addr16Long subroutine call35
RETReturn from subroutine16
RETIReturn from interrupt16
AJMP addr11Absolute jump24
LJMP addr16Long jump35
SJMP relShort jump (relative address)24
JMP @A+DPTRJump indirect relative to DPTR14
JZ relJump if A equals zero22/4
JNZ relJump if A does not equal zero22/4
CJNE A, direct, relCompare direct byte to A and jump if not equal33/5
CJNE A, #data, relCompare immediate to A and jump if not equal33/5
CJNE Rn, #data, relCompare immediate to Register and jump if not equal33/5
CJNE @Ri, #data, relCompare immediate to indirect and jump if not equal34/6
DJNZ Rn, relDecrement Register and jump if not zero22/4
DJNZ direct, relDecrement direct byte and jump if not zero33/5
NOPNo operation11
Clock
Cycles
Rev. 0.577
C8051F340/1/2/3/4/5/6/7
Notes on Registers, Operands and Addressing Modes:
Rn
- Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset r elative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s ad dress. This could be a direct-access Data RAM location
(0x00-0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywher e within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in
Figure 9.2.
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-Chip XRAM
(Available only on devices
with EMIF)
0x07FF
0x0400
0x0000
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memo ry sp ace. The C80 51F340/1/2 /3/4/5/6/7 implement s 64k or
32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the
C8051F340/2/4/6 (64k version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, th e CIP-51 can wr ite to pro gram m emory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro
vides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to
Section “12. Flash Memory” on page 109 for further details.
Rev. 0.579
-
C8051F340/1/2/3/4/5/6/7
9.2.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128
Either direct or indirect addressing may be used to access the lower 128
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16
bytes or as 128
The upper 128 bytes of data memory are accessible only b y indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128
9.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in
fast context switching when entering subroutines and interrupt service routines. Indir ect addressing mod es
use registers R0 and R1 as index registers.
bytes of data memory are used for general purpose registers and scratch pad memory.
bytes of data memory. Locations
bytes, locations 0x20 through 0x2F, may either be addressed as
bit locations accessible with the direct addressing mode.
bytes of data memory space or the SFRs. Instructions that use
bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51.
SFR Definition 9.4). This allows
9.2.4. Bit Addressable Locations
In addition to direct access to data memory or gan ized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128
0x00 to 0x7F. Bit
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOVC, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
0 of the byte at 0x20 has bit addre ss 0x00 while bit 7 of the byte at 0 x20 has bit addr ess
individually addressable bits. Each bit has a bit address from
9.2.5. Stack
A programmer's stack can be located anywhe re in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of registe r bank 1. T hus, if mor e than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The sta ck depth ca n exte nd up
to 256
bytes.
-
80Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set.
mented in the CIP-51 System Controller .
The SFR registers are accessed anyt ime the dire ct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are
bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corres ponding p ages of the dat asheet, as indicated in
for a detailed description of each register.
Table 9.2. Special Function Register (SFR) Memory Map
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller . Reserved bit s
should not be set to logic
case the reset value of the bit will be logic
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys
tem function.
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
l. Future product versions may use these bits to implement new features in which
0, selecting the feature's default state. Detailed descriptions of
SFR Definition 9.1. DPL: Data Pointer Low Byte
00000000
0x82
-
SFR Definition 9.2. DPH: Data Pointer High Byte
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
SFR Definition 9.3. SP: Stack Pointer
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
00000111
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
0x83
0x81
Rev. 0.585
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.4. PSW: Program Status Word
R/WR/WR/WR/WR/WR/WR/WRReset Value
CYACF0RS1RS0OVF1PARITY00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
Bit7:CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6:AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by a ll other arithmetic oper ations.
Bit5:F0: Use r F lag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1:F1: Use r F lag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0:PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd an d cleared if the
sum is even.
SFR Definition 9.5. ACC: Accumulator
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
ACC.7ACC.6ACC.5ACC.4ACC.3ACC.2ACC.1ACC.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
0xE0
86Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.6. B: B Register
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
B.7B.6B.5B.4B.3B.2B.1B.000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
9.3.Interrupt Handler
The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority
levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated inter
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid inter rupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interru pt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not en abled, the interr upt-pending fla g is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic
less of the interrupt's enable/disable state.)
0xF0
1 regard-
-
-
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cle ared by the hardware and must be cle ared by sof twar e before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
1 before the individual interrupt enables are recogn ized. Setting th e EA bit to logic 0 disables
9.3.1. MCU Interrupt Sources and Vectors
The MCU supports multiple interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and
the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources,
associated vector addresses, priority order and control bits are summarized in
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Table 9.4 on page 89. Refer
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (
or edge sensitive. The following table lists the possible configurations.
Section “21.1. Timer 0 and Timer 1” on page 243) select level
/INT0 and /INT1 are assigned to Port pins as de fined in the IT01CF register (see SFR Definition 9.13).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see
“15.1. Priority Crossbar Decoder” on page 149 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre
sponding interrupt-pending flag is automatically clear ed by th e hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
Section
-
-
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are reco gnized simult aneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in
Table 9.4.
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the in te rrupt occur s. Pending inter rupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interru pt. Th eref ore, the ma ximu m res pons e time for an int erru pt (wh en no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20
system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see
Section “13.2. Accessing USB FIFO Sp ac e” on p ag e 118). Interrupt service latency will be increased for
interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as descri bed above) and the amount of time the CPU is stalled.
clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
clock cycles to execute the LCALL to the ISR. If the CPU is
The SFRs used to enable the interrupt sources and set their pr iority le vel ar e descri bed below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrup t
conditions for the peripheral and the behavio r of its interrupt-p end ing flag (s) .
Rev. 0.589
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.7. IE: Interrupt Enable
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
EAESPI0ET2ES0ET1EX1ET0EX000000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
(bit addressable)
Bit7:EA: Enable All Interrupts.
This bit globally enables/disables all interrupt s. It override s the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6:ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Bit5:ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4:ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3:ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the T imer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2:EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Bit1:ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the T imer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0:EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Bit5:PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4:PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3:PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2:PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1:PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
Bit0:PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Bit1:EUSB0: Enable USB0 Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
Bit0:ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit1:PUSB0: USB0 Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7:IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter
rupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states;
the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is depen
dent upon the system clock frequency and the number of peripherals left in active mode before entering
Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON)
used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished through system clock and individual peripheral
management. Each analog peripheral can be disabled when not in use and placed in low power mode.
Digital peripherals, such as timers or serial buses, draw little power when they are not in us e. Turning off
the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
The internal oscillator can be placed in Suspend mode (see Section “14. Oscillators” on page 135). In
Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input
signal matches the polarity selected by the VBPOL bit in register REG0CN (
9.4.1. Idle Mode
SFR Definition 8.1).
-
-
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended per manent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the I dle mode if the WDT was initially configured to allow this operation. This pro
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “11.6. PCA Watchdog
Timer Reset ” on page 104 for more information on the use and configuration of the WDT.
-
9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be pu t to in ST OP mode for long er tha n the
MCD timeout of 100
96Rev. 0.5
µsec.
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.14. PCON: Power Control
R/WR/WR/WR/WR/WR/WR/WR/WReset Value
GF5GF4GF3GF2GF1GF0STOPIDLE00000000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0SFR Address:
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1:STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0:IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
0x87
Rev. 0.597
C8051F340/1/2/3/4/5/6/7
NOTES:
98Rev. 0.5
C8051F340/1/2/3/4/5/6/7
10. Prefetch Engine
The C8051F340/1/2/3/4/5/6/7 family of devices incorporate a 2-byt e prefetch engine. Because the access
time of the FLASH memory is 40
engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at
a time by the prefetch engine, an d given to the CIP-51 processor core to execute. When running linear
code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full
speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next
set of code bytes is retrieved from FLASH me mory. The FLRT bit (FLSCL.4) determines how many clock
cycles are used to read each set of two code bytes from FLASH. When operating from a system clock of
25
MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock cycle for
each read. When operating with a system clock of greater than 25
should be set to ‘1’, so that each prefetch code read lasts for two clock cycles.
SFR Definition 10.1. PFE0CN: Prefetch Engine Control
RRR/WRRRRR/WReset Value
PFENFLBWE00100000
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
ns, and the minimum instruction time is roughly 20 ns, the prefetch
MHz (up to 48 MHz), the FLRT bit
SFR Address: 0xAF
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5:PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0:FLBWE: FLASH Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of two.
Rev. 0.599
C8051F340/1/2/3/4/5/6/7
NOTES:
100Rev. 0.5
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