C8051F340/1/2/3/4/5/6/7
Full Speed USB Flash MCU Family
Analog Peripherals
- 10-Bit ADC
• Up to 200 ksps
• Built-in analog multiplexer with single-ended and
differential mode
• VREF from external pin, internal reference, or V
• Built-in temperature sensor
• External conversion start input option
DD
- Two comparators
- Internal voltage reference
- Brown-out detector and POR Circuitry
USB Function Controller
- USB specification 2.0 compliant
- Full speed (12 Mbps) or low speed (1.5 Mbps) operation
- Integrated clock recovery; no external crystal required for
full speed or low speed
- Supports eight flexible endpoints
- 1 kB USB buffer memory
- Integrated transceiver; no external resistors required
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
- Voltages from 3.6 to 5.25 V supported using On-Chip
Voltage Regulator
HIgh Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
Instructions in 1 or 2
system clocks
- 48 MIPS and 25 MIPS versions available.
- Expanded interrupt handler
Memory
- 4352 or 2304 Bytes RAM
- 64 or 32 kB Flash; In-system programmable in 512-byte
sectors
Digital Peripherals
- 40/25 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced SPI™, SMBus™, and one or two
enhanced UART serial ports
- Four general purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with five cap-
ture/compare modules
- External Memory Interface (EMIF)
Clock Sources
- Internal Oscillator: 0.25% accuracy with clock recovery
enabled. Supports all USB and UART modes
- External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin
modes)
- Low Frequency (80 kHz) Internal Oscillator
- Can switch between clock sources on-the-fly
Packages
- 48-pin TQFP (C8051F340/1/4/5)
- 32-pin LQFP (C8051F342/3/6/7)
Temperature Range: –40 to +85 °C
ANALOG
PERIPHERALS
A
M
U
X
TEMP
SENSOR
10-bit
200 ksps
ADC
PRECISION INTERNAL
OSCILLATORS
+
+
-
-
VREGVREF
DIGITAL I/O
UART0
UART1
SPI
SMBus
PCA
4 Timers
48 Pin Only
USB Controller /
CROSSBAR
Transceiver
Ext. Memory I/F
Port 0
Port 1
Port 2
Port 3
Port 4
HIGH-SPEED CONTROLLER CORE
64/32 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
Rev. 0.5 1/06 Copyright © 2006 by Silicon Laboratories C8051F34x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
8051 CPU
(48/25 MIPS)
DEBUG
CIRCUITRY
4/2 kB RAM
POR
WDT
C8051F340/1/2/3/4/5/6/7
NOTES:
2 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table Of Contents
1. System Overview.................................................................................................... 17
1.1. CIP-51™ Microcontroller Core.......................................................................... 21
1.1.1. Fully 8051 Compatible.............................................................................. 21
1.1.2. Improved Throughput............................................................................... 21
1.1.3. Additional Features .................................................................................. 21
1.2. On-Chip Memory............................................................................................... 23
1.3. Universal Serial Bus Controller......................................................................... 24
1.4. Voltage Regulator............................................................................................. 25
1.5. On-Chip Debug Circuitry................................................................................... 25
1.6. Programmable Digital I/O and Crossbar........................................................... 26
1.7. Serial Ports ....................................................................................................... 27
1.8. Programmable Counter Array........................................................................... 27
1.9. 10-Bit Analog to Digital Converter..................................................................... 28
1.10.Comparators..................................................................................................... 29
2. Absolute Maximum Ratings .................................................................................. 30
3. Global DC Electrical Characteristics.................................................................... 31
4. Pinout and Package Definitions............................................................................ 33
5. 10-Bit ADC (ADC0).................................................................................................. 41
5.1. Analog Multiplexer ............................................................................................ 42
5.2. Temperature Sensor......................................................................................... 43
5.3. Modes of Operation .......................................................................................... 45
5.3.1. Starting a Conversion............................................................................... 45
5.3.2. Tracking Modes . ....................................................................................... 46
5.3.3. Settling Time Requirements..................................................................... 47
5.4. Programmable Window Detector...................................................................... 52
5.4.1. Window Detector In Single-Ended Mode ................................................. 54
5.4.2. Window Detector In Differential Mode...................................................... 55
6. Voltage Reference.................................................................................................. 57
7. Comparators........................................................................................................... 59
8. Voltage Regulator (REG0)...................................................................................... 69
8.1. Regulator Mode Selection................................................................................. 69
8.2. VBUS Detection................................................................................................ 69
9. CIP-51 Microcontroller........................................................................................... 73
9.1. Instruction Set................................................................................................... 74
9.1.1. Instruction and CPU Timing ..................................................................... 74
9.1.2. MOVX Instruction and Program Memory ................................................. 75
9.2. Memory Organization........................................................................................ 79
9.2.1. Program Memory...................................................................................... 79
9.2.2. Data Memory............................................................................................ 80
9.2.3. General Purpose Registers...................................................................... 80
9.2.4. Bit Addressable Locations........................................................................ 80
9.2.5. Stack ....................................................................................................... 80
9.2.6. Special Function Registers....................................................................... 81
9.2.7. Register Descriptions............................................................................... 85
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9.3. Interrupt Handler............................................................................................... 87
9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87
9.3.2. External Interrupts.................................................................................... 87
9.3.3. Interrupt Priorities..................................................................................... 88
9.3.4. Interrupt Latency ...................................................................................... 88
9.3.5. Interrupt Register Descriptions................................................................. 89
9.4. Power Management Modes.............................................................................. 96
9.4.1. Idle Mode.................................................................................................. 96
9.4.2. Stop Mode................................................................................................ 96
10.Prefetch Engine ...................................................................................................... 99
11.Reset Sources....................................................................................................... 101
11.1.Power-On Reset............................................................................................. 102
11.2.Power-Fail Reset / VDD Monitor .................................................................... 103
11.3.External Reset................................................................................................ 104
11.4.Missing Clock Detector Reset ........................................................................ 104
11.5.Comparator0 Reset........................................................................................ 104
11.6.PCA Watchdog Timer Reset .......................................................................... 104
11.7.Flash Error Reset ........................................................................................... 104
11.8.Software Reset............................................................................................... 105
11.9.USB Reset . ..................................................................................................... 105
12.Flash Memory ....................................................................................................... 109
12.1.Programming The Flash Memory................................................................... 109
12.1.1.Flash Lock and Key Functions............................................................... 109
12.1.2.Flash Erase Procedure .......................................................................... 109
12.1.3.Flash Write Procedure ........................................................................... 110
12.2.Non-volatile Data Storage .............................................................................. 111
12.3.Security Options............................................................................................. 111
13.External Data Memory Interface and On-Chip XRAM........................................ 117
13.1.Accessing XRAM............................................................................................ 117
13.1.1.16-Bit MOVX Example........................................................................... 117
13.1.2.8-Bit MOVX Example............................................................................. 117
13.2.Accessing USB FIFO Space .......................................................................... 118
13.3.Configuring the External Memory Interface.................................................... 119
13.4.Port Configuration........................................................................................... 119
13.5.Multiplexed and Non-multiplexed Selection.................................................... 122
13.5.1.Multiplexed Configuration....................................................................... 122
13.5.2.Non-multiplexed Configuration............................................................... 123
13.6.Memory Mode Selection................................................................................. 123
13.6.1.Internal XRAM Only ............................................................................... 124
13.6.2.Split Mode without Bank Select.............................................................. 124
13.6.3.Split Mode with Bank Select................................................................... 125
13.6.4.External Only.......................................................................................... 125
13.7.Timing .......................................................................................................... 125
13.7.1.Non-multiplexed Mode........................................................................... 127
13.7.2.Multiplexed Mode................................................................................... 130
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14.Oscillators............................................................................................................. 135
14.1.Programmable Internal High-Frequency (H-F) Oscillator............................... 136
14.1.1.Internal H-F Oscillator Suspend Mode................................................... 136
14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 137
14.2.1.Calibrating the Internal L-F Oscillator..................................................... 137
14.3.External Oscillator Drive Circuit...................................................................... 139
14.3.1.Clocking Timers Directly Through the External Oscillator...................... 139
14.3.2.External Crystal Example....................................................................... 139
14.3.3.External RC Example............................................................................. 140
14.3.4.External Capacitor Example................................................................... 140
14.4.4x Clock Multiplier .......................................................................................... 142
14.5.System and USB Clock Selection .................................................................. 143
14.5.1.System Clock Selection ......................................................................... 143
14.5.2.USB Clock Selection.............................................................................. 143
15.Port Input/Output.................................................................................................. 147
15.1.Priority Crossbar Decoder.............................................................................. 149
15.2.Port I/O Initialization ....................................................................................... 151
15.3.General Purpose Port I/O............................................................................... 154
16.Universal Serial Bus Controller (USB0).............................................................. 163
16.1.Endpoint Addressing ...................................................................................... 164
16.2.USB Transceiver ............................................................................................ 164
16.3.USB Register Access..................................................................................... 166
16.4.USB Clock Configuration................................................................................ 170
16.5.FIFO Management ......................................................................................... 171
16.5.1.FIFO Split Mode..................................................................................... 171
16.5.2.FIFO Double Buffering........................................................................... 172
16.5.3.FIFO Access .......................................................................................... 172
16.6.Function Addressing....................................................................................... 173
16.7.Function Configuration and Control................................................................ 173
16.8.Interrupts ........................................................................................................ 176
16.9.The Serial Interface Engine............................................................................ 180
16.10.Endpoint0 ..................................................................................................... 180
16.10.1.Endpoint0 SETUP Transactions .......................................................... 181
16.10.2.Endpoint0 IN Transactions................................................................... 181
16.10.3.Endpoint0 OUT Transactions............................................................... 182
16.11.Configuring Endpoints1-3............................................................................. 184
16.12.Controlling Endpoints1-3 IN.......................................................................... 184
16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 184
16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 185
16.13.Controlling Endpoints1-3 OUT...................................................................... 187
16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 187
16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 188
17.SMBus ................................................................................................................... 193
17.1.Supporting Documents................................................................................... 194
17.2.SMBus Configuration...................................................................................... 194
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17.3.SMBus Operation........................................................................................... 194
17.3.1.Arbitration............................................................................................... 195
17.3.2.Clock Low Extension.............................................................................. 196
17.3.3.SCL Low Timeout................................................................................... 196
17.3.4.SCL High (SMBus Free) Timeout .......................................................... 196
17.4.Using the SMBus............................................................................................ 196
17.4.1.SMBus Configuration Register............................................................... 198
17.4.2.SMB0CN Control Register..................................................................... 201
17.4.3.Data Register......................................................................................... 204
17.5.SMBus Transfer Modes.................................................................................. 204
17.5.1.Master Transmitter Mode....................................................................... 204
17.5.2.Master Receiver Mode........................................................................... 206
17.5.3.Slave Receiver Mode............................................................................. 207
17.5.4.Slave Transmitter Mode......................................................................... 208
17.6.SMBus Status Decoding................................................................................. 208
18.UART0.................................................................................................................... 211
18.1.Enhanced Baud Rate Generation................................................................... 212
18.2.Operational Modes......................................................................................... 212
18.2.1.8-Bit UART............................................................................................. 213
18.2.2.9-Bit UART............................................................................................. 214
18.3.Multiprocessor Communications .................................................................... 214
19.UART1 (C8051F340/1/4/5 Only) ........................................................................... 219
19.1.Baud Rate Generator ..................................................................................... 220
19.2.Data Format.................................................................................................... 221
19.3.Configuration and Operation .......................................................................... 222
19.3.1.Data Transmission................................................................................. 222
19.3.2.Data Reception ...................................................................................... 222
19.3.3.Multiprocessor Communications............................................................ 223
20.Enhanced Serial Peripheral Interface (SPI0)...................................................... 229
20.1.Signal Descriptions......................................................................................... 230
20.1.1.Master Out, Slave In (MOSI).................................................................. 230
20.1.2.Master In, Slave Out (MISO).................................................................. 230
20.1.3.Serial Clock (SCK)................................................................................. 230
20.1.4.Slave Select (NSS) ................................................................................ 230
20.2.SPI0 Master Mode Operation......................................................................... 231
20.3.SPI0 Slave Mode Operation........................................................................... 233
20.4.SPI0 Interrupt Sources................................................................................... 233
20.5.Serial Clock Timing......................................................................................... 234
20.6.SPI Special Function Registers...................................................................... 236
21.Timers.................................................................................................................... 243
21.1.Timer 0 and Timer 1....................................................................................... 243
21.1.1.Mode 0: 13-bit Counter/Timer................................................................ 243
21.1.2.Mode 1: 16-bit Counter/Timer................................................................ 244
21.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 245
21.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 246
6 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
21.2.Timer 2 .......................................................................................................... 251
21.2.1.16-bit Timer with Auto-Reload................................................................ 251
21.2.2.8-bit Timers with Auto-Reload................................................................ 252
21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge...... 253
21.3.Timer 3 .......................................................................................................... 257
21.3.1.16-bit Timer with Auto-Reload................................................................ 257
21.3.2.8-bit Timers with Auto-Reload................................................................ 258
21.3.3.USB Start-of-Frame Capture.................................................................. 259
22.Programmable Counter Array (PCA0)................................................................ 263
22.1.PCA Counter/Timer........................................................................................ 264
22.2.Capture/Compare Modules ............................................................................ 265
22.2.1.Edge-triggered Capture Mode................................................................ 266
22.2.2.Software Timer (Compare) Mode........................................................... 267
22.2.3.High Speed Output Mode....................................................................... 268
22.2.4.Frequency Output Mode ........................................................................ 269
22.2.5.8-Bit Pulse Width Modulator Mode......................................................... 270
22.2.6.16-Bit Pulse Width Modulator Mode....................................................... 271
22.3.Watchdog Timer Mode................................................................................... 272
22.3.1.Watchdog Timer Operation.................................................................... 272
22.3.2.Watchdog Timer Usage ......................................................................... 273
22.4.Register Descriptions for PCA........................................................................ 274
23.C2 Interface........................................................................................................... 279
23.1.C2 Interface Registers.................................................................................... 279
23.2.C2 Pin Sharing ............................................................................................... 281
Contact Information.................................................................................................. 282
Rev. 0.5 7
C8051F340/1/2/3/4/5/6/7
NOTES:
8 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
List of Figures and Tables
1. System Overview
Table 1.1. Product Selection Guide........................................................................ 18
Figure 1.1. C8051F340/1/4/5 Block Diagram........................................................... 19
Figure 1.2. C8051F342/3/6/7 Block Diagram........................................................... 20
Figure 1.3. On-Chip Clock and Reset ...................................................................... 22
Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6) ................ 23
Figure 1.5. USB Controller Block Diagram............................................................... 24
Figure 1.6. Digital Crossbar Diagram....................................................................... 26
Figure 1.7. PCA Block Diagram ............................................................................... 27
Figure 1.8. PCA Block Diagram ............................................................................... 27
Figure 1.9. 10-Bit ADC Block Diagram..................................................................... 28
Figure 1.10. Comparator0 Block Diagram................................................................ 29
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings................................................................... 30
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics...................................................... 31
Table 3.2. Index to Electrical Characteristics Tables.............................................. 32
4. Pinout and Package Definitions
Table 4.1. Pin Definitions fo r the C8051F340/1/2/3/4/5/6/7.................................... 33
Figure 4.1. TQFP-48 Pinout Diagram (Top View) .................................................... 36
Table 4.2. TQFP-48 Package Dimensions.............................................................. 37
Figure 4.2. TQFP-48 Package Diagram................................................................... 37
Figure 4.3. LQFP-32 Pinout Diagram (Top View) .................................................... 38
Table 4.3. LQFP-32 Package Dimensions.............................................................. 39
Figure 4.4. LQFP-32 Package Diagram................................................................... 39
5. 10-Bit ADC (ADC0)
Figure 5.1. ADC0 Functional Block Diagram............................................................ 41
Figure 5.2. Temperature Sensor Transfer Function................................................. 43
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V).... 44
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing .............................. 46
Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 47
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data... 54
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 54
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data ....... 55
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data.......... 55
Table 5.1. ADC0 Electrical Characteristics............................................................. 56
6. Voltage Reference
Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 57
Table 6.1. Voltage Reference Electrical Characteristics......................................... 58
7. Comparators
Figure 7.1. Comparator Functional Block Diagram .................................................. 60
Figure 7.2. Comparator Hysteresis Plot ................................................................... 61
Table 7.1. Comparator Electrical Characteristics.................................................... 68
Rev. 0.5 9
C8051F340/1/2/3/4/5/6/7
8. Voltage Regulator (REG0)
Table 8.1. Voltage Regulator Electrical Specifications............................................ 69
Figure 8.1. REG0 Configuration: USB Bus-Powered............................................... 70
Figure 8.2. REG0 Configuration: USB Self-Powered............................................... 70
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 71
Figure 8.4. REG0 Configuration: No USB Connection............................................. 71
9. CIP-51 Microcontroller
Figure 9.1. CIP-51 Block Diagram............................................................................ 73
Table 9.1. CIP-51 Instruction Set Summary............................................................ 75
Figure 9.2. Memory Map .......................................................................................... 79
Table 9.2. Special Function Register (SFR) Memory Map...................................... 81
Table 9.3. Special Function Registers .................................................................... 82
Table 9.4. Interrupt Summary ................................................................................. 89
10.Prefetch Engine
11.Reset Sources
Figure 11.1. Reset Sources.................................................................................... 101
Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 102
Table 11.1. Reset Electrical Characteristics........................................................... 107
12.Flash Memory
Table 12.1. Flash Electrical Characteristics ........................................................... 111
Figure 12.1. Flash Program Memory Map and Security Byte................................. 112
13.External Data Memory Interface and On-Chip XRAM
Figure 13.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’.. 118
Figure 13.2. Multiplexed Configuration Example.................................................... 122
Figure 13.3. Non-multiplexed Configuration Example............................................ 123
Figure 13.4. EMIF Operating Modes...................................................................... 123
Figure 13.5. Non-multiplexed 16-bit MOVX Timing................................................ 127
Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing ................. 128
Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing ...................... 129
Figure 13.8. Multiplexed 16-bit MOVX Timing........................................................ 130
Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing......................... 131
Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing............................ 132
Table 13.1. AC Parameters for External Memory Interface.................................... 133
14.Oscillators
Figure 14.1. Oscillator Diagram.............................................................................. 135
Table 14.1. Oscillator Electrical Characteristics..................................................... 145
15.Port Input/Output
Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)................ 147
Figure 15.2. Port I/O Cell Block Diagram ............................................................... 148
Figure 15.3. Crossbar Priority Decoder with No Pins Skipped............................... 149
Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 150
Table 15.1. Port I/O DC Electrical Characteristics.................................................. 162
16.Universal Serial Bus Controller (USB0)
Figure 16.1. USB0 Block Diagram.......................................................................... 163
Table 16.1. Endpoint Addressing Scheme............................................................. 164
10 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Figure 16.2. USB0 Register Access Scheme......................................................... 166
Table 16.2. USB0 Controller Registers .................................................................. 169
Figure 16.3. USB FIFO Allocation.......................................................................... 171
Table 16.3. FIFO Configurations............................................................................ 172
Table 16.4. USB Transceiver Electrical Characteristics......................................... 191
17.SMBus
Figure 17.1. SMBus Block Diagram ....................................................................... 193
Figure 17.2. Typical SMBus Configuration............................................................. 194
Figure 17.3. SMBus Transaction............................................................................ 195
Table 17.1. SMBus Clock Source Selection........................................................... 198
Figure 17.4. Typical SMBus SCL Generation......................................................... 199
Table 17.2. Minimum SDA Setup and Hold Times................................................. 199
Table 17.3. Sources for Hardware Changes to SMB0CN...................................... 203
Figure 17.5. Typical Master Transmitter Sequence................................................ 205
Figure 17.6. Typical Master Receiver Sequence.................................................... 206
Figure 17.7. Typical Slave Receiver Sequence...................................................... 207
Figure 17.8. Typical Slave Transmitter Sequence.................................................. 208
Table 17.4. SMBus Status Decoding...................................................................... 209
18.UART0
Figure 18.1. UART0 Block Diagram....................................................................... 211
Figure 18.2. UART0 Baud Rate Logic.................................................................... 212
Figure 18.3. UART Interconnect Diagram.............................................................. 213
Figure 18.4. 8-Bit UART Timing Diagram............................................................... 213
Figure 18.5. 9-Bit UART Timing Diagram............................................................... 214
Figure 18.6. UART Multi-Processor Mode Interconnect Diagram.......................... 215
Table 18.1. Timer Settings for Standard Baud Rates
Using The Internal Oscillator ............................................................... 218
19.UART1 (C8051F340/1/4/5 Only)
Figure 19.1. UART1 Block Diagram....................................................................... 219
Table 19.1. Baud Rate Generator Settings for Standard Baud Rates.................... 220
Figure 19.2. UART1 Timing Without Parity or Extra Bit.......................................... 221
Figure 19.3. UART1 Timing With Parity ................................................................. 221
Figure 19.4. UART1 Timing With Extra Bit............................................................. 221
Figure 19.5. Typical UART Interconnect Diagram.................................................. 222
Figure 19.6. UART Multi-Processor Mode Interconnect Diagram.......................... 223
20.Enhanced Serial Peripheral Interface (SPI0)
Figure 20.1. SPI Block Diagram............................................................................. 229
Figure 20.2. Multiple-Master Mode Connection Diagram....................................... 232
Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram............. 232
Figure 20.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram... 232
Figure 20.5. Master Mode Data/Clock Timing........................................................ 234
Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0).................................... 235
Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1).................................... 235
Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 239
Figure 20.9. SPI Master Timing (CKPHA = 1)........................................................ 239
Rev. 0.5 11
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Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 240
Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 240
Table 20.1. SPI Slave Timing Parameters ............................................................. 241
21.Timers
Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 244
Figure 21.2. T0 Mode 2 Block Diagram.................................................................. 245
Figure 21.3. T0 Mode 3 Block Diagram.................................................................. 246
Figure 21.4. Timer 2 16-Bit Mode Block Diagram .................................................. 251
Figure 21.5. Timer 2 8-Bit Mode Block Diagram .................................................... 252
Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’).............................................. 253
Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’).............................................. 254
Figure 21.8. Timer 3 16-Bit Mode Block Diagram .................................................. 257
Figure 21.9. Timer 3 8-Bit Mode Block Diagram .................................................... 258
Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)............................................ 259
Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)............................................ 260
22.Programmable Counter Array (PCA0)
Figure 22.1. PCA Block Diagram............................................................................ 263
Table 22.1. PCA Timebase Input Options.............................................................. 264
Figure 22.2. PCA Counter/Timer Block Diagram.................................................... 264
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules..... 265
Figure 22.3. PCA Interrupt Block Diagram............................................................. 265
Figure 22.4. PCA Capture Mode Diagram.............................................................. 266
Figure 22.5. PCA Software Timer Mode Diagram.................................................. 267
Figure 22.6. PCA High Speed Output Mode Diagram............................................ 268
Figure 22.7. PCA Frequency Output Mode............................................................ 269
Figure 22.8. PCA 8-Bit PWM Mode Diagram......................................................... 270
Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 271
Figure 22.10. PCA Module 4 with Watchdog Timer Enabled................................. 272
Table 22.3. Watchdog Timer Timeout Intervals1.................................................... 273
23.C2 Interface
Figure 23.1. Typical C2 Pin Sharing....................................................................... 281
12 Rev. 0.5
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List of Registers
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.6. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte . . . . . . . . . . . . . 52
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte . . . . . . . . . . . . . . 52
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte . . . . . . . . . . . . . . . . 53
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte . . . . . . . . . . . . . . . 53
SFR Definition 6.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SFR Definition 7.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 63
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 64
SFR Definition 7.4. CPT1CN: Comparator1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection . . . . . . . . . . . . . . . . . . . . 66
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection . . . . . . . . . . . . . . . . . . . . 67
SFR Definition 8.1. REG0CN: Voltage Regulator Control . . . . . . . . . . . . . . . . . . . . . . 72
SFR Definition 9.1. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.2. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.3. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SFR Definition 9.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SFR Definition 9.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SFR Definition 9.7. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SFR Definition 9.8. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 92
SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 9.11. EIE2: Extended Interrupt Enable 2 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2 . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 9.13. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 9.14. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 10.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . . 99
SFR Definition 11.1. VDM0CN: VDD Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 103
SFR Definition 11.2. RSTSRC: Reset Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SFR Definition 12.1. PSCTL: Program Store R/W Control . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 12.2. FLKEY: Flash Lock and Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SFR Definition 12.3. FLSCL: Flash Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SFR Definition 13.1. EMI0CN: External Memory Interface Control . . . . . . . . . . . . . . 120
SFR Definition 13.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 121
SFR Definition 13.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 126
SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 136
SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 137
Rev. 0.5 13
C8051F340/1/2/3/4/5/6/7
SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138
SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 141
SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 142
SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 . . . . . . . . . . . . . . . . . . . . . 152
SFR Definition 15.2. XBR1: Port I/O Crossbar Register 1 . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 . . . . . . . . . . . . . . . . . . . . . 153
SFR Definition 15.4. P0: Port0 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.5. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SFR Definition 15.6. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.7. P0SKIP: Port0 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SFR Definition 15.8. P1: Port1 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.9. P1MDIN: Port1 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.10. P1MDOUT: Port1 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 156
SFR Definition 15.11. P1SKIP: Port1 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.12. P2: Port2 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.13. P2MDIN: Port2 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SFR Definition 15.14. P2MDOUT: Port2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 15.15. P2SKIP: Port2 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SFR Definition 15.16. P3: Port3 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.17. P3MDIN: Port3 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.18. P3MDOUT: Port3 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 159
SFR Definition 15.19. P3SKIP: Port3 Skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 15.20. P4: Port4 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SFR Definition 15.21. P4MDIN: Port4 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 15.22. P4MDOUT: Port4 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . 161
SFR Definition 16.1. USB0XCN: USB0 Transceiver Control . . . . . . . . . . . . . . . . . . . 165
SFR Definition 16.2. USB0ADR: USB0 Indirect Address . . . . . . . . . . . . . . . . . . . . . . 167
SFR Definition 16.3. USB0DAT: USB0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
USB Register Definition 16.4. INDEX: USB0 Endpoint Index . . . . . . . . . . . . . . . . . . . 169
USB Register Definition 16.5. CLKREC: Clock Recovery Control . . . . . . . . . . . . . . . 170
USB Register Definition 16.6. FIFOn: USB0 Endpoint FIFO Access . . . . . . . . . . . . . 172
USB Register Definition 16.7. FADDR: USB0 Function Address . . . . . . . . . . . . . . . . 173
USB Register Definition 16.8. POWER: USB0 Power . . . . . . . . . . . . . . . . . . . . . . . . 175
USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low . . . . . . . . . . . . . 176
USB Register Definition 16.10. FRAMEH: USB0 Frame Number High . . . . . . . . . . . 176
USB Register Definition 16.11. IN1INT: USB0 IN Endpoint Interrupt . . . . . . . . . . . . . 177
USB Register Definition 16.12. OUT1INT: USB0 Out Endpoint Interrupt . . . . . . . . . . 177
USB Register Definition 16.13. CMINT: USB0 Common Interrupt . . . . . . . . . . . . . . . 178
USB Register Definition 16.14. IN1IE: USB0 IN Endpoint Interrupt Enable . . . . . . . . 179
USB Register Definition 16.15. OUT1IE: USB0 Out Endpoint Interrupt Enable . . . . . 179
USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable . . . . . . . . . . 180
USB Register Definition 16.17. E0CSR: USB0 Endpoint0 Control . . . . . . . . . . . . . . . 183
USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count . . . . . . . . . . . 184
USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte . . . . 186
14 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187
USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189
USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190
USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 190
USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 190
SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . . . . . . . . . . . . . . . . . 200
SFR Definition 17.2. SMB0CN: SMBus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
SFR Definition 17.3. SMB0DAT: SMBus Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
SFR Definition 18.1. SCON0: Serial Port 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SFR Definition 18.2. SBUF0: Serial (UART0) Port Data Buffer . . . . . . . . . . . . . . . . . 217
SFR Definition 19.1. SCON1: UART1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SFR Definition 19.2. SMOD1: UART1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
SFR Definition 19.3. SBUF1: UART1 Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
SFR Definition 19.4. SBCON1: UART1 Baud Rate Generator Control . . . . . . . . . . . 226
SFR Definition 19.5. SBRLH1: UART1 Baud Rate Generator High Byte . . . . . . . . . . 227
SFR Definition 19.6. SBRLL1: UART1 Baud Rate Generator Low Byte . . . . . . . . . . . 227
SFR Definition 20.1. SPI0CFG: SPI0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SFR Definition 20.2. SPI0CN: SPI0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 20.4. SPI0DAT: SPI0 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
SFR Definition 21.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
SFR Definition 21.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SFR Definition 21.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
SFR Definition 21.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
SFR Definition 21.8. TMR2CN: Timer 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
SFR Definition 21.9. TMR2RLL: Timer 2 Reload Register Low Byte . . . . . . . . . . . . . 256
SFR Definition 21.10. TMR2RLH: Timer 2 Reload Register High Byte . . . . . . . . . . . 256
SFR Definition 21.11. TMR2L: Timer 2 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 21.12. TMR2H Timer 2 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
SFR Definition 21.13. TMR3CN: Timer 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
SFR Definition 21.14. TMR3RLL: Timer 3 Reload Register Low Byte . . . . . . . . . . . . 262
SFR Definition 21.15. TMR3RLH: Timer 3 Reload Register High Byte . . . . . . . . . . . 262
SFR Definition 21.16. TMR3L: Timer 3 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SFR Definition 21.17. TMR3H Timer 3 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
SFR Definition 22.1. PCA0CN: PCA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
SFR Definition 22.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 276
SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 277
SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 277
SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 277
SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 278
C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Rev. 0.5 15
C8051F340/1/2/3/4/5/6/7
C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279
C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 280
C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 280
C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 280
16 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1. System Overview
C8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed- signal System-on-a-Chip MCUs. Highlighted
features are listed below. Refer to
• High-speed pipelined 8051-compa tible microcontroller core (up to 48 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1 kB FIFO RAM
• Supply Voltage Regulator
• True 10-bit 200 ksps differential / single-ended ADC with analog multiplexer
• On-chip Voltage Reference and Temperature Sensor
• On-chip Voltage Comparators (2)
• Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier
• Internal low-frequency oscillator for additional power savings
• Up to 64 kB of on-chip Flash memory
• Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
• External Memory Interface (EMIF) available on 48-pin versions.
• SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
• On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
• Up to 40 Port I/O (5 V tolerant)
Table 1.1 for specific product feature selection.
With on-chip Power-On Reset, VDD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator,
C8051F340/1/2/3/4/5/6/7 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory
can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of
the 8051 firmware. User software has complete control of all peripherals, and may individually shut down
any or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C).
For voltages above 3.6
USB communication. The Port I/O and /RST pins are tolerant of input signals up to 5
4/5/6/7 are available in a 48-pin TQFP or a 32-pin LQFP package.
V, the on-chip Vo ltage Regulator must be used. A minimum of 3.0 V is required for
V. C8051F340/1/2/3/
-
Rev. 0.5 17
C8051F340/1/2/3/4/5/6/7
Table 1.1. Product Selection Guide
Ordering Part Number
C8051F340-GQ 48 64k 4352 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F341-GQ 48 32k 2304 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F342-GQ 48 64k 4352 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F343-GQ 48 32k 2304 3 3 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F344-GQ 25 64k 4352 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F345-GQ 25 32k 2304 3 3 3 3 3 3 2 4 3 40 3 3 3 3 2 TQFP48
C8051F346-GQ 25 64k 4352 3 - 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
C8051F347-GQ 25 32k 2304 3 - 3 3 3 3 1 4 3 25 - 3 3 3 2 LQFP32
MIPS (Peak)
Flash Memory (Bytes)
RAM
Calibrated Internal Oscillator
Low Frequency Oscillator
USB with 1k Endpoint RAM
Supply Voltage Regulator
SMBus/I2C
Enhanced SPI
UARTs
Timers (16-bit)
Programmable Counter Array
Digital Port I/Os
External Memory Interface (EMIF)
10-bit 200ksps ADC
Temperature Sensor
Voltage Reference
Analog Comparators
Package
18 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
C2D
C2CK/RST
VDD
VREG
GND
VBUS
Debug / Programming
Hardware
Reset
CIP-51 8051
Power-On
Reset
Supply
Monitor
Voltage
Regulator
Power
Net
Controller Core
64/32k Byte ISP FLASH
Program Memory
256 Byte RAM
4/2k Byte XRAM
SFR
Bus
XTAL1
XTAL2
System Clock Setup
External
Oscillator
Internal
Oscillator
Clock
Recovery
Clock
Multiplier
Low Freq.
Oscillator
USB Peripheral
D+
D-
Full / Low
Speed
Transceiver
Controller
1k Byte
RAM
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0, 1,
2, 3
Crossbar
PCA/WDT
Decoder
SMBus
SPI
Crossbar Control
External Memory
Interface
Control
Address
Data
Analog Peripherals
VREF
VREFVDD
2 Comparators
10-bit
200ksps
ADC
A
M
U
X
Priority
CP0
CP1
VDD
Temp
Sensor
P2 / P3
+
-
+
-
P1
P4
AIN0 - AIN19
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6/XTAL1
P0.7/XTAL2
P1.0
P1.1
P1.2
P1.3
P1.4/CNVSTR
P1.5/VREF
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Figure 1.1. C8051F340/1/4/5 Block Diagram
Rev. 0.5 19
C8051F340/1/2/3/4/5/6/7
C2CK/RST
VDD
VREG
GND
VBUS
C2D
Debug / Programming
Hardware
Reset
CIP-51 8051
Power-On
Reset
Supply
Monitor
Voltage
Regulator
Power
Net
Controller Core
64/32 kB ISP FLASH
Program Memory
256 Byte RAM
4/2 kB XRAM
System Clock Setup
XTAL1
XTAL2
External
Oscillator
Internal
Oscillator
Clock
Recovery
Clock
Multiplier
Low Freq.
Oscillator*
USB Peripheral
D+
D-
Full / Low
Speed
Transceiver
*Low Frequency Oscillator option not available on C8051F346/7
Controller
1 kB RAM
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0, 1,
2, 3
PCA/WDT
Crossbar
Decoder
SMBus
SPI
Crossbar Control
Analog Peripherals
VREF
VREFVDD
2 Comparators
10-bit
200 ksps
ADC
A
M
U
X
Priority
CP0
CP1
VDD
Temp
Sensor
+
-
+
-
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
AIN0 - AIN20
P0.0
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4
P0.5
P0.6/CNVSTR
P0.7/VREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Figure 1.2. C8051F342/3/6/7 Block Diagram
20 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F340/1/2/3/4/5/6/7 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The
CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x asse mblers and c ompil
ers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard
8052, including four 16-bit counter/timers, two full-duplex UARTs with extended baud rate configuration, an
enhanced SPI port, up to 4352
space, and up to 40 I/O pins.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12-to-24
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions listed by
the required execution time.
Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8
Number of Instructions 26 50 5 14 7 3 1 2 1
Bytes of on-chip RAM, 128 byte Special Function Register (SFR) address
MHz. By contrast, the CIP-51 core exe-
-
1.1.3. Additional Features
The C8051F340/1/2/3/4/5/6/7 SoC family includes several key enhancements to the CIP-51 core and
peripherals to improve performance and ease of use in end applications.
The extended interrupt handler provides 16 interrupt sour ces into the CIP-51 (as opp osed to 7 for the st andard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven
system requires less intervention by the MCU, giving it more effective throughput. The extra interrupt
sources are very useful when building multi-tasking, real-time systems.
Nine reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below V
(USB bus reset or a VBUS transition), a Watchdog Timer, a Missing Clock Detector, a voltage level detec-
tion from Comparator0, a forced software reset, an exte rnal reset pin, and an erran t Flash read/wr ite protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by
the user in software. The WDT may be permanently enabled in software after a power-on reset during
MCU initialization.
The high-speed internal oscillator is factory calibrated to 12 MHz ±1.5%. A clock recovery mechanism
allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed
mode; the internal oscillator can also be used as the USB clock source in Low Speed mode. External oscil
lators may also be used with the 4x Clock Multiplier. An internal low-frequency oscillator is also included to
aid applications where power savings are critical. Also included is an external oscillator drive circuit, which
allows an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system
clock. The system clock may be configured to use ether of the internal oscillators, an external oscillator, or
the Clock Multiplier output divided by 2. If desired, the system clock source may be switched on-the-fly
between oscillator sources. The low-frequency internal oscillator or an external oscillator can be useful in
low power applications, allowing the MCU to run from a slow (power saving) external clock source, while
periodically switching to a higher-speed clock source when fast throughput is necessary.
as given in Table 11.1 on page 107), the USB controller
RST
-
Rev. 0.5 21
C8051F340/1/2/3/4/5/6/7
VDD
Comparator 0
System
Clock
Clock Select
+
-
C0RSEF
Missing
Clock
Detector
(one-
shot)
EN
MCD
WDT
Enable
CIP-51
Microcontroller
Core
Extended Interrupt
Handler
PCA
XTAL1
XTAL2
Internal LF
Oscillator
Internal HF
Oscillator
Clock
Multiplier
External
Oscillator
Drive
Px.x
Px.x
EN
WDT
Enable
Supply
Monitor
+
-
System Reset
Enable
Power On
Reset
Software Reset (SWRSF)
Errant
FLASH
Operation
'0'
USB
Controller
(wired-OR)
Enable
Reset
Funnel
VBUS
Transition
/RST
Figure 1.3. On-Chip Clock and Reset
22 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four b anks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addr essable.
Program memory consists of 64 k (C8051F340/2/4/6) or 32 k (C8051F341/3/5/7) bytes of Flash. This
memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip program
ming voltage. On-chip XRAM is also included for the entire device family. The 64 k FLASH devices
(C8051F340/2/4/6) have 4
XRAM space. A separate 1
k of XRAM space. The 32 k Flash devices (C8051F341/3/5/7) have 2 k of
k Bytes of USB FIFO RAM is also included on all devices. See Figure 1.4 for
the MCU system memory map of the 64k Flash devices. Note that on the 64k devices, 1024 bytes at locations 0xFC00 to 0xFFFF are reserved.
-
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-Chip XRAM
(Available only on devices
with EMIF)
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
0x0000
USB FIFOs
1024 Bytes
Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6)
Rev. 0.5 23
0x07FF
0x0400
C8051F340/1/2/3/4/5/6/7
1.3. Universal Serial Bus Controller
The Universal Serial Bus Controller (USB0) is a USB 2.0 compliant Full or Low Speed function with integrated transceiver and endpoint FIFO RAM. A total of eight endpoint pipes are available: a bi-directional
control endpoint (Endpoint0) and three pairs of IN/OUT endpoints (Endpoints1-3 IN/OUT).
A 1k Byte block of RAM is used for USB FIFO space. This FIFO space is distributed among Endpoints0-3;
Endpoint1-3 FIFO slots can be configured as IN, OUT, or both IN and OUT (split mode). The maximum
FIFO size is 512 bytes (Endpoint3).
USB0 can be operated as a Full or Low Speed function. On-chip 4x Clock Multiplier and clock recovery circuitry allow both Full and Low Speed options to be implemented with the on-chip precision oscillator as the
USB clock source. An external oscillator source can also be used with the 4x Clock Multiplier to generate
the USB clock. The CPU clock source is independent of the USB clock.
The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The
pull-up resistors can be enabled/disabled in software, and will appear on the D+ or D- pin according to the
software-selected speed setting (Full or Low Speed).
D+
Transceiver Serial Interface Engine (SIE)
VDD
Data
Transfer
Control
D-
Endpoint0
IN/OUT
Endpoint1
Endpoint2
Endpoint3
IN OUT
IN OUT
IN OUT
USB FIFOs
(1k RAM)
USB
Control,
Status, and
Interrupt
Registers
CIP-51 Core
Figure 1.5. USB Controller Block Diagram
24 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.4. Voltage Regulator
C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output
appears on the V
abled by software.
1.5. On-Chip Debug Circuitry
The C8051F340/1/2/3/4/5/6/7 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging.
All the peripherals (except for the USB, ADC, and
gle stepping, or at a breakpoint in order to keep them synchronized.
The C8051F340DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F340/1/2/3/4/5/6/7 M CUs. The kit includes software with a developer's studio and debugger, 8051 assembler and linker, evaluation ‘C’ compiler, and a
debug adapter. It also has a target application board with the C8051F340 MCU installed, the necessary
cables for connection to a PC, and a wall-mount po wer sup ply. The development kit contents may also be
used to program and debug the device on the production PCB using the appropriate connections fo r the
programming pins.
pin, and can also be used to power other external devices. REG0 can be enabled/dis-
DD
SMBus) are stalled when the MCU is halted, during sin-
The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to
standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to
be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the
precision analog peripherals.
Rev. 0.5 25
C8051F340/1/2/3/4/5/6/7
1.6. Programmable Digital I/O and Crossbar
C8051F340/1/4/5 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7 devices include 25
I/O pins (three byte-wide Ports, and a 1-bit- wide Port ). The C8051F340 /1/2/3/4/5/6/7 Port s behave like typ
ical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital
I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. Th e
“weak pull-ups” that are fixed on typical 8051 devices may be globally disabled, providing power savings
capabilities.
The Digital Crossbar allows mapping of internal digital system resources to Port I/O pins (See Figure 1.6).
On-chip counter/timers, serial buses, HW interrupts, comparator outputs, and other digital signals in the
controller can be configured to appear on the Port I/O pin s specified in the Crossbar Control reg isters. This
allows the user to select the exact mix of general purpose Po rt I/O and digit al resour ces needed for the end
application.
-
Highest
Priority
Lowest
Priority
UART0
SMBus
Outputs
Outputs
SYSCLK
(Internal Digital Signals)
T0, T1
UART1*
P0
P1
P2
(Port Latches)
P3
SPI
CP0
CP1
PCA
2
4
2
2
2
6
2
2
8
(P0.0-P0.7)
8
(P1.0-P1.7)
8
(P2.0-P2.7)
8
(P3.0-P3.7*)
XBR0, XBR1, XBR2,
PnSKIP Registers
Priority
Decoder
Digital
Crossbar
PnMDOUT,
PnMDIN Registers
P0
8
I/O
Cells
P1
8
I/O
Cells
P2
8
I/O
Cells
P3
8
I/O
Cells
*Note: P3.1-P3.7 and UART1 only
available on 48-pin package
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7*
Figure 1.6. Digital Crossbar Diagram
26 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.7. Serial Ports
The C8051F340/1/2/3/4/5/6/7 Family includes an SMBus/I2C interface, full-duplex UARTs, and an
Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
1.8. Programmable Counter Array
An on-chip Programmable Counter/Timer Array (PCA) is included in add ition to the fou r 1 6-bit g enera l pu rpose counter/timers. The PCA consists of a dedicated 16 -bit cou nter /time r time base with five prog ra mmable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided
by 12, the system clock divided by 4, Timer 0 overflows, a dedicated External Clock Input (ECI), the sys
tem clock, or the external oscillator clock source divided by 8. The external clock source selection is useful
for real-time clock functionality, where the PCA may be clocked by an external source while the internal
oscillator drives the system clock.
Each capture/compare module can be configured to operate in one of six modes: Edge-Triggered Capture,
Software Ti mer, High Speed Output, 8- or 16-bit Pulse Wid t h Modu lator, or Frequency Output. Additionally,
Capture/Compare Module 4 offers watchdog timer (WDT) capabilities. Following a system reset, Module 4
is configured and enabled in WDT mode. The PCA Capture/Compare Module I/O and External Clock Input
may be routed to Port I/O via the Digital Crossbar.
-
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
ECI
CEX0
PCA
CLOCK
MUX
Capture/Compare
Module 1
CEX1
16-Bit Counter/Timer
Capture/Compare
Module 2
CEX2
Capture/Compare
Module 3
CEX3
Capture/Compare
Module 4 / WDT
CEX4
Crossbar
Port I/O
Figure 1.8. PCA Block Diagram
Rev. 0.5 27
C8051F340/1/2/3/4/5/6/7
1.9. 10-Bit Analog to Digital Converter
The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-b it SAR ADC with a true d if fe rential inpu t mul tiplexer. With a ma ximum throughput of 200 ksp s, the ADC of fer s true 10-bit linear ity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Twenty (48-pin package) or twenty-one (32-pin package) of the Port I/O pins can be used as analog
inputs to the ADC. Additionally, the on-chip Temperature Sensor output and the power supply voltage
(V
) are available as ADC inputs. User firmware may shut down the ADC to save power.
DD
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC output data can be con figur ed to inter rupt the contr oller whe n ADC
data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in
background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
* 21 Selections on 32-pin package
20 Selections on 48-pin package
Port I/O
Pins*
VDD
Temp
Sensor
Port I/O
Pins*
VREF
GND
Configuration, Control, and Data Registers
Positive
Input
(AIN+)
AMUX
(+)
10-Bit
SAR
(-)
Negative
Input
(AIN-)
AMUX
Figure 1.9. 10-Bit ADC Block Diagram
ADC
End of
Conversion
Interrupt
Start
Conversion
16
Window Compare
000 AD0BUSY (W)
001
010
011
100
101
Logic
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
ADC Data
Registers
Window
Compare
Interrupt
28 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
1.10. Comparators
C8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled and
configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux.
Two comp arator output s may b e routed to a Po rt pin if desired: a latched output and/o r an unlatched (asyn
chronous) output. Comparator response time is programmable, allowing the user to select between
high-speed and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.10 shows the Comparator0 block diagram.
CPnEN
CPnOUT
CMXnN2
CMXnN1
CMXnN0
CPTnMX
CMXnP2
CMXnP1
CMXnP0
CPnRIF
CPnFIF
CPnHYP1
CPTnCN
CPnHYP0
CPnHYN1
CPnHYN0
VDD
CPn
Rising-edge
CPn
Interrupt
CPn
Falling-edge
-
Port I/O connection options vary with
package (32-pin or 48-pin)
Figure 1.10. Comparator0 Block Diagram
CPn +
CPn -
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
Interrupt
Logic
+
-
GND
SET
SET
D
D
Q
Q
CLR
CLR
Q
Q
(SYNCHRONIZER)
Reset Decision Tree
(Comprator 0 Only)
Crossbar
CPnRIE
CPnFIE
CPn
CPnA
Rev. 0.5 29
C8051F340/1/2/3/4/5/6/7
2. Absolute Maximum Ratings
Table 2.1. Absolute Maximum Ratings*
Parameter Conditions Min Typ Max Units
Ambient temperature under bias –55 125 °C
Storage Temperature –65 150 °C
Voltage on any Port I/O Pin or /RST with
respect to GND
Voltage on V
Maximum Total current through V
GND
Maximum output current sunk by /RST or any
Port pin
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
with respect to GND –0.3 4.2 V
DD
and
DD
–0.3 5.8 V
500 mA
100 mA
30 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
–40 to +85 °C, 25 MHz System Clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Digital Supply Voltage
Digital Supply Current with CPU
active
Digital Supply Current with CPU
active and USB active (Full or
Low Speed)
Digital Supply Current with CPU
inactive (not accessing Flash)
Digital Supply Current (suspend
1
= 3.3 V, Clock = 24 MHz
V
DD
V
= 3.3 V, Clock = 1 MHz
DD
= 3.3 V, Clock = 32 kHz
V
DD
V
= 3.3 V, Clock = 24 MHz
DD
V
= 3.3 V, Clock = 6 MHz
DD
= 3.3 V, Clock = 24 MHz
V
DD
= 3.3 V, Clock = 1 MHz
V
DD
V
= 3.3 V, Clock = 32 kHz
DD
Oscillator not running < 0.1 µA
mode or shutdown mode)
Digital Supply RAM Data Reten-
tion Voltage
SYSCLK (System Clock)
2
C8051F340/1/2/3
C8051F344/5/6/7
T
(SYSCLK High Time) C8051F340/1/2/3 @ 50 MHz
SYSH
C8051F344/5/6/7
2.7 3.3 3.6 V
15
0.7
74
TBD
TBD
9
0.5
74
mA
mA
µA
mA
mA
mA
mA
µA
1.5 V
0
0
9
48
25
MHz
ns
18
(SYSCLK Low Time) C8051F340/1/2/3 @ 50 MHz
T
SYSL
C8051F344/5/6/7
Specified Operating Temperature Range
Notes:
1. USB Requires 3.0 V Minimum Supply Voltage.
2. SYSCLK must be at least 32 kHz to enable debugging.
9
ns
18
-40 +85 °C
Other electrical characteristics tables are foun d in the data sheet section corresponding to the associated
peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page
indicated in
Table 3.2.
Rev. 0.5 31
C8051F340/1/2/3/4/5/6/7
Table 3.2. Index to Electrical Characteristics Tables
Table Title
ADC0 Electrical Characteristics 56
Voltage Reference Electrical Characteristics 58
Comparator Electrical Characteristics 68
Voltage Regulator Electrical Specifications 69
Reset Electrical Characteristics 107
Flash Electrical Characteristics 111
AC Parameters for External Memory Interface 133
Oscillator Electrical Characteristics 145
Port I/O DC Electrical Characteristics 162
USB Transceiver Electrical Characteristics 191
Page
No.
32 Rev. 0.5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7
C8051F340/1/2/3/4/5/6/7
Name
V
DD
GND 7 3 Ground.
/RST/
C2CK
C2D 14 - D I/O Bi-directional data signal for the C2 Debug Interface.
P3.0 /
C2D
REGIN 11 7 Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
VBUS 12 8 D In VBUS Sense Input. This pin should be connected to the
Pin Numbers
Type Description
48-pin 32-pin
10 6 Power In
Power
Out
13 9 D I/O
D I/O
- 10 D I/O
D I/O
2.7–3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 15 for a complete description of Port
3.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS signal of a USB network. A 5
cates a USB network connection.
µs. See Section 11.
V signal on this pin indi-
D+ 8 4 D I/O USB D+.
D- 9 5 D I/O USB D–.
P0.0 6 2 D I/O or
A In
P0.1 5 1 D I/O or
A In
P0.2 4 32 D I/O or
A In
P0.3 3 31 D I/O or
A In
P0.4 2 30 D I/O or
A In
P0.5 1 29 D I/O or
A In
P0.6 48 28 D I/O or
A In
P0.7 47 27 D I/O or
A In
Port 0.0. See Section 15 for a complete description of Port
0.
Port 0.1.
Port 0.2.
Port 0.3.
Port 0.4.
Port 0.5.
Port 0.6.
Port 0.7.
Rev. 0.5 33
C8051F340/1/2/3/4/5/6/7
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued)
Name
P1.0 46 26 D I/O or
P1.1 45 25 D I/O or
P1.2 44 24 D I/O or
P1.3 43 23 D I/O or
P1.4 42 22 D I/O or
P1.5 41 21 D I/O or
P1.6 40 20 D I/O or
P1.7 39 19 D I/O or
P2.0 38 18 D I/O or
P2.1 37 17 D I/O or
Pin Numbers
Type Description
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 1.0. See Section 15 for a complete description of Port
1.
Port 1.1.
Port 1.2.
Port 1.3.
Port 1.4.
Port 1.5.
Port 1.6.
Port 1.7.
Port 2.0. See Section 15 for a complete description of Port
2.
Port 2.1.
P2.2 36 16 D I/O or
A In
P2.3 35 15 D I/O or
A In
P2.4 34 14 D I/O or
A In
P2.5 33 13 D I/O or
A In
P2.6 32 12 D I/O or
A In
P2.7 31 11 D I/O or
A In
P3.0 30 - D I/O or
A In
P3.1 29 - D I/O or
A In
P3.2 28 - D I/O or
A In
Port 2.2.
Port 2.3.
Port 2.4.
Port 2.5.
Port 2.6.
Port 2.7.
Port 3.0. See Section 15 for a complete description of Port
3.
Port 3.1.
Port 3.2.
34 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7 (Continued)
Name
P3.3 27 - D I/O or
P3.4 26 - D I/O or
P3.5 25 - D I/O or
P3.6 24 - D I/O or
P3.7 23 - D I/O or
P4.0 22 - D I/O or
P4.1 21 - D I/O or
P4.2 20 - D I/O or
P4.3 19 - D I/O or
P4.4 18 - D I/O or
Pin Numbers
Type Description
48-pin 32-pin
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Port 3.3.
Port 3.4.
Port 3.5.
Port 3.6.
Port 3.7.
Port 4.0. See Section 15 for a complete description of Port
4.
Port 4.1.
Port 4.2.
Port 4.3.
Port 4.4.
P4.5 17 - D I/O or
A In
P4.6 16 - D I/O or
A In
P4.7 15 - D I/O or
A In
Port 4.5.
Port 4.6.
Port 4.7.
Rev. 0.5 35
C8051F340/1/2/3/4/5/6/7
48
P0.6
P0.7
P1.0
47
46
45
P1.2
P1.1
44
P1.3
43
42
P1.5
41
P1.6
40
39
P1.4
38
P2.1
37
P2.0
P1.7
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
GND
D+
D-
VDD
REGIN
VBUS
10
11
12
1
2
3
4
5
6
7
8
9
13
C8051F340/1/4/5
Top View
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
C2D
P4.7
P4.5
P4.6
P4.4
/RST / C2CK
Figure 4.1. TQFP-48 Pinout Diagram (Top View)
36 Rev. 0.5
P4.1
P4.2
P4.3
P4.0
P3.6
P3.7
D
C8051F340/1/2/3/4/5/6/7
48
PIN 1
IDENTIFIER
A2
D1
Table 4.2. TQFP-48
Package Dimensions
MM
MIN TYP MAX
A--1.20
E1
E
1
e
A
A1 0.05 - 0.15
A2 0.95 1.00 1.05
b 0.17 0.22 0.27
D-9.00-
D1 - 7.00 -
e-0.50-
E-9.00-
E1 - 7.00 -
A1
b
Figure 4.2. TQFP-48 Package Diagram
Rev. 0.5 37
C8051F340/1/2/3/4/5/6/7
P0.4
P0.3
P0.2
32
31
30
P0.5
29
P0.6
28
P0.7
27
P1.0
26
P1.1
25
P0.1
P0.0
GND
D-
VDD
REGIN
VBUS
1
2
3
4
5
6
7
8
C8051F342/3/6/7
Top View
9
10
11
12
13
P2.6
P2.7
P2.5
14
P2.4
15
P2.3
16
P2.2
24
23
22
21
20
19
18
17
P1.2
P1.3
P1.4
P1.5D+
P1.6
P1.7
P2.0
P2.1
P3.0 / C2D
/RST / C2CK
Figure 4.3. LQFP-32 Pinout Diagram (Top View)
38 Rev. 0.5
32
PIN 1
IDENTIFIER
A2
C8051F340/1/2/3/4/5/6/7
D
D1
E1
E
1
Table 4.3. LQFP-32
Package Dimensions
MM
MIN TYP MAX
A--1.60
A1 0.05 - 0.15
A2 1.35 1.40 1.45
b 0.30 0.37 0.45
D-9.00D1 - 7.00 -
e-0.80-
E-9.00E1 - 7.00 -
A
A1
eb
Figure 4.4. LQFP-32 Package Diagram
Rev. 0.5 39
C8051F340/1/2/3/4/5/6/7
NOTES:
40 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5. 10-Bit ADC (ADC0)
The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7 consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window
detector are all configured und er software control via the Special Function Reg isters shown in
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure voltages
at port pins, the Temperature Sensor output, or V
with respect to a port pin, VREF, or GND. The connec-
DD
tion options for AMUX0 are detailed in SFR Definition 5.1 and SFR Definition 5.2. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Figure 5.1.
Port I/O
Pins*
VDD
Temp
Sensor
Port I/O
Pins*
VREF
GND
* 21 Selections on 32-pin package
20 Selections on 48-pin package
Positive
Input
(AIN+)
AMUX
Negative
Input
(AIN-)
AMUX
AMX0P
AMX0P4
AMX0P3
AMX0P2
AMX0P1
AMX0P0
AIN+
VDD
10-Bit
AD0EN
ADC0CN
AD0TM
AD0INT
AD0WINT
AD0BUSY
Conversion
SAR
AMX0N4
AMX0N
AMX0N3
AMX0N2
AMX0N1
AMX0N0
AD0SC4
AIN-
AD0SC2
AD0SC3
ADC0CF
AD0SC1
AD0SC0
AD0LJST
ADC
SYSCLK
ADC0LTH
ADC0GTH ADC0GTL
REF
ADC0LTL
Figure 5.1. ADC0 Functional Block Diagram
AD0CM2
AD0CM0
AD0CM1
000 AD0BUSY (W)
Start
001
010
011
100
101 Timer 3 Overflow
ADC0L
ADC0H
32
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
AD0WINT
Window
Compare
Logic
Rev. 0.5 41
C8051F340/1/2/3/4/5/6/7
5.1. Analog Multiplexer
AMUX0 selects the positive and negative inputs to the ADC. Th e positive input (AIN+) can be connecte d to
individual Port pins, the on-chip temperature sensor, or the positive power supply (V
input (AIN-) can be connected to individual Port pins, VREF, or GND.
ative input, ADC0 operates in Single-ended Mode; at all other times, ADC0 operates in Differential
The ADC0 input channels are selected in the AMX0P and AMX0N registers as described in SFR
Mode.
Definition 5.1 and SFR Definition 5.2.
The conversion code format differs between Single-ended and Differential modes. The registers ADC0H
and ADC0L contain the high and low bytes of the output conversion code from the ADC at the completion
of each conversion. Data can be right-justified or left- justified , depending o n the setting of the AD0LJST bit
(ADC0CN.0). When in Single-ended Mode, conversion codes are represented as 10-bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justi
fied and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
When GND is selected as the neg-
). The negative
DD
-
Input Voltage
(Single-Ended)
VREF x 1023/1024 0x03FF 0xFFC0
VREF x 512/1024 0x0200 0x8000
VREF x 256/1024 0x0100 0x4000
0 0x0000 0x0000
When in Differential Mode, conversion codes are represented as 10-bit signed 2’s complement numbers.
Inputs are measured from –VREF to VREF x 511/512. Example codes are shown below for both right-jus
tified and left-justified data. For right-justified data, the unused MSBs of ADC0 H ar e a sign-e xtension of the
data word. For left-justified data, the unused LSBs in the ADC0L register are set to ‘0’.
Input Voltage
(Differential)
VREF x 511/512 0x01FF 0x7FC0
VREF x 256/512 0x0100 0x4000
0 0x0000 0x0000
–VREF x 256/512 0xFF00 0xC000
–VREF 0xFE00 0x8000
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to ‘0’ the corresponding bit in register PnMDIN (for n = 0,1,2,3). To force the Crossbar to skip a
Port pin, set to ‘1’ the corresponding bit in register PnSKIP (for n = 0,1,2). See
Output” on page 147 for more Port I/O configuration details.
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
Section “15. Port Input/
-
42 Rev. 0.5
5.2. Temperature Sensor
C8051F340/1/2/3/4/5/6/7
The temperature sensor transfer function is shown in Figure 5.2. The outp ut volt age (V
ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Values for the
Offset and Slope parameters can be found in
V
= (Slope x TempC) + Offset
TEMP
Temp
= (V
C
Voltage
Table 5.1.
- Offset) / Slope
TEMP
Slope (V / deg C)
Offset (V at 0 Celsius)
) is the positive
TEMP
Temperature
Figure 5.2. Temperature Sensor Transfer Function
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature measurements (see Table 5.1 for linearity specifications). For absolute temperature measurements, offset and/
or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
Step 1. Control/m easure the ambient temperature (this temperature must be known).
Step 2. Power the device, and delay for a few seconds to allow for self-heating.
Step 3. Perform an ADC conversion with the temperature sensor selected as the po sitive input
and GND selected as the negative input.
Step 4. Calculate the o ffset characteristics, and store this value in non-volatile memory for use
with subsequent temperature sensor measurements.
Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that
parameters which affect ADC measurement, in particular the voltage reference value, will also
affect temperature measurement.
Rev. 0.5 43
C8051F340/1/2/3/4/5/6/7
5.0
0
4.0
0
3.0
0
2.0
0
1.0
0
0.0
0
-40.00 -20.00
-1.00
Error (degrees C)
-2.00
-3.00
-4.00
-5.00
0.0
0
20.0
0
Temperature (degrees C)
40.0
0
60.0
0
80.0
0
5.0
0
4.0
0
3.0
0
2.0
0
1.0
0
0.0
0
-1.00
-2.00
-3.00
-4.00
-5.00
Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V)
44 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.3. Modes of Operation
ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of
the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by
(AD0SC
5.3.1. Starting a Conversion
A conversion can be initiated in on e of five ways, d epending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Con versions may be initiate d by one of th e fol
lowing:
Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed
"on-demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when th e conver
sion is complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0
interrupt flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag
(AD0INT) should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when
bit AD0INT is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low
Byte overflows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit
mode. See
+ 1) for 0 ≤ AD0SC ≤ 31).
-
1. Writing a ‘1’ to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 1 overflow
5. A rising edge on the CNVSTR input signal
6. A Timer 3 overflow
-
Section “21. Timer s” on page 243 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as a Port pin. When the
CNVSTR input is used as the ADC0 conversion source,
Digital Crossbar. To configure the Crossbar to skip a pin, set th e corresponding bit in the PnSKIP register
to ‘1’. See
Section “15. Port Input/Output” on page 147 for details on Port I/O configuration.
the associated Port pin should be skipped by the
Rev. 0.5 45
C8051F340/1/2/3/4/5/6/7
5.3.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mod e. In its default state, the ADC0
input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1,
ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track
ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low; conversion begins
on the rising edge of CNVSTR (see
is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX settings are frequently changed, due to the settling time requirements described in Section “5.3.3. Settling
Time Requirements” on page 47.
CNVSTR
(AD0CM[2:0]=100)
Figure 5.4). Tracking can also be disabled (shut down) when th e device
A. ADC0 Timing for External Trigger Source
-
SAR Clocks
AD0TM=1
Write '1' to AD0BUSY,
Timer 0, Timer 2,
Timer 1, Timer 3 Overflow
(AD0CM[2:0]=000, 001,010
011, 101)
SAR Clocks
AD0TM=1
SAR Clocks
AD0TM=0
Low Power
or Convert
Track or Convert Convert TrackAD0TM=0
123456789
Track Convert
10 11
Low Po wer
B. ADC0 Timing for Internal Trigger Source
Low Po wer
or Convert
Track or
Convert
123456789101112
Track Convert Low Power Mode
123456789
Convert Track
10
13 14
11
Mode
Figure 5.4. 10-Bit ADC Track and Conversion Example Timing
46 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum
tracking time is required before an accurate conversion can be performed. This tracking time is determined
by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu
racy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the mini
mum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by
Sensor output or VDD with respect to GND, R
TOTAL
settling time requirements.
n
2
⎛⎞
t
------ -
×ln=
⎝⎠
SA
R
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (10).
is the sum of the AMUX0 resistance and any external source resistance.
TOTAL
Equation 5.1. When measuring the Temperature
reduces to R
TOTALCSAMPLE
. See Table 5.1 for ADC0 minimum
MUX
-
-
Differential Mode
MUX
Select
Px.x
RC
= R
Input
MUX
Px.x
MUX Select
Single-Ended Mode
MUX Select
R
* C
R
MUX
MUX
= 5k
SAMPLE
= 5k
C
SAMPLE
C
SAMPLE
= 5pF
= 5pF
Px.x
RC
Input
= R
MUX
R
* C
MUX
= 5k
SAMPLE
Figure 5.5. ADC0 Equivalent Input Circuits
C
SAMPLE
= 5pF
Rev. 0.5 47
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select
R R R R/W R/W R/W R/W R/W Reset Value
- - - AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection
0xBB
AMX0P4-0 ADC0 Positive Input
(32-pin Package)
00000 P1.0 P2.0
00001 P1.1 P2.1
00010 P1.2 P2.2
00011 P1.3 P2.3
00100 P1.4 P2.5
00101 P1.5 P2.6
00110 P1.6 P3.0
00111 P1.7 P3.1
01000 P2.0 P3.4
01001 P2.1 P3.5
01010 P2.2 P3.7
01011 P2.3 P4.0
01100 P2.4 P4.3
01101 P2.5 P4.4
01110 P2.6 P4.5
01111 P2.7 P4.6
10000 P3.0 RESERVED
10001 P0.0 P0.3
10010 P0.1 P0.4
10011 P0.4 P1.1
10100 P0.5 P1.2
10101 - 11101 RESERVED RESERVED
11110 Temp Sensor Temp Sensor
11111
V
DD
ADC0 Positive Input
(48-pin Package)
V
DD
48 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select
R R R R/W R/W R/W R/W R/W Reset Value
- - - AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection.
Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended
mode. For all other Negative Input selections, ADC0 operates in Differential mode.
0xBA
AMX0N4-0 ADC0 Negative Input
(32-pin Package)
00000 P1.0 P2.0
00001 P1.1 P2.1
00010 P1.2 P2.2
00011 P1.3 P2.3
00100 P1.4 P2.5
00101 P1.5 P2.6
00110 P1.6 P3.0
00111 P1.7 P3.1
01000 P2.0 P3.4
01001 P2.1 P3.5
01010 P2.2 P3.7
01011 P2.3 P4.0
01100 P2.4 P4.3
01101 P2.5 P4.4
01110 P2.6 P4.5
01111 P2.7 P4.6
10000 P3.0 RESERVED
10001 P0.0 P0.3
10010 P0.1 P0.4
10011 P0.4 P1.1
10100 P0.5 P1.2
10101 - 11101 RESERVED RESERVED
11110 VREF VREF
11111 GND (Single-Ended Mode) GND (Single-Ended Mode)
ADC0 Negative Input
(48-pin Package)
Rev. 0.5 49
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.3. ADC0CF: ADC0 Configuration
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST - - 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirement s
are given in Table 5.1.
SYSCLK
AD0SC
Bit2: AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Bits1–0: UNUSED. Read = 00b; Write = don’t care.
----------------------
CLK
SAR
1–=
0xBC
SFR Definition 5.4. ADC0H: ADC0 Data Word MSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0: Bits 7–2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits of the
10-bit ADC0 Data Word.
For AD0LJST = 1: Bits 7–0 are the most-significant bits of the 10-bit ADC0 Data Word.
SFR Definition 5.5. ADC0L: ADC0 Data Word LSB
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the 10-bit Data Word.
For AD0LJST = 1: Bits 7–6 are the lower 2 bits of the 10-bit Data Word. Bits 5–0 will always
read ‘0’.
0xBE
0xBD
50 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.6. ADC0CN: ADC0 Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: AD0TM: ADC0 Track Mode Bit.
0: Normal Track Mode: When ADC0 is enabled, tracking is continuous unless a conversion
is in progress.
1: Low-power Track Mode: Tracking Defined by AD0CM2-0 bits (see below).
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set
to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM2-0 = 000b
Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
0: ADC0 Window Comparison Data match h as not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bits2–0: AD0CM2–0: ADC0 Start of Conversion Mode Select.
When AD0TM = 0:
000: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 1.
100: ADC0 conversion initiated on rising edge of external CNVSTR.
101: ADC0 conversion initiated on overflow of Timer 3.
11x: Reserved.
When AD0TM = 1:
000: Tracking initiated on write of ‘1’ to AD0BUSY and lasts 3 SAR clocks, followed by conversion.
001: Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks, followed by conversion.
010: Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks, followed by conversion.
011: Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion.
100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion.
11x: Reserved.
0xE8
Rev. 0.5 51
C8051F340/1/2/3/4/5/6/7
5.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 conversion results to
user-programmed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster sys
tem response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used
in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag ca n be programmed to indicate when mea
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
The Window Detector registers must be written with the same format (left/right justified, signed/unsigned)
as that of the current ADC configuration (left/right justified, single-ended/differential).
SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
11111111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC4
-
-
Bits7–0: High byte of ADC0 Greater-Than Data Word.
SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: Low byte of ADC0 Greater-Than Data Word.
11111111
0xC3
52 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: High byte of ADC0 Less-Than Data Word.
SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xC6
0xC5
Bits7–0: Low byte of ADC0 Less-Than Data Word.
Rev. 0.5 53
C8051F340/1/2/3/4/5/6/7
5.4.1. Window Detector In Single-Ended Mode
Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode,
the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a
10-bit unsigned integer value. In the left example, an AD0WINT interrupt will be generated if the ADC0
conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if
ple using left-justified data with equivalent ADC0GT and ADC0LT register settings.
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and AD0WINT interrupt
ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 5.7 shows an exam-
ADC0H:ADC0L ADC0H:ADC0L
Input Voltage
(Px.x - GND)
0x03FF
VREF x (1023/1024)
0x03FF
VREF x (128/1024)
VREF x (64/1024)
0
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
VREF x (128/1024)
VREF x (64/1024)
0
0x0081
0x0080
0x007F
0x0041
0x0040
0x003F
0x0000
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data
ADC0H:ADC0L ADC0H:ADC0L
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
Input Voltage
(Px.x - GND)
VREF x (1023/1024)
VREF x (128/1024)
VREF x (64/1024)
0xFFC0
0x2040
0x2000
0x1FC0
0x1040
0x1000
0x0FC0
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT
not affected
0
0x0000
0
0x0000
AD0WINT=1
Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data
54 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
5.4.2. Window Detector In Differential Mode
Figure 5.8 shows two example window comparisons for right-justified, differential data, with
ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the
measurable voltage between the input pins is between -VREF a nd VREF*(511/512). Output codes are rep
resented as 10-bit 2’s complement signed integers. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL
and ADC0LTH:ADC0LTL (if
0xFFFF (-1d) < ADC0H:ADC0L < 0x0040 (64d)). In the right example, an
AD0WINT interrupt will be generated if the ADC0 conversion word is outside of the range defined by the
ADC0GT and ADC0LT registers (if
ADC0H:ADC0L < 0xFFFF (-1d) or ADC0H:ADC0L > 0x0040 (+64d)).
Figure 5.9 shows an example using left-justified data with equivalent ADC0GT and ADC0LT register settings.
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
0x01FF
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
0x01FF
-
VREF x (64/512)
VREF x (-1/512)
-VREF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
AD0WINT
not affected
AD0WINT=1
VREF x (64/512)
VREF x (-1/512)
-VREF
0x0041
0x0040
0x003F
0x0000
0xFFFF
0xFFFE
0x0200
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data
ADC0H:ADC0LADC0H:ADC0L
Input Voltage
(Px.x - Px.x)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
ADC0GTH:ADC0GTL
Input Voltage
(Px.x - Px.y)
VREF x (511/512)
VREF x (64/512)
VREF x (-1/512)
0x7FC0
0x1040
0x1000
0x0FC0
0x0000
0xFFC0
0xFF80
ADC0GTH:ADC0GTL
AD0WINT
not affected
ADC0LTH:ADC0LTL
AD0WINT=1
AD0WINT=1
-VREF
0x8000
AD0WINT
not affected
-VREF
0x8000
Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data
Rev. 0.5 55
C8051F340/1/2/3/4/5/6/7
Table 5.1. ADC0 Electrical Characteristics
VDD = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 10 bits
Integral Nonlinearity ±0.5 ±1 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error 0 LSB
Full Scale Error -1 LSB
Offset Temperature Coefficient 10 ppm/°C
Dynamic Performance (10 kHz sine-wave Single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 51 52.5 dB
Total Harmonic Distortion
Spurious-Free Dynamic Range 78 dB
SAR Conversion Clock 3 MHz
Conversion Time in SAR Clocks 10 clocks
Track/Hold Acquisition Time 300 ns
Throughput Rate 200 ksps
ADC Input Voltage Range Single Ended (AIN+ – GND)
Absolute Pin V oltage with respect
to GND
Input Capacitance 5 pF
Linearity
Slope
Offset
Power Supply Current (VDD supplied to ADC0)
Power Supply Rejection ±0.3 mV/V
1
2
1,2
Up to the 5th harmonic
Conversion Rate
Analog Inputs
0
Differential (AIN+ – AIN–)
Single Ended or Differential 0
Temperature Sensor
(Temp = 0 °C)
Power Specifications
Operating Mode, 200 ksps 400 900 µA
–VREF
–67 dB
VREF
VREF
V
DD
±0.1 °C
TBD
±TBD
TBD
±TBD
mV / °C
V
V
V
mV
Notes:
1. Includes ADC offset, gain, and linearity variations.
2. Represents mean ± one standard deviation.
56 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
6. Voltage Reference
The Voltage reference MUX on C8051F340/1/2/3/4/5/6/7 devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage VDD (see
Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For
the internal reference or an external source, REFSL should be set to ‘0’; For VDD as the reference source,
REFSL should be set to ‘1’.
The BIASE bit enables the internal ADC bias generator, which is used by the ADC and Internal Oscillator.
This enable is forced to logic 1 when either of the aforementioned peripherals is enabled. The ADC bias
generator may be enabled manually by writing a ‘1’ to the BIASE bit in register REF0CN; see
tion 6.1 for REF0CN register details. The Reference bias generator (see Figure 6.1) is used by the Internal
Voltage Reference, Temperature Sensor, and Clock Multiplier. The Reference bias is automatically
enabled when any of the aforementioned peripherals are enabled. The electrical specifications for the volt
age reference and bias circuits are given in Table 6.1.
Important Note About the VREF Pin: The VREF pin, when not using the on-chip voltage reference or an
external precision reference, ca n be co n fig ur ed a s a G PIO Port pin. When using an exte r na l vo ltage ref er
ence or the on-chip reference, the VREF pin sh ould be con figured as analog p in and ski pped by the Digital
Crossbar. To configure the VREF pin for analog mode, set the corresponding bit in the PnMDIN register to
‘0’. To configure the Crossbar to skip the VREF pin, set the corresponding bit in register PnSKIP to ‘1’.
Refer to
Section “15. Port Input/Output” on page 147 for complete Port I/O configuration details.
SFR Defini-
-
-
The temperature sensor connects to the ADC0 po sitive inp ut multiplexer (see Section “5.1. Analog Multi-
plexer” on page 42 for details). The TEMPE bit in register REF0CN enables/disables the temperature
sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0 measurements performed on the sensor result in meaningless data.
REF0CN
BIASE
REFSL
REFBE
TEMPE
AD0EN
To ADC,
Internal Oscillator
To Analog Mux
VREF
(to ADC)
To Clock Multiplier,
Temp Sensor
VDD
GND
R1
External
Voltage
Reference
Circuit
VREF
VDD
0
1
TEMPE
IOSCEN
CLKMUL
Enable
REFBE
EN
EN
EN
ADC Bias
Temp Sensor
Reference
Bias
EN
Internal
Reference
Figure 6.1. Voltage Reference Functional Block Diagram
Rev. 0.5 57
C8051F340/1/2/3/4/5/6/7
SFR Definition 6.1. REF0CN: Reference Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - REFSL TEMPE BIASE REFBE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–3: UNUSED. Read = 00000b; Write = don’t care.
Bit3: REFSL: Voltage Reference Select.
This bit selects the source for the internal voltage reference.
0: VREF pin used as voltage reference.
1: V
used as voltage reference.
DD
Bit2: TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
Bit1: BIASE: Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
Bit0: REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer disabled.
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.
0xD1
Table 6.1. Voltage Reference Electrical Characteristics
VDD = 3.0 V; –40 to +85 °C Unless Otherwise Specified
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient 2.38 2.44 2.50 V
VREF Short-Circuit Current 10 mA
VREF Temperature Coeffi-
cient
Load Regulation Load = 0 to 200 µA to GND 1.5 ppm/µA
VREF Turn-on Time 1
VREF Turn-on Time 2 0.1 µF ceramic bypass 20 µs
VREF Turn-on Time 3 no bypass cap 10 µs
Power Supply Rejection 140 ppm/V
Input Voltage Range 0
Input Current
ADC Bias Generator BIASE = ‘1’ 100 µA
Reference Bias Generator 40 µA
4.7 µF tantalum, 0.1 µF ceramic
bypass
External Reference (REFBE = 0)
Sample Rate = 200 ksps; VREF =
3.0
V
Bias Generators
15 ppm/°C
2 ms
V
DD
12 µA
V
58 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
7. Comparators
C8051F340/1/2/3/4/5/6/7 devices include two on-chip programma ble voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two
Comparators operate identically with the following exceptions: (1) Their input selections differ, and (2)
Comparator0 can be used as a reset source. For input selection details, refer to
SFR Definition 7.5.
Each Comparator offers pro grammable resp onse time a nd hysteresis, an an alog input multip lexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see
reset source (see Section “11.5. Comparator0 Reset” on page 104).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 7.2). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (
CMX1P1-CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the
Comparator1 negative input.
Section “15.2. Port I/O Initialization” on page 151). Comparator0 may also be used as a
SFR Definition 7.2 and
SFR Definition 7.5). The
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port co nfigur ation reg ister, and configured to be skipped by the
Crossbar (for details on Port configuration, see
Section “15.3. General Purpose Port I/O” on page 154).
Rev. 0.5 59
C8051F340/1/2/3/4/5/6/7
CPnEN
CPnOUT
CPnRIF
CMXnN2
CMXnN1
CMXnN0
CPTnMX
CMXnP2
CMXnP1
CMXnP0
CPnFIF
CPnHYP1
CPTnCN
CPnHYP0
CPnHYN1
CPnHYN0
VDD
CPn
Rising-edge
CPn
Interrupt
CPn
Falling-edge
CPnRIE
CPnFIE
CPn
CPnA
Port I/O connection options vary with
package (32-pin or 48-pin)
CPn +
CPn -
CPnRIE
CPnFIE
Interrupt
Logic
+
-
GND
SET
SET
Q
D
(SYNCHRONIZER)
Q
D
CLR
CLR
Q
Q
Reset Decision Tree
(Comprator 0 Only)
Crossbar
CPTnMD
CPnMD1
CPnMD0
Figure 7.1. Comparator Functional Block Diagram
Comparator outputs can be polled in software, used as an inte rrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and supply current falls to less than 100
page 149 for details on configuring Comparator outputs via the dig ital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator electrical specifications are given in Table 7.1.
nA. See Section “15.1. Priority Crossbar Decoder” on
-
Comparator response time may be configured in software via the CPTnMD registers (see SFR Definition
7.3 and SFR Definition 7.6). Selecting a longer response time reduces the Comparator supply current. See
Table 7.1 for complete timing and supply current specifications.
60 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
CP0+
VIN+
CP0-
VIN-
CIRCUIT CONFIGURATION
Positive Hysteresis Voltage
(Programmed with CP0HYP Bits)
VIN-
INPUTS
VIN+
OUTPUT
V
OL
Positive Hysteresis
Disabled
Figure 7.2. Comparator Hysteresis Plot
+
CP0
_
V
OH
OUT
Maximum
Posi tive Hysteresis
Negative Hysteresis
Disabled
Negative Hysteresis Voltage
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis
Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN (shown
in
SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is determined by
the settings of the CPnHYN bits. As shown in Figure 7.2, various levels of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see Section “ 9.3. Interrupt Handler” on page 87.) The CPnFIF flag is set
to ‘1’ upon a Comparator falling-edge, and the CPnRIF flag is set to ‘1’ upon the Comparator rising-edge.
Once set, these bits remain set until cleared by software. The output state of the Comparator can be
obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to
‘1’, and is disabled by clearing this bit to ‘0’.
Rev. 0.5 61
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.1. CPT0CN: Comparator0 Control
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP0EN CP0OUT CP0RIF CP0FIF CP0HYP1 CP0HYP0 CP0HYN1 CP0HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: CP0EN: Co mparat or 0 Enab le Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
Bit6: CP0 OU T: Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0–.
1: Voltage on CP0+ > CP0–.
Bit5: CP0RIF : Co mparator 0 Risin g -Ed ge Flag.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
Bit4: CP0FIF: Comparator0 Falling-Edge Flag.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge Interrupt has occurred.
Bits3–2: CP0HYP1–0: Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP0HYN1–0: Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
0x9B
62 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- CMX0N2 CMX0N1 CMX0N0 - CMX0P2 CMX0P1 CMX0P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: UNUSED. Read = 0b, Write = don’t care.
Bits6–4: CMX0N2–CMX0N0: Comparator0 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator0 negative input.
0x9F
CMX0N1 CMX0N1 CMX0N0 Negative Input
(32-pin Package)
0 0 0 P1.1 P2.1
0 0 1 P1.5 P2.6
0 1 0 P2.1 P3.5
0 1 1 P2.5 P4.4
1 0 0 P0.1 P0.4
Bit3: UNUSED. Read = 0b, Write = don’t care.
Bits2–0: CMX0P2–CMX0P0: Comparator0 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator0 positive input.
CMX0P1 CMX0P1 CMX0P0 Positive Input
(32-pin Package)
000 P1.0 P2.0
001 P1.4 P2.5
010 P2.0 P3.4
011 P2.4 P4.3
100 P0.0 P0.3
Note that the port pins used by the comparator depend on the package type (32-pin or 48-pin).
Negative Input
(48-pin Package)
Positive Input
(48-pin Package)
Rev. 0.5 63
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CP0RIE CP0FIE - - CP0MD1 CP0MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–6: UNUSED. Read = 00b. Write = don’t care.
Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 rising-edge interrupt disabled.
1: Comparator0 rising-edge interrupt enabled.
Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 falling-edge interrupt disabled.
1: Comparator0 falling-edge interrupt enabled.
Bits3–2: UNUSED. Read = 00b. Write = don’t care.
Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select
These bits select the response time for Comparator0.
Mode CP0MD1 CP0MD0 CP0 Response Time*
0 0 0 Fastest Response
101
210
311 Lowest Power
0x9D
* See Table 7.1 for response time parameters.
64 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.4. CPT1CN: Comparator1 Control
R/W R R/W R/W R/W R/W R/W R/W Reset Value
CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0x9A
Bit7: CP1EN: Co mparat or 1 Enab le Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
Bit6: CP1 OU T: Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
Bit5: CP1RIF : Co mparator 1 Risin g -Ed ge Flag.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
Bit4: CP1FIF: Comparator1 Falling-Edge Flag.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
Bits3–2: CP1HYP1–0: Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
Rev. 0.5 65
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- CMX1N2 CMX1N1 CMX1N0 - CMX1P2 CMX1P1 CMX1P0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: UNUSED. Read = 0b, Write = don’t care.
Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select.
These bits select which Port pin is used as the Comparator1 negative input.
0x9E
CMX1N2 CMX1N1 CMX1N0 Negative Input
(32-pin Package)
000 P1.3 P2.3
001 P1.7 P3.1
010 P2.3 P4.0
011 P2.7 P4.6
100 P0.5 P1.2
Bit3: UNUSED. Read = 0b, Write = don’t care.
Bits2–0: CMX1P1–CMX1P0: Comparator1 Positive Input MUX Select.
These bits select which Port pin is used as the Comparator1 positive input.
CMX1P2 CMX1P1 CMX1P0 Positive Input
(32-pin Package)
0 0 0 P1.2 P2.2
0 0 1 P1.6 P3.0
0 1 0 P2.2 P3.7
0 1 1 P2.6 P4.5
1 0 0 P0.4 P1.1
Note that the port pins used by the comparator depend on the package type (32-pin or 48-pin).
Negative Input
(48-pin Package)
Positive Input
(48-pin Package)
66 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - CP1RIE CP1FIE - - CP1MD1 CP1MD0 00000010
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–6: UNUSED. Read = 00b, Write = don’t care.
Bit5: CP1RIE: Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 rising-edge interrupt disabled.
1: Comparator1 rising-edge interrupt enabled.
Bit4: CP1FIE: Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 falling-edge interrupt disabled.
1: Comparator1 falling-edge interrupt enabled.
Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select.
These bits select the response time for Comparator1.
Mode CP1MD1 CP1MD0 CP1 Response Time*
0 0 0 Fastest Response
101
210
311 Lowest Power
0x9C
* See Table 7.1 for response time parameters.
Rev. 0.5 67
C8051F340/1/2/3/4/5/6/7
Table 7.1. Comparator Electrical Characteristics
VDD = 3.0 V, –40 to +85 °C unless otherwise noted.
All specifications apply to both Comparator0 and Comparator1 unless otherwise noted.
Parameter Conditions Min Typ Max Unit s
Response Time:
Mode 0, Vcm* = 1.5 V
Response Time:
Mode 1, Vcm* = 1.5 V
Response Time:
Mode 2, Vcm* = 1.5 V
Response Time:
Mode 3, Vcm* = 1.5 V
Common-Mode Rejection
Ratio
Positive Hysteresis 1 CP0HYP1–0 = 00 0 1 mV
Positive Hysteresis 2 CP0HYP1–0 = 01 2 5 10 mV
Positive Hysteresis 3 CP0HYP1–0 = 10 7 10 20 mV
Positive Hysteresis 4 CP0HYP1–0 = 11 15 20 30 mV
Negative Hysteresis 1 CP0HYN1–0 = 00 0 1 mV
Negative Hysteresis 2 CP0HYN1–0 = 01 2 5 10 mV
Negative Hysteresis 3 CP0HYN1–0 = 10 7 10 20 mV
Negative Hysteresis 4 CP0HYN1–0 = 11 15 20 30 mV
Inverting or Non-Inverting
Input Voltage Range
Input Capacitance 3 pF
Input Bias Current 0.001 nA
Input Offset Voltage –5 +5 mV
Power Supply Rejection 0.1 mV/V
Power-up Time 10 µs
Supply Current at DC
CP0+ – CP0– = 100 mV 100 ns
CP0+ – CP0– = –100 mV 250 ns
CP0+ – CP0– = 100 mV 175 ns
CP0+ – CP0– = –100 mV 500 ns
CP0+ – CP0– = 100 mV 320 ns
CP0+ – CP0– = –100 mV 1100 ns
CP0+ – CP0– = 100 mV 1050 ns
CP0+ – CP0– = –100 mV 5200 ns
1.5 4 mV/V
–0.25
Power Supply
Mode 0 7.6 µA
Mode 1 3.2 µA
Mode 2 1.3 µA
Mode 3 0.4 µA
VDD + 0.25
V
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
68 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
8. Voltage Regulator (REG0)
C8051F340/1/2/3/4/5/6/7 devices include a voltage regulator (REG0). When enabled, the REG0 output
appears on the V
software using bit REGEN in register REG0CN. See
Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network.
The VBUS signal should only be connected to the REGIN pin when operating the device as a bus-powere d
function. REG0 configuration options are shown in
8.1. Regulator Mode Selection
REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power
mode, the REG0 output remains as specified; however the REG0 dynami c performa nce (respo nse time) is
degraded. See
selection is controlled via the REGMOD bit in register REG0CN.
8.2. VBUS Detection
When the USB Function Controller is used (see section Section “16. Universal Serial Bus Controller
(USB0)” on page 163), the VBUS signal should be connected to the VBUS pin. The VBSTAT bit (register
REG0CN) indicates the current logic level of the VBUS signal. If enabled, a VBUS interrupt will be generated when the VBUS signal matches the polarity selected by the VBPOL bit in register REG0CN. The
VBUS interrupt is level-sensitive, and has no associated interrupt pending flag. The VBUS interrupt will be
active as long as the VBUS signal matc hes the polarity selected by VBPOL. See
parameters.
pin and can be used to po wer external devices. REG0 can be enabled/disabled by
DD
Table 8.1 for REG0 electrical characteristics.
Figure 8.1–Figure 8.4.
Table 8.1 for normal and low power mode supply current specifications. The REG0 mode
Table 8.1 for VBUS input
Important Note: When USB is selected as a reset source, a system reset will be generated when the
VBUS signal matches the polarity selected by the VBPOL bit. See
page 101 for details on selecting USB as a reset source
Section “11. Reset Sources” on
Table 8.1. Voltage Regulator Electrical Specifications
–40 to +85 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Voltage Range
Output Voltage (VDD)
Output Current
VBUS Detection Input Threshold 1.0 1.8 4.0 V
Bias Current
Dropout Voltage (VDO)
Notes:
1. Input range specified for regulation. When an external regulator is used, should be tied to VDD.
2. Output current is total regulator output, including any current required by the C8051F34x.
3. The minimum input voltage is 2.70 V or VDD + VDO (max load), whichever is greater.
1
2
2
3
Output Current = 1 to 100 mA 3.0 3.3 3.6 V
Normal Mode (REGMOD = ‘0’)
Low Power Mode (REGMOD = ‘1’)
IDD = 1 mA
IDD = 100 mA
2.7 5.25 V
100 mA
90
60
100
TBD
TBD
1
µA
mV/mA
Rev. 0.5 69
C8051F340/1/2/3/4/5/6/7
VBUS
From VBUS
To 3 V
Power Net
From VBUS
VBUS Sense
REGIN
VDD
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.1. REG0 Configuration: USB Bus-Powered
VBUS
VBUS Sense
Device
Power Net
From 5 V
Power Net
To 3 V
Power Net
REGIN
VDD
Figure 8.2. REG0 Configuration: USB Self-Powered
70 Rev. 0.5
Voltage Regulator (REG0)5 V In
3 V Out
Device
Power Net
C8051F340/1/2/3/4/5/6/7
From VBUS
From 3 V
Power Net
VBUS
REGIN
VDD
VBUS Sense
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled
VBUS
Device
Power Net
From 5 V
Power Net
To 3 V
Power Net
VBUS Sense
REGIN
VDD
Voltage Regulator (REG0)5 V In
3 V Out
Figure 8.4. REG0 Configuration: No USB Connection
Device
Power Net
Rev. 0.5 71
C8051F340/1/2/3/4/5/6/7
SFR Definition 8.1. REG0CN: Voltage Regulator Control
R/W R R/W R/W R/W R/W R/W R/W Reset Value
REGDIS VBSTAT VBPOL REGMOD Reserved Reserved Reserved Reserved 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: REGDIS: Voltage Regulator Disable.
0: Voltage Regulator Enabled.
1: Voltage Regulator Disabled.
Bit6: VBSTAT: VBUS Signal Status.
0: VBUS signal currently absent (device not attached to USB network).
1: VBUS signal currently present (device attached to USB network).
Bit5: VBPOL: VBUS Interrupt Polarity Select.
This bit selects the VBUS interrupt polarity.
0: VBUS interrupt active when VBUS is low.
1: VBUS interrupt active when VBUS is high.
Bit4: REGMOD: Voltage Regulator Mode Select.
This bit selects the Voltage Regulator mode. When REGMOD is set to ‘1’, the voltage regu-
lator operates in low power (suspend) mode.
0: USB0 Voltage Regulator in normal mode.
1: USB0 Voltage Regulator in low power mode.
Bits3–0: Reserved. Read = 0000b. Must Write = 0000b.
0xC9
72 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in Section 18), an Enhanced SPI (see description in Section 20), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 9.2.6), and 25 Port I/O (see description in Sec-
tion 15). The CIP-51 also includes on-chip debug hardware (see descr iption in Sectio n 23), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see
The CIP-51 includes the following features:
Section 21), an enhanced full-duplex UART (see description
Figure 9.1 for a block diagram).
-
- Fully Compatible with MCS-51 Instruction
Set
- 0 to 48 MHz Clock Frequency
- 256 Bytes of Internal RAM
- 25 Port I/O
DATA BUS
RESET
CLOCK
STOP
IDLE
D8
ACCUMULATOR
PSW
D8
BUFFER
DATA POINTER
PC INCREMENTER
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
CONTROL
LOGIC
POWER CONTROL
REGISTER
D8
TMP1 TMP2
ALU
PIPELINE
DATA BUS
D8
D8
DATA BUS
D8
D8
D8
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
B REGISTER
ADDRESS
REGISTER
D8
INTERFACE
D8
A16
INTERFACE
D8
INTERRUPT
INTERFACE
D8
D8
SRAM
D8
SFR
BUS
MEMORY
D8
STACK POINTER
SRAM
(256 X 8)
D8
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEM_WRITE_DATA
MEM_READ_DATA
SYSTEM_IRQs
EMULATION_IRQ
Figure 9.1. CIP-51 Block Diagram
Rev. 0.5 73
C8051F340/1/2/3/4/5/6/7
Performance
The CIP-51 employs a pipelined architectu re that grea tly increases its instruction throughput over the st andard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12
core executes 70% of its instructions in one or two system clock cycles, with no instruct ions taking more
than eight system clock cycles.
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that for execution time.
Clocks to Execute 1 2 2/4 3 3/5 4 5 4/6 6 8
Number of Instructions 26 50 5 10 7 5 2 1 2 1
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2). Note that the re-program
mable Flash can also be read and changed a single byte at a time by the application software using the
MOVC and MOVX instructions. T his featur e allows progra m memo ry to b e used for non -volatile data stor
age as well as updating program code under software control.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All ana log and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with
out occupying package pins. C2 details can be found in Section “23. C2 Interface” on page 279.
MHz. By contrast, the CIP-51
-
-
-
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs provides an integrated development environment (IDE) including editor, debugger, and programmer. The
IDE's debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient
in-system device programming and debugging. An 8051 assembler, linker and evaluation ‘C’ compiler are
included in the Development Kit. Many third party macro assemblers and C compilers are also available,
which can be used directly with the IDE.
9.1. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruction set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan
dard 8051.
9.1.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken a s opposed to wh en the branch is taken.
Table 9.1 is the
-
74 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
9.1.2. MOVX Instruction and Program Memory
The MOVX instruction is typically used to access external data memory (Note: the C8051F340/1/2/3/4/5/6/
7 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to
accesses external RAM (XRAM) and the on-chip program memory space implemented as re-progr amma
ble Flash memory. The Flash access feature provides a mechanism for the CIP-51 to update program
code and use the program memory space for non-vo latile dat a storage. Refer to
ory” on page 109 for further details.
Table 9.1. CIP-51 Instruction Set Summary
Section “12. Flash Mem-
-
Mnemonic Description Bytes
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract imme dia te fro m A with borr ow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement dir ec t byt e 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
Clock
Cycles
Rev. 0.5 75
C8051F340/1/2/3/4/5/6/7
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 1 2
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 3
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
Clock
Cycles
76 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 9.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 2 2/4
JNC rel Jump if Carry is not set 2 2/4
JB bit, rel Jump if direct bit is set 3 3/5
JNB bit, rel Jump if direct bit is not set 3 3/5
JBC bit, rel Jump if direct bit is set and clear bit 3 3/5
Program Branching
ACALL addr11 Absolute subroutine call 2 4
LCALL addr16 Long subroutine call 3 5
RET Return from subroutine 1 6
RETI Return from interrupt 1 6
AJMP addr11 Absolute jump 2 4
LJMP addr16 Long jump 3 5
SJMP rel Short jump (relative address) 2 4
JMP @A+DPTR Jump indirect relative to DPTR 1 4
JZ rel Jump if A equals zero 2 2/4
JNZ rel Jump if A does not equal zero 2 2/4
CJNE A, direct, rel Compare direct byte to A and jump if not equal 3 3/5
CJNE A, #data, rel Compare immediate to A and jump if not equal 3 3/5
CJNE Rn, #data, rel Compare immediate to Register and jump if not equal 3 3/5
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal 3 4/6
DJNZ Rn, rel Decrement Register and jump if not zero 2 2/4
DJNZ direct, rel Decrement direct byte and jump if not zero 3 3/5
NOP No operation 1 1
Clock
Cycles
Rev. 0.5 77
C8051F340/1/2/3/4/5/6/7
Notes on Registers, Operands and Addressing Modes:
Rn
- Register R0-R7 of the currently selected register bank.
@Ri - Data RAM location addressed indirectly through R0 or R1.
rel - 8-bit, signed (two’s complement) offset r elative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s ad dress. This could be a direct-access Data RAM location
(0x00-0x7F) or an SFR (0x80-0xFF).
#data - 8-bit constant
#data16 - 16-bit constant
bit - Direct-accessed bit in Data RAM or SFR
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2K-byte page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywher e within
the 8K-byte program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
78 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9.2. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The CIP-51 memory organization is
shown in
Figure 9.2.
PROGRAM/DATA MEMORY
(FLASH)
0xFFFF
0xFC00
0xFBFF
0x0000
RESERVED
FLASH
(In-System
Programmable in 512
Byte Sectors)
0xFF
0x80
0x7F
0x30
0x2F
0x20
0x1F
0x00
0xFFFF
0x1000
0x0FFF
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Special Function
Register's
(Direct Addressing Only)
Lower 128 RAM
(Direct and Indirect
Addressing)
EXTERNAL DATA ADDRESS SPACE
Off-Chip XRAM
(Available only on devices
with EMIF)
0x07FF
0x0400
0x0000
XRAM - 4096 Bytes
(Accessable using MOVX
instruction)
USB FIFOs
1024 Bytes
Figure 9.2. Memory Map
9.2.1. Program Memory
The CIP-51 core has a 64k-byte program memo ry sp ace. The C80 51F340/1/2 /3/4/5/6/7 implement s 64k or
32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the
C8051F340/2/4/6 (64k version), addresses above 0xFBFF are reserved.
Program memory is normally assumed to be read-only. However, th e CIP-51 can wr ite to pro gram m emory
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro
vides a mechanism for the CIP-51 to update program code and use the program memory space for
non-volatile data storage. Refer to
Section “12. Flash Memory” on page 109 for further details.
Rev. 0.5 79
-
C8051F340/1/2/3/4/5/6/7
9.2.2. Data Memory
The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF.
The lower 128
Either direct or indirect addressing may be used to access the lower 128
0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of
eight byte-wide registers. The next 16
bytes or as 128
The upper 128 bytes of data memory are accessible only b y indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128
9.2.3. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program st atus wo rd , RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in
fast context switching when entering subroutines and interrupt service routines. Indir ect addressing mod es
use registers R0 and R1 as index registers.
bytes of data memory are used for general purpose registers and scratch pad memory.
bytes of data memory. Locations
bytes, locations 0x20 through 0x2F, may either be addressed as
bit locations accessible with the direct addressing mode.
bytes of data memory space or the SFRs. Instructions that use
bytes of data memory. Figure 9.2 illustrates the data memory organization of the CIP-51.
SFR Definition 9.4). This allows
9.2.4. Bit Addressable Locations
In addition to direct access to data memory or gan ized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128
0x00 to 0x7F. Bit
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22h.3
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
0 of the byte at 0x20 has bit addre ss 0x00 while bit 7 of the byte at 0 x20 has bit addr ess
individually addressable bits. Each bit has a bit address from
9.2.5. Stack
A programmer's stack can be located anywhe re in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of registe r bank 1. T hus, if mor e than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The sta ck depth ca n exte nd up
to 256
bytes.
-
80 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set.
mented in the CIP-51 System Controller .
The SFR registers are accessed anyt ime the dire ct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are
bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corres ponding p ages of the dat asheet, as indicated in
for a detailed description of each register.
Table 9.2. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
B P0MDIN P1MDIN P2MDIN P3MDIN P4MDIN EIP1 EIP2
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
ACC XBR0 XBR1 XBR2 IT01CF SMOD1 EIE1 EIE2
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 P3SKIP
PSW REF0CN SCON1 SBUF1 P0SKIP P1SKIP P2SKIP USB0XCN
TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H - SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH P4
IP CLKMUL AMX0N AMX0P ADC0CF ADC0L ADC0H -
P3 OSCXCN OSCICN OSCICL SBRLL1 SBRLH1 FLSCL FLKEY
IE CLKSEL EMI0CN - SBCON1 - P4MDOUT PFE0CN
P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT P3MDOUT
SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H USB0ADR USB0DAT
TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
P0 SP DPL DPH EMI0TC EMI0CF OSCLCN PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Table 9.2 lists the SFRs imple-
Table 9.3,
Rev. 0.5 81
C8051F340/1/2/3/4/5/6/7
Table 9.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address Description Page
ACC 0xE0 Accumulator 86
ADC0CF 0xBC ADC0 Configuration 50
ADC0CN 0xE8 ADC0 Control 51
ADC0GTH 0xC4 ADC0 Greater-Than Compare High 52
ADC0GTL 0xC3 ADC0 Greater-Than Compare Low 52
ADC0H 0xBE ADC0 High 50
ADC0L 0xBD ADC0 Low 50
ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 53
ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 53
AMX0N 0xBA AMUX0 Negative Channel Select 49
AMX0P 0xBB AMUX0 Positive Channel Select 48
B 0xF0 B Register 87
CKCON 0x8E Clock Control 249
CLKMUL 0xB9 Clock Multiplier 142
CLKSEL 0xA9 Clock Select 144
CPT0CN 0x9B Comparator0 Control 62
CPT0MD 0x9D Comparator0 Mode Selection 64
CPT0MX 0x9F Comparator0 MUX Selection 63
CPT1CN 0x9A Comparator1 Control 65
CPT1MD 0x9C Comparator1 Mode Selection 67
CPT1MX 0x9E Comparator1 MUX Selection 66
DPH 0x83 Data Pointer High 85
DPL 0x82 Data Pointer Low 85
EIE1 0xE6 Extended Interrupt Enable 1 92
EIE2 0xE7 Extended Interrupt Enable 2 94
EIP1 0xF6 Extended Interrupt Priority 1 93
EIP2 0xF7 Extended Interrupt Priority 2 94
EMI0CN 0xAA External Memory Interface Control 120
EMI0CF 0x85 External Memory Interface Configuration 121
EMI0TC 0x84 External Memory Interface Timing 126
FLKEY 0xB7 Flash Lock and Key 114
FLSCL 0xB6 Flash Scale 115
IE 0xA8 Interrupt Enable 90
IP 0xB8 Interrupt Priority 91
IT01CF 0xE4 INT0/INT1 Configuration 95
OSCICL 0xB3 Internal Oscillator Calibration 137
OSCICN 0xB2 Internal Oscillator Control 136
OSCLCN 0x86 Internal Low-Frequency Oscillator Control 138
OSCXCN 0xB1 External Oscillator Control 141
P0 0x80 Port 0 Latch 154
P0MDIN 0xF1 Port 0 Input Mo de Con fig ur at ion 154
P0MDOUT 0xA4 Port 0 Output Mode Configuration 155
P0SKIP 0xD4 Port 0 Skip 155
P1 0x90 Port 1 Latch 156
82 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address Description Page
P1MDIN 0xF2 Port 1 Input Mo de Con fig ur at ion 156
P1MDOUT 0xA5 Port 1 Output Mode Configuration 156
P1SKIP 0xD5 Port 1 Skip 157
P2 0xA0 Port 2 Latch 157
P2MDIN 0xF3 Port 2 Input Mo de Con fig ur at ion 157
P2MDOUT 0xA6 Port 2 Output Mode Configuration 158
P2SKIP 0xD6 Port 2 Skip 158
P3 0xB0 Port 3 Latch 159
P3MDIN 0xF4 Port 3 Input Mo de Con fig ur at ion 159
P3MDOUT 0xA7 Port 3 Output Mode Configuration 159
P3SKIP 0xDF Port 3Skip 160
P4 0xC7 Port 4 Latch 160
P4MDIN 0xF5 Port 4 Input Mo de Con fig ur at ion 161
P4MDOUT 0xAE Port 4 Output Mode Configuration 161
PCA0CN 0xD8 PCA Control 274
PCA0CPH0 0xFC PCA Capture 0 High 278
PCA0CPH1 0xEA PCA Capture 1 High 278
PCA0CPH2 0xEC PCA Capture 2 High 278
PCA0CPH3 0xEE PCA Capture 3High 278
PCA0CPH4 0xFE PCA Capture 4 High 278
PCA0CPL0 0xFB PCA Capture 0 Low 277
PCA0CPL1 0xE9 PCA Capture 1 Low 277
PCA0CPL2 0xEB PCA Capture 2 Low 277
PCA0CPL3 0xED PCA Capture 3 Low 277
PCA0CPL4 0xFD PCA Capture 4 Low 277
PCA0CPM0 0xDA PCA Module 0 Mode Register 276
PCA0CPM1 0xDB PCA Module 1 Mode Register 276
PCA0CPM2 0xDC PCA Module 2 Mode Register 276
PCA0CPM3 0xDD PCA Module 3 Mode Register 276
PCA0CPM4 0xDE PCA Module 4 Mode Register 276
PCA0H 0xFA PCA Counter High 277
PCA0L 0xF9 PCA Counter Low 277
PCA0MD 0xD9 PCA Mode 275
PCON 0x87 Power Control 97
PFE0CN 0xAF Prefetch Engine Control 99
PSCTL 0x8F Program Store R/W Control 114
PSW 0xD0 Program Status Word 86
REF0CN 0xD1 Voltage Reference Control 58
REG0CN 0xC9 Voltage Regulator Control 72
RSTSRC 0xEF Reset Source Configuration/Status 106
SBCON1 0xAC UART1 Baud Rate Generator Control 226
SBRLH1 0xB5 UART1 Baud Rate Generator High 227
SBRLL1 0xB4 UART1 Baud Rate Generator Low 227
SBUF1 0xD3 UART1 Data Buffer 226
SCON1 0xD2 UART1 Control 224
Rev. 0.5 83
C8051F340/1/2/3/4/5/6/7
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register Address Description Page
SBUF0 0x99 UART0 Data Buffer 217
SCON0 0x98 UART0 Control 216
SMB0CF 0xC1 SMBus Configuration 200
SMB0CN 0xC0 SMBus Control 202
SMB0DAT 0xC2 SMBus Data 204
SMOD1 0xE5 UART1 Mode 225
SP 0x81 Stack Pointer 85
SPI0CFG 0xA1 SPI Configuration 236
SPI0CKR 0xA2 SPI Clock Rate Control 238
SPI0CN 0xF8 SPI Control 237
SPI0DAT 0xA3 SPI Data 238
TCON 0x88 Timer/Counter Control 247
TH0 0x8C Timer/Counter 0 High 250
TH1 0x8D Timer/Counter 1 High 250
TL0 0x8A Timer/Counter 0 Low 250
TL1 0x8B Timer/Counter 1 Low 250
TMOD 0x89 Timer/Counter Mode 248
TMR2CN 0xC8 Timer/Counter 2 Control 255
TMR2H 0xCD Timer/Counter 2 High 256
TMR2L 0xCC Timer/Counter 2 Low 256
TMR2RLH 0xCB Timer/Counter 2 Reload High 256
TMR2RLL 0xCA Timer/Counter 2 Reload Low 256
TMR3CN 0x91 Timer/Counter 3Control 261
TMR3H 0x95 Timer/Counter 3 High 262
TMR3L 0x94 Timer/Counter 3Low 262
TMR3RLH 0x93 Timer/Counter 3 Reload High 262
TMR3RLL 0x92 Timer/Counter 3 Reload Low 262
VDM0CN 0xFF
USB0ADR 0x96 USB0 Indirect Address Register 167
USB0DAT 0x97 USB0 Data Register 168
USB0XCN 0xD7 USB0 Transceiver Control 165
XBR0 0xE1 Port I/O Crossbar Control 0 152
XBR1 0xE2 Port I/O Crossbar Control 1 153
XBR2 0xE3 Port I/O Crossbar Control 2 153
All Other Addresses Reserved
VDD Monitor Control
103
84 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
9.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller . Reserved bit s
should not be set to logic
case the reset value of the bit will be logic
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys
tem function.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: DPL: Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
l. Future product versions may use these bits to implement new features in which
0, selecting the feature's default state. Detailed descriptions of
SFR Definition 9.1. DPL: Data Pointer Low Byte
00000000
0x82
-
SFR Definition 9.2. DPH: Data Pointer High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: DPH: Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed memory.
SFR Definition 9.3. SP: Stack Pointer
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–0: SP: Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented
before every PUSH operation. The SP register defaults to 0x07 after reset.
0x83
0x81
Rev. 0.5 85
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.4. PSW: Program Status Word
R/W R/W R/W R/W R/W R/W R/W R Reset Value
CY AC F0 RS1 RS0 OV F1 PARITY 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
Bit6: AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by a ll other arithmetic oper ations.
Bit5: F0: Use r F lag 0.
This is a bit-addressable, general purpose flag for use under software control.
Bits4–3: RS1–RS0: Register Bank Select.
These bits select which register bank is used during register accesses.
RS1 RS0 Register Bank Address
0 0 0 0x00 - 0x07
0 1 1 0x08 - 0x0F
1 0 2 0x10 - 0x17
1 1 3 0x18 - 0x1F
0xD0
Bit2: OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
Bit1: F1: Use r F lag 1.
This is a bit-addressable, general purpose flag for use under software control.
Bit0: PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd an d cleared if the
sum is even.
SFR Definition 9.5. ACC: Accumulator
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bits7–0: ACC: Accumulator.
This register is the accumulator for arithmetic operations.
0xE0
86 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.6. B: B Register
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bits7–0: B: B Register.
This register serves as a second accumulator for certain arithmetic operations.
9.3. Interrupt Handler
The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority
levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated inter
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid inter rupt condition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interru pt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an RETI
instruction, which returns program execution to the next instruction that would have been executed if the
interrupt request had not occurred. If interrupts are not en abled, the interr upt-pending fla g is ignored by the
hardware and program execution continues as normal. (The interrupt-pending flag is set to logic
less of the interrupt's enable/disable state.)
0xF0
1 regard-
-
-
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE-EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic
all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cle ared by the hardware and must be cle ared by sof twar e before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
1 before the individual interrupt enables are recogn ized. Setting th e EA bit to logic 0 disables
9.3.1. MCU Interrupt Sources and Vectors
The MCU supports multiple interrupt sources. Software can simulate an interrupt by setting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be generated and
the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU interrupt sources,
associated vector addresses, priority order and control bits are summarized in
to the datasheet section associated with a particular on-chip peripheral for information regarding valid
interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Table 9.4 on page 89. Refer
9.3.2. External Interrupts
The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (
or edge sensitive. The following table lists the possible configurations.
Section “21.1. Timer 0 and Timer 1” on page 243) select level
Rev. 0.5 87
C8051F340/1/2/3/4/5/6/7
IT0 IN0PL /INT0 Interrupt IT1 IN1PL /INT1 Interrupt
10Active low, edge sensitive 10Active low, edge sensitive
11Active high, edge sensitive 11Active high, edge sensitive
00Active low, level sensitive 00Active low, level sensitive
01Active high, level sensitive 01Active high, level sensitive
/INT0 and /INT1 are assigned to Port pins as de fined in the IT01CF register (see SFR Definition 9.13).
Note that /INT0 and /INT0 Port pin assignments are independent of any Crossbar assignments. /INT0 and
/INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin
via the Crossbar. To assign a Port pin only to /INT0 and/or /INT1, configure the Crossbar to skip the
selected pin(s). This is accomplished by setting the associated bit in register XBR0 (see
“15.1. Priority Crossbar Decoder” on page 149 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the /INT0 and /INT1 external
interrupts, respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corre
sponding interrupt-pending flag is automatically clear ed by th e hardware when the CPU vectors to the ISR.
When configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as
defined by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inac
tive. The external interrupt source must hold the input active until the interrupt request is recognized. It
must then deactivate the interrupt request before execution of the ISR completes or another interrupt
request will be generated.
Section
-
-
9.3.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP2) used to configure
its priority level. Low priority is the default. If two interrupts are reco gnized simult aneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in
Table 9.4.
9.3.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the in te rrupt occur s. Pending inter rupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 6
system clock cycles: 1
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interru pt. Th eref ore, the ma ximu m res pons e time for an int erru pt (wh en no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
20
system clock cycles: 1 clock cycle to detect the interrupt, 6 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 5
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see
Section “13.2. Accessing USB FIFO Sp ac e” on p ag e 118). Interrupt service latency will be increased for
interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the
standard interrupt service procedure (as descri bed above) and the amount of time the CPU is stalled.
clock cycle to detect the interrupt and 5 clock cycles to complete the LCALL to the
clock cycles to execute the LCALL to the ISR. If the CPU is
88 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
Table 9.4. Interrupt Summary
Interrupt Source
Reset 0x0000 Top None N/A N/A
External Interrupt 0 (/
INT0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (/
INT1)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4
Timer 2 Overflow 0x002B 5
SPI0 0x0033 6
SMB0 0x003B 7 SI (SMB0CN.0) Y N
USB0 0x0043 8 Special N N
ADC0 Window
Compare
ADC0 Conversion
Complete
Programmable Counter
Array
Comparator0 0x0063 12
Comparator1 0x006B 13
Timer 3 Overflow 0x0073 14
VBUS Level 0x007B 15 N/A N/A N/A
UART1 0x0083 16
Interrupt
Vector
0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
0x004B 9
0x0053 10 AD0INT (ADC0CN.5) Y N
0x005B 11
Priority
Order
Pending Flag
RI0 (SCON0.0)
TI0 (SCON0.1)
TF2H (TMR2CN.7)
TF2L (TMR2CN.6)
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
AD0WINT
(ADC0CN.3)
CF (PCA0CN.7)
CCFn (PCA0CN.n)
CP0FIF (CPT0CN.4)
CP0RIF (CPT0CN.5)
CP1FIF (CPT1CN.4)
CP1RIF (CPT1CN.5)
TF3H (TMR3CN.7)
TF3L (TMR3CN.6)
RI1 (SCON1.0)
TI1 (SCON1.1)
Enable
Flag
Cleared by HW?
Bit addressable?
Always
Enabled
Y N ES0 (IE.4) PS0 (IP.4)
Y N ET2 (IE.5) PT2 (IP.5)
Y N
Y N
Y N
N N
N N
N N
N N
ESPI0
(IE.6)
ESMB0
(EIE1.0)
EUSB0
(EIE1.1)
EWADC0
(EIE1.2)
EADC0
(EIE1.3)
EPCA0
(EIE1.4)
ECP0
(EIE1.5)
ECP1
(EIE1.6)
ET3
(EIE1.7)
EVBUS
(EIE2.0)
ES1
(EIE2.1)
Priority
Control
Always
Highest
PSPI0
(IP.6)
PSMB0
(EIP1.0)
PUSB0
(EIP1.1)
PWADC0
(EIP1.2)
PADC0
(EIP1.3)
PPCA0
(EIP1.4)
PCP0
(EIP1.5)
PCP1
(EIP1.6)
PT3
(EIP1.7)
PVBUS
(EIP2.0)
PS1
(EIP2.1)
9.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their pr iority le vel ar e descri bed below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrup t
conditions for the peripheral and the behavio r of its interrupt-p end ing flag (s) .
Rev. 0.5 89
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.7. IE: Interrupt Enable
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
EA ESPI0 ET2 ES0 ET1 EX1 ET0 EX0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: EA: Enable All Interrupts.
This bit globally enables/disables all interrupt s. It override s the individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Bit5: ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Bit4: ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Bit3: ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the T imer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Bit2: EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Bit1: ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the T imer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Bit0: EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
0xA8
90 Rev. 0.5
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.8. IP: Interrupt Priority
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- PSPI0 PT2 PS0 PT1 PX1 PT0 PX0 10000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable)
Bit7: UNUSED. Read = 1, Write = don't care.
Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
This bit sets the priority of the SPI0 interrupt.
0: SPI0 interrupt set to low priority level.
1: SPI0 interrupt set to high priority level.
Bit5: PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority level.
1: Timer 2 interrupts set to high priority level.
Bit4: PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority level.
1: UART0 interrupts set to high priority level.
Bit3: PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority level.
1: Timer 1 interrupts set to high priority level.
Bit2: PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority level.
1: External Interrupt 1 set to high priority level.
Bit1: PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority level.
1: Timer 0 interrupt set to high priority level.
Bit0: PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority level.
1: External Interrupt 0 set to high priority level.
0xB8
Rev. 0.5 91
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.9. EIE1: Extended Interrupt Enable 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
ET3 ECP1 ECP0 EPCA0 EADC0 EWADC0 EUSB0 ESMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Bit6: ECP1: Enable Comparator1 (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1RIF or CP1FIF flags.
Bit5: ECP0: Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF or CP0FIF flags.
Bit4: EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Bit3: EADC0: Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
Bit2: EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Bit1: EUSB0: Enable USB0 Interrupt.
This bit sets the masking of the USB0 interrupt.
0: Disable all USB0 interrupts.
1: Enable interrupt requests generated by USB0.
Bit0: ESMB0: Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
0xE6
92 Rev. 0.5
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SFR Definition 9.10. EIP1: Extended Interrupt Priority 1
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
PT3 PCP1 PCP0 PPCA0 PADC0 PWADC0 PUSB0 PSMB0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bit7: PT3: Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
Bit6: PCP1: Comparator1 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
Bit5: PCP0: Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
Bit4: PPCA0: Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
Bit3: PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
Bit2: PWADC0: ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
Bit1: PUSB0: USB0 Interrupt Priority Control.
This bit sets the priority of the USB0 interrupt.
0: USB0 interrupt set to low priority level.
1: USB0 interrupt set to high priority level.
Bit0: PSMB0: SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
0xF6
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SFR Definition 9.11. EIE2: Extended Interrupt Enable 2
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - ES1 EVBUS 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit1: ES1: Enable UART1 Interrupt.
This bit sets the masking of the UART1 interrupt.
0: Disable UART1 interrupt.
1: Enable UART1 interrupt.
Bit0: EVBUS: Enable VBUS Level Interrupt.
This bit sets the masking of the VBUS interr upt.
0: Disable all VBUS interrupts.
1: Enable interrupt requests generated by VBUS level sense.
0xE7
SFR Definition 9.12. EIP2: Extended Interrupt Priority 2
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
- - - - - - PS1 PVBUS 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit1: PS1: UART1 Interrupt Priority Control.
This bit sets the priority of the UART1 interrupt.
0: UART1 interrupt set to low priority level.
1: UART1 interrupts set to high priority level.
Bit0: PVBUS: VBUS Level Interrupt Priority Control.
This bit sets the priority of the VBUS interrupt.
0: VBUS interrupt set to low priority level.
1: VBUS interrupt set to high priority level.
0xF7
94 Rev. 0.5
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SFR Definition 9.13. IT01CF: INT0/INT1 Configuration
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xE4
Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7: IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is independent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN1SL2–0 /INT1 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
Bit3: IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
Bits2–0: INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is independent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configure d to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register P0SKIP).
IN0SL2–0 /INT0 Port Pin
000 P0.0
001 P0.1
010 P0.2
011 P0.3
100 P0.4
101 P0.5
110 P0.6
111 P0.7
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9.4. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter
rupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states;
the external oscillator is not affected). Since clocks are running in Idle mode, power consumption is depen
dent upon the system clock frequency and the number of peripherals left in active mode before entering
Idle. Stop mode consumes the least power. Figure 1.15 describes the Power Control Register (PCON)
used to control the CIP-51's power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished through system clock and individual peripheral
management. Each analog peripheral can be disabled when not in use and placed in low power mode.
Digital peripherals, such as timers or serial buses, draw little power when they are not in us e. Turning off
the oscillators lowers power consumption considerably; however a reset is required to restart the MCU.
The internal oscillator can be placed in Suspend mode (see Section “14. Oscillators” on page 135). In
Suspend mode, the internal oscillator is stopped until a non-idle USB event is detected, or the VBUS input
signal matches the polarity selected by the VBPOL bit in register REG0CN (
9.4.1. Idle Mode
SFR Definition 8.1).
-
-
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon
as the instruction that sets the bit completes execution. All internal registers and memory maintain their
original data. All analog and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU to resume
operation. The pending interrupt will be serviced and the next instruction to be executed after the return
from interrupt (RETI) will be the instruction immediately following the one that set the Idle Mode Select bit.
If Idle mode is terminated by an internal or external reset, the CIP-51 performs a normal reset sequence
and begins program execution at address 0x0000.
If enabled, the Watchdog Timer (WDT) will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This feature protects the system from an unintended per manent shutdown in the event
of an inadvertent write to the PCON register. If this behavior is not desired, the WDT may be disabled by
software prior to entering the I dle mode if the WDT was initially configured to allow this operation. This pro
vides the opportunity for additional power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake up the system. Refer to Section “11.6. PCA Watchdog
Timer Reset ” on page 104 for more information on the use and configuration of the WDT.
-
9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripherals are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be pu t to in ST OP mode for long er tha n the
MCD timeout of 100
96 Rev. 0.5
µsec.
C8051F340/1/2/3/4/5/6/7
SFR Definition 9.14. PCON: Power Control
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
GF5 GF4 GF3 GF2 GF1 GF0 STOP IDLE 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
These are general purpose flags for use under software control.
Bit1: STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
Bit0: IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
0x87
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NOTES:
98 Rev. 0.5
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10. Prefetch Engine
The C8051F340/1/2/3/4/5/6/7 family of devices incorporate a 2-byt e prefetch engine. Because the access
time of the FLASH memory is 40
engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at
a time by the prefetch engine, an d given to the CIP-51 processor core to execute. When running linear
code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full
speed. When a code branch occurs, the processor may be stalled for up to two clock cycles while the next
set of code bytes is retrieved from FLASH me mory. The FLRT bit (FLSCL.4) determines how many clock
cycles are used to read each set of two code bytes from FLASH. When operating from a system clock of
25
MHz or less, the FLRT bit should be set to ‘0’ so that the prefetch engine takes only one clock cycle for
each read. When operating with a system clock of greater than 25
should be set to ‘1’, so that each prefetch code read lasts for two clock cycles.
SFR Definition 10.1. PFE0CN: Prefetch Engine Control
R R R/W R R R R R/W Reset Value
PFEN FLBWE 00100000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ns, and the minimum instruction time is roughly 20 ns, the prefetch
MHz (up to 48 MHz), the FLRT bit
SFR Address: 0xAF
Bits 7–6: Unused. Read = 00b; Write = Don’t Care
Bit 5: PFEN: Prefetch Enable.
This bit enables the prefetch engine.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Bits 4–1: Unused. Read = 0000b; Write = Don’t Care
Bit 0: FLBWE: FLASH Block Write Enable.
This bit allows block writes to FLASH memory from software.
0: Each byte of a software FLASH write is written individually.
1: FLASH bytes are written in groups of two.
Rev. 0.5 99
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NOTES:
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