Siemens SDA9288X Datasheet

ICs for Consumer Electronics

Single Chip PIP System

SDA 9288X (A141)

PIP 2

Data Sheet 03.96

Edition 03.96

This edition was realized using the software system FrameMakerâ.

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

© Siemens AG 1996.

All Rights Reserved.

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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.

1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

SDA 9288X
Revision History:			Current Version: 03.96
Previous Version:
Page		Page	Subjects (major changes since last revision)
(in		(in new
previous		Version)
Version)
			25.1.1994:	Preliminary Specification V1.1
		22; 23; 24	25.1.1994:	warnings
		24	25.1.1994: additional bits VSIISQ, VSPISQ at subad. 07/08
		25	25.1.1994: additional bits DACONDE, DACONST at subad. 0D
		26	25.1.1994:	supply voltage range
		32	25.1.1994:	values DAC
		35	25.1.1994:	diagram
		43	25.1.1994: influence HSIDEL to VSIDEL adjustment
		19; 21	19.4.1994: additional note PLL switch READ27
		43	19.4.1994: timing of ADC clamping
		15	20.6.1994:	warning subaddr. 02
		20; 25	20.6.1994: additional bit SELDOWN at subaddr. 0B
		23	20.6.1994: value VOL outputs SEL, SELD added
		All	18.7.1994:	pages no. shifted
		10; 15; 18	18.7.1994: improvement: additional bits D5, D6 (CLPS; CLPFIX)
				at subaddr. 06
		15; 19	18.7.1994: bit D0 of subaddress 0D deleted
		17	18.7.1994: new: examples for adjustment of frame colors
		17	18.7.1994: text bits IMOD, PMOD
		22	18.7.1994: additional remark at subaddress 02
		25	18.7.1994: clamping current. Additional values
		28; 29	18.7.1994: application board layout and application circuit new
		30	18.7.1994: timing of ADC clamping changed
		32	18.7.1994:	values DAC output current

SDA 9288X

Table of Contents		Page
1	General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 5
1.1	Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 6
1.2	Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 8
1.3	Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 9
1.4	Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 11
2	System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 12
2.1	AD Conversion, Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 12
2.2	Input Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 13
2.3	PIP Field Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 14
2.4	Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 16
2.4.1	Matrix Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
2.4.2	Frame Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
2.4.3	Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 17
2.5	DA Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
2.6	PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
2.7	I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
2.7.1	I2C Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
2.7.2	I2C Bus Receiver Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 18
2.7.3	I2C Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 19
3	Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
3.1	Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 25
3.2	Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 26
3.3	Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 31
4	Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 34
4.1	Output Current of DA Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 34
4.2	Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 35
4.2.1	Reference Voltage Generation for ADC . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 35
4.2.2	Adjustment of YDEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 38
4.2.3	Three Level Interface (3-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 39
4.2.4	Application Board Layout Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 40
4.2.5	Application Circuit (R, G, B-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 41
4.3	Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 42
4.3.1	Timing of ADC Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 42
4.3.2	Phase Relation of Sync Pulses at Frame Mode . . . . . . . . . . . . . . . . . . . . .	. 43
5	Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 45

I2C Bus

Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.

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SDA 9288X

1 General Description

The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of a video signal (inset channel) for the purpose of combining it with another video signal (parent channel). The easy implementation of the IC in an existing system needs only a few additional external components. There is a great variety of application facilities in professional and consumer products (TV sets, supervising monitors, multi-media, …)

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Single Chip PIP System

SDA 9288X

Data Sheet

MOS

1.1Features

•Single chip solution

Clamping, AD conversion, filtering, field memory,

RGB matrix, DA-conversion and clock generation integrated on one chip

	•	2 picture sizes
		1/9 or 1/16 of normal size	P-DSO-32-2
	•	High resolution display

13.5 MHz/27 MHz display clock frequency

212 luminance and 53 chrominance pixels per inset line for picture size 1/9 6-bit amplitude resolution for each incoming signal component

Field and frame mode display Horizontal and vertical filtering

Special antialias filtering for the luminance signal

•16:9 compatibility

Operation in 4:3 and 16:9 sets

4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively

•Analog inputs

Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y)

•Analog outputs

Y, + (B-Y), + (R-Y) or Y, – (B-Y), – (R-Y) or RGB

3 RGB matrices: EBU, NTSC (Japan), NTSC (USA)

•Free programmable position of inset picture

Steps of 1 pixel and 1 line

All PIP and POP positions are possible

•Programmable framing

4096 frame colors Variable frame width

Type	Ordering Code	Package
SDA 9288X	on request	P-DSO-32-2

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•Freeze picture

•I2C Bus control

•Threefold PIP/POP facility

Three different I2C-addresses (pin-programmable) Tri-State outputs

•Numerical PLL circuit for high stability clock generation

•No necessity of PAL/SECAM delay lines

(using suitable color decoders i.e. TDA 8310)

•Multistandard applications

625 lines/525 lines standard (inset and parent channel)

Scan conversion systems as flickerfree display systems (parent channel) HDTV (parent channel)

•P-DSO-32-2 package/350 mil (SMD)

•5 V supply voltage

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SDA 9288X

1.2Pin Configuration

(top view)

P-DSO-32-2

Figure 1

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SDA 9288X

1.3Pin Definitions and Functions

Pin No.	Symbol	Function1)	Descriptions
1	VSSA1	S	Analog voltage supply (VSS) for ADC
2	VREFL	I	Lower reference voltage for AD converters
3	XIN	I	Quartz oscillator (input) or quartz clock
			(from another PIP IC) or line locked clock
			(27 MHz, from a digital parent channel)
4	XQ	Q	Quartz oscillator (output)
5	VDD	S	Digital voltage supply (VDD)
6	VSSA2	S	Analog voltage supply (VSS) for DAC and PLL
7	OUT1	Q/ana	Analog output: chrominance signal
			+ (R-Y) or – (R-Y) or R
8	OUT2	Q/ana	Analog output: luminance signal Y or G
9	OUT3	Q/ana	Analog output: chrominance signal
			+ (B-Y) or – (B-Y) or B
10	VDDA2	S	Analog voltage supply (VDD) for DAC and PLL
11	IREF	Q/ana	Reference current for DA-converters
12	SEL	Q	Single frequency fast PIP switching output (tristate)
13	SELD	Q	Double frequency fast PIP switching output (tristate)
14	VBB	S	Capacitor connection for smoothing internally
			generated substrate bias
15	ADR	I3-L	I2C Bus address control
16,27	VSS	S	Digital voltage supply (VSS)
17	VP	I	Multifrequency vertical sync for parent channel
18	HP/SCP	I	Multifrequency horizontal sync for parent channel
19	VPD/VI	I	Double frequency vertical sync for parent channel
			or vertical sync input for inset channel
20	HPD/SCI	I	Double frequency horizontal sync for parent channel
			or horizontal sync input for inset channel
21	SDA	I/Q	I2C Bus data
22	SCL	I	I2C Bus clock
23	SW1	Q3-L	I2C Bus controlled output1
24	SW2	Q3-L	I2C Bus controlled output2
1) I : input, Q : output, ana : analog, TTL : digital (TTL), 3-L : 3-level, S : supply voltage
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SDA 9288X

1.3Pin Definitions and Functions (cont’d)

Pin No.	Symbol	Function1)	Descriptions
25	HVI	I3-L	Special 3-level hor. and vert. sync signal for inset
			channel
26	SYS	I3-L	Input for standard depending internal switching
			(LOW (L) = PAL, MID (M) = NTSC,
			HIGH (H) = SECAM)
28	YIN	I/ana	Analog input: luminance signal Y
29	VDDA1	S	Analog voltage supply (VDD) for ADC
30	UIN	I/ana	Analog input: chrominance signal + (B-Y) or – (B-Y)
31	VREFH	I	Upper reference voltage for AD converters
32	VIN	I/ana	Analog input: chrominance signal + (R-Y) or – (R-Y)

I : input, Q : output, ana : analog, TTL : digital (TTL), 3-L : 3-level, S : supply voltage

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1.4Functional Block Diagram

Figure 2

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2 System Description

2.1AD Conversion, Inset Synchronization

The inset video signal is fed to the SDA 9288X A141 as analog luminance and chrominance components1). The polarity of the chrominance signals is programmable. After clamping the video components are AD-converted with an amplitude resolution of 6 bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375 MHz clock for the chrominance signals.

For the adaption to different application the clamp timing for the analog inputs can be chosen (CLPS; CLPFIX). Setting this bits to ‘1’ can be useful for non-standard input signals.

For inset synchronization it is possible to feed either a special 3-level signal via pin HVI (detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL compatible levels by a simple external circuit. Centering of the displayed picture area is possible by a programmable delay for the horizontal synchronization signal (HSIDEL).

The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock and the AD converter clocks are derived from the parent horizontal synchronization pulse (see chapter 2.6) or from the quartz frequency converted by a factor of 4/3.

Delay differences between luminance and chrominance signals at the input of the IC caused by chroma decoding are compensated by a programmable luminance delay line (YDEL) of about – 290 ns … 740 ns (at decimation input; see Application Information).

By analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. For applications with fixed line standard (only 625 lines or 525 lines) the automatic detection can be switched off.

The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a correct detection of the field number is possible, an important condition for frame mode display.

Note: The adjustment of VSIDEL is influenced by HSIDEL (see chapter 4.3), vertical synchronization via pin HVI causes an additional internal delay for the vertical sync pulse of about 16 μs.

1) To improve the signal-to-noise ratio the amplitude of the input signals should be as large as possible.

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2.2Input Signal Processing

This stage performs the decimation of the inset signal by horizontal and vertical filtering and sub-sampling. A special antialias filter improves the frequency response of the luminance channel. It is optimized for the use of the horizontal decimation factor 3:1.

A window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. For HSIDEL = ‘0’ the decimation window is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse. For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines standard decimation starts in the 26th video line.

The following filters are implemented:

Horizontal Decimation	Component	Filter
3:1	Luminance	1	+ z– 1	+ z– 2
3:1	Chrominance	1	+ 2 × z– 1 + z– 2
4:1	Luminance	1	+ z– 1	+ z– 2+ z– 3
4:1	Chrominance	1	+ z– 1	+ z– 2+ z– 3

Vertical Decimation	Component	Filter
3:1	Luminance	1	+ z– L + z– 2L
3:1	Chrominance	1	+ 2 × z– L + z– 2L
4:1	Luminance	1	+ z– L + z– 2L+ z– 3L
4:1	Chrominance	1	+ z– L + z– 2L+ z– 3L

z = ejωT,T = 1/13.5 MHz for luminance T = 1/3.375 MHz for chrominance L = samples per line for luminance respectively chrominance

The realized chrominance filtering allows omitting the color decoder delay line for PAL and SECAM demodulation if the color decoder supplies the same output voltages independent of the kind of operation. In case of SECAM signals an amplification of the chrominance signals by a factor of 2 is necessary because just every second line a signal is present. This chrominance amplification is programmable via pin SYS or I2C Bus (AMSEC).

The horizontal and vertical decimation factors are free programmable (DECHOR, DECVER). Using different decimations horizontal and vertical 16:9 applications become realizable:

DECHOR = ‘1’, DECVER = ‘0’: picture size 1/9 for 4:3 inset signals on 16:9 displays

DECHOR = ‘0’, DECVER = ‘1’: picture size 1/16 for 16:9 inset signals on 4:3 displays

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2.3PIP Field Memory

The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812 bits. The picture size depends on the horizontal and vertical decimation factors.

Horizontal Decimation		PIP PIXELS per Line
	Y	(B-Y)		(R-Y)
3:1	212	53		53
4:1	160	40		40
Vertical Decimation	Line Standard		PIP Lines
3:1	625		88
3:1	525		76
4:1	625		66
4:1	525		57

In field mode display just every second inset field is written into the memory, in frame mode display the memory is continuously written. Data are written with the lower inset clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz). Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems. For progressive scan conversion systems and HDTV displays a line doubling mode is available (LINEDBL). Every line of the inset picture is read twice.

Memory writing can be stopped by program (FREEZE), a freeze picture display results (one field).

Having no scan conversion and the same line numbers in inset and parent channel (625 lines or 525 lines both) frame mode display is possible. The result is a higher vertical and time resolution because of displaying every incoming field. For this purpose the standards are internally analysed and activating of frame mode display is blocked automatically when the described restrictions are not fulfilled.

As in the inset channel a field number detection is carried out for the parent channel. Depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter.

The display position of the inset picture is free programmable (POSHOR, POSVER). The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz) after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this position the picture can be moved over the whole display area. Even POP-positions (Picture Outside Picture) at 16:9 applications are possible.

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