SDA9189X
ICs for Consumer Electronics
Quarter PIP Processor
SDA 9189X (A123 / A132)
4PIP
Data Sheet 03.96
Edition 03.96
This edition was realized using the software
system FrameMaker
.
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
Siemens AG 1996.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed
for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For information on the types in question please
contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to
you. We can also help you – get in touch with
your nearest sales office. By agreement we
will take packing material back, if it is sorted.
You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept,
we shall have to invoice you for any costs incurred.
Components used in life-support devices
or systems must be expressly authorized
for such purpose!
Critical components
Group of Siemens AG, may only be used in
life-support devices or systems
1
of the Semiconductor
2
with the express written approval of the Semiconductor
Group of Siemens AG.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is
reasonable to assume that the health of
the user may be endangered.
SDA 9189X
Revision History: Current Version: 03.96
Previous Version:
Page
(in previous
Version)
Page
(in new
Version)
15 26.01.1994: not allowed display areas, display position
30 26.01.1994: character ‘m’ instead of ‘%’
32 26.01.1994: bit D6 of register 0F inverted
36 26.01.1994: adjustment values VSIDEL
38 26.01.1994: DA converter
30 08.04.1994: character ‘&’ instead of ‘!’
35; 38 08.04.1994: text subaddress 06 and 0F
38 08.04.1994: output voltage ANACON
41 08.04.1994: supply voltage range
24 20.09.1994: examples for the adjustment of frame colors
32; 36 20.09.1994: new I2C bits VSIISQ and VSPISQ
33 20.09.1994: notes at subaddress 00; bits D1 and D3
Subjects (major changes since last revision)
26.01.1994: Target Specification
34 20.09.1994: note & warning at subaddress 02
35 20.09.1994: warning at subaddress 06
36 20.09.1994: warning at subaddress 07
38 20.09.1994: elimination of bit d6 of subaddress 0F
41 20.09.1994: output voltage
43 20.09.1994: remark for series resistance
46 20.09.1994: values supply current
47 20.09.1994: values DAC current
49 20.09.1994: new diagram
51; 52 20.09.1994: new application circuit and layout proposal
SDA 9189X
Table of Contents Page
1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Input Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Decimation Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 PIP Field Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 Picture Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.2 Memory Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.3 Memory Reading and Synchronization to Parent Channel . . . . . . . . . . . . . 22
2.4 Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 Display Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 Line Standard of the PIP Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.3 Interpolation of the Chrominance Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.4.4 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.5 Full Screen Background Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.6 Filling PIP Picture with Color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.7 Wipe-In/Wipe-Out Facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.8 Output Formats and RGB Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4.9 Matrix Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.10 Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.11 Blanking Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4.12 Pedestal for the Chrominance Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5.1 Analog Video Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5.2 Analog Control Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6 On-Screen Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.1 Display Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.2 Character Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.6.3 Character and Character Background Luminance . . . . . . . . . . . . . . . . . . . . 28
2.6.4 Character Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.7 Numerical PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.8 I
2.8.1 I
2.8.2 I
2.8.3 I
2
C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
C Bus Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
C Bus Receiver Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
C Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Semiconductor Group 4 03.96
SDA 9189X
Table of Contents Page
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2 Operational Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.1 Output Current of DA Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.2 Application Board Layout Proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.1 Phase Relation of Sync Pulses at Frame Mode . . . . . . . . . . . . . . . . . . . . . . 52
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
I2C Bus
2
Purchase of Siemens I
to use the components in the I
C components conveys the license under the Philips I2C patent
2
C system provided the system conforms to the I2C
specifications defined by Philips.
Semiconductor Group 5 03.96
SDA 9189X
1 General Description
The Picture Insertion Processor SDA 9189X generates a reduced size picture of an inset
video channel for the purpose of combining it with another video signal (parent channel).
The easy implementation of the IC into an existing system needs only a few additional
external components. There is a great variety of application facilities in consumer and
professional products (TV sets, VCRs, supervising monitors, multi-media, etc.).
Semiconductor Group 6 03.96
Quarter PIP Processor SDA 9189X
Data Sheet
1.1 Features
• High system integration
Filtering, field memory, RGB-matrix,
DA-Conversion, clock generation, and control
circuits integrated on one chip
• 4 picture sizes
1/4th, 1/9th, 1/16th, or 1/36th of normal size
• High resolution display
13.5 MHz/27 MHz display clock frequency
288 luminance and 72 chrominance pixels per inset line for picture size 1/4
6-bit amplitude resolution for each incoming signal component
Frame mode display in single-PIP modes
Horizontal and vertical filtering
Special antialias filtering for the luminance signal
P-DSO-32-2
• Single and multi PIP display
Up to 9 pictures of 1/36th size (8 still and 1 moving)
Up to 4 pictures of 1/16th size (3 still and 1 moving)
Up to 2 pictures of 1/9th size (1 still and 1 moving)
Up to 3 pictures of 1/9th size (2 still and 1 moving) as POP display in 16:9 TV sets
(In multi-PIP modes only field mode display possible)
• Multistandard applications
Automatic recognition of 625 lines/525 lines standard (inset and parent channel)
Scan conversion systems as flickerfree display systems (parent channel)
• HDTV (parent channel)
• 16:9 compatibility
Operation in 4:3 and 16:9 TV sets
4:3 inset signals on 16:9 displays (picture size 1/4 and 1/9)
16:9 inset signals on 4:3 displays (picture size 1/9 and 1/16)
Type Ordering Code Package
SDA 9189X Q67100-H5148 P-DSO-32-2
Semiconductor Group 7 03.96
SDA 9189X
• Digital inputs
Y, + (B-Y), + (R-Y)
Compatible with Triple ADC SDA 9187-2X
• Analog outputs
Y, + (B-Y), + (B-Y) or Y, – (B-Y), – (B-Y) or RGB
3 RGB-matrices: EBU, NTSC (Japan), NTSC (USA)
• Digital to analog converter output e.g. for color decoder adjustment
6-bit resolution
• Freely programmable position of inset picture
Steps of 1 pixel and 1 line
All PIP and POP positions are possible inside the standard display area
• Programmable framing
4096 frame colors
Variable frame width
• Full screen background insertion
64 background colors or transparent display (parent picture seen)
• Wipe-in/Wipe-out facility
Start and end of insertion is the lower right PIP corner
4 periods programmable
• Freeze picture
• I2C Bus control
• Up to three ICs in one application
2
Three different I
C Bus addresses
Up to 3 moving pictures using 3 ICs
Up to 27 pictures of 1/36th size
• On-screen display of channel index
64 characters programmable (alphanumeric and special symbols)
5 characters displayed in every PIP picture
4 different character luminance values (B-Y = R-Y = ‘0’)
4 background luminance values (B-Y = R-Y = ‘0’) or transparent mode
(inset picture seen)
• Numerical display PLL circuit for high stability clock generation
• No necessity of PAL/SECAM delay lines when using suitable color decoders
• P-DSO-32 package/350 mil (SMD)
• 5 V supply voltage
Semiconductor Group 8 03.96
1.2 Pin Configuration
(top view)
SDA 9189X
P-DSO-32-2
Figure 1
Semiconductor Group 9 03.96
1.3 Pin Definitions and Functions
1)
Pin No. Symbol Function
Descriptions
1 VSI I/TTL Inset vertical sync input
2 XIN I PLL quartz oscillator input
3 XQ Q PLL quartz oscillator output
SDA 9189X
4 ADR I
5
6
7
V
V
V
REF
DDA
SS
3-L
I/ana DACs reference voltage
S DACs and PLL positive voltage supply
S Digital ground
I2C address
8 OUT1 Q/ana Analog output R or + (R-Y) or – (R-Y)
9 OUT2 Q/ana Analog output G or Y
10 OUT3 Q/ana Analog output B or + (B-Y) or – (B-Y)
11 ANACON Q/ana Analog output (e.g. color decoder adjustment)
12
13
V
V
SSA
DD
S DACs and PLL ground
S Digital positive voltage supply
14 SEL Q/var Signals OUT1 - OUT3 valid
15 HSP I/TTL Parent horizontal sync input
16 VSP I/TTL Parent vertical sync input
17 SDA IQ/TTL I
18 SCL I/TTL I
2
C data input/output
2
C clock
19
V
SS
S Digital ground
20 LL3I I/TTL Line locked clock inset picture
21 UVIN0 I/TTL Digital UV input data
22 UVIN1 I/TTL Digital UV input data
23 UVIN2 I/TTL Digital UV input data
24 UVIN3 I/TTL Digital UV input data
1)
S: supply, I: input, Q: output, TTL: digital (TTL), ana: analog, 3-L: 3 level signal,
var: variable configuration of output stage (open source, open drain, TTL)
Semiconductor Group 10 03.96
1.3 Pin Definitions and Functions (cont’d)
1)
Pin No. Symbol Function
Descriptions
25 YIN0 I/TTL Digital Y input data
26 YIN1 I/TTL Digital Y input data
27 YIN2 I/TTL Digital Y input data
28 YIN3 I/TTL Digital Y input data
29 YIN4 I/TTL Digital Y input data
30 YIN5 I/TTL Digital Y input data
SDA 9189X
31
V
DD
S Digital positive voltage supply
32 HSI I/TTL Inset horizontal sync input
1)
S: supply, I: input, Q: output, TTL: digital (TTL), ana: analog, 3-L: 3 level signal,
var: variable configuration of output stage (open source, open drain, TTL)
Semiconductor Group 11 03.96
1.4 Functional Block Diagram
SDA 9189X
Figure 2
Semiconductor Group 12 03.96
SDA 9189X
2 System Description
2.1 Display Modes
8 single- and 10 multi-PIP display modes are available. Decimation, memory controlling,
framing and on-screen display insertion depend on the selected display mode
(PIPMOD).
In the multi-PIP modes the complete inset picture can contain up to 9 partial pictures
(see diagrams below). One of the partial pictures shows a moving picture, whereas the
others show still pictures. The partial picture that has to be written is addressed via
2
C Bus. The addresses (WRPOS) for the individual pictures are shown in the diagrams.
I
The same addresses serve to choose the position of the moving picture. The multi-PIP
modes allow tuner scanning.
Four display modes are provided for applications with 16:9 inset signals or displays
(see table 1). The single-PIP display modes 15 and 18 can be used to display 4:3 inset
signals on 16:9 displays. To show 16:9 inset signals on 4:3 displays the single-PIP
display modes 16 and 19 have been added. By means of multi-PIP display mode 17
a POP picture on a 16:9 display can be created.
If a display mode is chosen that is not realized (modes 9, 12, and 20 to 31), the
PIP insertion is switched off automatically (PIPON = ‘0’).
Table 1
Display Mode (PIPMOD) Picture Size, Picture Configuration
0 (00000) 1 × 1/4
1 (00001) 1 × 1/9
2 (00010) 1 × 1/16
3 (00011) 1 × 1/36
4 (00100) 4 × 1/16, 2 rows of 2 pictures
5 (00101) 4 × 1/16, side by side
6 (00110) 4 × 1/16, one upon another
7 (00111) 9 × 1/36, 3 rows of 3 pictures
8 (01000) 2 × 1/9, side by side
9 (01001) Not realized (PIPON = ‘0’)
10 (01010) 8 × 1/36, 2 rows of 4 pictures
11 (01011) 2 × 1/9, one upon another
12 (01100) Not realized (PIPON = ‘0’)
13 (01101) 8 × 1/36, 2 columns of 4 pictures one upon another
Semiconductor Group 13 03.96
SDA 9189X
Table 1(cont’d)
Display Mode (PIPMOD) Picture Size, Picture Configuration
14 (01110) 4 × 1/36, 2 rows of 2 pictures
15 (01111) 1 × 1/9, 4:3 inset signal on 16:9 display horizontal
decimation 4:1, vertical decimation 3:1
16 (10000) 1 × 1/16, 16:9 inset signal on 4:3 display horizontal
decimation 3:1, vertical decimation 4:1
17 (10001) 3 × 1/9, 4:3 inset signals on 16:9 display horizontal
decimation 4:1, vertical decimation 3:1 one
upon another
18 (10010) 1 × 1/4, 4:3 inset signal on 16:9 display horizontal
decimation 3:1, vertical decimation 2:1
19 (10011) 1 × 1/9, 16:9 inset signal on 4:3 display horizontal
decimation 2:1, vertical decimation 3:1
20 (10100)
:
Not realized (PIPON = ‘0’)
31 (11111)
The following diagrams show the various display modes. The figures on top of the
rectangles give the width of the complete inset picture in pixels whereas the figures on
the right specify its height by the number of lines. The values for the multi-PIP display
modes are obtained by adding the widths and heights of the partial pictures. The sizes
of the partial pictures correspond to the sizes of the inset pictures of the single-PIP
modes (see below).
Semiconductor Group 14 03.96
288
SDA 9189X
192
Mode 0
144
Mode 2
0
126
(102)
0
84
(68)
Mode 1
96
0
63
(51)
0
42
(34)
Mode 3
288
Mode 4
Mode 5
Figure 3
01
126
(102)
23
576
0123
63
(51)
Semiconductor Group 15 03.96
SDA 9189X
144
0
1
2
3
Mode 6
252
(204)
Mode 8
288
012
345
126
(102)
678
Mode 7
384
01
64
(68)
384
0123
4567
Mode 10
192
01
23
168
(136)
45
The display modes 9 and 12 are not realized.
For a PIP display line standard of 525 lines
67
the values in parenthesis are valid.
84
(68)
192
0
168
(136)
1
Mode 11
Mode 13
Figure 4
Semiconductor Group 16 03.96
SDA 9189X
192
01
23
Mode 14
144
0
84
(68)
144
0
Mode 15
192
0
84
(68)
126
(102)
Mode 16
192
0
63
(51)
Mode 17
Figure 5
1
2
252
(204)
Mode 18
Mode 19
288
0
84
(68)
Semiconductor Group 17 03.96
Loading...