Siemens SDA5650, SDA5650X Datasheet

ICs for Consumer Electronics

VPS / PDC-plus Decoder

SDA 5650/X

Data Sheet 02.97

SDA 5650/X Revision History: Current Version: 02.97

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Edition 02.97



This edition was realized using the software system FrameMaker

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

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with the express

SDA 5650/X

Table of Contents Page

1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 I

2.2.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.3 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.4 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Order of Data Output on the I

2.4 Order of Data Output on the I

2.5 Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

C Bus and Bit Allocation

of PDC/VPS Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

C Bus and Bit Allocation

for the Header Time Mode (MAB=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 PDC/VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Control Register Write (I

5.2 Data Register Read (I

C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 Position of Teletext and VPS Data Lines within

the Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.5 Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . . 33

5.6 BDSP 8/30 Format 1 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.7 Structure of the Teletext Data Packet 8/30 Format 2 . . . . . . . . . . . . . . . . . . 35

5.8 BDSP 8/30 Format 2 Bit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.9 Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 38

6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components

in the I

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C system provided the system conforms to the I2C specifications defined by Philips.

VPS / PDC-plus Decoder SDA 5650/X

CMOS

1 General Description

The PDC plus SDA 5650 decoder chip receives all VPS and 8/30 Format 1 and 2 data together with the teletext header information for easy identification of broadcast transmitter. The SDA 5650 includes a storage capacity of 16 bytes which can be used in different ways depending on selected modes.

P-DIP-14-1

1.1 Features

• Single chip receiver for PDC data for

Broadcast Data Service Packet (BDSP 8/30/2

according to CCIR teletext system B.) VPS Data in dedicated line no. 16 of the vertical blanking interval (VBI)

• Reception of BDSP packet 8/30/1

Unified Date and Time (UDT) Network indentification code (NIC) Short program label (SPL)

• Reception of teletext header row

Bytes no. 14 - 45 containing date, clock time and identification

• On chip data slicer

• Low external component count

• I

C-Bus interface

Communication with external microcontroller

• PDC/VPS operation mode selectable via I

C-Bus register

• Pin and software compatible to PDC/VPS decoder SDA 5649

• 5 V supply voltage

• Video input signal level: 0.7 Vpp to 2.0 Vpp

• Technology: CMOS

• P-DIP-14-1 and P-DSO-20-1 package

P-DSO-20-1

Type Ordering Code Package

SDA 5650 Q67100-H5164 P-DIP-14-1 SDA 5650X Q67106-H5163 P-DSO-20-1 (SMD)

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1.2 Pin Configurations

P-DIP-14-1 P-DSO-20-1

SDA 5650/X

Figure 1

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1.3 Pin Description

Pin No. Symbol Function

P-DIP-14-1 P-DSO-20-1

SDA 5650/X

1 V

1 2

V V

SS SSA SSD

Ground (0 V) Analog ground (0 V) Digital ground (0 V)

3, 8, 13, 18 N.C. Not connected 2 4 SCL Serial clock input of I 3 5 SDA Serial data input of I 4 6 CS0 Chip select input determining the I

/ 21H, when pulled low

/ 23H, when pulled high.

C Bus.

C-Bus addresses:

5 7 VCS Video Composite Sync output from sync slicer used for

PLL based clock generation.

6 9 DAVN Data available output active low, when VPS data is

received.

7 10 EHB Output signaling the presence of the first field active

high.

8 11 TI Test input; activates test mode when pulled high.

Connect to ground for operating mode.

9 12 PD1 Phase detector/charge pump output of data PLL

(DAPLL).

10 14 PD2/

Connector of the loop filter for the SYSPLL.

VCO2

11 15 VCO1 Input to the voltage controlled oscillator #1 of the

DAPLL.

12 16

REF

Reference current input for the on-chip analog circuit. 13 17 CVBS Composite video signal input. 14

V V

DD DDD

Positive supply voltage (+ 5 V nom.).

Positive supply voltage for the digital circuits

(+ 5 V nom.).

DDA

Positive supply voltage for the analog circuits

(+ 5 V nom.).

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Block Diagram

SDA 5650/X

Figure 2

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SDA 5650/X

2 System Description

2.1 Functions

Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels.

The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal.

The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (DEW) in PDC mode.

The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL’s) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequencies are 10 MHz and

13.875 MHz for VPS mode and PDC mode, respectively. All signals necessary for the control of sync and data slicing as well as for the data

acquisition are generated by the Timing block. The SDA 5650 can be operated in three different modes: Depending on the selected

operating mode, either teletext lines carrying 8/30 packages, the dedicated TV line no. 16 (VPS) or the teletext header bytes 38-45, 30-37, 22-29 and 14-21 are acquired.

In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the transfer register to the I

C Bus

is signalled by the DAVN output going low.

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SDA 5650/X

In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to the I as well.

In TTX header mode A bytes 38-45 and 30-37 are accessed in this order. This assures software compatibility to the SDA 5649. In mode B bytes 22-29 and 14-21 are accessed in this order.

In all three operating modes data are updated when a new data line has been received, provided that the chip is not accessed via the I2C Bus at the same time.

A micro controller can read the stored bytes via the I However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the PDC decoder is being accessed via the I

Note: In order to achieve maximum system performance it is recommended to start the

SDA 5650 in VPS mode (state after power on) and read the register to check whether line 16 is received. After reception of VPS data inline 16 the SDA 5650 can be switched to 8/30 mode and waiting for packet 8/30 data. Since VPS data in line 16 is transmitted every frame and PDC data in packet 8/30 is transmitted nearly every second the recognition of both VPS and 8/30 packets can be done within PDC-system constraints (about 1 sec).

C Bus. That transfer is signalled by a H/L transition of the DAVN output,

C-Bus interface at any time.

C Bus.

2.2 I

C Bus

2.2.1 General Information

The I

C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i. e., both reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i. e., both SDA and SCL lines are in a high state. As a general rule for the I

C Bus, the SDA line changes state only when the SCL line is low. The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used:

START: Start Condition generated by master AS: Acknowledge by slave AM: Acknowledge by master NAM: No Acknowledge by master STOP: Stop condition generated by master

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SDA 5650/X

2.2.2 Chip Address

There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table:

CS0 Input Write Mode Read Mode

Low 20 (hex) 21 (hex) High 22 (hex) 23 (hex)

2.2.3 Write Mode

For writing to the PDC decoder, the following format has to be used:

Start Chipaddress and Write Mode AS Byte to set Control Register AS Stop

Description of Data Transfer (Write Mode)

Step1: In order to start a data transfer the master generates a Start Condition on the

bus by pulling the SDA line low while the SCL line is held high.

Step 2: The bus master puts the chip address on the SDA line during the next eight

SCL pulses.

Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave

can generate an acknowledge (AS) by pulling the SDA line to a low level. Step 4: The controller transmits the data byte to set the Control register Step 5: The slave acknowledges the reception of the byte. Step 6: The master concludes the data communication by generating a Stop

Condition.

The write mode is used to set the I

C-Bus control register which determines the

operating mode:

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SDA 5650/X

Control Register:

Bit Number: 7 6 5 43210

T4 T3 T2 T1 MAB HDT PDC/

VPS

FOR1/ FOR2

Default: All bits are set to 0 on power-up. Bits 4 through 7 are used for test purposes and must not be changed for normal

operation by user software!

Bit 0: determines, which kind of data is accessed via the I

C Bus when PDC

mode is active:

Value

01 BDSP 8/ 30/ 2 data accessible BDSP 8/ 30/ 1 or header row

data accessible (refer to description of Bit 2)

Bit 1: determines the operating mode:

Value

01 VPS mode active PDC mode active

Bit 2: determines whether BDSP 8/30/1-data or header row data is

accessible:

Value

01 BDSP 8/30/1 data accessible Bytes of teletext header in mode A or B

(see Bit 3)

Bit 3: determines mode of teletext header access:

Value

01 Mode A: header bytes in order 38-45,

30-37

Mode B: header bytes in order 22-29, 14-21

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SDA 5650/X

2.2.4 Read Mode

For reading from the PDC decoder, the following format has to be used

Start Chipaddress Read Mode AS 1st Byte AM ..... Last Byte NAM Stop

The contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to the table Order of Data Output on the I operating mode.

Description of Data Transfer (Read Mode)

Step1: To start a data transfer the master generates a Start Condition on the bus by

pulling the SDA line low while the SCL line is held high. The byte address

counter in the decoder is reset and points to the first byte to be output. Step 2: The bus master puts the chip address on the SDA line during the next eight

SCL pulses.

C Bus and...) depending on the selected

Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave

can generate an acknowledge (AS) by pulling the SDA line to a low level. At

this moment, the slave switches to transmitting mode. Step 4: During the next eight clock pulses the slave puts the addressed data byte

onto the SDA line. Step 5: The reception of the byte is acknowledged by the master device which, in

turn, pulls down the SDA line during the next SCL clock pulse. By

acknowledging a byte, the master prompts the slave to increment its internal

address counter and to provide the output of the next data byte. Step 6: Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have

been read. Step 7: The last byte is output by the slave since it will not be acknowledged by the

master. Step 8: To conclude the read operation, the master doesn’t acknowledge the last byte

to be received. A No Acknowledge by the master (NAM) causes the slave to

switch from transmitting to receiving mode. Note that the master can

prematurely cease any reading operation by not acknowledging a byte. Step 9: The master gains control over the SDA line and concludes the data transfer

by generating a Stop Condition on the bus, i. e., by producing a low/high

transition on the SDA line while the SCL line is in a high state. With the SDA

and the SCL lines being both in a high state, the I

C Bus is free and ready for

another data transfer to be started.

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SDA 5650/X

2.3 Order of Data Output on the I2C Bus and Bit Allocation of PDC/VPS

Operating Modes

C Bus PDC Packet 8/30 VPS Mode

Format 1 Format 2

Byte 1 bit 7

byte 15 bit 0 6 5 4 3 2 1 0

byte 16 bit 0 1 2 3 4

byte 17 bit 0 5 6 7

byte 11 bit 0 1 2 3

1 2 3

4 1 2 3

Byte 2 bit 7

Byte 3 bit 7

Byte 4 bit 7

byte 16 bit 0 6 5 4 3 2 1 0

1 2 3 4 5 6 7

byte 17 bit 0 6 5 4 3 2 1 0

1 2 3 4 5 6 7

byte 18 bit 0 6 5 4 3 2 1 0

1 2 3 4 5 6 7

byte 18 bit 0

1 2 3

byte 19 bit 0

1 2 3

byte 20 bit 0

1 2 3

byte 21 bit 0

1 2 3

byte 22 bit 0

1 2 3

byte 23 bit 0

1 2 3

byte 12 bit 0

1 2 3 4 5 6 7

byte 13 bit 0

1 2 3 4 5 6 7

byte 14 bit 0

1 2 3 4 5 6 7

Message bit numbers according to EBU specification of PDC system.

Transmission bit number.

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