Siemens SDA5642-6, SDA5642-6X Datasheet

ICs for Consumer Electronics

VPS-Decoder

SDA 5642-6/X

Data Sheet 02.97

SDA 5642-6/X Revision History: Current Version: 02.97

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Edition 02.97

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This edition was realized using the software system FrameMaker

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

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failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

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with the express

SDA 5642-6/X

Table of Contents Page

1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 I

2.2.1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.3 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.4 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Order of Data Output on the I

2.4 Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

C Bus and Bit Allocation . . . . . . . . . . . . . . . 12

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Control Register Write (I

5.2 Data Register Read (I

C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.3 DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.4 Position of VPS Data Lines within the Vertical Blanking Interval . . . . . . . . . 23

5.5 Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . . 23

5.6 Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 24

6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components

in the I

Semiconductor Group 3 02.97

C system provided the system conforms to the I2C specifications defined by Philips.

VPS-Decoder SDA 5642-6/X

MOS

1 General Description

The SDA 5642-6 VPS decoder chip receives all VPS data.

1.1 Features

• On chip data slicer

• Low external component count

C-Bus interface

• I communication with external microcontroller

• 5 V supply voltage

• Video input signal level: 0.7 Vpp to 2.0 Vpp

• Technology: CMOS

• P-DIP-14-1 and P-DSO-20-1 package

P-DIP-14-1

P-DSO-20-1

Type Ordering Code Package

SDA 5642-6 Q67100-H5182 P-DIP-14-1 SDA 5642-6X Q67106-H5183 P-DSO-20-1 (SMD)

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1.2 Pin Configurations

P-DIP-14-1 P-DSO-20-1

SDA 5642-6/X

Figure 1

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1.3 Pin Description

Pin No. Symbol Function

P-DIP-14-1 P-DSO-20-1

SDA 5642-6/X

1 V

1 2

V V

SS SSA SSD

Ground (0 V) Analog ground (0 V) Digital ground (0 V)

3, 8, 13, 18 N.C. Not connected 2 4 SCL Serial clock input of I 3 5 SDA Serial data input of I 4 6 CS0 Chip select input determining the I

/ 21H, when pulled low

/ 23H, when pulled high.

C Bus.

C-Bus addresses:

5 7 VCS Video Composite Sync output from sync slicer used

for PLL based clock generation.

6 9 DAVN Data available output active low, when VPS data is

received.

7 10 EHB Output signaling the presence of the first field active

high.

8 11 TI Test input; activates test mode when pulled high.

Connect to ground for operating mode.

9 12 PD1 Phase detector/charge pump output of data PLL

(DAPLL).

10 14 PD2/

Connector of the loop filter for the SYSPLL.

VCO2

11 15 VCO1 Input to the voltage controlled oscillator #1 of the

DAPLL.

12 16

REF

Reference current input for the on-chip analog circuit. 13 17 CVBS Composite video signal input. 14

V V

DD DDD

Positive supply voltage (+ 5 V nom.).

Positive supply voltage for the digital circuits

(+ 5 V nom.).

DDA

Positive supply voltage for the analog circuits

(+ 5 V nom.).

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1.4 Block Diagram

SDA 5642-6/X

Figure 2

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SDA 5642-6/X

2 System Description

2.1 Functions

Referring to the functional block diagram of the VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels.

The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal.

The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16.

The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL’s) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequency is 10 MHz.

All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block.

The extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to the I

C Bus.

That transfer is signalled by a H/L transition of the DAVN output. Data are updated when a new data line has been received, provided that the chip is not

accessed via the I2C Bus at the same time.

A micro controller can read the stored bytes via the I

C-Bus interface at any time. However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the VPS decoder is being accessed via the I

C Bus.

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SDA 5642-6/X

2.2 I2C Bus

2.2.1 General Information

The I i.e., both reading from and writing to the VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As a general rule for the I The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used:

START: Start Condition generated by master AS: Acknowledge by slave AM: Acknowledge by master NAM: No Acknowledge by master STOP: Stop condition generated by master

C-Bus interface implemented on the VPS decoder is a slave transmitter/receiver,

C Bus, the SDA line changes state only when the SCL line is low.

2.2.2 Chip Address

There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table:

CS0 Input Write Mode Read Mode

Low 20 (hex) 21 (hex) High 22 (hex) 23 (hex)

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