ICs for Consumer Electronics
VPS-Decoder
SDA 5642-6/X
Data Sheet 02.97
SDA 5642-6/X |
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Edition 02.97
This edition was realized using the software system FrameMakerâ.
Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München
© Siemens AG 1997.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 5642-6/X
Table of Contents |
Page |
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1 |
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . 4 |
1.1 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 4 |
1.2 |
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 5 |
1.3 |
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 6 |
1.4 |
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 7 |
2 |
System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 8 |
2.1 |
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 8 |
2.2 |
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 9 |
2.2.1 |
General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 9 |
2.2.2 |
Chip Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . 9 |
2.2.3 |
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 10 |
2.2.4 |
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 11 |
2.3 |
Order of Data Output on the I2C Bus and Bit Allocation . . . . . . . . . . . . . . |
. 12 |
2.4 |
Description of DAVN and EHB Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 14 |
3 |
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 15 |
4 |
VPS-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 19 |
5 |
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 20 |
5.1 |
Control Register Write (I2C-Bus Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 20 |
5.2 |
Data Register Read (I2C-Bus Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 21 |
5.3 |
DAVN and EHB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 22 |
5.4 |
Position of VPS Data Lines within the Vertical Blanking Interval . . . . . . . . |
. 23 |
5.5 |
Definition of Voltage Levels for VPS Data Line . . . . . . . . . . . . . . . . . . . . . |
. 23 |
5.6 |
Data Format of Programme Delivery Data in the Dedicated TV Line (VPS) 24 |
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6 |
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 26 |
Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
Semiconductor Group |
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02.97 |
VPS-Decoder |
SDA 5642-6/X |
MOS
1 General Description
The SDA 5642-6 VPS decoder chip receives all VPS data.
1.1 |
Features |
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• On chip data slicer |
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• Low external component count |
P-DIP-14-1 |
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• I2C-Bus interface |
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communication with external microcontroller |
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•5 V supply voltage
•Video input signal level: 0.7 Vpp to 2.0 Vpp
•Technology: CMOS
• P-DIP-14-1 and P-DSO-20-1 package
P-DSO-20-1
Type |
Ordering Code |
Package |
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SDA 5642-6 |
Q67100-H5182 |
P-DIP-14-1 |
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SDA 5642-6X |
Q67106-H5183 |
P-DSO-20-1 (SMD) |
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Semiconductor Group |
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02.97 |
SDA 5642-6/X
1.2Pin Configurations
P-DIP-14-1 |
P-DSO-20-1 |
Figure 1
Semiconductor Group |
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02.97 |
SDA 5642-6/X
1.3Pin Description
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Pin No. |
Symbol |
Function |
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P-DIP-14-1 |
P-DSO-20-1 |
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1 |
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VSS |
Ground (0 V) |
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1 |
VSSA |
Analog ground (0 V) |
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2 |
VSSD |
Digital ground (0 V) |
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3, 8, 13, 18 |
N.C. |
Not connected |
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2 |
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4 |
SCL |
Serial clock input of I2C Bus. |
3 |
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5 |
SDA |
Serial data input of I2C Bus. |
4 |
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6 |
CS0 |
Chip select input determining the I2C-Bus addresses: |
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20H / 21H, when pulled low |
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22H / 23H, when pulled high. |
5 |
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7 |
VCS |
Video Composite Sync output from sync slicer used |
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for PLL based clock generation. |
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6 |
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9 |
DAVN |
Data available output active low, when VPS data is |
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received. |
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7 |
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10 |
EHB |
Output signaling the presence of the first field active |
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high. |
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8 |
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11 |
TI |
Test input; activates test mode when pulled high. |
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Connect to ground for operating mode. |
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9 |
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12 |
PD1 |
Phase detector/charge pump output of data PLL |
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(DAPLL). |
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10 |
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14 |
PD2/ |
Connector of the loop filter for the SYSPLL. |
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VCO2 |
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11 |
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15 |
VCO1 |
Input to the voltage controlled oscillator #1 of the |
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DAPLL. |
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12 |
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16 |
IREF |
Reference current input for the on-chip analog circuit. |
13 |
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17 |
CVBS |
Composite video signal input. |
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14 |
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VDD |
Positive supply voltage (+ 5 V nom.). |
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19 |
VDDD |
Positive supply voltage for the digital circuits |
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(+ 5 V nom.). |
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20 |
VDDA |
Positive supply voltage for the analog circuits |
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(+ 5 V nom.). |
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Semiconductor Group |
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02.97 |
SDA 5642-6/X
1.4Block Diagram
Figure 2
Semiconductor Group |
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02.97 |
SDA 5642-6/X
2 System Description
2.1Functions
Referring to the functional block diagram of the VPS decoder, the composite video signal with negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the slicer, an analogue circuitry separating the sync and the data parts of the CVBS signal, thus yielding the digital composite sync signal VCS and a digital data signal for further processing by comparing those signals to internally generated slicing levels.
The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other hand, to the clock generator and the timing block. The VCS signal represents a key signal that is used for deriving a system clock signal by means of a PLL and all other timing signal.
The data slicer separates the data signal from the CVBS signal by comparing the video voltage to an internally generated slicing level which is found by averaging the data signal during TV line no. 16.
The clock generator delivers the system clock needed for the basic timing as well as for the regeneraton of the dataclock. It is based on two phase locked loops (PLL’s) all parts of which are integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed of a voltage controlled relaxation oscillator (VCO), a phase/ frequency detector (PFD), and a charge pump which converts the digital output signals of the PFD to an analogue current. That current is transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequency is 10 MHz.
All signals necessary for the control of sync and data slicing as well as for the data acquisition are generated by the Timing block.
The extracted data bits of TV line no. 16 are checked for biphase errors. With no biphase errors encountered, the acquired bytes are stored in the transfer register to the I2C Bus. That transfer is signalled by a H/L transition of the DAVN output.
Data are updated when a new data line has been received, provided that the chip is not accessed via the I2C Bus at the same time.
A micro controller can read the stored bytes via the I2C-Bus interface at any time. However, one must be aware that the storage of new data from the acquisition interface is inhibited as long as the VPS decoder is being accessed via the I2C Bus.
Semiconductor Group |
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02.97 |
SDA 5642-6/X
2.2I2C Bus
2.2.1General Information
The I2C-Bus interface implemented on the VPS decoder is a slave transmitter/receiver, i.e., both reading from and writing to the VPS decoder is possible. The clock line SCL is controlled only by the bus master usually being a micro controller, whereas the SDA line is controlled either by the master or by the slave. A data transfer can only be initiated by the bus master when the bus is free, i.e., both SDA and SCL lines are in a high state. As a general rule for the I2C Bus, the SDA line changes state only when the SCL line is low. The only exception to that rule are the Start Condition and the Stop Condition. Further Details are given below. The following abbreviations are used:
START: |
Start Condition generated by master |
AS: |
Acknowledge by slave |
AM: |
Acknowledge by master |
NAM: |
No Acknowledge by master |
STOP: |
Stop condition generated by master |
2.2.2Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the following table:
CS0 Input |
Write Mode |
Read Mode |
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Low |
20 (hex) |
21 (hex) |
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High |
22 (hex) |
23 (hex) |
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Semiconductor Group |
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02.97 |
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