Siemens HYS64V4200GU-10, HYS64V4200GU-8, HYS64V4200GU-8B, HYS64V8220GU-10, HYS64V8220GU-8 Datasheet

Semiconductor Group 1

3.3V 4M x 64/72-Bit 1 BAN K SD RAM Module

3.3V 8M x 64/72-Bit 2 BAN K SD RAM Module

PC66 & PC100 168 pin unbuffered DIMM M odules

HYS64(72)V 4200GU
HYS64(72)V 8220GU

• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules

for PC main memory applications

• One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation

• Optimized for byte-write non-parity and ECC applications

• JEDEC standard Synchronous DRAMs (SDRAM)

• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification

• SDRAM Performance:

• Programmed Latencies :

• Single +3.3V(± 0.3V ) power supply

• Programmable CAS Latency, Burst Length and Wrap Sequence

(Sequential & Interleave)

• Auto Refresh (CBR) and Self Refresh

• Decoupling capacitors mounted on substrate

• All inputs, outputs are LVTTL compatible

• Serial Presence Detect with E

2

PROM

• Utilizes 4M x16 SDRAMs in TSOPII-54 packages

• 4096 refresh cycles every 64 ms

• 133,35 mm x 29,31 mm x 4,00 mm card size with gold contact pads

-8 -8B -10 Units

f

CK

Clock frequency (max.) 100 100 66 MHz

t

AC

Clock access time 6 6 8 ns

Product Speed CL tRCD tRP

-8 PC100 2 2 2

-8B PC100 3 2 3

-10PC66222

18.98

HYS64(72)V4200/8220GU

SDRAM-Modules

Semiconductor Group 2

The HYS64(72)V 4200 and HYB64(72 )V8220 are an in dustry st andard 168-pin 8- byte Dual in- line M emory Modu le
(DIMM) which are organised as 4M x 64, 4M x 72 in an one bank and 8M x 64, 8M x72 in two banks high speed
memory arrays designed with 64Mbit Synchronous DRAMs (SDRAMs Die Rev.B) for non-parity and ECC
application. The DIMMs use -8 and -8B speed sort 4M x 16 SDRAM devices in TSOP54 packages to meet the
PC100 requirements and -10 par ts for 66 MHz bus speed ap plications. De coupling c apacitors ar e mounted on the

PC board. The PC board design is according to INTEL’s module specification.
The DIMMs have a seria l presen ce detect, imp lemented with a ser ial E

2

PROM using the two pin I2C protocol. The

first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All SIEMENS 168-pin DIMMs pr ovi de a high performanc e, flexi ble 8- by te interface in a 133,35 mm long footp rint,

with t.d.b. height.

Ordering Information

Pin Names

Address Format:

Type Ordering Code Package Descriptions Module

Height

HYS 64V4200GU-8 PC 100-222-620 L-DIM-168-31

100 Mhz 4M x 64 1 bank SDRAM module

1,15”

HYS 72V4200GU-8 PC 100-222-620 L-DIM-168-31

100 MHz 4M x 72 1 bank SDRAM module

1,15”

HYS 64V8220GU-8 PC 100-222-620 L-DIM-168-31

100 Mhz 8M x 64 2 bank SDRAM module

1,15”

HYS 64V8220GU-8 PC 100-222-620 L-DIM-168-31

100 MHz 8M x 72 2 bank SDRAM module

1,15”

HYS 64V4200GU-8B PC100-323-620 L-DIM-168-31

100 Mhz 4M x 64 1 bank SDRAM module

1,15”

HYS 64V8220GU-8B PC100-323-620 L-DIM-168-31

100 Mhz 8M x 64 2 bank SDRAM module

1,15”

HYS 64V4200GU-10 PC66-222-620 L-DIM-168-31

66 Mhz 4M x 64 1 bank SDRAM module

1,15”

HYS 72V4200GU-10 PC66-222-620 L-DIM-168-31

66 MHz 4M x 72 1 bank SDRAM module

1,15”

HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31

66 Mhz 8M x 64 2 bank SDRAM module

1,15”

HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31

66 MHz 8M x 72 2 bank SDRAM module

1,15”

A0-A11 Address Inputs

(RA0~ RA11 / CA0 ~ CA7, CA10)

CLK0 - CLK3 Clock Input

BA0 , BA1 Bank Select DQMB0 - DQMB7 Data Mask

DQ0 - DQ63 Data Input/Output CS0

- CS3 Chip Select

CB0-CB7 Check Bits (x 72 organisation

only)

Vcc Power (+3.3 Volt)

RAS

Row Address Strobe Vss Ground

CAS

Column Address Strobe SCL Clock for Presence Detect

WE

Read / Write Input SDA Serial Data Out for Pres. Detect

CKE0, CKE1

Clock Enable N.C. / DU No Connection

Part Number Rows Columns Bank Select Refresh Period Interval
4M x 64 HYS64V4200GU 12 8 2 4k 64 ms 15,6 µs
4M x 72 HYS72V4200GU 12 8 2 4k 64 ms 15,6 µs
8M x 64 HYS64V8220GU 12 8 2 4k 64 ms 15,6 µs
8M x 72 HYS72V8220GU 12 8 2 4k 64 ms 15,6 µs

HYS64(72)V4200/8220GU

SDRAM-Modules

Semiconductor Group 3

Pin Configuration

Note : Pinnames in brackets are for the x72 ECC versions

PIN # Symbol PIN # Symbol P IN # Symbol PIN # Symbol

1 VSS 43 VSS 85 VSS 127 VSS
2 DQ0 44 DU 86 DQ32 128 CKE0
3 DQ1 45 CS2 87 DQ33 129 CS3
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 VCC 48 DU 90 VCC 132 NC
7 DQ4 49 VCC 91 DQ36 133 VCC
8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC
10 DQ7 52 NC (CB2) 94 DQ39 136 CB6
11 DQ8 53 NC (CB3) 95 DQ40 137 CB7
12 VSS 54 VSS 96 VSS 138 VSS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 VCC 101 DQ45 143 VCC
18 VCC 60 DQ20 102 VCC 144 DQ52
19 DQ14 61 NC 103 DQ46 145 NC
20 DQ15 62 DU 104 DQ47 146 DU
21 NC (CB0) 63 CKE1 105 NC (CB4) 147 NC
22 NC (CB1) 64 VSS 106 NC (CB5 ) 148 VSS
23 VSS 65 DQ21 107 VSS 149 DQ53
24 NC 66 DQ22 108 NC 150 DQ54
25 NC 67 DQ23 109 NC 151 DQ55
26 VCC 68 VSS 110 VCC 152 VSS
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 CS0 72 DQ27 114 CS1 156 DQ59
31 DU 73 VCC 115 RAS 157 VCC
32 VSS 74 DQ28 116 VSS 158 DQ60
33 A0 75 DQ29 117 A 1 159 DQ61
34 A2 76 DQ30 118 A 3 160 DQ62
35 A4 77 DQ31 119 A 5 161 DQ63
36 A6 78 VSS 120 A7 162 VSS
37 A8 79 CLK2 121 A9 163 CLK3
38 A10 80 NC 122 BA0 164 NC
39 BA1 81 WP 123 NC 165 SA0
40 VCC 82 SDA 124 VCC 166 SA1
41 VCC 83 SCL 125 CLK1 167 SA2
42 CLK0 84 VCC 126 NC 168 VCC

HYS64(72)V4200/8220GU

SDRAM-Modules

Semiconductor Group 4

Block Diagram for 4M x 64 and 4M x 72 1 bank SDRAM DIMM modules (HYS64V4200GU)

A0-A11, BA0, BA1
VCC
VSS

D0 - D3, (D4)

C

E

2

PROM (256wordx8bit)

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D0

CS0

DQMB0
DQ(7:0)

DQMB1

DQ(15:8)

DQMB4
DQ32-DQ39

DQMB5

DQ40-DQ47

D0 - D3, (D4)

D0 - D3, (D4)

D0 - D3, (D4)

D0 - D3, (D4)

RAS

, CAS, WE

CKE0

notes: 1) all resistors are 10 Ohms

CLK1,CLK3

10 pF

WP

SDA

SA0
SA1
SA2

SA0
SA1
SA2

47k

SCL

SCL

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D2

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D1

CS2

DQMB2

DQ(23:16)
DQMB3

DQ(31:24)

DQMB6
DQ(55:48)

DQMB7

DQ(63:56)

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D3

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D4

Vcc

CB(7:0)

2) D4 is only used in the x72 ECC version

Clock Wiring

CLK0 2 SDRAM+15pF 3 SDRAM+10pF
CLK1 Termination Termination
CLK2 2 SDRAM+15pF 2 SDRAM+15pF
CLK3 Termination Termination

4M x 64 4M x 72

3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous
board layout to obtain minimum DQ trance length

HYS64(72)V4200/8220GU

SDRAM-Modules

Semiconductor Group 5

A0-A11, BA0, BA1
VCC
VSS

D0 - D7, (D8,D9)

C

E

2

PROM (256wordx8bit)

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D0

CS0

DQMB0
DQ(7:0)

DQMB1

DQ(15:8)

DQMB4
DQ(39:32)

DQMB5

DQ(47:40)

D0 - D7, (D8,D9)

D0 - D7, (D8,D9)

D0 - D7, (D8,D9)

D0 - D3, (D8)

RAS

, CAS, WE

CKE0

notes: 1) all resistors are 10 Ohms

WP

SDA

SA0
SA1
SA2

SA0
SA1
SA2

47kSCL

SCL

CS

LDQM
DQ0-DQ7

UDQM

DQ8-DQ15

D2

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D8

Vcc

CB(7:0)

2) D8 & D9 are only used in the x72 ECC version

Clock Wiring

CLK0 2 SDRAM+15pF 3 SDRAM+10pF
CLK2 2 SDRAM+15pF 2 SDRAM+15pF

CLK3 2 SDRAM+15pF 2 SDRAM+15pF

8M x 64 8M x 72

3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous
board layout to obtain minimum DQ trance length

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D4

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D6

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D9

Vcc

CS1

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D1

CS2

DQMB2
DQ(23:16)

DQMB3

DQ(31:24)

DQMB6
DQ(55:48)

DQMB7

DQ(63:56)

CS

LDQM
DQ0-DQ7

UDQM

DQ8-DQ15

D3

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D5

CS

LDQM
DQ0-DQ7

UDQM
DQ8-DQ15

D7

CS3

CLK1 2 SDRAM+15pF 3 SDRAM+10pF

D4 - D7,(D9)

CKE1

VDD

10k