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HYS64V16200GU-8B
Datasheet
17 pgs86.99 Kb0

Siemens HYS64V16200GU-8B, HYS64V32200GU-8, HYS64V32220GU-8, HYS64V32220GU-8B, HYS64V64220GU-8 Datasheet

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3.3 V 16M × 64/72-Bit SDRAM Modules
3.3 V 32M × 64/72-Bit SDRAM Modules
3.3 V 64M × 64/72-Bit SDRAM Modules
HYS 64/72V16200GU HYS 64/72V32220GU HYS 64/72V32200GU HYS 64/72V64220GU
PC100-168 pin unbuffered DIMM Modules
Preliminary Information
• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
• One bank 16M × 64, 16M × 72, 32M × 64 and 32M × 72 organization
• Two bank 32M × 64, 32M × 72, 64M × 64 and 64M × 72 organization
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• JEDEC standard Synchronous DRAMs (SDRAM)
• SDRAM Performance:
-8 -8B Units
f
CK
t
AC
• Programmed Latencies:
-8 PC100 2 2 2
-8B PC100 3 2 3
• Single + 3.3 V (± 0.3 V) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 32M × 8 SDRAMs in TSOPII-54 packages
• Uses SIEMENS 128Mbit and 256Mbit SDRAM components
Clock frequency (max.) 100 100 MHz Clock access time 6 6 ns
Product Speed CL t
RCD
t
RP
• Gold contact pad
• Card Size: 133.35 mm × 31.75 mm × 4.00 mm
Semiconductor Group 1 1998-08-01
HYS 64(72)V16200/3222(0)0/64220G
U
SDRAM Modules
The HYS 64/72V1600, HYS 64/72V32220, HYS 64/72V32200 and HYS 64/72V64220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 16M × 64, 16M × 72, 32M × 64 and 32M × 72 in 1 bank and 32M × 64, 32M × 72, 64M × 64 and 64M × 72 in two banks high speed memory arrays designed with 128M and 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort for 16M × 8 and 32M × 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC 100 module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height.
Ordering Information Type Ordering Code Package Descriptions Module
Height
HYS 64V16200GU-8 PC100-222-620 L-DIM-168-30 PC100 16M × 64 1 bank
SDRAM module
HYS 72V16200GU-8 PC100-222-620 L-DIM-168-30 PC100 16M × 72 1 bank
SDRAM module
HYS 64V32220GU-8 PC100-222-620 L-DIM-168-30 PC100 32M × 64 2 bank
SDRAM module
HYS 72V32220GU-8 PC100-222-620 L-DIM-168-30 PC100 32M × 72 2 bank
SDRAM module
HYS 64V16200GU-8B PC100-323-620 L-DIM-168-30 PC100 16M × 64 1 bank
SDRAM module
HYS 72V16200GU-8B PC100-323-620 L-DIM-168-30 PC100 16M × 72 1 bank
SDRAM module
HYS 64V32220GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 64 2 bank
SDRAM module
HYS 72V32220GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 72 2 bank
SDRAM module
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
HYS 64V32200GU-8 PC100-222-620 L-DIM-168-30 PC100 32M × 64 1 bank
SDRAM module
HYS 72V32200GU-8 PC100-222-620 L-DIM-168-30 PC100 32M × 72 1 bank
SDRAM module
HYS 64V64220GU-8 PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank
SDRAM module
HYS 72V64220GU-8 PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank
SDRAM module
Semiconductor Group 2 1998-08-01
1.25“
1.25“
1.25“
1.25“
HYS 64(72)V16200/3222(0)0/64220G
U
SDRAM Modules
Ordering Information (cont’d) Type Ordering Code Package Descriptions Module
Height
HYS 64V32200GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 64 1 bank
SDRAM module
HYS 72V32200GU-8B PC100-323-620 L-DIM-168-30 PC100 32M × 72 1 bank
SDRAM module
HYS 64V64220GU-8B PC100-323-620 L-DIM-168-30 PC100 64M × 64 2 bank
SDRAM module
HYS 72V64220GU-8B PC100-323-620 L-DIM-168-30 PC100 64M × 72 2 bank
SDRAM module
Pin Names
A0-A12 Address Inputs
(RA0 ~ RA10/CA0 ~ CA9) BA0, BA1 Bank Selects DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Chip Select CB0-CB7 Check Bits
(× 72 organization only) RAS Row Address Strobe V CAS Column Address Strobe SCL Clock for Presence Detect
CLK0 - CLK3 Clock Input
V
CC
SS
Power (+ 3.3 Volt)
Ground
1.25“
1.25“
1.25“
1.25“
WE Read/Write Input SDA Serial Data Out for Presence
Detect
CKE0, CKE1 Clock Enable N.C. / DU No Connection
Address Format
Part Number Rows Columns Bank
Select
16M × 64/72 HYS 64/72V16200GU 12 10 2 4k 64ms 15.6 µ 32M × 64/72 HYS 64/72V32220GU 12 10 2 4k 64ms 15.6 µ 32M × 64/72 HYS 64/72V32220GU 13 10 2 8k 64ms 7.8 µ 64M × 64/72 HYS 64/72V64220GU 13 10 2 8k 64ms 7.8 µ
Refresh Period Interval
Semiconductor Group 3 1998-08-01
HYS 64(72)V16200/3222(0)0/64220G
U
SDRAM Modules
Pin Configuration
PIN # Symbol PIN # Symbol PIN # Symbol PIN # Symbol
1 V
SS
2 DQ0 44 DU 86 DQ32 128 CKE0 3 DQ1 45 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6
V
CC
7 DQ4 49 8 DQ5 50 NC 92 DQ37 134 NC
9 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 NC (CB2) 94 DQ39 136 CB6 11 DQ8 53 NC (CB3) 95 DQ40 137 CB7 12
V
SS
13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59
18
V
CC
19 DQ14 61 NC 103 DQ46 145 NC 20 DQ15 62 DU 104 DQ47 146 DU 21 NC (CB0) 63 22 NC (CB1) 64
23
V
SS
24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26
V
CC
27 WE 69 DQ24 111 CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30
CS0 72 DQ27 114 CS1 156 DQ59
31 DU 73 32
V
SS
33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78
37 A8 79 CLK2 121 A9 163 CLK3 38 A10 80 NC 122 BA0 164 NC 39 BA1 81 WP 123 A11 165 SA0 40
41
V
CC
V
CC
42 CLK0 84
43 V
SS
85 V
SS
127 V
SS
CS2 87 DQ33 129 CS3
48 DU 90
91 DQ36 133
96
101 DQ45 143
54
V
CC
V
SS
V
CC
60 DQ20 102
V
CC
V
SS
V
CC
132 NC
V
CC
138
V
SS
V
CC
144 DQ52
CKE1 105 NC (CB4) 147 NC
V
SS
65 DQ21 107
68
V
SS
V
CC
74 DQ28 116
V
SS
82 SDA 124
106 NC (CB5) 148
149 DQ53
152
110
V
SS
V
CC
115 RAS 157
V
SS
158 DQ60
120 A7 162
V
CC
166 SA1
V
SS
V
SS
V
CC
V
SS
83 SCL 125 CLK1 167 SA2
V
CC
126 A12 168
V
CC
Note: Pinnames in brackets are for the x72 ECC versions
Semiconductor Group 4 1998-08-01
U
WE CS0
HYS 64(72)V16200/3222(0)0/64220G
SDRAM Modules
DQMB0 DQ(7:0)
DQMB1
CS2
DQMB2 DQ(23:16)
DQMB3 DQ(31:24)
CS CS WE
DQM DQ0-DQ7
CS
DQM DQ0-DQ7DQ(15:8)
CS
DQM DQ0-DQ7CB(7:0)
CS
DQM DQ0-DQ7
CS
DQM DQ0-DQ7
WE
DQMB4 DQ(39:32)
D0
WE
DQMB5
D1
WE
D8
WE WE
DQMB6 DQ(55:48)
D2
WE
DQMB7 DQ(63:56)
D3
DQM DQ0-DQ7
WECS
DQM DQ0-DQ7DQ(47:40)
CS
DQM DQ0-DQ7
CS
DQM DQ0-DQ7
WE
D4
D5
D6
D7
2
A0-A11, (A12), BA0, BA1 D0-D7, (D8)
V
CC
C
V
SS
RAS D0-D7, (D8)
CKE0 D0-D7, (D8)
Note: D8 is only used in the x72 ECC version.
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)CAS
CLK0 4 SDRAM + 3.3 pF 5 SDRAM
CLK3
E PROM (256 word x 8 Bit)
SA0 SA1 SA2
Termination Termination
SA0 SA1 SA2 SCLSCL
Clock Wiring
32 M x 64 32 M x 72
SDA
WP
TerminationTerminationCLK1 4 SDRAM + 3.3 pF4 SDRAM + 3.3 pFCLK2
Block Diagram for 16M × 64/72 & 32M × 64/72 one bank SDRAM DIMM Modules (HYS 64/72V16200GU & HYS 64/72V32200GU)
47 k
Ω
SPB03970
Semiconductor Group 5 1998-08-01
U
CS1 CS0
HYS 64(72)V16200/3222(0)0/64220G
SDRAM Modules
DQMB0 DQ(7:0)
DQMB1
CS3 CS2
DQMB2 DQ(23:16)
DQMB3 DQ(31:24)
CS
DQM DQ0-DQ7
CS
DQM DQ0-DQ7DQ(15:8)
DQM DQ0-DQ7CB(7:0)
D16
DQM DQ0-DQ7
DQM DQ0-DQ7
D0
D1
D2
D3
CS
DQM DQ0-DQ7
CS
DQM DQ0-DQ7
CSCS
DQM
DQ0-DQ7
D17
DQM DQ0-DQ7
D10
CSCS
DQM DQ0-DQ7
D8
D9
D11
DQMB4
DQMB5
DQMB6 DQ(55:48)
DQMB7 DQ(63:56)
CS
DQM DQ0-DQ7DQ(39:32)
DQM DQ0-DQ7DQ(47:40)
CS CSCS CS
DQM DQ0-DQ7
CS
DQM DQ0-DQ7
D4
D5
D6
D7
CS
DQM DQ0-DQ7
D12
CSCS
DQM DQ0-DQ7
D13
DQM DQ0-DQ7
D14
CS
DQM DQ0-DQ7
D15
2
A0-A12, BA0, BA1 D0-D15, (D16, D17)
V
DD
C0-C31, (C32...C35)
V
SS
RAS, CAS, WE D0-D15, (D16, D17)
V
DD
10 k
Ω
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.
D0-D15, (D16, D17)
D0-D7, (D8)
D0-D7, (D16)CKE0
CLK0 4 SDRAM + 3.3 pF 5 SDRAM
D9-D15, (D17)CKE1
E PROM (256 word x 8 Bit)
SA0 SA1 SA2
4 SDRAM + 3.3 pFCLK3 4 SDRAM + 3.3 pF
SA0 SA1 SA2 SCLSCL
Clock Wiring
64 M x 64 64 M x 72
SDA
WP
5 SDRAM4 SDRAM + 3.3 pFCLK1 4 SDRAM + 3.3 pF4 SDRAM + 3.3 pFCLK2
Block Diagram for 32M × 64/72 & 64M × 64/72 two bank SDRAM DIMM Modules
47 k
Ω
SPB03971
Semiconductor Group 6 1998-08-01
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