The radio part realizes the conversion of the GMSK-HF-signals from the antenna to the
base-band and vice versa.
In the receiving direction, the signals are split in the I- and Q-component and led to the D/Aconverter of the logic part. In the transmission direction, the GMSK-signal is generated in an
Up Conversion Modulation Phase Locked Loop by modulation of the I- and Q-signals which
were generated in the logic part. After that the signals are amplified in the power amplifier.
Transmitter and Receiver are never active at the same time. Simultaneous receiving in two
bands is impossible. Simultaneous transmission in two bands is impossible, too. However
the monitoring band (monitoring timeslot) in the TDMA-frame can be chosen independently
of the receiving respectively the transmitting band (RX- and TX timeslot of the band).
The RF-part of the CF62/CF62R is dimensioned for triple band operation (EGSM900,
GSM1800, GSM1900) supporting GPRS functionality up to multiclass 10. CF63 is
dimensioned for trible band operation (GSM850, GSM 1800, GSM1900) supporting GPRS
functionality up to multiclass 10.
The RF-circuit consists of the following components:
• Hitachi Bright VE chip set with the following functionality:
o PLL for local oscillator LO1 and LO2 and TxVCO
o Integrated local oscillators LO1, LO2 (without loop filter)
o Integrated TxVCO (without loop filter and core inductors for GSM)
o Direct conversion receiver including LNA, DC-mixer, channel filtering and PGC-
amplifier
o Active part of 26 MHz reference oscillator
• Hitachi LTCC transmitter power amplifier with integrated power control circuitry
• Hitachi Frontend-Module including RX-/TX-switch and EGSM900 / GSM1800 / GSM
1900 receiver SAW-filters for CF62/CF62R
• Hitachi Frontend-Module including RX-/TX-switch and GSM850 / GSM 1900 receiver
SAW-filters for CF63
Quartz and passive circuitry of the 26MHz VCXO reference oscillator.
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
The voltage regulator for the RF-part is located inside the ASIC D361.(see chapter 5.2).It generates
the required 2,8V “RF-Voltages” named VCC2_8 and VCC_SYN .The voltage regulator is activated
as well as deactivated via SLEEPQ(VCC2_8)
(Miscellaneous R6)provided by the EGOLD+. The temporary deactivation is used to extend the stand by
time.
Circuit diagram
(TDMA-Timer H16)and VCXOEN_UC(VCC_SYN)
VCC2_8
VCC_SYN
4.3 Frequency generation
4.3.1 Synthesizer: The discrete VCXO (26MHz)
The CF62/62R,63 mobile is using a reference frequency of 26MHz. The generation of the 26MHz
signal is done via a VCXO. This oscillator consists mainly of:
A 26MHz VCXO Z3961
A capacity diode V3961
TP (test point) of the 26MHz signal is the TP 3920
Page
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
The oscillator output signal 26MHz_RF is directly connected to the BRIGHT IC (pin 35) to be used
as reference frequency inside the Bright (PLL). The signal leaves the Bright IC as BB_SIN26M (pin
31) to be further used from the EGOLD+ (D171
(functional T3)).
Bright VE
VCXO Out
EGOLD In
To compensate frequency drifts (e.g. caused by temperature) the oscillator frequency is controlled
by a (AFC) signal, generated through the internal EGOLD+ (D100
diode V3961. Reference for the “EGOLD-PLL” is the base station frequency received via the
Frequency Correction Burst. To compensate a temperature caused frequency drift, the temperaturedepending resistor R3967 is placed near the VCXO to measure the temperature. The measurement
result TVCXO is reported to the EGOLD+
(Analog Interface P3) via R138 as the signal TENV.
The required voltage VCC_SYN is provided by the ASCI D361
Waveform of the AFC_PNM signal from EGOLD+ to Oscillator
Signalform
EGOLD+
1 23
(functional U5)) PLL via the capacity
1
AFC
R158
30K 22K
C165
GND
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
The first local oscillator (LO1) consists of a PLL and VCO inside Bright (N3921) and an
external loop filter The first local oscillator is needed to generate frequencies which enable
the transceiver IC to demodulate the receiver signal and to perform the channel selection in
the TX part. To do so, a control voltage for the LO1 is used, gained by a comparator. This
control voltage is a result of the comparison of the divided LO1 and the 26MHz reference
Signal. The division ratio of the dividers is programmed by the EGOLD+, according to the
network channel requirements.
RF VCO
OUT
3476 - 3980
external
Loopfilter
Bright V
MHz
RF PLL
CP
+
PFD
D
1
R
1
3 wire bus
from EGOLD
26MHz
Matrix to calculate the TX and RX frequencies CF62:
The required voltage VCC_SYN is provided by the ASIC D361.
4.3.3 Synthesizer: IFVCO(LO2)
The second local oscillator (LO2) consists of a PLL and a VCO which are integrated in
Bright and a second order loopfilter which is realized external (R3927; C3940; C3948). Due
to the direct conversion receiver architecture, the LO2 is only used for transmit-operation.
The LO2 covers a frequency range of at least 16 MHz (640MHz – 656MHz).
Before the LO2-signal gets to the modulator it is divided by 8. So the resulting TX-IF
frequencies are 80/82 MHz (dependent on the channel and band). The LO2 PLL and powerup of the VCO is controlled via the tree-wire-bus of Bright (EGOLD+ signals RFDATA;
RFCLK; RFSTR). To ensure the frequency stability, the 640MHz VCO signal is com pared
by the phase detector of the 2
signal passes the external loop filter and is used to control the 640/656MHz VCO.
The required voltage VCC_SYN is provided by the ASIC D361
nd
PLL with the 26Mhz reference signal. The resulting control
640 - 656 MHz
external
Loopfilter
Bright V
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
The frequency-step is 400 kHz in GSM1800/GSM1900 mode and 800kHz in
GSM850/EGSM900 mode due to the internal divider by two for GSM1800/GSM19000 and
divider by four for GSM850/EGSM900. To achieve the required settling-time in GPRS
operation, the PLL can operate in fastlock-mode a certain period after programming to
ensure a fast settling. After this the loopfilter and currents are switched into normal-mode to
get the necessary phasenoise-performance. The PLL is controlled via the tree-wire-bus of
Bright.
4.4 Antenna switch (electrical/mechanical)
Internal/External <> Receiver/Transmitter
The CF62/CF62R/CF63 mobile have two antenna switches.
a) The mechanical antenna switch for the differentiation between the internal and
external antenna, which is used only RF adjustment.
b) The electrical antenna switch, for the differentiation between the receiving and
transmitting signals.
To activate the correct settings of this diplexer, the EGOLD+ signals RF_SW and
TXON_GSM are required
CF62/CF62R, CF63 have an integrated “SAR detection” circuit. This circuit is used to
decide if the internal antenna or an external antenna is used. The goal is, to reduce the
transmit power when the internal antenna is used and the mobile is held very close to the
body. On the other hand, the mobile can send with more power, if the external antenna is
used. This distinction is done by the SAR detection circuit which consists of the voltage
divider R872 and R873. The ANT_DET output provides a high level when the external
antenna is used. ANT_DET
ntenna
to / from FEM
(Serial Interface L16) is connected to the EGOLD+
External Antenna
(only for RF adjustment)
Internal antenna
to EGOLD
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
The band filters are located inside the frontend module (N3901). The filters are centred to
the band frequencies. The symmetrical filter output is matched to the LNA input of the Bright
(N3921).The Bright VE incorporates three RF LNAs for GSM850/EGSM900, GSM1800 and
GSM1900 operation. The LNA/mixer can be switched in High- and Low-mode to perform an
amplification of ~ 20dB. For the “High Gain“ state the mixers are optimised to conversion
gain and noise figure, in the “Low Gain“ state the mixers are optimised to large-signal
behavior for operation at a high input level. The Bright performs a direct conversion mixers
which are IQ-demodulators. For the demodulation of the received GSM signals the LO1 is
required. The channel depending LO1 frequencies for 1800MHz/1900MHz bands are
divided by 2 and by 4 for 850MHG/900MHz band. Furthermore the IC includes a
programmable gain baseband amplifier PGA (90 dB range, 2dB steps) with automatic DCoffset calibration. LNA and PGA are controlled via EGOLD+ signals RFDATA; RFCLK;
RFSTR
baseband filter for both IQ chains. Only two capacitors which are part of the first passive
RC-filters are external. The second and third filters are active filters and are fully integrated.
The IQ receive signals are fed into the A/D converters in the EGAIM part of EGOLD+. The
post-switched logic measures the level of the demodulated baseband signal and regulates
the level to a defined value by varying the PGA amplification and switching the appropriate
LNA gains.
From the antenna switch, up to the demodulator the received signal passes the following
blocks to get the demodulated baseband signals for the EGOLD+:
Filter
N3901 Bright(N3921)
The required voltage VCC_SYN is provided by the ASIC D361
(RF Control J15, J16, J17). The channel-filtering is realized inside the chip with a three stage
LNA
Demodulator
PGC
Service Repair Documentation
Level 2.5e - CF62, CF62R, CF63
Page
15 of 49
Release 1.1
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