Siemens BGA427 Datasheet
BGA 427
Semiconductor Group
Au -11-19981
in SIEGET 25-Technologie
Si-MMIC-Amplifie
r
VPS05605
4
2
1
3
Preliminary data
• Cascadable 50 Ω-gain block
• Unconditionally stable
• Gain |
S
21
|2 = 18,5 dB at 1.8 GHz (appl.1)
gain |
S
21
|2 = 22 dB at 1.8 GHz (appl.2)
I
P
3out
= +7 dBm at 1.8 GHz (
V
D
=3V,
I
D
=9.4mA)
• Noise figure
NF
= 2.2 dB at 1.8 GHz
• typical device voltage
V
D
= 2 V to 5 V
• Reverse isolation < 35 dB (appl.2)
EHA07378
V
2
1
IN
OUT
+
4
3
GND
Circuit Diagram
ESD: Electrostatic discharge sensitive device, observe handling precaution!
Type Marking Ordering Code PackagePin Configuration
Q62702-G0067 1, INBGA 427 2, GND 3, +V 4, Out SOT-343BMs
Maximum Ratings
Symbol
ValueParameter Unit
Device current
I
D
mA25
Device voltage 6 V
V
D
,+V
P
tot
150 mW
Total power dissipation,
T
S
≤ tbd °C
dBm
R
F
input power
P
RFin
-10
Junction temperature
T
j
150 °C
Ambient temperature -65 ...+150
T
A
Storage temperature
T
stg
-65 ...+150
Thermal Resistance
≤ tbd
K/WJunction - soldering point
1)
R
thJS
1)
T
S
is measured on the emitter (GND) lead at the soldering point to the pcb
Semiconductor Group 1 1998-11-01
BGA 427
Semiconductor Group
Au -11-19982
Electrical Characteristics at
T
A
= 25 °C, unless otherwise specified.
Parameter
Symbol UnitValues
typ. max.min.
AC characteristics
V
D
= 3 V,
Z
o
= 50W, Testfixture Appl..1
|
S
21
|
2
-
-
-
Insertion power gain
f
= 0.1 GHz
f
= 1 GHz
f
= 1.8 GHz
27
22
28.5
-
-
-
dB
Reverse isolation
f
= 1.8 GHz
S12
- 22 -
Noise figure
f
= 0.1 GHz
f
= 1 GHz
f
= 1.8 GHz
-
-
-
-
-
-
1.9
2
2.2
NF
Intercept point at the output
f
= 1.8 GHz
IP
3out
-
+ 7
- dBm
Return loss input
f
= 1.8 GHz
RL
in
- >12 - dB
Return loss output
f
= 1.8 GHz
RL
out
- >9 -
Typical configuration
Appl.2
Appl.1
EHA07379
100 pF
100 pF
1 nF
RF OUT
RF IN
GND
+
V
BGA 427
EHA07380
2.2 pF
100 pF
RF IN
100 pF
GND
RF OUT
100 nH
10 nF 100 pF
+
V
BGA 427
Note: 1) Large-value capacitors should be connected from pin 3 to ground right at the device
to provide a low impedance path! (appl.1)
2) The use of plated through holes right at pin 2 is essential for pc-board-applications. Thin
boards are recommended to minimize the parasitic inductance to ground!
Semiconductor Group 2 1998-11-01
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