Sharp PC-1251, PC-1250 Service Manual
PC-1251
SHARP
SERVICE MANUAL
MODEL
CODE:
PC-12
PC
O
OZPC1251
-1250
///
E
51
1.
PRODUCTS
2. SPECIFICA
3. BLOCK DIAGRAM . . .
4. CPU
5. LCD DRI
6. SER VICE PR
7. SCHEMATICS 10
8. PARTS SIGNAL LAYOUT CHART
9. PARTS
*
Differen
Program da
-t:<
CE-125 option
Microcassette tape recorder
thermal
ce
dot pr
INTERNAL BLOCK DIAGRAM AND PIN/SI
VE CIRCUIT
GUIDE AND PARTS LIST
between PC 1 2
ta
area
of the PC-1251 is
:
inter is in
OUTLIN
TIO
N
ECAUTIONS
50 and PC 1251:
is
available as an external me
corporate
d as the output
E
. . . . . . . . . . . . . . . . . . . . . . . .
AND TIMINGS . . . .
. . . . . . . . . . . . . . . . .
larger by 2048
bytes.
devi
. . . . . . . . . .
mory device and 2
ce.
. .
. . . . . . . .
GNAL DESC
. .
. . . .
. .
.
.
. . .
. . .
. .
. .
3
RIPTION
. . . . . . . . . . .
. . . . . . . . . . . . . . . . 9
4-digit
. .
. . . 7
. .
4
11
1
2
SHARP
CORPORATION
1
.
iNTRODUCTiON TO
The
SHARP PC-1251
*
52-character keyboard.
*
24-character
*
Powerful BASIC in 24K ROM.
*
8 bit
CMOS processor.
*
4KB
RAM
*
Optional CE-125
system consists of:
display
.
.
Printer/Microcassette Recorder.
THE
2. SPECiFiCATiON
Model: PC-1251 Pocket Computer
Processor: 8
Programming
Memory Capacity:
Stack
:
Operators:
Numeric Precision:
Editing Features:
Memory
Display:
Keys:
Power Supply:
Power Consumption:
Operating Temperature: 0°C ~ 40°C (32°F ~ 104°F)
Dimensions
Weight:
Accessories
Options
Language: BASIC
Protection
:
:
:
:
bit
CMOS CPU
ROM
RAM
System
User
Fixed Memory Area
(A~ Z,
Reserve Area
Program/Data Area
Sub-routine:
FOR-NEXT
Function:
Data
:
Addition,
inverse
sion, square root, sign, absolute,
10 digits (mantissa) + 2
Cursor
CMOS Battery backup
24 character
52
defined keys.
6.0 V DC
Type: CR-
6.0 V
(Sufficient for
135 (W) x 70 (D) x 9.
5-5/16
Approximately
Wallet, two
Printer/Micr
subtraction,
trigonometric functions, logarithmic and exponential functions, angle conver-
left
and right, line up and
keys: Alphabetic, numeric,
Lithium
2032
DC@0.03
11
(W) x 2-3/411(D)x3/8
ocassette Recorder
PC-1251
:
About
A$~
Z$)
10 stacks
:
liquid
lithium
5
stacks
16 stacks
8 stacks
multiplication,
digits (exponent)
crystal display
cells
W
approximately 300 hours
5 (H) mm
115 g (0.25 lbs) (with cells)
cells
(built-in), two
(RAM: 4 K)
integer, relational operators, logical
down, character insert, character
special
11
(H)
(CE-125)
24 K Bytes System
500 Bytes
208 Bytes
48 Bytes
3486 Bytes
division, exponentiation,
with
5 x 7 dot characters
symbols, and
usage
without
keyboard templates and instruction manual
functions. Numeric pad.
external power
trigonometric
operators
delete
.
supply
and
.
Use
r
. )
•KEY LAYOUT
Key board
Display
Reserve
/
Conditioning key
section
Power /Mode slide s
witch
.
•SYSTEM LAYOUT
O
PTiON CE-1
MiCRO C
ASS
ETTE REC
:cAssETT-E:
~ci~-~~i1:~--1
: Co
ntrol
ler
1
----
---
- - -----
REMOT
DIDO
OFF ON
UM-3 Type
NicdX4
11Pin
25
I
:
..
E
ROLL PAP
24 Dig it
THERMAL
OFF
0
: 2/4 K
: By
..
R
AM
PRINTER
PRiNTER
llilI[J
:
te
:
_
P C-1250I
ER
I
ON
24 DiG L
System
: 16K
: Byte
1251
CD
ROM CPU
:
:
NOTE:
Standard cassette tape recorder can
Recording
to
the standard cassette tape
SP
Lithium cel
/
s:
<,
I
..
__
'
X2
,,..
ls
'
only
AC
Adaptor
STANDARD C
be
used
to write
is
not
possible
.
data
ASS
ETTE RECORDE
to
the computer via the CE-
R
125
.
2
3.
PC-1250 / PC-1251
SYSTEM
BLOCK DiAGRAM
~-G ...
T ..
. . . ....
~~
~
V
GG
,KEY M
(
51 KE
B
UZZ
. .
....
N_D
+
z~
-
V
CJ
~
-
--.
.....--1A1
Slide Switch
ER
.
.L
.r,
dT
....
....
(OPTiON) CE-125
V
GG
3'
!
__ vcc v
oc
GG
SC61860
SC618
TEST
RES
ET
- KON
I
r+ IA
s
I
B1
ATR
iX
Y+ ON KEY
c:::i
Y.~:0
Vots
C.P.U.
o
60 A02LD
-IB4 Xo
)
IY
1
Vs VM
A02
r
Xi
• . .
VA
H
D
R/W~---
¢AL>-------+.-...._--+l--~------t--
01-0s •
AO 1-3
B01-1~=
I
IBs IB1 FOu
IB5 IB
Se
SeiZ Din Dou
L':::::
3
11 V\cK BUSY
.
1')..
.
4
~
' ~
~
VGG-
A
IS
...__ _ __._..,DiS
LCD 24Dig +
VA
Vs
Vrns
SC43536LD
-
HA
C
BOs
SC
E
PAL R/
J
4 3 5
or
I
?symbols
36
W
01-
s
--+--+-_._--1-1---------,,.........----~
-
---~
DATA BUS
l
~=====l==::::;::;:=:#:======t===n=fj=~=
B03,F01
====
t
====
-3
=l==;:;:il:=:#:======t==n::::fl=fj=~
=:!==l:l:::li==J~====;==r=t==fAF~:::>~
F0
5
ROM
16KBYte
LH532916
.
F03 I
'
~
C
E
R/W
CE RAM
2KBy
HM61 1
or
CTC5517)
RAM 2Kbyte
PC1251 Only
Ao-
10.
01-8
te
6
I
)
ADDRESS BUS
CHiP E
NABL
E
'
MiCRO CASS
MiCRO CASSETTE
tape recorde
CiRCUi
M
-13H
ETTE
T
remot
e
THER
r
PCU
SC6858
MAL PRi
MTP 201-24BA
NTE
R
3
4. C.P.U.iNTERNAL
BLOCK DiAGRAM
TERMiNAL DESCRiPTiONS
&
• C.P.U.
(SC61860A02) ········· 8 Bits C-MOS C.P.U.
ROM (
BK Byte)
I
,
1
DO
07
Hg-15
I
B
•
!
•CPU pin No.
Pin Signal
No.
10
11
12
name
1
A01 OUT
2
3
4
5
6
7
8
R/W OUT
0AL
TES
01
00
RES
Xin
9 ON IN
Xout
Dis
HA
xLh:~.
¢
AL
R/W F01 F01 F03 F04 FO;
Addre
ss
Latch
and si
I
N/OUT
Address
Write clock, normally
OUT
Low order bits address latch, normally hi
address signal on the data bus line
Test pin, normally
IN
Oscillator input
IN
.
CCE)(CEJCCE)
F01 · 11F
Out
Por
F02 : !IF
FOi .
RAM
FO,
F
O; . PROGRAM ROM CE
gnal description
t
Out Port
Basic
RAM
GRAOEUP
RAM
bus, high during standby
low
.
s
Description (Standby = power
.
high
.
gh. The clock used
when a larae caoacltv ROM is
.
to
off)
latch
used.
U
181
-B
110 PORT
1-4
KEY
5-8 for
low
order 8 bits
j
OUT
TERMINAL
INTER FACE
OUT Oscillator output.
Reset input, active high.
IN
IN Input (MT in)
of
microcassette signal from the CE-125 option.
Normally, pulled down to low level.
ON (BREAK) key input, normally pulled down to low level.
OUT Output (MT out
OUT
LCD dri
ver
1)
of mi
crocassette signal to the CE-125 option and the buzzer.
control signal.
OUT LCD driver clock, low during standby and in 2 kHz oscillation during display.
of
16-bit
4
Pin
No
1
3
14
.
Si
gna
l
name
i
A8
i
A7 IN
IN/OUT
IN/OUT
/OU
T
Key input/strobe signal, l
Key
input/strobe signal, l
Description (
Standby = power
ow during standby and key-in
ow during st
andby and key-in pulse
off
)
pulse
is
genera
ted when
is
generated when
low
low
.
.
15
16 iA5
17
18
IN/
i
A6
IN/OUT
IN/OUT Key input
i
A4
i
A3
IN/OUT
OUT
Key input/strobe si
Key input
Key input/strobe
/strobe
/strobe si
gnal, low during standby and
signal , l
ow during
gnal
, l
ow duri
signal, low duri
19 iA2 IN/OUT Key input/strobe signal, low
20 iA1
21
22
23 iB6
24
25
26 iB3
27
28
29 VM IN
30
31
GND IN
32
33 H2
3
4 H3 OUT
35
36
37
38 H7 OUT
39
40
41
42
43
44
45
46 H15
47
48
49
VD i
50
IN/OUT Key input/strobe sig
iB8 IN
i
B7 IN
OUT
i
B5 OUT
iB4
OU
iB
2
OUT
iB
1
OUT
ACK
Data in
SEL2 output, P-type open drain.
S
EL 1 output, P-type open
I
N
S
lide switch input.
Key strobe output,
T
Key strobe
Key strobe
LCD power supply
L
VA
IN
CD
Powe
H1
OUT
O
H4
H
OUT
5
OUT
H6 OUT
H8 OUT
H9
H10
H 11
H12
H13
H14
OU
OU
O
OUT
OU
OU
--
H16
Vs
Vee
-
s
LC
L
UT
UT
CD
LCD
LCD
LCD
LCD
LCD
LCD
T
LCD
T
LC
LC
LCD
T
LCD
T
LCD
Not used. (D
-
Not used. (Display
L
I
N
IN
IN
CD power
LCD pow
LCD power supply,
D
D
D
nal, low duri
signal
that en
ables the CPU
(Din). Ser
ial data input fr
low
output, low
outpu
t,
low during standby and
during
during standb
.
powe
r supply
.
r supply.
back
plate
bac
kplate sign
b
ackp
late
bac
kplate
b
ackplate si
backpla
te signal,
backplate signal,
backplate
backplate
backplate
backplate signal
backplate
backplate signal, high impedance
backplate
isplay
signal
al,
signal
signal,
gnal
signal,
signal,
signal
signal
signal
high
,
hi
high
,
high
high
,
high
high
high
high
high
,
hi
,
high
,
high
,
of this
gh
gh
of this unit opera
supply, high during
er supply, high du
normally
key-in pulse
standby and key
ng
standby and key-in pulse
ng standby and -key-in pulse is
during standby and
ng
standby and key-in pulse
to re
ad
data through
om PCU
drain
.
standby and
key-in
(bit
by
bit serial handshake).
key-in pulse
y and key-in pulse
key-in pulse
i
mpedance
i
mpedance
impedance
impedance
i
mpedan
i
mpedance
imp
edance during standby and 4-l
impedance
impedanc
impedance
impedanc
impedanc
impedance du
unit op
ring stan
duri
ng standby 'and 4-
during
standby
during standby and
during standby
ce during
e
e
e
erat
tes in 1/
standby a
standby and
duri
ng
sta
duri
ng
standby
during standby and
during
standby and 4-l
during standby
during
stand
during
sta
ring
standby
es in 1/14
14
nd low when the high level clock
dby and low when the
low
.
ndby
by and 4-level pulse
ndby and 4-le
duty.
duty.)
is generate
-in pulse
is
ge nerated when
is
generat
genera
pulse
is
ge n
era
is
generated w
1/0 port
(
PCU).
is
gen
erated
is generated when
is generated when
level pulse
and 4-level
and 4-level
and 4-l
and 4-l
and 4-l
and 4-level
pulse dur
4-level pulse during display
puls
e
4-level pulse
evel pulse
evel pulse
evel pulse du
4-level pulse du
evel pulse
evel pulse
vel pulse
pulse during
)
high level cloc
d when low
low
ed wh
en low.
ted when low.
ted when low
hen low.
when
low
.
low
.
low
.
during display
ing
dis
play
during dis
during display
during display
during di
duri
during
during
during displa
ring
ring
ng
display.
display
dis
dis
display
display.
stops
play
spla
play
play.
.
k stops.
.
.
.
.
.
.
.
.
.
y.
.
.
.
y.
5
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