SHARP CORPORATION
CONTENTS
1. Specifications . .
. . . . . . . .
. . . . . . .
. . . . . .
. . . .
. . . . . . . . . . . . . . . . . . 2
2. Block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. .
. . .
. .
. .
4
3. LSI signal description
12
4
.
About servicing
17
5. Cassette operation
. . . . . . . . . . . . . . . .
. . .
. . . . . . . . . . . . . . . . . . . . . . .
18
6. Check program
·
· · ·
25
7. Circuit diagram
. . . . . . .
. .
. . . . . . . .
. .
. . .
. . . . . . . . . . . . . . . . . . . . . .
26
8. PC-1211 parts list & guide
· ·
32
9. CE-
121 parts list & guide . . . .
. . . . . . . . . . .
. .
. . . . .
· · · · . ·
· · ·
· ·
· ·
· · ·
34
MODEL
PC-1211, CE-121
----SHARP----
SERVICE
MANUAL
2
Add
(+),Subtract(-), Multiply
(+),Divide(/), Power raising (A
)
Trigonometric
functions
:
SIN (sine), COS (cosine), TAN (tangent)
Inverse trigonometric functions: ASN (sine " ), ACS
(cosine
-
1
),
ATN (tangent
-
1
)
Logarithmic functions: LOG (common logarithm), LN (natural
logarit
hm
[ln]
)
·
Exponential functions: EXP (exponential)
Angular transformations: DMS (decimal notation to sexagesimal notation),
DEG (sexagesimal notation to decimal n
otation
)
Square root extraction:
r
Signum
function
.
SGN
Absolute
value
:
ABS
(IX
I)
In terization: INT
Execution of arithmetic operation
is
commanded by the ENTER key
.
1-3. Arithmetic functions
•
Buffers
:
•
Capacities
:
12
digits of mantissa and 2 digits of exponent.
According to mathematical formula (with priority consideration
and judge function)
Program memory; 1424
steps, max (PC1211)
Data memory; Fixed memory
26 memories
Flexible memory (commonly usable with the
program memory)
178 memories, max (PC 1211)
Reserve program; 18 kinds, 48 steps, max
Input buffer; 80 steps
Data buffer;
8
stages
Functional buffer;
16
stages (but
15
stages for
parenthesis
)
Subroutine buffer; 4 stages
"FOR NEXT" stagement
buffer: 4 stages
•
Computational capacity:
•
Computational method:
1-2. Basic
functions
•
Displaytube: LF8017JE
•
Display method: 5 x 7 dot matrix liquid crystal
•
Display capacity: 24 coulumns (alphanumerics and symbols)
1-1 . Display
INS
OJ
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DEL
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ERi
RESERVABLE
KEY
S
1. SPECIFICATIONS
3
Data
protection
:
Program memory, data
memory, reserve program memory
P
eripheral unit: Audio cassette unit
(recording/reading of the program memory,
d
ata
memory and reserve program memory)
Physical dimensions: 175(W)
x 70(D) x 44(H) mm
1-7. Others
Four MR44 (mercury batteries)
300 hours
0.01
iw
About 6 minutes
B
attery:
B
attery life:
Power con
sumption:
Automatic power shut off:
1
-6. Power source
1-5. Programming language
BAS
IC (Beginne
r's All purpose Symbolic Instruction Code)
....
(right), ~(left)
INS
D
EL
+(down), t (up)
Cursor shift:
Insertion
.
Deletion
:
Line control:
1-4. Editorial
functions
4
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5
•
The CPU I functions to read key-in data or read the instruction to be executed from the
RAM
,
and decides what
is
to be done for the control of arithmetical operation (i.e. control of
arithmetic sequence, memorizing of arithmetical
data, and its readout), or interprete the syntax
of the BASIC instruction for deciding what
is
to be executed, or determines and prepares the
information to be displayed, but the CPU I does not perform any execution by
itself
.
It
only
arranges the data and information in proper sequence and acts to provide instruction code to the
CPU II via the buffer. On the other
hand, the CPU II constantly receives execution instructions
from the CPU I via the transfer buffer and executes operation against each of instructions or
sometimes performs to exchange data depending on the
situation. Although it shares major part
of execution in term of execution, it performs some kinds of auxiliary CPU when looked in the
view that it does not perform any decision by
itself
.
Clock stop
Clock stop control
I
Power shut off control
I
Power off
Display processing routine
Input buffer
Computational result
Error
Arithmetic routine
Character generator
Cassette routine
Print routine
Buzzer
Recognition of printer
Key input routine
Acknowledgement of the remaining
program
One instruction to one program step
incorporation
Interpreter:
Program execute statement
Cassette control statement
Command statement
Printer control
Execution of manual operation
CPU
II
CPUI
These CPUs are provided with internal ROM, and each of CPUs shares the following assignments:
2-1. CPU I,
CPU II
System
configuration
(see
the
system
block
diagram)
System of this unit consists of the following components:
1)
CPU I (SC43157) x 1
2) CPU II (SC43178) x 1
3) 4K-bit RAM (TC5514P x 3)
4) Display chip (SC43125 x 3, with built-in RAM)
5) 2AND gate (TC401 l UBP x 1)
6) 2AND
20R
(TC4019BP x 1)
7) Inverter (TC4069BP x 1)
8) Quard Analog Switch Multiplexer (TC4066BP)
9) LCD (24-digit FEM dot LCD)
10) Key
11) Crystal (CSB2560)
8
6
In the case of manual operation of the pocket computer, the instruction code (key code)
is
written
into the RAM in the display chip (input buffer) after information
is
put through the keyboard and
converted into the instruction code by the CPU
I,
then this instruction code (display, at this case)
is
transfered to the CPU II
via
the transfer buffer.
As
the CPU II receives this instruction, the CPU
II
then decodes this instruction
(display, at this case) and executes display processing. Upon the
completion of this processing,
it
is
then notified to the CPU I, then the CPU I confirms the comple-
tion of the task by the CPU II before terminating their jobs.
CPU
Il
Ex: Actions of CPU I and CPU II at the time of key data entry.
7
Although RAM area is mainly shared by the
program, data
and reserve program
memories, it
is
also used for the sub-
routine stack, FOR NEXT statement stack and fixed
memories (W, X, Y, Z).
1536
1472
1504
001
048
(PC1211)
Reserve pro
gram
------- - - - - - --
Program
or
flexible
memory
~------
-------
Fixed memories (W - Z)
Subroutine I FOR
NEXT
stack statement
stack
A certain number
of
C-MOS RAM
(1
-
3
chips, 4K bits each) and another RAM incorporated inside
the display chip are used in this pocket computer, having varieties of configurations
as
described
below:
•
Map
of
4K-bit RAM
153
6 Bytes
2-2.
RAM
II
8
•
Input buffer
Remaining 80 bytes (10 memories equivalent) of the display chip 1 is
used for the input
buffer
,
which
is
used in the following
functions:
1.
Any information entered through the keyboard
is
stored once in this
buffer, thus allowing up
to 80 steps.
2. The display contents
is
stored by the CPU I and the CPU II makes selection out of this dat
a.
3. When an
arithmetical instruction is
entered, its procedure
is
stored in this buffer by the CPU
I
and the CPU
II
performs operation according to this procedure.
4. When program or reserve program
is to
be recorded or read out during the execution of the
cassette control
instruction, action takes place through this input buffer.
•
Transfer buffer
8
bytes
(1
memory
equivalent) of the
display chip 1 is used
as a transfer buffer which
is
used in
the
transaction of instruction between the CPU I and the CPU II.
16 bi
ts
----1}4bit
1
memory
•
Fixed memory
The total memory of 176 bytes from the display chip 2 and 3 is
used
as a
fixed
memories, A-V
(22 memories).
•
8-digit display buffer
40 bytes of 8-digit display buffer
is
used
as a
display data buffer during displaying and also used
as a buffer memory for arithmetical result during the arithmetical operation.
128
80 step input buffer
Fixed memories
(L-V, 11
memories)
Fixed memories
(A-K, 11
memories)
Transfer buffer
040
04
8
8-digit display buffer
8-digit display buffer
8-digit display buffer
000
DISPLAY CHIP
3
DISPLAY CHIP
2
DISPLAY CHIP
1
•
Map of the RAM incorporated in the display chip
There are three lK-bit RAMs (128 bytes each) incorporated in each of display chips (SC43125),
having the following
configurations
:
9
Fig 2-3-1
The
numeri
ca
figure "4
", to be displayed by the CPU II,
is converted into the relevant character
code and carried through on the address data bus. First of
all
,
the segment Sl
is
selected with the
address
A8-Al "
00000000" to store the data DI04-DI01
"1000
"
in
t
he display buffer
(see Fig
.
2-3-1
). To store second half 4 bits of the
data, only
AS
in the address in turned "1
" to make the
address "00010000" to store data "0001 ". In the same
manner, the address "00000001"
is
selected
for storing the first half 4-
bit data
"O
100" for he segment S2 and the sec
ond half 4-bit data "000 I"
is
stored with the address "00010001 ".
S40
S32
S3
3
S34
Sl6
Sl7
Sl
8
1
S2
A5=0
A5=1
DI04 DI02 DI04 DI02
'--------..,..-~
Address
0
1
0
0 0
)
F
0
1
0 0
1
)
F
0
1
0
1
0
~
F
Al
I
A8
A7
A6 A4
Hl
DDD•D
H2
oo••
o
H3
o•o•
o
H4
•oo•o
H
5
•••••
H6
ooo•o
H7
ooo•o
Sl
S2 S3
S4 S5
Ex: Displaying numerical figure
"4"
There are 8 x
40=320 bits ( 40 bytes)
of area in the display buffer in the
display chip.
Disp
lay bu
ffer
XOOl 0100
H8 H7 H6 H5 H4 H3 H2
Hl
X
OOl 1000
Co
unter/
decoder
HA
T
he contents of disp
lay
indicated by the CPU
I is
received
by the CPU II
via the input buffer and
m
akes converted into
respecti
ve
character codes,
then they are carried over to the display buffer in
t
he disp
lay
chi
p through the address data
bus
.
• Designatio
n of the display data
The following structure is
observed in the display buffer in the display
chip
.
2-3. Display
the
ata.
'U
I
up
er
,
10
HA: Clock frequency for the counter. This signal
is
counted and decoded to perform sy
nchroni
-
zation with the comman
signal, Hl-H7, generated from the CPU II.
DSIP: With high level of this
signal, processing of display operation
is
indicated (RAM data
designated by
Hl-H8
is
sent out on SI
-S40).
The data stored in the display buffer
is
carried through
SI-S40
(Fig. 2-3-2) to be fed to
the LCD.
(To
indicate "4
" on the
display, H4 and HS are
engag
ed for SI,
H3 and HS
for S2,
etc.,
all the same
throughout
S6-S40.)
F
ig 2-3-
2
S
2
Sl
H7
H6
LJl....____flJ
L
I
H
5
LJ
H
4
H3
H
2
Hl
-----------
--------
-
--
GND
--
---
VA
--------.
-----------Vs
--------
Vn1SP
HA
DI SP
0.5ms
~
- -----
-3.9V
VDISP
VB
------
-2.lV
- - - --- -3.
9V
L_
VM
-------IV
...._
__ - - - --- -
2.8
V
6.8ms--
--
VA
-- ---
ov
...._
__ - - - --- -I.8V
11
E
ye positi
on
30
°
o
Adjustments of reference voltage VD ISP
The VDISP had been precisely adjusted to become -3.74V at an
ambient temperature of 20°C and -4.29V at 0°C.
In case there
is
a
n
eed of
readjusting the voltage after servicing the LCD or exchanging
some of power source
components, be sure to look on the LCD from
30° of angle from the ve
rtical line while adjusting the pot.
:D.
Low side voltage of common signals
(Hl-H7)
for
LCD
.
High side voltage for segment signals (Sl - S40)
Intermediate voltage of the common and
segment signals
Low side voltage of segment signals.
VA
,
VM and VB become pulses in an amplitude of several volts owing to influence
caused from the LSI.
VA:
VM:
VB
:
NOTE
:
ata
o The
liquid
crystal
reference voltage
VDISP
is
generated in the above
circuitry in order to
avoi
d
occurrence of such unpleasant phenomena
as
blurred character or contrast
variation that might
degrade display
performance, which
is
caused by a slight voltage variation in the liquid crystal
reference voltage VD ISP, since the
5 x 7
dot matrix liquid crystal
is
used in the disp
lay of this
pocket
computer.
A) VDD is
generated in the CPU
II
on the basis of VGG.
B) The gate vol
tage of MOS FET is
controlled by the 250KS1 pot to regurate the voltage for VDISP.
Furthermore, the voltage of VDISP
is
changed by the thermistor to meet with temperature
varia
-
tion,
so as to maintain proper display
performance
.
C) Line between the reference voltage VD ISP and GND
is divided by resistor to make ou
t VA, VM
and VB
.
V
DISP
:
20°
o
o
C PUil
Yoo
Relation between
ternperture
and VDISP
M
OS FET
ioo»
2-4. Power source
12
Pin No.
Signal name In/Out
Description
1
F4a Out
Chip Enable signal (RAM3 select signal)
2
F3a Out
Chip Enable signal (RAM2 select signal)
3
F2a Out
Chip Enable signal (RAM 1 select signal)
4
Fla
Out
Chip Enable signal (Display chip 1 select signal, for input
buffer and transfer buffer usage)
During
display: Low
/
- - - -
-
- -
During read-in: turns momentarily high
6
VGG
In
Source
voltage("-"
voltage of battery)
7
VGG
In
8
Xin
In
Basic clock (pulse signal in 256KHz)
9
TESTl
Connected with GND
10
TEST2
11
RESET In All reset switch input
Normally high but turns low when the all reset switch
is
depressed.
12
R/Wa
Out
RAM Data Read/Write signal
During display: High
________
Depression of the key causes it momentary
low!
13
DIO
l
In/Out
Data Bus (for address designation of the input buffer and
14
DI02
In/Out
transfer buffer in RAM and display chip 1 ).
15
DI03
In/Out
During display: High
\_
\_
\_
\_
\_
\_
\_
16
DI03
In/Out
During
read-in: Low
17
B8a
Out
Address Bus (for address designation
of
the input buffer and
18
B7a
Out transfer buffer in RAM and display chip 1 )
.
19
B6a
Out
20
BS
a
Out
During
display
:
___
Mementary generation
21
B
4a Out
22
B3a
Out During read-in
:
lllllllllll
l
llllllllllll
l
23
B2a Out
24
Bla
Out
30
GND
In
Source voltage
(OV)
40 S16a
Out
Busy signal to the CPU II (High during the execution in the
CPU
I)
During display: Low
During read-in: turns momentarily high
3. LSI SIGNAL DESCRIPTIONS
3-1. SC43157 (CPU
I)
13
Pin
No
.
Signal name
In
/Out
Description
1
F4
Out
Buzzer signal
When the buzzer
is
off: Low
----i
0. 2 5msl--
When the buzzer
is on:
LS1___J
2
F3
Out
Chip Enable signal (Display chip 3 select signal)
3
F2
Out
Chip Enable signal (Display chip 2 select signal)
4
Fl
Out
Chip Enable signal (Display chip 1 select signal)
During display: Low
----- ____
__
During read-in: Turns mementarily high
5
VDD
Out
For liquid crystal drive voltage preparation (VDD :; V GG)
6
VGG
In
Source
voltage("-"
voltage of the battery)
7
VGG
In
-
8
Xin
In
Basic clock (Pulse signal in 256KHz)
11
RESET
In
All reset switch input
3-2.
SC43178 (CPU
II)
Pin No.
Signal name
In/Out
Description
-
41
Sn Out
Key Strobe
signal, RAM Address signal
42
Si
Out
Key Strobe signal, RAM Address signal
43
Sl3 Out
Key Strobe signal
44
Sl2
Out
45
Sll
Out
During display: High
46 SlO
Out
Depression of the key causes it momentary low
47 S9
Out
48
S8 Out
49 S7 Out
50
S6 Out
51
SS
Out
52
S4 Out
53
S3
Out
54 S2
Out
55
Kil
In
Key input signal
56
Ki2 In
57
Ki3
In
During display: Low
58
Ki4
In
Depression of the key causes it momentary high
59
S16b
In
Busy signal of the CPU II (high during the execution
of
the
(Ki5)
CPU II)
I
During
display: Low
Depression
of
the key causes it momentary
high'.
n
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