SHARP PB2, PB2 A Diagram

PCB STACK UP

LAYER 1 : TOP LAYER 2 : SGND1 LAYER 3 : IN1 LAYER 4 : SVCC LAYER 5 : IN2

D D

LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT

CPU CORE MAX8736

SYSTEM POWER MAX8734

DDR II SMDDR_VTERM

1.8V/1.8VSUS(TPS51116)

VCCP +1.5V AND GMCH

C C

1.05V(TPS51124)

VGACORE(1.025V)MAX1993

SYSTEM CHARGER(MAX8672)

PAG 40

PAG 41

PAG 42

PAG 43

PAG 44

PAG 45,46

Voltage Rails

VCC_CORE VCCP

B B

SMDDR_VTERM

VGACORE VGA1.2

RVCC3

VCC1.25 VCC1.5 VCC1.8 VCC2.5 VCC3 VCC5

1.8VSUS 3VSUS

A A

5VSUS

3VPCU 5VPCU 15VPCU

ON S0~S2 Ctl Signal

X X X

X X

X X X X X X

X X X

ON S3 ON S4 ON S5

PCI DEVICES IRQ ROUTING

R5C832 INT A/B#

X X X

IDSEL#

AD17 REQ0# / GNT0#

DDRII-SODIMM1

DDRII-SODIMM2

SATA - HDD

PATA-

USB2.0 I/O Ports

VR_ON MAINON MAINON

MAINON MAINON

RVCCD

MAINON MAINON MAIND MAINON MAIND MAIND

SUSON SUSD SUSD

8734LDO5

5VPCU

PAG 12,13

PAG 33

CD-ROM

PAG 33

Express Card

Keyboard Touch Pad

InterruptsPCI DEVICE REQ# / GNT#

DDRII 533,667 MHz

SATA0 150MB

PATA

0,1,2,3

Bluetooth

WebCam

Mini_PCI_E

TV Tune

CIR

Flash

PAG 38

PAG 29

(66/100/133)

USB2.0

SPI

CPU Merom

478P (uPGA)/35W

NORTH BRIDGE

Crestline

PAG 5,6,7,8,9,10,11

DMI LINK

SOUTH BRIDGE

ICH-8M

PAG 20,21,22,23

LPC

ITE8512

PAGE 38

FAN

PAG 30

PAG 3,4

INT-MIC

PAG 35

MAX9789A

AUDIO Amplifier

PAG 35

HP Jack/ Speaker

PAG 35

CPU THERMAL SENSOR

PAG 30

PCI-Express 16X

CRT PORT

PCI BUS / 33MHz

PCI-E

Azalia

CONEXANT

CX20549

PAG 34

MDC DAA

CX20548

PAG 37

MODEM RJ 11

PAG 37

CLK_CPU_BCLK,CLK_CPU_BCLK# CLK_MCH_BCLK,CLK_MCH_BCLK#

DREFCLK,DREFCLK# DREFSSCLK,DREFSSCLK#

CLOCK GEN

ICS9LPR363DGLF 64pinsTSSOP

NVDIA NB8X

NB8P-SE-256M NB8M-SE-128M

P 15,16,17,18,19,20

DVI-I PORT

PAG 24

LCD CNN

PAG 32

PAG 24

PAG 25

RICOH

RICOH 832

PAG 26~28

TV Tune

Mini PCI-E Card

WLAN

PAG 31

LAN

Marvell

M8039

PAG 32

RJ45

PAG 32

MB PCB: DA0PB2MB8D0

SW/B PCB: DA0PB2PI8D0

USB/B PCB: DA0PB2TB8D0

TP/B PCB: DA0PB2TR8D0

256M MB:31PB2MB0010 PB2A/NB8P-SE MB:31PB2MB0020 128M

MB:31PB2MB0000

MB:31PB2MB0040 PB2/NB8M-SE Hynix

Size Document Number Rev

Date: Sheet

LVDS(1 Channel)

NBSRCCLK, NBSRCCLK#

IEEE1394

PAG 27

Memory CardReader

PAG 28

Express Card

PAG 28

USB:32PB2UB0000

TP:33PB2TB0000 SW:34PB2SB0000

/K0 /I0

PB2A/NB8P-SE Hynix

/L0

PB2/NB8M-SE

/J0

Quanta Computer Inc.

PROJECT : PB2

BLOCK DIAGRAM

E_SATA

PB2/PB2A BLOCK DIAGRAM

14.318MHz

PAG 2

HDMI CON

PAG 25

E_SATA JMB360

PAG 33

Infineon

146Friday, March 23, 2007

VCC3

L23

1 2

BLM21PG600SN1D(60,3A)

A A

VCC3 VDDA

B B

C425

C423

0.1U

10U

VCC3 VDDCPU

L25

1 2

BLM21PG600SN1D(60,3A)

L24

1 2

BLM21PG600SN1D(60,3A)

C434

C434 10U

10U

PDAT_SMB(22,28,31)

PCLK_SMB(22,28,31)

CPU Clock select

C C

D D

CPU_BSEL0(3)

VCCP

BSEL2 BSEL1 BSEL0 CPU

0 1

011

FSAFSBFSC

0 1 0 1 0

0 1

C452

C435

0.1U

VDDCPU

C450

0.1U

0.1U C445

C445

10U

VDDA

C442

0.1U

VCC3

R220

Q14

10K

2N7002E

Q15

2N7002E

266.66

133.33

200.00

166.66

333.33

100.00

400.00

10K

VCC3

R214 0R214 0 R217 *56R217 *56 R225 1K/FR225 1K/F

SRC

PCI

100

33.33

33.33 14.318 48 96

100

33.33 14.318 48 96

100

33.33 14.318 48 96

100

33.33 14.318 48 96

100

33.33 14.318 48 96

100

33.33 14.318 48 96

100

200.00 100 33.33

CLK_3.3V

C462

C449

0.1U

R216

R216 10K

10K

CGDAT_SMB

* Internal pull up to VDD **Internal pull down to GND

CLK_BSEL0CPU_BSEL0

REF

USB48DOT

14.318

14.318 48 96

C454

0.1U

PM_STPCPU#(22) PM_STPPCI#(22)

CLKUSB_48(22)

14M_ICH(22)

R222 0R222 0

Spread

0.5 Down

14.318MHz

BG614318Q33

C475 30PC475 30P

C474 30PC474 30P

CLK_3.3V

VDDCPU

R_DREFCLK

R_DREFCLK#

PWRSAVE#

PCIE_L6 PCIE_L8 PCIE_L4

BG614318Q33 XTL-5_3X3_2-3_8-1_2H

XTL-5_3X3_2-3_8-1_2H

14.318MHZ/20P

CLK_XIN

CLK_XOUT

CGCLK_SMB CGDAT_SMB

CLK_BSEL1 CLK_BSEL2

VDDA

R246 *10KR246 *10K R237 *10KR237 *10K

R242 10KR242 10K R219 10KR219 10K R233 10KR233 10K

PCIE_L7

CLK_XIN

CLK_XOUT

57 62

63 54

12 16 61

1 7

56 21 28 42 50

47 45

10 14

15 34

6 13 29 53 59 46

FCE P/N:BG614318F84

P/N:BG614318Q33

U10

ICS9PR363DGLF

X2 CPU_STOP#

PCI/PCIEX_STOP# SCLK

SDATA

FSA/USB_48MHZ FSB/TEST_MODE FSC/REF1/TEST_SEL

REF0

VDDPCI VDDPC1 VDD48

VDDREF VDDPCIEX VDDPCIEX VDDPCIEX VDDCPU

VREF VDDA

VTTPWR_GD/PD# PCIET_L9/DOTT_96MHZ

PCIEC_L9/DOTC_96MHZL *PWRSAVE#

GND GND GND GND GND GND GND GNDA

ALLPR363K00

VCC3 VCC3

ALLPR363K00

10/24 modify

PIN 5

(10K)

(NC)

CPUT_L0

CPUC_L0

CPUT_L1F CPUC_L1F

CPUITPT_L2/PCIET_L8

CPUITPC_L2/PCIEC_L8

27FIX/LCD_SSCGT/PCIET_L0 27SS/LCD_SSCGC/PCIEC_L0

SATACLKT_L SATACLKC_L

PCIET_L1 PCIEC_L1

PCIET_L2 PCIEC_L2

PCIET_L3 PCIEC_L3

PCIET_L4 PCIEC_L4

PCIET_L5 PCIEC_L5

PCIET_L6 PCIEC_L6

PEREQ1#/PCIET_L7 PEREQ2#/PCIEC_L7

*PEREQ3# *PEREQ4#

**REQ_SEL/PCICLK0

PCICLK1

*SELPCIEX0_LCD#/PCICLK3

*SELLCD_27#/PCICLK_F5

PCICLK2

ITP_EN/PCICLK_F4

P/N:ALLPR363K00 VER:D

PCIE_REQ3# PWRSAVE# SELPCIEX0_LCD#

96/100M

PCIE_REQ4#

PIN 9 Pin14/15

(10K)

LO HI

(NC) (10K) (NC)

PCIEX9

DOT96HI PCIEX9

DOT96

3/13 Modify 0==>33 ohm

RHCLK_CPU

RHCLK_CPU#

RHCLK_MCH

RHCLK_MCH#

RSRC_TV

RSRC_TV#

R_DREFSSCLK

R_DREFSSCLK#

RSRC_SATA

RSRC_SATA#

R_CLK_PCIE_VGA

R_CLK_PCIE_VGA#

CLK_PCIE_NEW

CLK_PCIE_NEW#

RSRC_ICH

RSRC_ICH#

CLK_PCIE_MINI_

CLK_PCIE_MINI_#

RSRC_MCH

RSRC_MCH#

RSRC1_LAN

RSRC1_LAN#

PCIE_JMB360

PCIE_JMB360#

40 32 33

R_PCLK_DEBUG PCLK_DEBUG

R_PCLK_R5C832

3 4

SELPCIEX0_LCD#

R_PCLK_ICH PCLK_ICH

R_PCI_CLK_8512 PCI_CLK_8512

R191 10KR191 10K

R197 *10KR197 *10K

R227 *10KR227 *10K R239 10KR239 10K

R195 10KR195 10K

RP47 4P2R-S-33RP47 4P2R-S-33

4 2

RP44 4P2R-S-33RP44 4P2R-S-33

4 2

RP42 4P2R-S-33RP42 4P2R-S-33

4 2

R218 33R218 33

RP45 *4P2R-S-33RP45 *4P2R-S-33

2 4

R215 33R215 33

RP37 4P2R-S-33RP37 4P2R-S-33

2 4

RP43 4P2R-S-33RP43 4P2R-S-33

2 4

RP41 4P2R-S-33RP41 4P2R-S-33

2 4

RP39 4P2R-S-33RP39 4P2R-S-33

2 4

RP35 4P2R-S-33RP35 4P2R-S-33

2 4

RP36 4P2R-S-33RP36 4P2R-S-33

4 2

RP38 4P2R-S-33RP38 4P2R-S-33

4 2

RP40 4P2R-S-33RP40 4P2R-S-33

R_PCIE_REQ3# R_PCIE_REQ4#CGCLK_SMB

R193 475/FR193 475/F

R194 475/FR194 475/F R247 22R247 22 R234 33R234 33

R232 22R232 22 R221 22R221 22

VCC3

3 1

1 3

3 1

3/16 Modify 33==>22 ohm

Pin17/187

27M

LCD PCIEX0 PCIEX0

CLK_CPU_BCLK (3) CLK_CPU_BCLK# (3)

CLK_MCH_BCLK (5) CLK_MCH_BCLK# (5)

CLK_PCIE_MINI_TV (31) CLK_PCIE_MINI_TV# (31)

VGA_27M_IN (14)

DREFSSCLK (6) DREFSSCLK# (6)

VGA_27M_SSIN (14)

CLK_PCIE_SATA (20) CLK_PCIE_SATA# (20)

CLK_PCIE_VGA (19) CLK_PCIE_VGA# (19)

CLK_PCIE_NEW_C (28) CLK_PCIE_NEW_C# (28)

CLK_PCIE_ICH (21) CLK_PCIE_ICH# (21)

CLK_PCIE_MINI_WLAN (31) CLK_PCIE_MINI_WLAN# (31)

CLK_PCIE_3GPLL (6) CLK_PCIE_3GPLL# (6)

CLK_PCIE_LAN (32) CLK_PCIE_LAN# (32)

CLK_PCIE_JMB360 (33) CLK_PCIE_JMB360# (33)

PCIE_REQ3# (28) PCIE_REQ4# (6)

PCLK_R5C832

3/16 Modify 15p==>10p

14M_ICH PCLK_DEBUG CLKUSB_48 PCI_CLK_8512 PCLK_ICH

PCLK_R5C832 (26)

PCLK_ICH (21) PCI_CLK_8512 (38)

C458 15PC458 15P C466 10PC466 10P C465 15PC465 15P C457 10PC457 10P C470 10PC470 10P

CLK_3.3V

C441

C438

0.1U

VCC3

R243

R235

*10K

CGCLK_SMB(13) CGDAT_SMB(13)

CLKUSB_48

CLK_BSEL0

14M_ICH

R203 1K/FR203 1K/F

VCC3

R204 220/FR204 220/F

CK_PWG(22)

DREFCLK(6)

DREFCLK#(6)

RP46 *4P2R-S-0RP46 *4P2R-S-0

VCC3

1 3

(96MHz)

R241 33R241 33 R236 2.2KR236 2.2K R223 10KR223 10K R229 10KR229 10K

R224 33R224 33

P/N:CS12202FB14 P/N:CS12202FB06

2 4

R_PCLK_DEBUG H:PEREQ

MCH_BSEL0 (6)

R_PCI_CLK_8512 L:27M H:PCI_E

L:PCI_E

R_PCLK_DEBUG R_PCI_CLK_8512 R_PCLK_ICH

ITP_EN(PIN8)

LOW : PIN43/44 SRC

HIGH : PIN43,44 CPUITP PCIE_REQ1# PCIE_REQ2#

PCIE_L0 PCIE_L1 PCIE_L2PCIE_REQ3#

PCIE_REQ4# PCIE_L5

PCIE_L3

1.Level 1 Environment-related Substances Should NEVER be Used.

2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.

PCLK_DEBUG (31)

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

CLOCK GENERATOR

Date: Sheet

PROJECT : PB2

246Friday, March 23, 2007

H_A#[3..16](5)

A A

H_ADSTB#0(5) H_REQ#[0..4](5)

H_A#[17..35](5)

B B

H_ADSTB#1(5)

H_A20M#(20)

H_FERR#(20)

H_IGNNE#(20) H_STPCLK#(20)

H_INTR(20) H_NMI(20) H_SMI#(20)

C C

Populate ITP700Flex for bringup

ITP_TDI ITP_TMS ITP_TCK ITP_TDO ITP_TRST#

H_RESET#

D D

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

VCCP

Layout Note: Place R4,R361,R346 & R7 close to CPU.

R167

R19251R192

51/F

R190 0R190 0

Layout Note: Place R8 close ITP.

R198 27/FR198 27/F R196 649/FR196 649/F

12 12

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

R189

R189 39/F

39/F

1 2

R170 22.6/FR170 22.6/F

1 2

ITP_TCK ITP_TRST#

U39A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

Merom Ball-out Rev 1a

R186

R186 150/F

150/F

*PAD

*PAD *PAD

*PAD

*PAD *PAD

*PAD

ADDR GROUP 0

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

THERMAL

PROCHOT#

THERMDA THERMDC

ICH

THERMTRIP#

H CLK

RESERVED

T82

T82 T84

T84 T89

T89 T85

T85 T87

T87

T79

T86

T86 T83

T83

ADS#

BNR#

BPRI#

DEFER#

F21

DRDY#

DBSY#

BR0#

D20

IERR#

INIT#

LOCK#

RESET#

RS[0]#

RS[1]#

RS[2]#

TRDY#

HIT#

HITM#

AD4

BPM[0]#

AD3

BPM[1]#

AD1

BPM[2]#

AC4

BPM[3]#

AC2

PRDY#

AC1

PREQ#

AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6

TRST#

C20

DBR#

D21 A24 B25

A22

BCLK[0]

A21

BCLK[1]

ITP debug signals

T91 *PADT91 *PAD T90 *PADT90 *PAD T202 *PADT202 *PAD T88 *PADT88 *PAD T201 *PADT201 *PAD T200 *PADT200 *PAD

H_IERR#

H_RESET#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET#

CPU_PROCHOT#CPU_PROCHOT# H_THERMDA H_THERMDC

PM_THRMTRIP#

R491 56R491 56

1 2

*PAD

T194

R485 56R485 56

1 2

R48675/F R48675/F

ITP_DBRESET#

ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5

H_ADS# (5) H_BNR# (5) H_BPRI# (5)

H_DEFER# (5) H_DRDY# (5) H_DBSY# (5) H_BR0# (5)

VCCP

H_INIT# (20) H_LOCK# (5) H_RESET# (5)

H_RS#0 (5) H_RS#1 (5) H_RS#2 (5) H_TRDY# (5)

H_HIT# (5) H_HITM# (5)

SYS_RST# (22)

VCCP

H_THERMDA (30)

H_THERMDC (30) PM_THRMTRIP# (6,20)

VCCP

CLK_CPU_BCLK (2) CLK_CPU_BCLK# (2)

R487 150/FR487 150/F

H_D#[0..63](5)

H_DSTBN#0(5) H_DSTBP#0(5) H_DINV#0(5)

H_D#[0..63](5)

Layout Note: Place voltage divider within

0.5" of GTLREF pin

VCCP

R499

VCC3

R499 1K/F

1K/F

1 2

R500

R500 2K/F

2K/F

1 2

R488 *1K/FR488 *1K/F

1 2

R489 *1K/FR489 *1K/F

1 2

C772 *0.1UC772 *0.1U

R490 *0R490 *0

1 2

Place C close to the CPU_TEST4 pin. Make sure CPU_TEST4 routing is reference to GND and away from other noisy signal.

FSB

H_DSTBN#1(5) H_DSTBP#1(5) H_DINV#1(5)

CPU_BSEL0(2)

CPU_TEST1 CPU_TEST2

CPU_TEST4

CPU_TEST6

BCLK

533 0 0 1133

166

667 800

200

ITP disable guidelines

Signal Resistor Value Connect To Resistor Placement

150 ohm +/- 5%

TDI

39 ohm +/- 1%

TMS

500-680ohm +/- 5%

TRST#

27 ohm +/- 1%

TCK TDO

150 ohm +/- 5%

VTT GND GND VTT

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

H_D#[0..63]

T198PAD T198PAD T80PADT80PAD

BSEL2 BSEL1 BSEL0

1 1

Within 2.0" of the ITPVTT Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP Within 2.0" of the ITP

U39B

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

V_CPU_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6

T81

PAD

T203PAD T203PAD

For the purpose of testability, route these signals through a ground referenced Z0 = 55ohm trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection.

U39B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CPU_TEST3 CPU_TEST5

DATA GRP 0 DATA GRP 1

DATA GRP 2DATA GRP 3

DSTBN[2]# DSTBP[2]#

DINV[2]#

DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

MISC

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]#

D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]#

SLP#

PSI#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0 COMP1 COMP2 COMP3

1 00

Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.

Size Document Number Rev

CPU

Date: Sheet of

Date: Sheet

H_D#[0..63]

Note: H_DPRTSTP need to daisy chain from ICH8 to IMVP6 to CPU.

R187

54.9/F

1 2

Quanta Computer Inc.

PROJECT : PB2

R188

27.4/F

1 2

H_D#[0..63] (5)

H_DSTBN#2 (5) H_DSTBP#2 (5) H_DINV#2 (5)

H_D#[0..63] (5)

H_DSTBN#3 (5) H_DSTBP#3 (5) H_DINV#3 (5)

H_DPRSTP# (6,20) H_DPSLP# (20) H_DPWR# (5) H_PWRGD (20) H_CPUSLP# (5) PM_PSI# (40)

R498

R497

54.9/F

27.4/F

1 2

346Friday, March 23, 2007

VCC_CORE

C416

C433

C433 10U

10U

C763

C763 10U

10U

C428

C428 10U

10U

A A

VCC_CORE

8 inside cavity, north side, secondary layer.

VCC_CORE

B B

VCC_CORE

C431

C431 10U

10U

C374

C374 10U

10U

C429

C429 10U

10U

C373

C373 10U

10U

8 inside cavity, south side, secondary layer.

VCC_CORE

C417

C417 10U

10U

C385

C385 10U

10U

6 inside cavity, north side, primary layer.

VCC_CORE

C C

C746

C746 10U

10U

C747

C747 10U

10U

6 inside cavity, south side, primary layer.

VCCP

C413

0.1U

C386

0.1U

Layout out: Place these inside socket cavity on North side secondary.

D D

10U

C764

C764 10U

10U

C767

C427

C427 10U

10U

C430

C430 10U

10U

C368

C368 10U

10U

C748

C748 10U

10U

C415

0.1U

C765

C765 10U

10U

C768

C768 10U

10U

C426

C426 10U

10U

C387

C387 10U

10U

C370

C370 10U

10U

C749

C749 10U

10U

C388

0.1U

C371

C371 10U

10U

C750

C750 10U

10U

C414

0.1U

VCC_CORE VCC_CORE

C766

C766 10U

10U

C376

C376 10U

10U

C432

C432 10U

10U

C375

10U

C372

C372 10U

10U

C751

C751 10U

10U

C389

0.1U

U39C

VCC[001]

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

VCC[010]

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

VCC[033]

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

VCC[042]

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

VCC_CORE (40) VCC1.5 (9,21,23,28,31,41,43) VCCP (2,3,5,6,8,9,20,23,43)

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

VCCSENSE

VSSSENSE

ICCODE: for Merom processors recommended design target is 44A

ICCP: 1before vccore stable peak current is 4.5A

2.after vccore stable

VCCP

continue current is

2.5A

C409

C409 330U/2.5V

330U/2.5V

ICCA 130mA

CPU_VID0 (40) CPU_VID1 (40) CPU_VID2 (40) CPU_VID3 (40) CPU_VID4 (40) CPU_VID5 (40) CPU_VID6 (40)

VCCSENSE (40)

VSSSENSE (40)

VCC_CORE

R502

R502 100/F

100/F

VCCSENSE VSSSENSE

R501

R501 100/F

100/F

Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.

VCC1.5

Layout Note: Place C105 near PIN B26.

C727

0.01U

C725

C725 10U

10U

U39D

A4 A8

A11 A14 A16 A19 A23 AF2

B6 B8

B11 B13 B16 B19 B21 B24

C5 C8

C11 C14 C16 C19

C22 C25

D1 D4 D8

D11 D13 D16 D19 D23 D26

E3 E6 E8

E11 E14 E16 E19 E21 E24

F5 F8

F11 F13 F16 F19

F22 F25

G4 G1

G23 G26

H3 H6

H21 H24

J2 J5

J22 J25

K1 K4

K23 K26

L3 L6

L21 L24

M5 M22 M25

N4 N23 N26

Size Document Number Rev

CPU

Date: Sheet of

Date: Sheet

VSS[082]

VSS[001] VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147] VSS[148]

VSS[067] VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

Merom Ball-out Rev 1a

Quanta Computer Inc.

PROJECT : PB2

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

446Friday, March 23, 2007

U38A

M10 N12

W10

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9 AE11 AH12

AH5

AE7

AE5

AH2 AH13

G2 G7 M6 H7 H3 G4

F3 N8 H2

N9 H5

P13

K9 M2

V4 M3

J1 N5 N3

W6 W9

Y7 Y9 P4

AJ9

AJ5 AJ6 AJ7

AJ2 AJ3

W1 W2

B6 E5

B9 A9

U38A

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

CRESTLINE_1p0

H_ADSTB#_0 H_ADSTB#_1

HOST

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0 H_RS#_1 H_RS#_2

J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_D#[0..63]

H_CPUSLP#(3)

C358

0.1U

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_RESET#(3)

H_REF

H_D#[0..63](3)

A A

VCCP

R177

R177 221/F

221/F

H_SWING

R180

R180 100/F

100/F

B B

VCCP

C398

0.1U

1 2

impedance 55 ohm

R495

R496

54.9/F

H_SCOMP H_SCOMP#

R176

24.9/F

C C

H_RCOMP

Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.

VCCP

R175

R175 1K/F

1K/F

1 2

R172

R172 2K/F

2K/F

H_A#[3..35]

H_ADS# (3) H_ADSTB#0 (3) H_ADSTB#1 (3) H_BNR# (3) H_BPRI# (3) H_BR0# (3) H_DEFER# (3) H_DBSY# (3) CLK_MCH_BCLK (2) CLK_MCH_BCLK# (2) H_DPWR# (3) H_DRDY# (3) H_HIT# (3) H_HITM# (3) H_LOCK# (3) H_TRDY# (3)

H_DINV#0 (3) H_DINV#1 (3) H_DINV#2 (3) H_DINV#3 (3)

H_DSTBN#0 (3) H_DSTBN#1 (3) H_DSTBN#2 (3) H_DSTBN#3 (3)

H_DSTBP#0 (3) H_DSTBP#1 (3) H_DSTBP#2 (3) H_DSTBP#3 (3)

H_REQ#0 (3) H_REQ#1 (3) H_REQ#2 (3) H_REQ#3 (3) H_REQ#4 (3)

H_RS#0 (3) H_RS#1 (3) H_RS#2 (3)

H_A#[3..35] (3)

965GM P/N:AJ0QN120T45

Layout Note: Place the 0.1 uF

D D

decoupling capacitor within 100 mils from GMCH pins.

965PM P/N:AJ0QN140T46

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

Date: Sheet of

Date: Sheet

PROJECT : PB2

546Friday, March 23, 2007

A A

WW22 update

--- MA14 needs to be routed if customers are planning on using 2Gb technology and width=8 (by 8) DIMMs

SA_MA14(12,13) SB_MA14(12,13)

VCCP

R106 0R106 0 R116 0R116 0

R126 0R126 0 R164 100R164 100

R168 *0R168 *0 R125 0R125 0

1 2 1 2

T186 PADT186 PAD T60 PADT60 PAD

R153 1K/F_4R153 1K/F_4 R162 1K/F_4R162 1K/F_4

T72

PAD

T195

PAD

T70

PAD

T78

PAD

T74

PAD

T69

PAD

T75

PAD

T76

PAD

T71

PAD

T68

PAD

T67

PAD

CRESTLINE new pin define

Layout Note:

B B

DELAY_VR_PWRGOOD(22,40)

C C

D D

Location of all MCH_CFG strap resistors needs to be close to minmize stub.

MCH_BSEL0(2)

MCH_CFG_5(11)

MCH_CFG_9(11)

MCH_CFG_12(11) MCH_CFG_13(11)

MCH_CFG_16(11)

MCH_CFG_19(11) MCH_CFG_20(11)

PM_BMBUSY#(22) H_DPRSTP#(3,20) PM_EXTTS#0(13) PM_EXTTS#1(13)

PLT_RST-R#(19,21)

PM_THRMTRIP#(3,20)

DPRSLPVR(22,40)

GMCH pwrok is 3.3v tolerant

VCC3

R124 10KR124 10K R130 10KR130 10K

CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20

PM_BMBUSY#_R ICH_DPRSTP#_R

PM_EXTTS#1_R

PLTRST_MCH# PM_THRMTRIP#_GMCH PM_DPRSLPVR_GMCH

PM_EXTTS#0 PM_EXTTS#1

P36 P37 R35

N35 AR12 AR13 AM12 AN13

J12 AR37 AM36

AL36

AM37

D20

H10 B51

BJ20 BK22 BF19 BH20 BK18

BJ18

BF23 BG23 BC23 BD24

BJ29 BE24 BH39

AW20

BK20

C48 D47 B44 C44 A35 B37 B36 B34 C34

P27 N27 N24 C21 C23 F23 N23

G23

J20 C20 R24

L23

J23 E23 E20 K23 M20 M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20 G36

BJ51 BK51 BK50

BL50

BL49

BL3 BL2 BK1 BJ1

A5 C51 B50 A50 A49 BK2

CRESTLINE_1p0

U38B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14

RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 SA-MA14 SB_MA14 RSVD34 RSVD35 RSVD36 LVDSA_DATA#_3 LVDSA_DATA_3 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16

SM_RCOMP_VOH

C306

0.01U

SM_RCOMP_VOL

C307

0.01U

C299

2.2U/10V

C283

2.2U/10V

CFGRSVD

SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4

SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4

SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3

SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3

SM_RCOMP

DDR MUXINGCLKDMI

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0 SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3

GFX_VR_EN

GRAPHICS VIDME

CL_PWROK

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

1.8VSUS

R134

R134 1K/F

1K/F

R142

3.01K/F

R122

R122 1K/F

1K/F

SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4

CL_CLK

CL_DATA CL_RST#

CL_VREF

TEST_1 TEST_2

AV29 BB23 BA25 AV23

AW30 BA23 AW25 AW23

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

SMRCOMPP

BL15

SMRCOMPN

BK14

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31

SMDDR_VREF_MCH

AR49 AW4

B42 C42 H48 H47

K44 K45

DMI_TXN0

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

DFGT_VID_0

E35

DFGT_VID_1

A39

DFGT_VID_2

C38

DFGT_VID_3

B39

DFGT_VR_EN

E36

AM49 AK50 AT43 AN49 AM50

MCH_CLVREF

H35 K36 G39 G40

A37 R32

M_A_CLK0 (13) M_A_CLK1 (13) M_B_CLK0 (13) M_B_CLK1 (13)

M_A_CLK0# (13) M_A_CLK1# (13) M_B_CLK0# (13) M_B_CLK1# (13)

M_A_CKE0 (12,13) M_A_CKE1 (12,13) M_B_CKE0 (12,13) M_B_CKE1 (12,13)

M_A_CS#0 (12,13) M_A_CS#1 (12,13) M_B_CS#0 (12,13) M_B_CS#1 (12,13)

M_A_ODT0 (12,13) M_A_ODT1 (12,13) M_B_ODT0 (12,13) M_B_ODT1 (12,13)

R179 *10K/FR179 *10K/F R182 *10K/FR182 *10K/F

DREFCLK (2) DREFCLK# (2) DREFSSCLK (2) DREFSSCLK# (2)

CLK_PCIE_3GPLL (2) CLK_PCIE_3GPLL# (2)

<check lisr & CRB> For Calero : 255 For Cresstline:1.3K/F For external VGA:0 ohm

CL_CLK0 (22)

CL_DATA0 (22) ECPWROK (15,22,38) CL_RST#0 (22,31)

T65T65 T63T63

PCIE_REQ4# (2) MCH_ICH_SYNC# (22)

R4790R479

R145

20K

1 2

VCC1.25

MCH_CLVREF

C244

0.1U

1 2

<check list & CRB> For Calero : 1.5K For Cresstline:2.4K

C399 0.1UC399 0.1U C406 0.1UC406 0.1U R183 0R183 0

1.8VSUS

DMI_TXN[3:0] (21)

DMI_TXP[3:0] (21)

DMI_RXN[3:0] (21)

DMI_RXP[3:0] (21)

R147 *0R147 *0

<FAE> Flexible and safe

IV&EV Dis/Enable setting

T64T64 T189T189 T190T190 T188T188 T191T191

R471

R471 1K/F

1K/F

R472

R472 392/F

392/F

In Crestline EDS Rev.1.0, Render Standby Voltage is not finalized yet(TBD), 1.05V for Graphic Voltage range(VCC_AXG) is between 0.9975V(min.) and 1.1025V(max.). Vgfx max at 1.1025V @ 8A (estimated)

only resever AT3/5 not support IAMT,but design line suggest to connection these pin ,do not NC

CLKREQ# ( MCH drives CLK_REQ# to control the PCI-E diff clk input itself )

R169

R169 20/F

20/F

SMRCOMPP SMRCOMPN

R173

R173 20/F

20/F

VCC3

SMDDR_VREF (13,42)

VCC3

CRT_B(14,24) CRT_G(14,24) CRT_R(14,24)

DVICLK(14,24) DVIDAT(14,24)

HSYNC_COM(14,24) VSYNC_COM(14,24)

1.8VSUS

BLON(15,25)

EDIDCLK(15,25) EDIDDATA(15,25)

DIGON(15,25)

R112 *2.4KR112 *2.4K

IV&EV Dis/Enable setting

For 965GM TV disable

R128 *2.2KR128 *2.2K R135 *2.2KR135 *2.2K

<FAE> If no use can be NC

R87 *0R87 *0 R86 *0R86 *0 R85 *0R85 *0

T62T62 R113 *0R113 *0 R120 *10KR120 *10K R115 *10KR115 *10K R118 *0R118 *0 R123 *0R123 *0 R110 *0R110 *0

T61

LA_CLK#(14) LA_CLK(14)

LA_DATAN0(14) LA_DATAN1(14) LA_DATAN2(14)

LA_DATAP0(14) LA_DATAP1(14) LA_DATAP2(14)

R596 *75/FR596 *75/F R597 *75/FR597 *75/F R599 *75/FR599 *75/F

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE1 CRT_GREEN1 CRT_RED1

R114 *0R114 *0 R119 *0R119 *0

R132 *39R132 *39 R138 *39R138 *39

<check list> HSYNC/VSYNC serial R place close to NB

DREFSSCLK DREFSSCLK#

<FAE> If no use DREFCLK PU and DREFCLK# PD

IV&EV Dis/Enable setting

DREFCLK DREFCLK#

<design guide> If no use DREFCLK PU and DREFCLK# PD

J40 H39 E39 E40 C37 D35 K40

LVDS_IBG

L41

*PAD

L43 N41 N40 D46 C45 D44 E42

G51 E51

F49

G50 E50

F48

G44 B47 B45

E44 A47 A45

E27 G27 K27

F27

J27

L27 M35

P33

H32 G32 K29

J29

F29 E29

DDCCLK_R

K33

DDCDATA_R

G35

HSYNC11

F33

CRTIREF

C32

VSYNC11

E33

R101 4.7KR101 4.7K R103 4.7KR103 4.7K

R111 4.7KR111 4.7K R104 4.7KR104 4.7K

U38C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN

LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN TVB_RTN TVC_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CRESTLINE_1p0

1.8VSUS (8,9,13,41,42) VCC1.25 (9,23,43) VCC3 (2,3,8,9,11,13,14,15,16,19,20,21,22,23,24,25,26,28,30,31,33,38,40,41)

VCC1.25

LVDS

TV VGA

N43

PEG_COMPI

PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

R144 0R144 0 R143 0R143 0

R137 0R137 0 R149 0R149 0 R150 0R150 0

M43

J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

PEG_COMPO

PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PCI-EXPRESS GRAPHICS

<check list> For EV@ Connect to GND CRT R/G/B TV A/B/C HSYNC/VSYNC

Size Document Number Rev

Date: Sheet

+VCC_PEG

PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15

PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15

R105 24.9/FR105 24.9/F

1 2

C229 0.1UC229 0.1U C697 0.1UC697 0.1U C231 0.1UC231 0.1U C699 0.1UC699 0.1U C701 0.1UC701 0.1U C232 0.1UC232 0.1U C235 0.1UC235 0.1U C703 0.1UC703 0.1U C237 0.1UC237 0.1U C705 0.1UC705 0.1U C239 0.1UC239 0.1U C707 0.1UC707 0.1U C709 0.1UC709 0.1U C241 0.1UC241 0.1U C695 0.1UC695 0.1U C243 0.1UC243 0.1U

C228 0.1UC228 0.1U C696 0.1UC696 0.1U C230 0.1UC230 0.1U C698 0.1UC698 0.1U C700 0.1UC700 0.1U C233 0.1UC233 0.1U C234 0.1UC234 0.1U C702 0.1UC702 0.1U C236 0.1UC236 0.1U C704 0.1UC704 0.1U C238 0.1UC238 0.1U C706 0.1UC706 0.1U C708 0.1UC708 0.1U C240 0.1UC240 0.1U C694 0.1UC694 0.1U C242 0.1UC242 0.1U

PEG_RXN0 (19) PEG_RXN1 (19) PEG_RXN2 (19) PEG_RXN3 (19) PEG_RXN4 (19) PEG_RXN5 (19) PEG_RXN6 (19) PEG_RXN7 (19) PEG_RXN8 (19) PEG_RXN9 (19) PEG_RXN10 (19) PEG_RXN11 (19) PEG_RXN12 (19) PEG_RXN13 (19) PEG_RXN14 (19) PEG_RXN15 (19)

PEG_RXP0 (19) PEG_RXP1 (19) PEG_RXP2 (19) PEG_RXP3 (19) PEG_RXP4 (19) PEG_RXP5 (19) PEG_RXP6 (19) PEG_RXP7 (19) PEG_RXP8 (19) PEG_RXP9 (19) PEG_RXP10 (19) PEG_RXP11 (19) PEG_RXP12 (19) PEG_RXP13 (19) PEG_RXP14 (19) PEG_RXP15 (19)

PEG_TXN_C0 (19) PEG_TXN_C1 (19) PEG_TXN_C2 (19) PEG_TXN_C3 (19) PEG_TXN_C4 (19) PEG_TXN_C5 (19) PEG_TXN_C6 (19) PEG_TXN_C7 (19) PEG_TXN_C8 (19) PEG_TXN_C9 (19) PEG_TXN_C10 (19) PEG_TXN_C11 (19) PEG_TXN_C12 (19) PEG_TXN_C13 (19) PEG_TXN_C14 (19) PEG_TXN_C15 (19)

PEG_TXP_C0 (19) PEG_TXP_C1 (19) PEG_TXP_C2 (19) PEG_TXP_C3 (19) PEG_TXP_C4 (19) PEG_TXP_C5 (19) PEG_TXP_C6 (19) PEG_TXP_C7 (19) PEG_TXP_C8 (19) PEG_TXP_C9 (19) PEG_TXP_C10 (19) PEG_TXP_C11 (19) PEG_TXP_C12 (19) PEG_TXP_C13 (19) PEG_TXP_C14 (19) PEG_TXP_C15 (19)

VCC3G_PCIE_R

C_PEG_TXN0 C_PEG_TXN1 C_PEG_TXN2 C_PEG_TXN3 C_PEG_TXN4 C_PEG_TXN5 C_PEG_TXN6 C_PEG_TXN7 C_PEG_TXN8 C_PEG_TXN9 C_PEG_TXN10 C_PEG_TXN11 C_PEG_TXN12 C_PEG_TXN13 C_PEG_TXN14 C_PEG_TXN15

C_PEG_TXP0 C_PEG_TXP1 C_PEG_TXP2 C_PEG_TXP3 C_PEG_TXP4 C_PEG_TXP5 C_PEG_TXP6 C_PEG_TXP7 C_PEG_TXP8 C_PEG_TXP9 C_PEG_TXP10 C_PEG_TXP11 C_PEG_TXP12 C_PEG_TXP13 C_PEG_TXP14 C_PEG_TXP15

IV&EV Dis/Enable setting

<check list> SDVO/PCIE/LVDS not implement 16 lanes NC

<check list> For IV@ Connect to 150ohm CRT R/G/B TV A/B/C Connect to 0ohm HSYNC/VSYNC

HSYNC11 VSYNC11

CRT_BLUE1 CRT_GREEN1 CRT_RED1

Quanta Computer Inc.

PROJECT : PB2

646Friday, March 23, 2007

M_A_DQ[63:0](13) M_B_DQ[63:0](13)

A A

B B

C C

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AR43

AW44

BA45 AY46 AR41 AR45

AT42

AW47

BB45

BF48

BG47

BJ45 BB47 BG50 BH49 BE45

AW43

BE44 BG42 BE40

BF44 BH45 BG40

BF40 AR40

AW40

AT39

AW36 AW41

AY41 AV38

AT38 AV13

AT13

AW11

AV11 AU15

AT11 BA13 BA11 BE10 BD10

BG10

AW9

AM8

AN10

AN9 AM9

AN11

BD8 AY9

BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3

AT9

U38D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS# SA_DM_0

SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16

BE18 AY20

BA19

M_A_DQM0 M_A_DQM1 M_A_DQM2 M_A_DQM3 M_A_DQM4 M_A_DQM5 M_A_DQM6 M_A_DQM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

TP_SA_RCVEN#

M_A_BS#0 (12,13) M_A_BS#1 (12,13) M_A_BS#2 (12,13) M_A_CAS# (12,13)

M_A_DQM[0..7] (13)

M_A_DQS[7:0] (13)

M_A_DQS#[7:0] (13)

M_A_A[13:0] (12,13)

M_A_RAS# (12,13)

T73T73

M_A_WE# (12,13)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AP49

AR51 AW50 AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50 BJ44

BJ43 BL43 BK47 BK49 BK43 BK42

BJ41 BL41

BJ37

BJ36 BK41

BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

BJ10

BK10

BG1 BC2 BK3 BE4 BD3

BA3 BB3 AR1

AY2 AY3 AU2

BL9 BK5 BL5 BK9

BJ8 BJ6 BF4 BH5

BJ2

AT3

AT2

U38E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS# SB_DM_0

SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13

AV16 AY18

BC17

M_B_DQM0 M_B_DQM1 M_B_DQM2 M_B_DQM3 M_B_DQM4 M_B_DQM5 M_B_DQM6 M_B_DQM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13

TP_SB_RCVEN#

M_B_BS#0 (12,13) M_B_BS#1 (12,13) M_B_BS#2 (12,13)

M_B_CAS# (12,13) M_B_DQM[0..7] (13)

M_B_DQS[7:0] (13)

M_B_DQS#[7:0] (13)

M_B_A[13:0] (12,13)

M_B_RAS# (12,13)

T77T77

M_B_WE# (12,13)

D D

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

Date: Sheet of

Date: Sheet

PROJECT : PB2

746Friday, March 23, 2007

VCCP

D D

IVCCSM supply current 1 channel

1.615A 2 channel

3.318A

C C

B B

A A

1.8VSUS

+VGFX_CORE_INT

AT35 AT34 AH28 AC32 AC31 AK32

AJ31

AJ28 AH32 AH31 AH29 AF32

AU32 AU33 AU35 AV33

AW33 AW35

AY35 BA32 BA33 BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35 BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35

BJ32

BJ33

BJ34 BK32 BK33 BK34 BK35 BL33 AU30

W13 W14

AA20 AA23 AA26 AA28 AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23 AH24 AH26 AD31

AJ20 AN14

R30

R20 T14

Y12

U38G

VCC_1 VCC_2 VCC_3 VCC_5 VCC_4 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55

VCC GFX NCTF

VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 VCC_AXG_NCTF_61 VCC_AXG_NCTF_62 VCC_AXG_NCTF_63 VCC_AXG_NCTF_64 VCC_AXG_NCTF_65 VCC_AXG_NCTF_66 VCC_AXG_NCTF_67 VCC_AXG_NCTF_68 VCC_AXG_NCTF_69 VCC_AXG_NCTF_70 VCC_AXG_NCTF_71 VCC_AXG_NCTF_72 VCC_AXG_NCTF_73 VCC_AXG_NCTF_74 VCC_AXG_NCTF_75 VCC_AXG_NCTF_76 VCC_AXG_NCTF_77 VCC_AXG_NCTF_78 VCC_AXG_NCTF_79 VCC_AXG_NCTF_80 VCC_AXG_NCTF_81 VCC_AXG_NCTF_82 VCC_AXG_NCTF_83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31

AW45 BC39 BE39 BD17 BD4 AW8 AT6

Ivcc_AXG Graphics core supply current 7.7A

C419

C419 *330U/2.5V

*330U/2.5V

H=1.9mm

P/N:CH733LM8812

Layout Note: Inside GMCH cavity for VCC_AXG.

C336

C316

*0.1U

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

12.313SUM

C362

0.1U

VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

Ivcc (External GFX 1.310 A, integrate 1.572 A)

Layout Note: 370 mils from edge.

C331

C331 *0.47U/10V

*0.47U/10V

R5980R598 0

C314

C314 *1U

*1U

VCCP

C759

C759 220U/2.5V

220U/2.5V

+VGFX_CORE_INT

Layout Note: 370 mils from edge.

C411

C411 *10U

*10U

Remark

( 1.3A for external GFX )

for integrated Gfx

Ivcc_AXM Controller supply current 540mA

FSB VCCP

for PCIEG

for IAMT function

DMI

C354

0.1U

C402

0.22U/10V

C340

0.22U/10V

C281

0.47U/10V

VCC3

R493 10R493 10

1 2

C740

C740 22U/6.3V

22U/6.3V

Layout Note: Inside GMCH cavity.

R185 *0R185 *0 R184 *0R184 *0

C412

C412 *22U/6.3V

*22U/6.3V

Layout Note: Place close to GMCH edge.

C2821UC282 1U

+VCC_GMCH_L

C290

0.22U/10V

for IAMT power if not support need to connection to S0 power

VCCP

C288

0.1U

C296

C296 22U/6.3V

22U/6.3V

C2621UC262 1U

CH751H-40HPT

C275

0.22U/10V

VCCP

A test check when use external VGA can remove or not.. andrew

Layout Note: Inside GMCH cavity.

C285

0.1U

C320

0.22U/10V

D17

C303

0.1U

C305

0.1U

C297

0.22U/10V

1.8VSUS

C310

0.1U

Layout Note: Place C901 where LVDS and DDR2 taps.

U38F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

C771

C771 330U/2.5V

330U/2.5V

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16

VSS NCTF

VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21

VCC NCTF

POWER

VSS_SCB1 VSS_SCB2 VSS_SCB3 VSS_SCB4 VSS_SCB5 VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1 VCC_AXM_2 VCC_AXM_3 VCC_AXM_4 VCC_AXM_5 VCC_AXM_6 VCC_AXM_7

VCC AXM NCTF

1.8VSUS

Layout Note: Place on the edge.

C319

C319 22U/6.3V

22U/6.3V

C329

C329 22U/6.3V

22U/6.3V

T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28

A3 B2 C1 BL1 BL51 A51

VCCP

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

CRESTLINE_1p0

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

Date: Sheet of

Date: Sheet

PROJECT : PB2

846Friday, March 23, 2007

IV&EV Dis/Enable setting

L36

1 2

*BLM18PG181SN1

+VCC_TVBG

50mA

+1.25V_VCCA_HPLL

C769

C769 22U/10V

22U/10V

150mA

+1.25V_VCCA_MPLL

+VCCA_MPLL_L

C284

0.1U

+VCCQ_TVDAC

C317

C317 *0.1U

*0.1U

+3V_VCCSYNC

C756

0.1U

C757

0.1U

+1.5V_VCCD_TVDAC

R121 0R121 0

1 2

C298

C298 *0.1U

*0.1U

C726

C726 *0.1U

*0.1U

VCC1.25

R141 *0R141 *0

VCC3

<FAE> INT VGA disable VCCSYNC connect to GND

D D

VCC3

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

+3V_TV_DAC

VCC1.25

C C

VCC1.5

B B

FB_180ohm+-25%_ 100mHz_1500mA_

0.09ohm DC

R492

*0.03/F

FB_120ohm+-25%_100mHz _200mA_0.2ohm DC

L38

BLM11A121S

L39

L39 BLM11A121S

BLM11A121S

R494

0.5/F/0603

1 2

+VCCA_MPLL_L

C770

C770 22U/10V

22U/10V

L18

1 2

*BLM18PG181SN1

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

L37

VCC3

1 2

*BLM18PG181SN1

22nF & 0.1uF for VCC_TVDACA:C_R should be placed with in 250 mils from Crestline.

+3V_TV_DAC

C732

C732 *10U

*10U

IV&EV Dis/Enable setting

A A

R1310R131 0

R480 *0R480 *0

+VCCA_CRTDAC

C722

C722 *0.1U

*0.1U

R483 *0R483 *0

L14*0L14 *0

10uH+-20%_100mA

L34*0L34 *0

0.1Caps should be placed 200 mils with in its pins.

VCC1.25

100U/6.3V-3528

R152 0R152 0

+1.5V_VCCD_TVDAC

R1590R159 0

1 2

C424

1.8VSUS

R4840R484 0

+1.25V_VCCA_DPLLA

C256

*470U/4V

+1.25V_VCCA_DPLLB

C693

*470U/4V

R178 0R178 0

C300

C300 22U/6.3V

22U/6.3V

+VCCA_MPLL_L

R4820R482

80mA

C251

0.1U

80mA

C248

0.1U

250mA

R100 *0R100 *0

+3V_VCCA_CRT_DAC

+1.8VSUS_VCC_TX_LVDS

C332

4.7U

1 2

C3131UC313

C3021UC302 1U

R146 0R146 0 R136 *0R136 *0

C259

C259 *1U

*1U

VCC1.25

FB_220ohm+-25%_100MHz _2A_0.1ohm DC

+1.8VSUS_VCC_TX_LVDS

IV&EV Dis/Enable setting

10mA

R4760R476

+1.25V_VCCD_PEG_PLL

+1.25V_VCCA_SM

C410

C410 22U/6.3V

22U/6.3V

+1.25V_VCCA_SM_CK

C311

VCC3

0.1U

C258

0.1U

C261

C261 *10U

*10U

L33

1 2

BLM21PG600SN1D(60,3A)

+1.5V_VCCD_CRT +1.5V_VCCD_TVDAC

+1.5V_VCCD_QDAC +VCCA_MPLL_L +1.25V_VCCD_PEG_PLL

VCC3

C252

0.1U

Ivcca_PEG_BG supply current 100mA

C350

C350 22U/6.3V

22U/6.3V

C762

0.1U

CRT/TV Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

VCCA_CRT_DAC

VCCD_CRT

+1.25V_VCCA_DPLLA +1.25V_VCCA_DPLLB +1.25V_VCCA_HPLL +1.25V_VCCA_MPLL

C716

C716 *1000P

*1000P

100mA

C3441UC344 1U

R151 *0R151 *0 R148 0R148 0

+1.8V_VCCD_LVDS

150mA

R1070R107 0

100mA

R464

R464 1/F/0603

1/F/0603

C685

C685 10U/6.3V

10U/6.3V

Ball

U38H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

+1.25V_VCCD_PEG_PLL

C253

0.1U

Enable

3.3V

1.5V

3.3V

+VTTLF1 +VTTLF2 +VTTLF3

Disable

GND VCCA_TVC_DAC

GND

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

C758

0.47U/10V

Ball

VCCD_TVDAC

VCCA_DAC_BG

VSS_DAC_BG

VCCSYNC

AXD

VCC_AXD_NCTF

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

PEG

VCC_RXR_DMI_1 VCC_RXR_DMI_2

DMI

CRESTLINE_1p0

C384

0.47U/10V

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14

VTT

VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22

VCC_AXD_1 VCC_AXD_2 VCC_AXD_3 VCC_AXD_4 VCC_AXD_5 VCC_AXD_6

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

VCC_DMI

VCC_HV_1 VCC_HV_2

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5

VTTLF1 VTTLF2 VTTLF3

VTTLF

Enable

3.3V

1.5V

3.3VVCCD_QDAC

GNDVCCA_TVA_DAC

3.3VVCCA_TVB_DAC

U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

BK24 BK23 BJ24 BJ23

A43

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

A7 F2 AH1

C742

0.47U/10V

Disable

+3V_VCC_HV

GND

1.5V

GND

C352

2.2U/6.3V

Place on the edge.

C361

0.1U

Place on the edge.

+1.25V_AXD

C3241UC324 1U

+1.25V_VCC_AXF

+1.25V_VCC_DMI

+1.8VSUS_VCC_SM_CK

200mA

+1.8VSUS_VCC_TX_LVDS

C717

0.1U

+VCC_RXR_DMI

+VTTLF1 +VTTLF2 +VTTLF3

LVDS Disable/Enable guideline

External VGA with EV@part,Internal VGA with IV@ part

VCCD_LVDS VCCA_LVDS VCC_TX_LVDS

Signal

If SDVO Disable LVDS Disable

GND GND GND

If LVDS enable

1.8V

+3V_VCC_HV

D7 CH751H-40HPT_NC

CH751H-40HPT_NC

Ivcc_VTT FSB

supply

C761

4.7U

C760

4.7U

C339

C339 22U/10V

22U/10V

R4750R475 0

C222

C222 220U/2.5V

220U/2.5V

C227

C227 220U/2.5V

220U/2.5V

current

0.85A

VCCP

C418

C418 220U/2.5V

220U/2.5V

R174 0R174 0

Place caps close to VCC_AXD.

Ivcc_DMI supply current 100mA

R470 0R470 0

C710

0.1U

+1.8VSUS_VCC_TX_LVDS

100mA

C715

C715 *1000P

*1000P

+VCC_PEG

R5420R542

91uH+-20%_1.5A

C268

C268 10U/6.3V

10U/6.3V

R5690R569

91uH+-20%_1.5A

C249

C249 10U/6.3V

10U/6.3V

+1.8VSUS_VCC_SM_CK

C334

C334 22U/10V

22U/10V

C333

0.1U

VCC1.25

L35 *0L35 *0

1uH+-20%_300mA

C712

C712 *220U/6.3V

*220U/6.3V

VCCP

L190L19 0

1uH+-20%_300mA

R163

R163 1/F/0603

1/F/0603

+VCC_SM_CK_L

C330

C330 10U/6.3V

10U/6.3V

+3V_VCC_HV

R478 0R478 0

VCC1.25

1.8VSUS

IV&EV Dis/Enable setting

Ivcc_PEG supply current

1.2A

Ivcc_RX_DMI supply current 250mA

1.8VSUS

VCCP

R9610R96 10

VCC3

VCC1.25

+1.25V_VCC_AXF

C3421UC342 1U

Place caps close to VCC_AXF

C343

C343 10U/6.3V

10U/6.3V

40 mil wide

+3V_VCC_HV_L

R1580R158

Quanta Computer Inc.

PROJECT : PB2

946Friday, March 23, 2007

Size Document Number Rev

Date: Sheet

U38I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

D D

C C

B B

A A

AB20 AB23 AB26 AB28 AB31 AC10 AC13

AC3 AC39 AC43

AC47

AD1 AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8 AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43 AG47 AG50

AH3 AH40 AH41

AH7

AH9

AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45

AJ49 AK20 AK21 AK26 AK28 AK31 AK51

AM11 AM13

AM3

AM4 AM41 AM45

AN1 AN38 AN39 AN43

AN5

AN7

AP4

AP48 AP50

AR11

AR2 AR39 AR44 AR47

AR7

AT10 AT14 AT41 AT49

AU1 AU23 AU29

AU3 AU36 AU49 AU51

AV39 AV48

AW1 AW12 AW16

AL1

VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CRESTLINE_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41

U38J

C46

VSS_199

C50

VSS_200

VSS_201

D13

VSS_202

D24

VSS_203

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

VSS_217

F40

VSS_218

F50

VSS_219

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

VSS_231

H24

VSS_232

H28

VSS_233

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

VSS_247

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

VSS_260

M50

VSS_261

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

VSS_272

P19

VSS_273

VSS_274

P23

VSS_275

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

VSS_285

VSS_286

CRESTLINE_1p0

VSS

VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305

VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

Date: Sheet of

Date: Sheet

PROJECT : PB2

10 46Friday, March 23, 2007

Strap table

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal CFG[17:3] Have internal Pull-up

CFG[18:19] Have internal Pull-down Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description

D D

CFG[2:0]

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

C C

CFG[13:12]

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

B B

DMI X2 Select

MCH_CFG_5 Low = DMIX2

MCH_CFG_5(6)

High = IDMIX4(Default)

R156

R156 *4.02K/F

*4.02K/F

FSB Dynamic ODT

MCH_CFG_16 Low = ODT Disable

A A

MCH_CFG_16(6)

High = ODT Enable(Default)

R161

R161 *4.02K/F

*4.02K/F

FSB Frequency Select

Reserved

DMI X2 Select

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

DMI Lane Reversal

MCH_CFG_19 Low = Normal operation(Default)

MCH_CFG_19(6)

SDVO/PCIE Concurrent operation

MCH_CFG_20

MCH_CFG_20(6)

High = Reverse Lane

VCC3

R129

R129 *4.02K/F

*4.02K/F

Low = Only SDVO or PCIE X1 is operational(Default) High = SDVO andPCIE X1 are operating simultaneously via the PEG port

VCC3

R127

R127 *4.02K/F

*4.02K/F

Configuration

010 = FSB 800MHz 011 = FSB 667MHz

0 = DMI X2 1 = DMI X4(Default)

0 = Reserved 1 = Mobile CPU(Default)

0 = Normal mode 1 = Low Power mode

0 = Reverse Lanes 1 = Normal operation(Default)

00 = Reserved 01 = XOR Mode Enable 10 = All-Z Mode Enabled 11 = Normal operation(Default)

0 = Dynamic ODT disable 1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default) 1 = SDVO Card Present

0 = Normal operation(Default) 1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default) 1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

XOR /ALLz /Clock Un-gating

MCH_CFG_12MCH_CFG_13 Configuration

MCH_CFG_12(6) MCH_CFG_13(6)

Clock gating disable

XOR Mode Enable

ALL-z Mode Enable

Normal operation(Default)

R155

R155 *4.02K/F

*4.02K/F

R157

R157 *4.02K/F

*4.02K/F

PCI Express Graphics

MCH_CFG_9 Low = Reverse Lane

High = Normal operation(Default)

MCH_CFG_9(6)

SDVO Present

Strap define at External DVI control page

R160

R160 *4.02K/F

*4.02K/F

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

Date: Sheet

PROJECT : PB2

11 46Friday, March 23, 2007

C407

0.1U

DDRII DUAL CHANNEL A,B.

A A

M_B_A[13..0]

1.8VSUS VCC3

DDRII A CHANNEL

SMDDR_VTERM

C347

0.1U

C408

0.1U

SMDDR_VTERM

C337

C367

0.1U

M_A_A[13..0] SMDDR_VTERM

C365

C353

0.1U

C359

0.1U

M_A_A[13..0] (7,13) SMDDR_VTERM (42)

C338

C396

0.1U

C335

0.1U

C395

0.1U

C366

0.1U

C381

0.1U

SMDDR_VTERM

M_B_A[13..0] (7,13)

1.8VSUS (6,8,9,13,41,42) VCC3 (2,3,6,8,9,11,13,14,15,16,19,20,21,22,23,24,25,26,28,30,31,33,38,40,41)

DDRII B CHANNEL

C379

C397

0.1U

C379

0.1U

C380

0.1U

C341

0.1U

C382

0.1U

C394

0.1U

C348

0.1U

C357

0.1U

C360

0.1U

C404

0.1U

C349

0.1U

C403

0.1U

Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM

B B

M_A_ODT0(6,13)

M_A_CKE1(6,13)

M_A_CAS#(7,13)

M_A_RAS#(7,13)

M_A_BS#1(7,13)

C C

M_A_WE#(7,13) M_A_BS#0(7,13)

M_A_ODT0 M_A_A13 M_A_A8 M_A_A5 M_A_A3 M_A_A1

M_A_CKE1 M_A_A11 M_A_A10

M_A_A7 M_A_A6 M_A_A2 M_A_A4

M_A_BS#1 M_A_A9 M_A_A12

M_A_BS#0

RP32 56X2RP32 56X2

1 3

RP17 56X2RP17 56X2

1 3

RP22 56X2RP22 56X2

1 3

RP13 56X2RP13 56X2

3 1

RP30 56X2RP30 56X2

3 1

RP18 56X2RP18 56X2

3 1

RP20 56X2RP20 56X2

1 3

RP28 56X2RP28 56X2

3 1

RP14 56X2RP14 56X2

3 1

RP26 56X2RP26 56X2

1 3

2 4 2 4 2 4

4 2 4 2 4 2 2 4

4 2 4 2 2 4

SMDDR_VTERM

M_B_BS#1(7,13)

M_B_BS#2(7,13)

M_B_CKE0(6,13) M_B_RAS#(7,13)

M_B_CS#0(6,13) M_B_BS#0(7,13)

M_B_WE#(7,13)

M_B_CAS#(7,13)

M_B_A0 M_B_A3 M_B_A1 M_B_A8 M_B_A5

M_B_A4 M_B_A2 M_B_A12 M_B_A9 M_B_A7 M_B_A6

M_B_A10

RP23 56X2RP23 56X2

1 3

RP21 56X2RP21 56X2

1 3

RP16 56X2RP16 56X2

1 3

RP19 56X2RP19 56X2

1 3

RP12 56X2RP12 56X2

1 3

RP15 56X2RP15 56X2

1 3

RP9 56X2RP9 56X2

1 3

RP27 56X2RP27 56X2

3 1

RP25 56X2RP25 56X2

1 3

RP29 56X2RP29 56X2

3 1

2 4 2 4 2 4

2 4 2 4 2 4 2 4

4 2 2 4 4 2

SMDDR_VTERM

R165 56R165 56

SB_MA14(6,13) SA_MA14(6,13)

D D

1 2

R166 56R166 56

1 2

SMDDR_VTERM

RP24 56X2RP24 56X2

M_A_CS#0(6,13)

M_B_ODT0(6,13) M_B_ODT1(6,13) M_B_CS#1(6,13) M_A_CS#1(6,13) M_A_ODT1(6,13) M_B_CKE1(6,13)

M_A_CKE0(6,13)

M_A_BS#2(7,13)

M_A_A0 M_B_A13

M_ODT3

M_ODT1 M_B_A11

1 3

RP31 56X2RP31 56X2

3 1

RP33 56X2RP33 56X2

1 3

RP34 56X2RP34 56X2

1 3

RP11 56X2RP11 56X2

3 1

RP10 56X2RP10 56X2

1 3

Size Document Number Rev

Date: Sheet

2 4 4 2 2 4 2 4 4 2 2 4

DDR2

SMDDR_VTERM

Quanta Computer Inc.

PROJECT : PB2

12 46Friday, March 23, 2007

CGCLK_SMB VCC3 CGDAT_SMB

M_A_CKE[0..1] M_A_CS#[0..1]

M_A_RAS# M_A_CAS# M_A_WE#

CGCLK_SMB (2) CGDAT_SMB (2)

M_A_CKE[0..1] (6,12) M_A_CLK0 (6)

M_A_CS#[0..1] (6,12)

M_A_RAS# (7,12) M_A_CAS# (7,12) M_A_WE# (7,12)

M_A_CLK0 M_A_CLK0# M_A_CLK1 M_A_CLK1# M_A_BS#[0..2] M_A_ODT[0..1]

M_A_CLK0# (6) M_A_CLK1 (6) M_A_CLK1# (6) M_A_BS#[0..2] (7,12) M_A_DQS#[0..7] (7) M_A_ODT[0..1] (6,12)

M_A_DQM[0..7] M_A_DQ[0..63] M_A_DQS[0..7] M_A_DQS#[0..7] M_A_A[13..0]

M_A_DQM[0..7] (7) M_A_DQ[0..63] (7) M_A_DQS[0..7] (7)

M_A_A[13..0] (7,12)

M_B_CKE[0..1] M_B_CS#[0..1]

M_B_RAS# M_B_CAS# M_B_WE#

M_B_CKE[0..1] (6,12)

M_B_CS#[0..1] (6,12)

M_B_RAS# (7,12) M_B_CAS# (7,12) M_B_WE# (7,12)

1.8VSUS M_B_CLK0

M_B_CLK0# M_B_CLK1 M_B_CLK1# M_B_BS#[0..2] M_B_ODT[0..1]

VCC3 (2,3,6,8,9,11,14,15,16,19,20,21,22,23,24,25,26,28,30,31,33,38,40,41)

1.8VSUS (6,8,9,41,42) M_B_CLK0 (6)

M_B_CLK0# (6) M_B_CLK1 (6) M_B_CLK1# (6) M_B_BS#[0..2] (7,12) M_B_ODT[0..1] (6,12)

M_B_DQM[0..7] M_B_DQ[0..63] M_B_DQS[0..7] M_B_DQS#[0..7] M_B_A[13..0]

M_B_DQM[0..7] (7) M_B_DQ[0..63] (7) M_B_DQS[0..7] (7) M_B_DQS#[0..7] (7) M_B_A[13..0] (7,12)

A A

M_B_DQ4 M_B_DQ5 M_B_DQ2 M_B_DQ3 M_B_DQ1 M_B_DQ0 M_B_DQ7 M_B_DQ6 M_B_DQ13 M_B_DQ12 M_B_DQ11 M_B_DQ10 M_B_DQ8 M_B_DQ9 M_B_DQ14 M_B_DQ15 M_B_DQ20 M_B_DQ17 M_B_DQ19 M_B_DQ23 M_B_DQ21 M_B_DQ16 M_B_DQ18 M_B_DQ22 M_B_DQ28 M_B_DQ29 M_B_DQ27 M_B_DQ26 M_B_DQ24 M_B_DQ25 M_B_DQ31 M_B_DQ30

B B

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_B_CLK0 M_B_CLK0#

M_B_CLK1 M_B_CLK1#

CGCLK_SMB CGDAT_SMB DIM2_SA0 DIM2_SA1

C C

7 17 19

6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76

102 101 100

99 98 97 94 92 93 91

105

90 89

107 106

85 30

164 166

197 195 198 200

199

DDR2-H=9.2

DDR2-H=9.2 CN10A

CN10A

DIM2_SA0 DIM2_SA1

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12

BA0 BA1 NC/BA2

CLK0 CLK0

CLK1 CKL1

SCL SDA SA0 SA1

VDDSPD

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DM0 DM1 DM2 DM3 DM4 DM5 DM6

DM7 DQS0 DQS0 DQS1 DQS1

PC2100 DDR2 SDRAM SO-DIMM

(200P)

PC2100 DDR2 SDRAM SO-DIMM

(200P)

DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7

CS0

CS1

RAS

CAS

WE CKE0 CKE1

R202 10KR202 10K R200 10KR200 10K

123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

10 26 52 67 130 147 170 185 13 11 31 29 51 49 70 68 131 129 148 146 169 167 188 186

110 115 108 113 109 79 80

CKEA 0,1

VCC3

M_B_DQ36 M_B_DQ38 M_B_DQ35 M_B_DQ39 M_B_DQ37 M_B_DQ32 M_B_DQ34 M_B_DQ33 M_B_DQ40 M_B_DQ41 M_B_DQ46 M_B_DQ43 M_B_DQ45 M_B_DQ44 M_B_DQ47 M_B_DQ42 M_B_DQ55 M_B_DQ49 M_B_DQ51 M_B_DQ53 M_B_DQ48 M_B_DQ52 M_B_DQ50 M_B_DQ54 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ63 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ62

M_B_DQM0 M_B_DQM1 M_B_DQM2 M_B_DQM3 M_B_DQM4 M_B_DQM5 M_B_DQM6 M_B_DQM7 M_B_DQS0 M_B_DQS#0 M_B_DQS1 M_B_DQS#1 M_B_DQS2 M_B_DQS#2 M_B_DQS3 M_B_DQS#3 M_B_DQS4 M_B_DQS#4 M_B_DQS5 M_B_DQS#5 M_B_DQS6 M_B_DQS#6 M_B_DQS7

M_B_DQS#7

M_B_CS#0 M_B_CS#1 M_B_RAS# M_B_CAS# M_B_WE# M_B_CKE0 M_B_CKE1

M_A_DQ5 M_A_DQ1 M_A_DQ3 M_A_DQ2 M_A_DQ4 M_A_DQ0 M_A_DQ7 M_A_DQ6 M_A_DQ13 M_A_DQ8 M_A_DQ15 M_A_DQ10 M_A_DQ9 M_A_DQ12 M_A_DQ14 M_A_DQ11 M_A_DQ16 M_A_DQ21 M_A_DQ23 M_A_DQ19 M_A_DQ20 M_A_DQ17 M_A_DQ18 M_A_DQ22 M_A_DQ24 M_A_DQ28 M_A_DQ31 M_A_DQ30 M_A_DQ25 M_A_DQ29 M_A_DQ27 M_A_DQ26

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_CLK0 M_A_CLK0#

M_A_CLK1 M_A_CLK1#

CGCLK_SMB CGDAT_SMB DIM1_SA0 DIM1_SA1

VCC3VCC3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

102

101

100

105

A10/AP

A11

A12

107

BA0

106

BA1

NC/BA2

CLK0

164

CLK1

166

CKL1

197

SCL

195

SDA

198

SA0

200

SA1

199

VDDSPD

DDR2-H=5.2

CN9A

R201 10KR201 10K R199 10KR199 10K

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DM0 DM1 DM2 DM3 DM4 DM5 DM6

DM7 DQS0 DQS0 DQS1 DQS1

PC2100 DDR2 SDRAM SO-DIMM

(200P)

PC2100 DDR2 SDRAM SO-DIMM

(200P)

DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7

CS0

CS1 RAS CAS

WE CKE0 CKE1

DIM1_SA0 DIM1_SA1

125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194

10 26 52 67 130 147 170 185 13 11 31 29 51 49 70 68 131 129 148 146 169 167 188 186

110 115 108 113 109 79 80

CKEB 0,1

M_A_DQM0 M_A_DQM1 M_A_DQM2 M_A_DQM3 M_A_DQM4 M_A_DQM5 M_A_DQM6 M_A_DQM7 M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7

M_A_CS#0 M_A_CS#1 M_A_RAS# M_A_CAS# M_A_WE# M_A_CKE0 M_A_CKE1

H 5.2H 9.2

M_A_DQ35 M_A_DQ37 M_A_DQ38 M_A_DQ33 M_A_DQ36 M_A_DQ39 M_A_DQ34 M_A_DQ40 M_A_DQ41 M_A_DQ46 M_A_DQ42 M_A_DQ45 M_A_DQ44 M_A_DQ43 M_A_DQ47 M_A_DQ52 M_A_DQ48 M_A_DQ55 M_A_DQ54 M_A_DQ53 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ60 M_A_DQ56 M_A_DQ62 M_A_DQ58 M_A_DQ57 M_A_DQ61 M_A_DQ59 M_A_DQ63

SB_MA14(6,12) SA_MA14(6,12)

M_A_DQ32

123

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32

SO-DIMM (200P)

VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_59

2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 202

M_A_ODT0 M_A_ODT1

1.8VSUS

81 82 87 88 95

96 103 104 111 112 117 118

114 119

86 116 120 163

162 165 168 171 172 177 178 183 184 187 190 193 196 201

VREF

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12

ODT0 ODT1

NC_1 NC_2 NC_3 NC_4/A15 NC_5/A14 NC_6/A13 NC_7 NC_8

VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

DDR2-H=9.2

DDR2-H=9.2 CN10B

CN10B

PC2100 DDR2 SDRAM

SMDDR_VREF_DIMM SMDDR_VREF_DIMM

M_B_ODT0 M_B_ODT1

PM_EXTTS#1(6) PM_EXTTS#0(6)

M_B_A13

FOX P/N:DGMK0002610 TYCO P/N:DGMK0004205

C713 470P/50VC713 470P/50V

1 2

R477 *10K/FR477 *10K/F

SMDDR_VREF_DIMM

R99

*10K/F

R97 0R97 0

SMDDR_VREF (6,42)

1.8VSUS

VREF

1.8VSUS

81 82 87 88 95

96 103 104 111 112 117 118

114 119

86 116 120 163

162 165 168 171 172 177 178 183 184 187 190 193 196 201

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12

ODT0 ODT1

NC_1 NC_2 NC_3 NC_4/A15 NC_5/A14 NC_6/A13 NC_7 NC_8

VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58

DDR2-H=5.2

DDR2-H=5.2 CN9B

CN9B

1.8VSUS

M_A_A13

FOX P/N:DGMK00000C0 TYCO P/N:DGMK0000498

PC2100 DDR2 SDRAM

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32

SO-DIMM (200P)

VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_59

2 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 202

SMbus address A0SMbus address A4

1.8VSUS

C738

2.2U/6.3V

SMDDR_VREF_DIMM

D D

Place these Caps near So-Dimm1. Place these Caps near So-Dimm2.

C401

C364

C356

C356 .1U/10V

.1U/10V

C364 .1U/10V

.1U/10V

C393

C393 .1U/10V

.1U/10V

C714

C714 .1U/10V

.1U/10V

C755

2.2U/6.3V

C735

2.2U/6.3V

C718

2.2U/6.3V

C745

2.2U/6.3V

VCC3

C741

2.2U/6.3V

C436

2.2U/6.3V

C355

C355 .1U/10V

.1U/10V

C439

C439 .1U/10V

.1U/10V

C754

C754 .1U/10V

.1U/10V

SO-DIMM BYPASS PLACEMENT :

1.8VSUS

C744

2.2U/6.3V

SMDDR_VREF_DIMM

C255

C255 .1U/10V

.1U/10V

C739

2.2U/6.3V

C247

2.2U/6.3V

C743

2.2U/6.3V

C752

2.2U/6.3V

VCC3

C437

2.2U/6.3V

C734

2.2U/6.3V

C753

C383

C369

C400

C400 .1U/10V

.1U/10V

C440

C440 .1U/10V

.1U/10V

C369 .1U/10V

.1U/10V

SO-DIMM BYPASS PLACEMENT :

C345

C345 .1U/10V

.1U/10V

C346

C346 .1U/10V

.1U/10V

Place these Caps near So-Dimm1. Place these Caps near So-Dimm2 No Vias Between the Trace of PIN to CAP.

No Vias Between the Trace of PIN to CAP.

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

DDR2

Date: Sheet

PROJECT : PB2

13 46Friday, March 23, 2007

15mil

IFPA_IOVDD

15mil

YELLOW BLOCK is for G8X chip only

AC9

AD9

AF9 AF8

AM4

AL5

45mA

R40 0R40 0

R68 *0R68 *0

C124 470P/50VC124 470P/50V C125 4700P/25VC125 4700P/25V C129 10U/6.3VC129 10U/6.3V

VCC1.8

C154 470P/50VC154 470P/50V C148 4700P/25VC148 4700P/25V C158 10U/6.3VC158 10U/6.3V

R70 0R70 0

T178T178 T176T176

IFPAB_PLLVDD

IFPABVPROBE IFPABRSET

VCC1.8

80mA

D D

VCC2.5

15mil

VCC3

R66 0R66 0

DACA_VDD

C133 470P/50VC133 470P/50V C137 4700P/25VC137 4700P/25V C146 10U/6.3VC146 10U/6.3V

AD10

15mil

C149 .01U/16VC149 .01U/16V R458 124/FR458 124/F

NB8X:VCC1.8 G73:VCC2.5

C C

R42 0R42 0

VCC1.8

R56 *0R56 *0

VCC2.5

40mA

300mA

need add to 3v

VGA1.2V

VCC2.5

40mA

B B

40mA

VGA1.2V

IFPC_DVI_3V

15mil

IFPC_DVI_3V

15mil

120mA

R49 0R49 0 R53 *0R53 *0

R45 *0R45 *0

R48 0R48 0

C111 470P/50VC111 470P/50V C112 4700P/25VC112 4700P/25V C106 10U/6.3VC106 10U/6.3V

Modify 09/27

R14 0R14 0

C126 470P/50VC126 470P/50V C127 4700P/25VC127 4700P/25V C679 10U/6.3VC679 10U/6.3V R69 0R69 0 C159 10U/6.3VC159 10U/6.3V C147 470P/50VC147 470P/50V C139 4700P/25VC139 4700P/25V

C90 .1U/10VC90 .1U/10V C91 4700P/25VC91 4700P/25V C92 10U/6.3VC92 10U/6.3V

C88 .1U/10VC88 .1U/10V C93 4700P/25VC93 4700P/25V C78 10U/6.3VC78 10U/6.3V

T59T59 T58T58

15mil

R67 10KR67 10K

YELLOW BLOCK is for G8X chip only

DACA_VREF DACA_RSET

R71 10KR71 10K

15mil

IFPCDVPROBE IFPCDRSET

IFPCD_PLLVDD

IFPC_IOVDD

IFPD_IOVDD

NV_PLLVDD

DISP_PLLVDD

15mil

DACC_VD

AH10

AH9 AG9

AK3 AH3

AA10 AB10

AD6

AE7

AD7

AH4 AF5 AG4

U10

R5 R7

T10

U31D

IFPAB_PLLVDD

IFPAB_PLLGND

IFPA_IOVDD IFPB_IOVDD

IFPAB_VPROBE IFPAB_RSET

DACA_VDD

DACA_VREF DACA_RSET DACA_IDUMP

DACB_VDD

DACB_VREF DACB_RSET DACB_IDUMP

IFPCD_VPROBE IFPCD_RSET

IFPCD_PLLVDD IFPCD_PLLGND

IFPC_IOVDD

IFPD_IOVDD

DACC_VDD

DACC_VREF DACC_RSET DACC_IDUMP

PLLVDD

VID_PLLVDD

PLLGND

U_GPU_G3

LVDS

DACA_HSYNC

CRT

DACA_VSYNC

DACA_GREEN

DACB_GREEN

TMDS

DACC_HSYNC

DAC

DACC_VSYNC DACC_GREEN

XTALOUTBUFF

XTAL

IFPA_TXC#

IFPA_TXC

IFPA_TXD0#

IFPA_TXD0

IFPA_TXD1#

IFPA_TXD1

IFPA_TXD2#

IFPA_TXD2

IFPA_TXD3#

IFPA_TXD3 IFPB_TXC#

IFPB_TXC

IFPB_TXD4#

IFPB_TXD4

IFPB_TXD5#

IFPB_TXD5

IFPB_TXD6#

IFPB_TXD6

IFPB_TXD7#

IFPB_TXD7

I2CA_SCL

I2CA_SDA

DACA_RED

DACA_BLUE

DACB_RED

DACB_BLUE

IFPC_TXC#

IFPC_TXC

IFPC_TXD0#

IFPC_TXD0

IFPC_TXD1#

IFPC_TXD1

IFPC_TXD2#

IFPC_TXD2 IFPD_TXC#

IFPD_TXC

IFPD_TXD4#

IFPD_TXD4

IFPD_TXD5#

IFPD_TXD5

IFPD_TXD6#

IFPD_TXD6

I2CB_SCL

I2CB_SDA

DACC_RED

DACC_BLUE

XTALSSIN

XTALIN

XTALOUT

AJ9 AK9 AJ6 AH6 AH7 AH8 AK8 AJ8 AH5 AJ5 AL4 AK4 AM5 AM6 AL7 AM7 AK5 AK6 AL8 AK7

K2 J3

AF10 AK10

AH11 AJ12 AH12

R6 T5 T6

AM3 AM2 AE1 AE2 AF2 AF1 AH1 AG1 AH2 AG3 AJ1 AK1 AL1 AL2 AJ3 AJ2

H4 J4

AG7 AG5 AF6 AG6 AE5

R432 10KR432 10K

T2 T1

R440 10KR440 10K

C_TXLCLKOUTC_TXLCLKOUT+ C_TXLOUT0C_TXLOUT0+ C_TXLOUT1C_TXLOUT1+ C_TXLOUT2C_TXLOUT2+

L_DDCCLK L_DDCDAT

CRT_HSYNC CRT_VSYNC

L_CRT_R L_CRT_G L_CRT_B

TXC_HDMITXC_HDMI+ TX0_HDMITX0_HDMI+ TX1_HDMITX1_HDMI+ TX2_HDMITX2_HDMI+

HDMI_SCL HDMI_SDA

DAC_HSYNC DAC_VSYNC DAC_RED DAC_GRN DAC_BLU

VGA_27M_IN_R

R30 0R30 0 R29 0R29 0

R77 0R77 0 R78 0R78 0

R82 0R82 0 R83 0R83 0 R84 0R84 0

TXC_HDMI- (25) TXC_HDMI+ (25) TX0_HDMI- (25) TX0_HDMI+ (25) TX1_HDMI- (25) TX1_HDMI+ (25) TX2_HDMI- (25) TX2_HDMI+ (25) DVI_CLK- (24) DVI_CLK+ (24) DVI_TX0- (24) DVI_TX0+ (24) DVI_TX1- (24) DVI_TX1+ (24) DVI_TX2- (24) DVI_TX2+ (24)

HDMI_SCL (25) HDMI_SDA (25)

T52T52 T57T57 T49T49 T55T55 T54T54

R434 0R434 0

R437 0R437 0

R435

R435 *301/F

*301/F

DVICLK DVIDAT

HSYNC_COM VSYNC_COM

CRT_R CRT_G CRT_B

HDMI_SCL HDMI_SDA

VGA_27M_SSINVGA_27M_SSIN_R VGA_27M_IN

DVICLK (6,24) DVIDAT (6,24)

HSYNC_COM (6,24) VSYNC_COM (6,24)

CRT_R (6,24) CRT_G (6,24) CRT_B (6,24)

R415 2KR415 2K R28 2KR28 2K

G73 use 150/301 ohm NB8X use 0 ohm

VGA_27M_SSIN (2) VGA_27M_IN (2)VCC2.5

OPTION SIGNAL FROM NB FOR UMA VGA

TXLCLKOUT+

RP8 *4P2R-S-0RP8 *4P2R-S-0

TXLCLKOUTTXLOUT0+

TXLOUT0TXLOUT1+ TXLOUT1-

TXLOUT2+ TXLOUT2-

3 1

RP5 *4P2R-S-0RP5 *4P2R-S-0

1 3

RP6 *4P2R-S-0RP6 *4P2R-S-0

3 1

RP7 *4P2R-S-0RP7 *4P2R-S-0

1 3

OPTION SIGNAL FROM Nvidia to VGA

C_TXLCLKOUT+

RP4 4P2R-S-0RP4 4P2R-S-0

3 1

RP1 4P2R-S-0RP1 4P2R-S-0

3 1

RP2 4P2R-S-0RP2 4P2R-S-0

1 3

RP3 4P2R-S-0RP3 4P2R-S-0

3 1

L_CRT_R L_CRT_G L_CRT_B

VCC5

C_TXLCLKOUTC_TXLOUT0C_TXLOUT0+ C_TXLOUT1C_TXLOUT1+ C_TXLOUT2C_TXLOUT2+

4 2

2 4 4 2

2 4

4 2 4 2 2 4 4 2

R79 150/FR79 150/F R80 150/FR80 150/F R81 150/FR81 150/F

LA_CLK LA_CLK#

LA_DATAP0 LA_DATAN0 LA_DATAP1 LA_DATAN1

LA_DATAP2 LA_DATAN2

LA_CLK (6)

LA_CLK# (6) LA_DATAP0 (6)

LA_DATAN0 (6) LA_DATAP1 (6) LA_DATAN1 (6)

LA_DATAP2 (6) LA_DATAN2 (6)

TXLCLKOUT+ (25) TXLCLKOUT- (25) TXLOUT0- (25) TXLOUT0+ (25) TXLOUT1- (25) TXLOUT1+ (25) TXLOUT2- (25) TXLOUT2+ (25)

NB8X:VGA1.2 G73:VCC2.5

NB8P-SE NB8M-SE

A A

P/N:AJB8PSE0T02 P/N:AJB8MSE0T02

R11

AO3409Q2AO3409

VGA_GD#

R13 10KR13 10K

2N7002E-T1-E3

2N7002E-T1-E3 Q1

R373*0R373 *0

15mil

IFPC_DVI_3V

FOR IFPC VDD LEAKAGE CIRCIUT

VCC3

10K

IPFC_C

R372 0R372 0

C10

C10 .1U/10V

.1U/10V

VCC3

Quanta Computer Inc.

PROJECT : PB2

Size Document Number Rev

VGA

Date: Sheet of

Date: Sheet

PROJECT : PB2

14 46Friday, March 23, 2007

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