Sharp MZ-700 User Manual
MZ-700
SHARP
SERVICE MANUAL
.............................................................
MODEL
(FOR THE MZ-lPOI MECHANICAL SECTION
REFER
CODE: OOZMZ700SMI/E
PERSONAL COMPUTER
MZ-700
MZ-1TOl
MZ-1POl
TO
THE DPG2306 SERVICE MANUAL)
..
1.
SPECIFICATIONS.
2.
NAMES OF
3.
SYSTEM BLOCK
4.
SYSTEM
5.
DATA
6.
COLOUR ENCODER
7.
MICRO COLOUR GRAPHIC PRINTER
8.
POWER
9.
IC
SIGNAL
10.
CIRCUIT
11.
PARTS GUIDE & LIST
FUNCTIONAL
DESCRIPTION.
RECORDER
SUPPLy
POSITION
DIAGRAM
. . . . . . . . . . . . . . . .
DIAGRAM
....................................
.......
...................
.......................•...........
& PARTS
INDEX
..
. . . . .
COMPONENTS. . . . . . . . . . . . . . . . . . .
..............................
. . . . . . . . . . . . • . . . . . . . . . . . . .
.
........
LAyOUT
. .........
.........................
.
.............
...•.
..
..
. . . . .
.
............
...
..
..
•.
•
....
. .
..
. . . . .
........
..
. .
_
....
....
..
..
2
..
3
..
4
15
19
20
24
. . 27
29
1
SHARP
CORPORATION
~\~Z~
700
1.
SPECIFICATION
1-1.
MZ-700
CPU
Oock(ct»
Memory
output
Video
Screen structure
designation
Color
Music function
Timepiece
function
Keyboard
Editing functions
Power
requirements
Temperature
Humidity
Weight
Physical
dimensions
Sharp LH0080A (Z-80A)
3.5MHz
ROM (monitor)
4KB
4KB
ROM (character generator)
64KB RAM (program area)
4KB RAM
System: PAL
Type: RGB composite video (con-
40
cters)
8
x 8
Character: 8 colours
Background: 8 colours (per character)
Internally provided (audio
55OmVmax.)
Internally provided
without data retention)
ASCII compatible
Defmable keys, cursor control keys, etc.
Screen editor (cursor control, home,
clear, insert, delete)
220/240V ± 10V, SO/60Hz
Operating temperature: 0
Storage temperature:
Operating humidity: 85%RH or
3.6Kg
440
(VIDEO)
vertible
RCB
composite)
RF
tible
character x 25 lines
dot
(body
(W) x 305 (D) x
to
B/W)
+ Syncronization
(UHF
36
to
B/W)
matrix
(per
69
only)
character)
(24
keys
86
(non
± 3ch, conver-
(1000
chara-
(per
character)
output,
hours clock,
to
35°C
-20
to
70°C
below
(H)
1-3. Micro-colour graphics printer specification (option)
Printing method Ball point pen recording, four colours
rotary selection type.
of
Kind
Printing speed
Printing capacity
Character set 115 characters
Resolution
1-4. Cassette recorder specification (option)
Type
Record/playback
method
Rated speed 4.8cm/±3.5%
Operation control
method Piano key
Control
Data transfer .
system
Baud rate
Tape
1-5.
Input:
Output:
colours I = black, 2 = blue, 3 = green, 4= red
10
characters/sec, average (Printing the
smallest characters.)
80
digits,
40
digits, 26 digits, soft-
ware designated
(ASCII characters and
others)
0.2mm
IEC compatible cassette mechanism
Dual tracks, single channel, monophonic
method
buttons
used
Power supply specification
(Including colour graphics printer and cassette tape
power source)
220/24OV ± 10V, 60/50Hz, 20W
5V
PLAY,
COUNTER RESET
Sharp,
1200bps (nominal)
Philips standard tape,
FF,
REW, STOP/EJECT, REC,
PWM
method
(not
C120)
CPU board specification
1-2.
CPU
PlO 8255
CTC 8253
Memory controller M60719
(CRTC)
ROM
RAM
I/O bus
LH0080A (Z80A) . . . . . . . .
4KB
4KB character generator
64K bits DRAM . . . . . . . . . . .
2KB
Expansion
Printer I/O bus . . . . . . . . . . . .
(Only one can be used, selectable
switching)
External cassette read/write terminals
..................
...................
monitor
SRAM
I/O bus
................
ROM . . . . . . . . .
ROM
................
...........
...
..
..
..
..
I
I
I
I
I
I
8
2
I
2
by
2.
NAME
MZ-700 Front view
OF
FUNCTIONAL
COMPONENT
plolter
prioter
recorder (cassette)
INS.
MZ-700
DEL
key
MZ-700
Main
Aeer
kev
board
-----'
view
Channel switch
RF
terminal
BrN-Colour
Composi!
Dat8 recorder
!c3S$IIttll)
switch
terminal
AGe
terminal
plOHtr
printer
":::d'---,----CUrSOI
.
Reset switch
socket
control
keV$
CantUI!
re<:order
jKk
Joy
nick
ulfminal
EKt.
output
terminal
1
Ext.
printer
terminal
Volume
Adiust
F,.me
termmal
ground
~"q-700
3. SYSTEM BLOCK DIAGRAM
F.G
A.C.
sw
I~
-""
100V
(
CRT
t t
eJ
0-
~PO~UP'
PLY CIRCUIT
Reset
sw
Z80A
CPU
RESET 1
CIRCUITJ
i-
A
\ ADDRESS
A
~dJA
"
..
(ONTROl
...-
5V
MONITOR
ROM
III
BUS
ft
BUS
~
8253 (CTC)
CO
C1
n
H
r
C2
t,;J~
Audio
amp.
TEMPO. +
CURSOR
OSC.
MEMORY CONTRa.
llER
?8m
~I
r-
(CRTC)
~
t\.0
ER!-
t
KEY I
BOARD
,.--
rn.
f--
f..--
"
0(
I
PRINTER
CONTROL
LER
PRINTER BUS
VIDEO
Fi
I GEN
MAIN
MEMORY
64KB
DRAM
IT
I
f--
8255 (PlO)
>
CASSETTE
TERMINAL
n=
-
I-I--
>
I--
I--
!.
CASSET·
TECONT·
ROLLER
r "\
11
JOY STICK 1
CIRCUIT
~
RAM
~~
CHAR
t
~
JOY STICK
TERMINAL
w
a::
Cl
-uw
~
a::
....
c(
~
:Ja::
00
...JU
oz
p
~
t
EMPO
CONTROLLER
I--
J
!II
R.G.B. I I
-..,
RF I I
VIDEO
,......
\
I
-y
"
\
I
"
.
...
'--
en
:J
III
Q.
-
a:
X
w
I I
_J
...J
I
I
~
3
U U I
CASSETTE
4.
SYSTEM
DESCRIPTION
4-1.
Memory map
a) At power
$0000
$1000
$1200
$0000
$0800
$EOoo
$FOoo
• Shown above
on.
the
on
MONITOR
(ROM)
MONITOR WORK
SYSTEM
TEXT
(DRAM)
V·RAM<CHARACTER>
(SRAMI
V·RAM<COLORDATA>
(SRAMI
KEY
and
FLOPPY CONTROLLER
Enable
VRAM
contents from$DOOO to $DFFF differ from
MZ·80K.
$0000
$1000
and
AREA
$0000
TIMER
PORT
is
the memory map at the time
SYSTEM
TEXT
SYSTEM
TEXT
(DRAM)
and
AREA
and
AREA
Disable
• The monitor (ROM) has the same entry point
the MZ·80K.
(DRAM)
of
power
as
that
of
• Boot command: L
• With the entry
loading program
system program
of
the boot command
is
transferred
is
loaded
to
to
the system area designated
L,
the system area and the
in the DRAM.
NOTE: The boot program shown in the figure
program loaded from the tape and
program from the monitor
(ROM).
c) System initiation
$0000
$0000
$1000
.$0000
MONITOR
,-------,
(ROM)
V·RAM
V·RAM
,-----,
$1000 ----------------------
$0000
---------------------------
$Eooo I--KE-Y-ond-TI-M-ER-P-OR-T-l
:$Fooo
1--------1
only the tape
is
the
is
not the
SYSTEM
b) Bootstrap (loading
$0000 $0000
$1000
$7EOD
$0000
$EOoo
MONITOR
SYSTEM
Boot PROGRAM
V·RAM
KEY and
• With the input
the
BASIC
loading program
area composed
(Only the cassette tape
of
system program)
Ir--
(ROfv\)
V·RAM
TIMER
Eneble
of
1'-
~
'11
PORT
the LOAD command
of
the
RAM
is
this case).
LOAD
$0000
is
transferred
and starts
subject
SYSTEM
SYSTEM
Disable
of
the monitor,
to
the system
to
bootstrap.
to
bootstrapping in
Disable
Enable
• The above memory map is valid upon completion
system program loading.
• The system program
memory depending upon what
is
programmed
is
accessed,
to
switch the
VRAM,
keyboard, or timer.
d) At
the
time
of
manual reset
$0000
$1000
$0000
$EOoo
MONITOR
(ROM)
SYSTEM
V·RAM
V-RAM
KEY
and
TIMER
PORT
$0000 I SYSTEM
$1000
~-----~
$0000
,-------,
SYSTEM
$FOoo
of
4
Enable
Disable
~1Z
-7CO
At the time
$0000
$1000
$0000
$EOoo
of
manual reset (with I
MONITOR
(ROM)
SYSTEM
V-RAM
V-RAM
KEY
and
TIMER
$FOOO
Disable
•
When
the I C T R L I key
through $OFFF and
the
RAM
area.
• With input
(ROM)
is
active, it
of
e) Floppy bootstrap
$0000
....--------,
MONITOR
(ROM)
f----------I
$1000
CTRL
I in depression)
$0000
PORT
-
$1000
$0000
~
is
in depression, address $0000
$DOOO
through $FFFF become
SYSTEM
SYSTEM
MEMORY CHANGE
Enable
~
'--
the command ":If' when the monitor
is
switched
to
the
RAM.
$0000 I
~----~
$1000
SYSTEM
a.
8 x 8 dot characters are displayed on the CRT screen
40
characters (horizontal) x 25 lines (vertical). Displayed
character font
is
dependent on the
4KB
generator (ROM).
Manages
b.
peripherals (keyboard, timer,
the monitor
ROM,
DRAM, video
RAM,
ETC.) mapped to the
memory.
c.
Generates clock to the Z-80A microprocessor.
d.
Selects the printer I/O port.
CRT controller
1)
of
There are major variations
colour television systems
described below.
1.
NTSC
system (Japan, U.S.A., etc.)
2.
PAL system (U.K., Germany, etc.)
3.
SECAM
Because
the
MZ-
system (French, etc.)
of
the different specification requirements above,
700 may not be suitable for overseas operation.
PAL signal specification
Signal name
NTPL
LPHI 17.734475
CLKN
COLR
WAD
PHIO 3.546875
HBLN
VBLN 50.0363
CRT
controller
Signal frequency
8.8672375
4.43361875
1.108404688
15.6113
system
block
"L"
MHz
MHz
MHz
MHz
MHz
kHz
Hz
diagram
of
character
and
as
SYSTEM
$DOOO~----~
$EOoo
$FOoo
V-RAM
V-RAM
i-
-an-d T-IM-E-R-PO-R-l
-
y
K-E
f----------I
FLOPPYCONTRO~L-
Enable
• Because the floppy control area
compatibility with the
from the adress
•
Map
configuration after boot will
iI-
Iv
-I
$FOOO.
LOAD
$0000
,------,
SYSTEM
Disable
is
mapped to
$FOOO
for
MZ-80K series, boot begins
be
considered sepa-
rately.
4-2. Memory controller
(CRT
C)
Both the momory controller and the CRT controller
are
contained in a
single
chip custom
LSI
(M60719), it
has the following functions:
COLR
HSY
SYN
VBLK
HBLK
CLK
LOAD
Oata written in
from
the
CPU
01-08
via
the
buffer
5245.
is
CPU
CPU
NTPL
H
WA
Blanking period
To display characters on the CRT screen, the
the character data ( display code) to the
WR
along with the control signal
that character
the address
data
is
via
the bidirectional buffer LS245, and the data will then
be written when
01-08
of
to
the
2KB
VRAM-
($DOOO
,..,
$D7FF)
supplied to the VRAM-l input (01-08)
WE
is
low. The color data
the
VRAM-2
to be written when
and the color data
2.
In other words,
is
output. The character
CPU
2KB
is
also sent to
WE
TV
the
VAAM
input
to
bidirectional
writes
VRAM-l
of
is
low.
as
5
To read the contents
sends
out
the relevant address. When
data
is
then read
via
However, the address range
be addressed in order to access
is
change
carried
of a VRAM
the bidirectional buffer LS245.
$0000
all
the
out
inside the custom
command described later.
Accessing
period (BLNK
applied to the
VRAM
= "H").
CPU
(WA
is carried
If
BLNK =
= "L").
out
of
the
The blanking period discussed here
BLNK
is
in high level.
High
period
shorter than the low period
of
the BLNK signal
is
of
HBLK (horizontal blanking
period).
HBLK
versus
BLNK
character, the
RD
is forced low, the
CPU
through $DFFF must
VRAM.
This address
LSI
with the OUT
within the blinking
"L",
then
WAIT
is
is
the period that
so
designed that it
is
LOAD:
CLK:
•
HBLK
The signal that determines the function (shift
out
or data set)
High state
of
state
this signal acts
of
of
the shift register LS165.
this
signal
acts
as
as
data set.
shift and low
Shift register clock. Data shifts at the rising
of
CLK
edge
versus
1J
when the
HSY
36.0881-1S
1-1
-----:...----;I-!'j
I I '
1
64.05603/015
I·
LOAD
signal
is
!------Jr---
I 1
1 1 '
9.02201-1S
1
I
I
W.
-l
:--
4.567375j.1S
high.
HBLK~
BLNK--,L.
____________
!
~--~I
~
-:
,
I:
L"I----
, 1
I'
l--
2.165081-1S
Display period
The data written in the
character
by
character based on the display address counter
located inside the custom LSI, to become the
data (VRAM-l data). Also, the data
to the LS174, at this point. The
data and low order address bits (Q-Q3).
VRAM
is
sent
to
the
CG
CG
of
VRAM-2
CG
receives the VRAM-l
It
is
then sent to
ROM,
address
is
sent
the shift register LS165 after being converted into the
8-bit parallel character row data. The shift register converts
this signal into serial data and it
is
added to the color
matrix circuit along with the data from the LS174 to
become the R.G.B.
Po
- PlO: These are
character position
Ql
- Q3: These represent the rows
character. Row number
HBLK,
CVIDEO signal.
VRAM
addresses
on
the CRT screen.
that
of
is
represent the
the 8 x 8 dot
increased with
and it repeats 0 through 7
as
shown
below. These signals are also generated inside
the custom
1st row
2nd
row
3rd row
4th
row
5th
row
6th
row
7th
row
8th
row
LS!.
as
0 0
0 0
0
0
1
1
1
1 1
a2 a
1
0 0
0 1
1
1
0
1
0
1
0
1
• VBLK versus
VBLK
Custom
LSI
SYN
____
~
: 12.8112ms
r-I--------·~I
1
~_~1~9=.98==5m~s~
~
__
:;
__
~_~.:.
--,
~r---
I
r--2;8825mms
u
, 1
1 1
r--
0.19216ms
internal CRT controUer block diagram and
description
• Ql -
• Internal signal
VRAM
Q3
are created by dividing
CSDD
addressing, which
HBLK
by half.
is
used to make the choice
is
carried out by address
muitiplexing through the internal display address, or
CPU.
comes direct from the
A through K are the display
addresses.
• The
LPHI
signal (l7.7MHz)
is
divided and ANDed to
derive the horizontal synchronization signal
or PAL)
to
make the choise
of
either
NTSC
horizontal synchronization signal, output by means
ofNTPL.
of
(NTSC
or PAL
6
\
,'1Z
-700
2) Memory controller
MZ·
In the
700, it needs
to
segregate the memory in order
to acheive the above mentioned memory mapping. The
memory controller
of
management
as
DRAM, monitor
peripherals assigned
bank select method
selection
port
$EO
$El
$E2
$E3
$E4
$E5
$E6
I/O
is
acheived using the OUT command.
$0000
~
$OFFF
D·RAM
-
MONITOR
ROM
-
MONITOR
ROM
-
-
therefore used
ROM,
video
is
used to switch memory. Memory
$DOOOO
l
$FFFF
-
D-RAM
-
V·RAM,8255
8253
V·RAM,8255
8253
Prohibited
Returns
to
state before
to
perform address
to
the memory such
RAM,
and keyboard. The
INHl INH2 INH3
L
-
H
-
H H H
- -
the
-
-
L -
-
H
-
-
-
-
L
H
is
prohibitied.
• Custom LSI internal memory controller block diagram
and description
When the above mentioned
Ao
,..,
A2
address
INH3,
against
•
RA~
•
CSO
becomes active when the monitor
•
CSE
(8255,8253)
then
CPU addressing
becomes active when the DRAM
becomes active when the memory mapped I/O
is stored in
ROM,
VRAM, and
is accessed.
OUT command
"FF"
DRAM
on
the basis
of
is
executed,
to
create INHl
,..,
may be accessed
those INH signals.
is
accessed.
ROM
is accessed.
• CSDN (internal signal) becomes active when the VRAM
is
accessed.
So
that, the address from the CPU
•
If
the display period is
If
in the blnk period, CSDD becomes active.
is
sent
of
Po
,..,
PlO.
on
when accessing the
ROM
or
VRAM, W ATN becomes active.
•
line
address and row address switching signal (LS157
RAM
input) when accessing the
WRN,
MRQN, and RDN.
edge
of
CAS
during the write cycle,
As
is derived from PHI,
WR
rises before the falling
it
becomes an early
cycle.
-
INH3
INHl
are custom
LSI
internal signals which cause
the memory map to change.
INH1
INH2
INH3
INH1
INH2
INH3
H L H H
H H L H
H H H L
I--D-_R:_:_M---I
V·RAM V·RAM
D·RAM
D-RAM
D·RAM
1--:-.:-:-:---1
L
L
H
ROM
D-RAM
H
L
L
I---D-_:_OA_MM----j
D-RAM
L
H
L
D-RAM
D-RAM
I
:::
D-RAM
D·RAM
L
L
L
NOTE: The command with which the memory selection
to
be
done should not
be
written in the memory
block to be selected.
I
is
7
4-4. Memory controller (CRTC) circuit description
the
The memory controller and
Memory controller signal description
Pin No.
1
l
16
17
18
19
10 CL
21
22
23
24
25
26
27
28
29
20
31
32
33
34
35 WATN
36
37
38
l
40
41
42
43
44
45
46
l
52
53
54
l
57
58
59
60
Signal name IN/OUT
AO
l
A15
LPH1
PHI
CSEN
GATE
CSON OUT
VCC
RASN
RFSN IN
PHIO
MRQN
10RN
RDN IN
WRN IN
RSTN
SEL
VBLN
HBLN
COLR
PRCN OUT Printer I/O address select
Q1
l
Q3
NTPL IN NTSC/PAL system switching (PAL=L)
BLNK
HSYN OUT
ABC
LOAD
PO
~
P6
GND
P7 Display address signal
l
PlO
S157 OUT V-RAM display/CPU address switching signal
SYNN OUT Vertical synchronizing signal
CLKN
CRTC are contained in
CPU address Bus
IN
IN
IN CPU clock (3.55MHz)
OUT
IN GND
IN GND
-
OUT
OUT
IN
IN CPU I/O request IORQ
IN Reset
IN DRAM row/column address switching signal
OUT
OUT Horizontal blanking signal (CRT)
OUT
OUT
OUT (Display address
OUT Timer clock
OUT
OUT
OUT
-
OUT l
OUT Character
Clock (17.7MHz)
8255, 8253, joystick enable
Monitor ROM enable
Power supply
D-RAM row address select
CPU refresh
CPU
clock create signal (3.55MHz)
CPU memory request MREQ
CPU read
CPU write
Vertical blanking signal (CRT)
wait
CPU
Colour
Display: Address data
PO
with
Horizontal synchronizing signal
Character,
Display address signal
GND
the
single chip custom LSI (M60719).
&
Function
sub-carrier wave (4,4361 875MHz: PAL)
output
(Line
Count
Signals)
is
- PlO).
indicated
display start signal
display shift register clock
to
the
CG ROM together
IV?
Circuit diagram
signal name
AO
l
A15
<I>
cp
CSE
CL
GATE
CSO
5V
RAS
RFSH
cpo
RD
WR
RESET
SEL
VBLK
HBLK
WA
COLR
PRC
Ql
l
Q3
N/P
BLNK
HSY
ABC
LOAD
PO
l
P6
P7
PlO
S157
SYN
CLK
7ce
8
CUSTOM
1.
BLOCK
CRT
LSI
< YTl >
DIAGRAM
Control
LPHI
NTPL
0
0
Eh
COLR
J
I
l-{
H
1/2
1/2
1/4
I
J
I
ABC
r--
I--
I.....-
SCREEN
POSITION (1)
SCREEN
POSITION (2)
"
I'
AND
5
IMT
LOO
r--
A-C
~
H. SYNC. (NTSC)
H. SYNC. (PAL)
...,
8
\
,
D-K
-
-
CLKN
~
COLR
-
HSY
NTSC
PAL
r--
SELECT
a:
w
X
w
..J
0..
i=
..J
::>
::i:
Cl)
Cl)
w
a:
0
0
et
BLNK0
~
f----
3
\.
,
~
~
BLNK
~
"V
HBLN
LOAD
~
PO
~
P1
~
"U
P2
P3
~
P4
~
P5
~
P6
~
P7
Y
P8
V
pg
~
P10
"!
S157
"0
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
0
('
-
9
0
0
0
0
0
0
0
/
"
/
/
/
/
/
/
~
L---
V.
BLNK
•
CIRCUIT
\
11
,
0123
~
V. SYNC.
AND
CIRCUIT
I
I
1
It
-
Y
1/2
1/2
1/2
f
1
r
3
CS
DD
SYNN
VBLN
-0
I
-
f
I
-
I
"0
Q
01
02
03
9
Memory
IORN
A1
A2
A3
A4
A5
AS
A7
AO
WRN
A15
A14
A13
A12
MRQN
Management
,...
"
0
0
0
0
0
0
.....
"
0
0
0
0
0
-
0
(1)
~
"
'\
"
."
"
-"
"
r--
'"
•
AND
BLNK
3
\.
,
LACH
4
INH1
INH2
INH3
4
\
,
I-
:;
u
!!:
U
(/)
<C
a:
2
'----
Z
0
~
<C
(f.I
Z
w
a..
~
0
U
•
~
CSDD
-0
PRCN
RASN
RFSN
RDN
PHI
A11
A10
A9
AB
0
0
0
-
:::.
~
'-
0
~
INH1
')
CSON
'"
-0
WATN
INH2
INH3
AND
AND
-
CSDN
WAIT
CYCLE
CIRCUIT
1
INH2
INH3
4
\.
AND
CSEN
10
Memory Management
PH111
(2)
WRN
MRQN
RDN
LPH1
NTPL
CL
GATE
VCC
GND
0
0
0
0
CAS
1/4
circuit
~------------------------------<1SEL
COLR
NTSC
PAL
~-------------In
PH
10
select
Colour VRAM (VRAM-2)
•
MZ-
700 colour infonnation
character. One byte
ed
to
each characters displayed on the
D7
D6
D5
D4
D3
D2
D1
DO
FRONT G
FRONT R
FRONT
Not used
BACK
BACK R
BACK
of
ATB
B
G
B
Character iqfonnation
colour infonnation table is assign-
is
managed character by
ATB: CGROM
ingbit
....
BACK
is
stored in address
address switch-
$D7FF and colour infonnation in $D80Q.$DFFF
VRAM.
TV
screen.
+-_FRONT
$DOOQ.
of
the
4-3. Memory
CPU
memory Controller
address
$EOOO
$EOOl
$E002
$E003 Mode controller
$E004
$E005
$E006
$E007
$E008
mapped
8255
8253
LS367 and
others
I/O
($EOOO -$EOO8)
: Output
PA
Pe : Input
Pc
: Input/output mode controller
by bit cell
: Mode 3
Co
(square wave rate ge»erator)
: Mode 2
C,
(rate generator)
: Mode 0
C
2
(terminal counter)
Mode controller
Tempo,joystick,
Function
HBLNK input
11
a) Signals around
the
8255
The 8255 Programmable Peripehral I/O Controller assumes
the control
of
the cassette recorder, CRT screen cursor
blinking timing, keyboard scan strobe output, and key
return data.
Cassette
control
Key data
input
terminal
(8P)
RDATA
MOTOR
M·ON
WDATA
Key data
strobe terminal
(lOP)
r---
'-
VBLNK
5560UT
INTMSK
556RST
0
-
\
9
LS
145
8255
PBO
\
PB7
PC7
PC6
PC2
PC5
PC4
PC3
PCl WR
PA7
0
C
B
A
PA,
PA.
PAl
PA
o
0,
\
Do
AI
Ao
RD
CS
RESET
0,
AI
8255
RESET
Port
PA
($EOOO)
PB
($EOOl)
PC·
($EOO2)
•
Output
b)
Cassette controller
data handled in the
Port terminal
PA
o
PAl
PA
2
PA
3
PA
7
PB
o
PB
I
PB
2
PB
3
PB
4
PB
s
PB
6
PB
7
PC
I
PC
2
PC
3
PC
4
PC
s
PC
6
PC
7
I/O
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
bit
cell mode. (Port C in control mode)
Active state
Data transfer with the cassette recorder is carried
PCI, PC4, and
format (Sharp
PC5
PWM
of
the 8255. Shown next
method)
of
the cassette tape.
is
H
H
L
L
L
-
L
51..
H
-
-
-
out
on
the data
Control function
}
Keyboud
scan stwhe slgnal output
Cursor blinking timer reset
Keyboard scan data input
Cassette data write
Timer interrupt disable
Motor rotate control
Motor rotation check
Cassette data read
Cursor blinking timer input
Vertical blanking
•
Signal name
556RST
WDATA
INTMSK
M-ON
MOTOR
RDATA
5560UT
VBLNK
12
1-o1
..
_--464~-
, I
I I I ,
__
...
II.oo
...
_-49
.•
4j.1S----I
..
-+oI
.....
240~-'-
"I
264~'"
I
;.'
______
_
CASE1 LONG
368j.1S 368j.1S
READ
EDGE
(Rising
edge
starts sampling
counter) (LOW) 264lls
"LONG"
is
the data written for the bit value
"SHORT" for the bit value
after the rising edge
SHORT
10
sec
of
the data. The data is recorded
TAPE
MARK
I
22000
LONG40
SHORT40
-----
READ READ
POINT
of"
of
"0".
Data is read
1
LONG
INFORMATION
BLOCK
128
bytes.
....
EDGE t
1" and
368~
--
SHORT
--J
as
a repetition
block written twice.
Check
!SHORT
sum,
~56
2 bytes
~ytes
U
'
READ
SHORT
(HIGH)
LONG
(HIGH)
(LOW)
READ
INFORMA·
POINT
240lls
464lls
494j.1S
POINT
368lls
of
LONG and SHORT, with the same data
E
..
:;,a>
BLOCK
128
bytes
TION
.....
~>
u.rJ
1!N
u
1
LONG
SHORT
5
sec
11000
The
information block consists
Name
ATRB
NAME
SIZE
Byte numbers End address Function
1
17
2
DTADR 2
EXADR 2
COMNT
124 $1170 Comment Not used
TAPE
MARK
LONG
SHORT
of
1
20
20
the following:
DATA
BLOCK
$lOF1 Attribute
$1102 File name (up to 16 characters)
$1104
File byte size
$1106 Loading address
$1108 Executing address
E"
E
Xl
1 256
LONG
isHORT
Ibytes
as:
~.rJ
1!N 1!N
U
DATA
BLOCK
..
:;,a>
.....
~>
u.rJ
U
Note
CR (OD) at the end
In
order or low and high order bytes
I
1
LONG
13
c) Keyboard controDer
The 8255 writes strobe (key scan signals) on
reads key data from
PB.
The table shown below
key map.
PA
is
and
the
d) Signals around the 8253
The 8253 Programmable Timer generates the buzzer tone
through the counter
via
function
the counters
The counter #(J
(Mode 3). The counter #1
(Mode
(Mode
2)
0).
and #2
The counter #(J counts the input pulse
is
divided by a predetermined factor (musical note), and
is
then supplied to the amplifier to generate sound. The
#1
counter
pulse
a
those pulses
after.
receives
on OUTl every second. The counter #2 counts
and
As
OUT2
#(J and keeps the internal timer
#1
and #2.
is
used
as
a square waveform generator
is
used
as
a rate generator
as
an
interrupt upon terminal count
of
895KHz which
an input pulse
OUT2 turns to a high
is
connected to the
of
15.6KHz and creates
level
CPU
interrupt pin,
12
hours
it then goes into an interrupt processing routine.
14
D7
Do
8253
OUT2+----TO
OUT1
ClK1
OUTO
ClKO
CPU
BlNK
895KHz
INT
05.6KHz)
sp,
5.
DATA
5-1.
Data recorder (MZ-lT01)
RECORDER
Data transfer with the recorder is carried out
The
read data
write data
on/off control
activation
The
signal
pushbutton
is
sent out through
is
received through the port
is
carried out
of
the motor
SENSE
is
pushed on the
is
goes
via
confmned through the port
low when FF,
MZ-}
the
the port
TO
I.
port
C5.
REW,
via
the 8255.
Cl
and the
The motor
C3
and that
or PLAY
C4.
• Cassette specification
Method
Rated power
Rated
current
Semiconductors used
Tape used
Rated
tape
speed 4.75cm/sec
Tracks
Motor
Bias DC
Erasure
Standard playback
Nominal
level
input
Nominal
input
and
impedance
input
point
level
PWM
recording
5V
± O.25V
Wait: 2mA
Record:
Playback:
Transistor x 5
IC x 2
Diode
C30 - C90
2 tracks, monoral
5V
DC
lmsec -500
L: O.4V, max.
H: 2.0V, min.
R~cording
L:
H:
210mA
150mA
x4
electronic governor
sec
terminallOkn
O.4V, max.
2.0V, min.
method
(TEAC TEST TAPE)
(TEAC TEST TAPE)
motor
min.
Block
diagram
Control
circuit
+5V
o-
__ ~ ______________ ~ __ ~ ____________ ~ ____
SW3002
Mechanically
WRITE
interlinked
switch
Erase
head
------
Differentiation
circuit
~03003
R3003
R3004
Amplifier
circuit
03001
03002
Record/playback head TAPE
Amplifier
03003
+5V
-~---!
Amplifier/
Limiter
circuit(1/2),
IC3001
Waveform
shaping
circuit
(2/2),
IC3001
READ
Amplifier
circuit,
03004
15
Troubleshooting procedure
I
iv1Z
700
Phenomennon
Check
if
M+
and
M·5V
are
supply.
in
Phenomenon
Check
if
the
with
properly
REC
Check
SW3OO1
the R EC push
operating when the
pushbutton
if
+5V
CD:
@:
button
is pushed.
on
Cl)
Motor
NO
Program
interlinked
is
.
and
can
tape
Motor
Check
interlinked
P
LAY
active.
not
be
NO
OK
do
not rotate,
fai lure
if
the SW302
with
push
button
saved
itch
fai lure
heck
if
on
from
is
terminal
the
signa
the
!J).
is
when
OV: when
+5V:
when
NO
OK
the
Check
is
of
PLAY
SW
is
SW
is
Check
on
03002.
on
off
if
to
the
button
the
CPU
the signal
base
is
pushed.
Check
Check
voltage. Check
board.
OK
+5V
on
REMOTE
the
+5V
input
R3009.
OK
Failure
Check R30OS.
signal
is
to
the recor
ding
head.
of
SW3OO1.
on
terminal
Check the
and
the
Check
if
remote
OK
@.
motor
motor
transistor (2S0468)
voltage is
control
transistor
Failure
playback head.
NO
Check
to
lead
on
to
of
Contact
in
SW3OO1.
03001
if
the
erasure head.
wire
(REM)
the
base
of
the CPU board.
the recordl
failure
Check
and
03002.
voltage
is
of
the
on
Phenomenon
Check
if
a
waveform
on
the terminal
®.
®:
is
Program
OK
1...----1+5V
NO
No
waveform
too
much
can
noise.
with
not
Check
supply.
be
loaded
the
or
resulted
in
error
16
Check
if
the erasu
should have been inactive
to
failure
due
Check
peripheral
around
03003
maladjustment
NO
playback
head.
re
head
of
SW3001 .
components
and
for
of
the record I
azimuth
Mechanical adjustments
RECORD/FAST FORWARDjREWIND torque measure-
ments
1.
Set the torque measuring instrument on the cassette
tape recorder.
2.
Torque
Position
PLAYBACK
FAST
FORWARD
REWIND
value
under each mode must be
Torque measuring
cassette
TW-2111
TW-2231
TW-2231
30
60
60
'"
'"
'"
as
follows:
Value
70gram·cm
160gram·cm
160gram·cm
Record/playback head azimuth adjustment
1.
Set the instrument
2.
Playback the test tape (Teac's
as
shown in Fig. 4-2.
MTTlll,
recorded with
3KHz signals).
3.
Adjust the head azimuth adjusting screw
reading on the digital voltmeter
is
so
that the
at its maximum
value.
Cleaning
The
head
of
head
is
critical for a proper performance
of
the tape
recorder. Dust on the head, capstan, pinch roller, etc.
impedes proper recording and playback. Open the cassette
holder, take out the tape, push down the
pushbutton, then clean those components.
see
any oxide deposit, clean them using a cotton bud
PLAYBACK
If
you can
damped with alcohol.
Tape speed adjustment
1.
Connect the wow-flutter measuring instrument to
pin
of
the
CNW3001
connector.
:f#!,
2. Playback the test tape (UKOG-0119CSZZ, MTT-1l3
recorded with 8KHz signals).
Use
the middle part
of
the
tape for the test.
3. Adjust the
Board
semi-fix~
so
that the playback frequency should become
resistor located on the Motor
8000 ± 250Hz.
Test tape,
MTT-113
Pinch
Collector
roller
of
Figure 4-2.
transistor
Head
03003
Digital
voltmeter
RECORD
The
erasure protect tab
depression
pushbutton can not be pushed in
RECORD pushbutton can not be pushed in,
of
the cassette tape
of
the button may result in machine failure.
is
if
the
broken. Forcible
17
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