Sharp MZ-5500, MZ-5600 Tehnical Manual

MZ-5500/5600

TECllNICAL REFERENCE

Vol.2

(HARDWARE)

SlIARP CORPORATION

TABLE

OF

CONTENTS

1.
1

1

1
1
1
1
1

-1.

-2.

-3.

-4.

-5.

-6.

-7.

Introduction

MZ-5500
MZ-5600
MZ-5500
MZ-5600
Optional
Optional
Optional

-------­series
series

hardware

hardware
specification
specification

devices
devices
devices

specificationß
specifications

specificatio~s

S~ction

-

One

---------------------­description
description

-----~----~----------------

--------

System 'Specifications

----

-----

-----

------------r---------------------

------

---------------

(for

MZ -5500/5600)

(for

MZ-5500)

(for

MZ-5600)

-------------

-----

---

---

-------------------------

--

-------~--

--------

--------------

--------

--------

---

----------------------

----------------------

--------

-

-

------

-------

---

-------

---------

--

--

----

------

-------

-

2

3

~

b

g

/0

10

,

Section

Two

Hardware

Specifications

I.

2.

2 - 1 •

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-2

L

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- 1 •

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- 2 .

3- J .

I, •

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r

,.,

)-

L.

)-

3.

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4.

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()

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()

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()

- 2 .

ho, 3.

7 .

7 - I •

7 - 2 •

R.

<).

9-

I .

9

-2

9-.3 .

10.

1 () - I •

10

-2

lO-

J.

10

- 4 .

I

()

- 5 .

1

I.

1 1-

I.

I 1- 2 .

I 1-°3 .

1 1- 4 .

12 .
12-1 .

13.

11-

1 .

13-2.

14.

15.
15-

I.

1')-2.
1

6.

1,

7.

C

PU

pe

ripheral

M('mory

~lZ-5500/5600

.

1/0

IllterrtJpt

Inlrrrupt

lI~nclling

SysLem
Software
Expansion

- ----------------------------------------------------------------------

map

---

-----

circuit

circuit

of

user

interrupt

timer

slot

MZ-5500/5600 e xpansion

.

Expnnsion

1/
1/0

•

1/

UMA

m1t\ C on t

Op

lis
Milli -

(

~e

~l

11

;n

Print

Circ

.

lI<1ndling

M<1king a
RS

Sp

.

Input/output

0

address
slot

0

port

--0------

r r;l t i olla 1 t
t"

of

floppy

n e

ral

l-56

00

cl

dis
e r

lIit

2J2C

ec

ification

signal

setup

timings

interfacing

------------------------------------------------------------------43

ro

L w i t h HZ-

mlt\

channeL
disk

descr

~lFD

(640Kß)

kin

t e r

interface

description

printer
hard

interface

Proc e S s ou t 1i

Wiring example

RS2J2C

Kp

ybo

K

ey

K

ey
Kpy
Eig

MOli

se

()pprating

R-rc

Operational
Acce

PCG
Vid

e o

Fe

<1 t ure

IIS

p.

Pov.1P r SlIpp I y un i t

sample

ard

and keyboard
hoard
board

searcll

llt

-bit

(~lZ-

(Real

ssing

(p

rogr

display

s 0 f t h e v i

of

video

specifications

interface

timing

keyboard

I X 10)

principle

Time

description

the

ammab

80H7 COf)[oceSSor

------

memory

-----------

----

heo

iption

fa

copy

----------------------------------------------~------

si~nals

ne

------

program

----------------------------------------------------

Clock)

RTC

le

circuit

display

--

--------

and

memory map

--

-----------------------------------------------------------

---

---------------

------------------------------------------------------

interrupt

(IR-2S)

------

-------------------~---------------------------------31

slot

description

-----

-------

------------------

-

examples

5500/

r y

- -

--------------~------

J

------

interface

(MZ-5500)

interface

c e

gen

e r a L

---------------------------------~----

-----------------------~-------------------------------

control

of

tlle

---

-----

-------

and

-------------

-----

----

interface

-----------------------------------------------------~0

--

--~

-------------------------------------------------

-------

processo

--

-----

-------------------------

-~-------

internal

Sound

Gene

--------------------------------------------------------~6

deo

dis

circuit

----

--

----------------------

option --------

--

--------

-----

----

-

---

---------------

specification

-

---------------------------------------------------34

(HZ-IUOS)

(common

--

---------

--

-------------------

--

--------

--

--

----------------------------

-

------------

-

------

--------------------------------------30

---------------------------------------37

for

the

HZ-SSOO

---

----------------~-

and

HZ-S600)

--

---------------------------------------------­(user's

S600

-----------------------------------------------4-3

------

----

---

--------

----

general

des

c r i p t

code

(function

video

control

-----

-------

---

r

----------------

RAH

ra

p1a y

screen

-------------------------------------~-

signals

--

----------------------------------------------

-----

----

------------~--.:....-----------------

--------------~-

pP080C49

---

-----

tor)

ci rcu i t

(software

-----

job)

--------

---

-----

-----

description

ion

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55

--

---------

--

------------------

------

-----

code)

--

--~----

-------------

-------

-----

-----

-----

----------

-----

- -

-----------------------------50

------

(HZ-S600)

-----

~

---------------------~-g

---------------5o

----

----

----

------

-----

------------------------------------62

--

---------------------------------------66

-----

--------------------

---------

---

-------

---------------------

--------

-----

--~-------------------------------

-----

--

---------

-------­control)

-

-----

----------------------

-----------------------------~4

--

-----------------------------~~

---------

---

------

--

------

------------

----------------

---

------------------~1

---

--------

--

--------

----

------

--------

-.:---

-----

--

-----

-----

--------------

---------/2

~

,q

2\

-.:....

--

------'21.:>

-----;2b

-----

------27

---

--------38

-----

---

-------

---------

------

-

--

---

--------

------

--3q

------1-0

----------4~

-----

-

-----

-

------------ryo

------

--

---------

-----

----------

------

-----er

------

------52.

-----

-------bl

---------6\

-

-

----60

---60

4(,

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64-

------6

----~o

-

-----q2

-

----q2

----

rr:\-

------

-----

----

-----

--

82

---').}

--

&b

W

10(,

toS

3

~

~

1.

Introduction
The MZ-ssOO
the

It

has
the
introduced

It

has

and
The
192KB,
Up

to

internally

5.25"

Not
MZ-5500
and

1)

8MHz/5MHz

2)

Implementation

3)

Use

Intel's

been

bit

map

the

:i.

t

can

96KB

permitting

two

disk

only

series,

higher

of

series

8086

is

designed \·.dth
display

to

the

system

also

be

video

units

RAM

of

installed,

media.

the

MZ~s600

but,

processing

selective

the

10.7MB

is

the

used

system,

MZ-5500

RAM

area

expanded

area

clear

color

320KB

and

The

OS
series
it

also

speed.

for

of

the
(formatted),

System

first

for

the

intense

and

series.

of

128KB (MZ-5511)

to sl,

1s

provided

graphie

(formatted)

the

OS

supports

succeeds

permits

operation

640KB

SECTION

ONE

Specifications

16-bit

MZ

series

CPU.

care

the

2KB

for

man-machine

multiwindow

at a max

standard

imum.
and

displaying.

mini-floppy

(Operating

CP/M-86

all
the

of

(form~tted),

5.25"

System)

and
functions
following

the

8086-11

5.25

hard

disk

persona)

display

ur

256KB

it

disk

MS-DOS

11

floppy

(MZ-s64s).

interface:

function

(HZ-5521)

also

drives

is

contained

as

and

features

external

epu.

computer

can

be

can

option.

me~ory

disk

drive.

in

which

th

e

mOllSt~ ,

are

as

standard

expanded

be
in

the

from

the

expansion

to

Not

only
enhances
added

the

expansion

(applicable' for
The MZ-S600
series.
Since

the

processing

time

processing

Such

as

CP/M-86,
option.
Because
been

the

developed
eonsideration
See

Table-l

MZ-s600

series~

MZ-s645

enables

8086-11

speed

,

MZ-S600

on

has

for

has

to

21.4MB when
the

absorption

is

adopted.

and

graphie

of

the

software

MS-DOS,

series

the

basis

been

given

individual

one

unit

of

the

200V

version
of

the

improvement

speed,

developed

MZ-3500series

is a up-graded

of

MZ-SsOO

for

compatibility

model

configurations

the

internal

MZ-IF18

only).

software

and

consideration

BASIC,

peripherals

has

on

the

model

llard

external

cre~ted

been

achieved

MZ-5500

and

GW-BASTC

for . the

and

in

basic

of

the

disk

drive,

hard

disk

on

the

MZ-S500

for

is

given

in

the
are

MZ-SSOO

software,

terms.

~IZ-5s00

it

drive

higher

for

the

SMHz

mode.

availabie

and

lias

series

also

is

real

as

and

' 1

1-1

MZ-5500

SERIES HARDWARE DESCRIPTION

System

lhe

following figure shows

tion

for the

pheral device-s

Color

CRT

configuration

MZ ·5500

which

(EX)

MZ1D14

display

the

Series syst'em.

are

to

be

marketed

Mono
chrome

CRT

complete

including

·

system

in

the

Oevice

RS-232C

interface

configura-

some

near

with

"

4

____

"

, /

interface

cable

MZ1CJ4

peri-

future_

//

/

Expansion

,/

Unlt

C"ble

MZ1C33

I

(256KB

MZ1R11

&

MZ1P02

L7

......

"

Expansion

----.:.(8087

Arlthmetic

processor

M21M03

RAM

or

more)

.

logicaIOD

PWB

MZ1F02

MZ1K07-10

Specifications

System

1) High
microprocessor

2) Large addr essable
255KB

3)

High ·

video

4) One or
provided

5)

Powerful
Integrateq

5)

7)

ep/M86

highlights

data

processing

plus an

resolution

screen

memory

two

mini ·

as a standard

standard

sound

as

the

.

additional

color

standard

Keyboar d

capability

memory

graphie

and

floppy

feature.

1/0

system

generator

operating

achieved

space

256KB

.

display

bit -

map

display .

disk drives,

interface

.

system

of

wilh a 16-bit

512

K B:

with

large-

each

of

.

.

f

Mouse

MZ I X

Standard

capacity

320K

10

Bare

\

\

VRAM

MZ1R09

Fig. 1

\

PWB

(96KB)

..

Model

description

MFO
MFO

Oescription

plus

256KB

's

plus

256KB

of

RAM

of

RAM

.

.

Model

MZ-5511
MZ -

5521

Conlains
Contains

one
two

2.

1- 2

MZ-5600

SERIES

HARDWARE

DESCRIPTION

System

The following figury shows
tion

for

configuration

the

complete

the

MZ -5600 Series system, including some peri-

pheral devices which are to be marke

Mono-

chrome

eRT

MZ 1

014/1018

system configura-

ted

in

the

RS-232C
interface
cable
MZ1C34

near

/

L

____

/

/

/

/

future.

7

/

/

~

//

//

Printer
MZ1C32

\

\

\

\

,

cable

MZ1P02

Expansion

----1

Hard

Disk

I/F

CZ56450i/

~

,/'

processor
MZ1M09

.21

8087

Expansion

(256KB)

MZ 1 R

Unit

Cabla
MZ1

11

/MZ

C't~

RAM

PWB

1 R

22

7

MZ1F16

MFD

DIG

5"

ß;/.Z

MZ 1KOg
MZ 1
MZ 1 K

KlO

11

(Germany)
(Frenchl
(English)

Mouse

MZ

lX

I

10

Specifications

System

1) High
microprocessor .

2) Large addressable

256KB

3) High-resolution color graphie display with large-capacity
video screen

4) One or

provided as a

10.7MB

5) Powerful

6j

Integraled

ep/M86

7)

highlights

data

processing capability achieved

memory

plus an additional

memory

two

mini·floppy disk drives, each

standard

Hard disk

standard

as

sound

the

is

standard.

1/0

generator .

standard

2~6KB

and

bit·map

feature.

system

operating

space

of

.

display.

And

interface .

system .

5·

12

the

with a 16

Kß:

Standard

of

640KB

MZ5645

-bit

are

is

~

VRAM
MZ1R09

Fig.2

.

L;?

PWB

{96KB)

Model

Model

MZ ·
MZ ­MZ -

Specification

No.

..

Tracks/side
By

les/sec
Sef'ors/lrack
T

dlal

Bytes/block

description

5631
5641
5645

Ilem

of

side/drive

lor

Bytes/Drive

Conlains
Contains
Comains

of

I

one

IwO

one

Disk

MFD

MFD's

MF 0

5513216

4096

Description

plus

256KB

plus

and

one

HO

1

673

512

16

256K

HO

01

Bol

plus

RAM

RAM

256K

MFD

327680

.

2

40

256

16

2048

.

BRAM

._

-

---

~

--

-

-"

-

~

1-3

HZ-5500

specification

I'em

--_

CPU

. .

_._

----

MEMOR

DISPLAY

..

Y

ROM

RAM

I/ F

Display

scheme

Screen

con"guratlo~

by

system

soft

(CPM

111)

ware

Std./Opl.

Sto

.

.

.

.

.

.

8086
8087
80C49

IPL

SYSTEM
VRAM
SYSTEM

VRAM

Opt

Std

Std

Std

Std
Opt
Opl.

Monochrome

Color

Std. Resolution

Pages

Arithmetic
For

keyboard

16KB

256KB
96KB
256KB
96KB

Composite
A.G

.B.V.H

Bit

map

Resolution

640 x 400

B/W

640 x 200
320 x 200

640 x 400

C

640 x 200
320 x 200

and

signal
SYNC

display

logic

contro!.

processor.

Number

Installed
Available

of

pages

3

6
B

6

B
B

Descriptioll

in

the

Expansion

by a RAM

PWB.

Unit

.

Opt

.

! .

Color

Gr

anat

Ion B

SCI

een/char

acter

Display

confIguration

Character

-

~

Screen

control

Super

Multi·window

Serail

Reduct

expansion

Palette

Background
Color
Reverse

Boundary

capacity

~

fell

imposed

ion/

feature

priority

video

color

color

640 x 400

BIW

640 x 200
320 x 200

640 x 400

C

640 x 200

8

colors

dot'

gradat

dedicated

40

or

80

The

number

progr

ammable

8 x

B.

8 x

3

pages

4

windows
Character
Smooth
Software

B

colors
Can

be
Planes
Reversible

320 x 200

lean

be

ions

available

monitor.

characters

of

.

16

seroll

scroll

control

availahle

specilied

with

order

for

each

specified

on

rOw5

per

lor

each

of

priority

window

with

each

sereen· is

4
4

4

2
4

B

for

each

the

row

window

.

.

.

.

When

optional

InstaHed

Available
monitor
400

matrix

Controlled

Horizontal
Verlical

colors

8

Availahle

other

than

model.

VRAM

.

on a monochrome

(J

013'

wilh a 640

.

by

software

or-vertical

direction

on

the

only

all

color

640 x 400

direction

is

x

.

.

.

models

dot

I
I

Integrated

1/0

Item

interläce

Sound

Centronics
C.

lock

MFO

I/F

AS·232C

Key

ItF

Casselte

I/F

I/F

Std./Opl.

Std

Std.
Std
Std

Std

.

Std
Std
Std

. .

.
.

.
.
.
.

Real·time

Chennel

A

Channel

B

clock

Three

codes

in

speaker.

One

channel

Backed

Capable

Start

-$Iop

Stan·uop

I

~

available

up

by

battery

01

controlling

asynchronous!sync

asynchronous

througha

.

up

tO 4 drives

.

.

built

·

For

Built
Two

.

external
Programmable
and

Not

printer

·in

13

built'ln

9600

u~d

Descriptlon

attachment

byte

dr Ives

drives

.

between

bauds

RAM

.

plus

.

twO

110

OP

1/0

Additional
device

CRT

Printer

I/F

256KB

HO

I/F

Expansion

SFP

I/F

Mouse
MFO

MFO

unit

Hard

disk

sFD

unil

12"

monochrome

12"

color

15"

color

BO

columns

BO

columns

AAM

PWB

PWB

unit

display

display

PWB

Unit

. -' - .

in

color

Opl.
Op\.
Opt
Opt.

Opl.
Opt.

Opt

Opt.
Opt.

Opt.
Opt.
Opa.

Opt.
Op\.

.

.

-

Single

drive
incremenl.
Contains
drives.

Contains
drives

.

,wo

two

Expansion

Hard

dlsk

SFD

I/F

Attached
Additional
the

Synem

E)(

,er

nal

1a.'1M

Bytes

External

640 x 400
640 x 400

640 x 400

RAM

dr

ive

PWB .

to

drive

Unit

dr

ives

drives

dot
dot

dot

PWB.

I/F

·.PWB.

keyboard

to

.

matrix
matrix

matrix

.

be

installed

MZ-1Ett

Avallable

in

Available
For
ÄVililable

Available

Available

MZ·'

with
wilh

MZ5511

with

with
wlth

013

the
the

only

the

the
Ihe

MZ-IX
MZ ·

IF

MZ ·1f02

MZ · IF10
MZ

· !

Fa5

10

oq

.

MZ -l0'4

MX-l0IB

MZ 1

MZ ·

IP02

MZ · IP04

P07

----

.

e;-

1-4

HZ-5600

specificatiqn

Itern

CPU

MEMORY

DISPLAY

ROM

RAM

1/ F

Display

Scre!,n
by

system

(CPM

scheme

conllguratlon

soft

1111

ware

Std./Opt

Std.
Opt.
Std.

Std.

Std.

Std
Opt.
Opt.

Sld

.

.

.

t

8086·2

8087·2
eOC49

IPl

SYSTEM
VRAM
SYSTEM
VRAM

Monochrome

Color

Resolution

"

Pages

(8

MHz)

(8MHz)

Maln
Numarlc
For

keyboard

l8KB

(8KB x 2)

256KB
96KB
256KB
96KB

Composite
R.G.B.V.H

Bit

map

Resolution

640)(

B/W

640)(

320)(

640)(

C

640)(

320)(

deta

signal

SYNC

display

400

200
200

400

200
200

procauor.

contra!.

.

Number

Description

Insta"ed
Available

of

pages

3

6
8

6
8
8

in

the

Expansion

by a RAM

PWB.

Unit

.

Opt

...

.

COlor

Gradation

I

Scr

!'en.char

conl'gurat.on

I--

Sereen

ac ter

conlrol

Display

cClpacity

Character

Super

~

Mull i­Scroli

I

Reduclion/

expansion

Palette

Background
Color
Reverse

80undary

eell 8 x

imposed

window

fealure

priorily

video

color

color

B/W

640 x 400

640)(

320)(

640)(

C

640)(

320)(

8

calors

lean

dotl

8

gradations

dedlcated

40

or

80

charaete,s

The

number

programmable.

8,

8)(

3

pages

4

windows
Character
Smooth

Software

8

calors

Can

be

speeified '.or

Planes

with

Reversible

sero"

available

.

200
200

400
200
200

be

available

monilor

of

16

sero"

control

order

for

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disk

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expansion

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option

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disk

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line

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READY

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8284

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to

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132K

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192KB

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512KB

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for
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is

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user

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user's

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MZ-5500,

for

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bit

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300 - 33FH

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area

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MZ-5600,

signal
in

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the

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is

automatically

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area

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the

same

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the

8MHz

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180 -

and

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created

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the

system.

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wait

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inserted

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to

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to

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120-12F

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140-14F
150-15F
160-16F
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340

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o
o

1 0

1 0
1 1

1 1

o

o

1
1

o

o

o

1

o

o

1

1

1

o X X

o

1 X X

o

o

1

1

A3 A2

1 X X X

o X X X

1 X X X

o X X X

1 X X X

o

o

o

o

o

o

1

1

o

o

X

A2

Al

0

X A2

Al

0

X X X X

X }

X X

X

Al

AO

Al

AO

Al

AO

X PSG (AY-3-

X CTC INT Aeset

X

X CTC

X

Note}
Note

User

Note
Note

Reserved

SIO

(LHOOB4A)

CTC (Z -

ATC

(PA5COl)

510

INT

Return

PORT

-B

}

R.",v.d

area

User

}

} Aeserved
}

Reserved

Not

Ready

the

Syslem

}

area

80CTC)

8198)

Aeset

INT

For
generales Wlt

Unit

... 1 Waitl

100

-7

100

-7

100

-7

100

-3

X

X

100-7

100

-3

.

, 3 Wait

~

1/0 sIal

h'

-

In

User area ,

T I

o

Waitl

5MHz

8MHz

Byte

Access

__

X AC K

NOlf' :

XACK:

In
returned

initiates

180H

the

10

1BF H:

8MHz

in

bootstrnpping.

PWB

checker

mode

of

the 0 wait

the

MZ-5600, 1

timing.

X :

If

Not

in

wait
XACK

Oecode

is

was

00
100

automatically

not

-15 - 16 Bit

-8 - 8 Bit

returned

syslem

"0

BUS

inserted

within

BUS

when

130ps,

XACK
CP/M

is

I/U

(1)

System

OEV

8255

[G'OUP

Mode
Group

Mode

bit

,ICE

A.

1

B

0

map

board

AOD

DlOH

Dl1H

012H

(013H)

NOTES

1)

Group

2)

Group B is

3)

The

4)

The

5)

While '

MZ-5500/5600

BIT

SIGNAL

fAD
PAl
PA2
PA3

PA4
PA5
PA6
PA7

PBO

PBl
PB2
PB3 DK
PB4
PB5
PB6
PB7

PCD

PCl
PC2

PC3 IA-PAT
PC4
PC5
PC6 ACK
PC7

:

,A

is

used

used

desired

bit

bit

PC6

the

AC!<

is

in

in M'

otfthe

an

interrupt

may

nATAS""

6DATA6

MOTOA

EXCLK

STRÖBE

Mode

ode

be

NAME

OATAl

OATA~

OATA3
DATA4

DATA7

DATA8

BUSY

PE

POTA

SRK

CO

er

ON

OC

STC

EN

1.

O.

output

enable

read

to

Group C may

tlag

by

PC3,

1/0

OUT

IN

OUT
OUT
OUT

OUT

OUT

IN

OUT

is

Output
Carrier

Called

Strobe
BSC

Centronia
Centronia
Not

(INTEl.

needs

Table 2 - 2c\.

Data

output

Null

codes

Centronics
Centronics
Centronics
Oata

bit

from

requested

sense

signal

MFD

motor

Data

bit

to

to

external

Interrupt

used

.

be

set

or

and

is

set

not

be

read

to

are

hex

I/F

busy

I/F.

I/F

select signal

keyboard

}

on

$latus

keYboard}

keyboard

dock

bV

ACK

I/F

STROBE

I/F

ACK '

reset

or

reset

8S

its Status

Centronics

trom

fCir

input

using

I/F (negative

F F.

(busy it

zero

,)

(selecu

it

one.)

CPU.

mode

(LI)

register

to

}

the

keyboard

synchrOnQI~

input

(BSC if High)

to

Centronics

output

input

the

control

by

the

is

known

polarityl.

K,y

I/F.

(013HI.

CPU

via

the

PIC.

AFTER

Input

mode
(FF

Mode
input

Input

mode

(FFH)

P/O

'H)

INITIAL

OEFAULT

Output
mode

(FFH)

Mode
input

1
0
0

0
0

1

X
X

OEVICE

AY·3·8912
(Sound

IC)

PORT·A
(

LS5411

AOO

230H

060H

SIGNAL

BIT

IOA4
IOA5
IOA6
IOA7 MA2

100
101
102
103

104
105
106
107

MOTOA

MAO
MAl

High Den

ASTSW

DIP

SWl

DIP SW2

DIP

sm

DIP SW4
DIP SW5
DIP SW6

NAME

ON

1/0

OUT

IN

Table

motor

Drive

}

Am

IAOOOOH-BFFFFHI

RESET

switch

,

SWl
SW2
SW3

SW4
SW5
SW6

Z-2~

on

input

System

next

(see

signal (on if

(on

if

zero) -MFO

DIP

switches

page)

Low

b,nk

,)

,,'eet

';gn,'

selection

AFTER

P/O

Input

mode

(FFH)

Input
mode

INITIAL

DEFAULT

0
0
0

0

t

0
0

Input

mode

23

When

sound

wr

ite

accessing

le),

load

the

1/0 data

the

rIo

to

1/0

port

register

230H.

of

the

address

AY·3-8912

into

231

H,

then

(2)

When
output
output
MOTOR

initializing

(described

mode.

This

ON

signals

the

above),

is

needed

inactive

lOA

port,

then

to

during

write

the

place

the

maintain

initialization

port

the

data

SE

in

.

to

the

land

be

Table

2 -30..

OEVICE

PO

RT

-C

(LS175)

PO

f-H

-B

(LS125)

TL\.ble.

DEVICE

PORT

(LS74)

PORT-B

(LS367)

*1/0

2 -

-C

the

AOO

070H

nOH

3b

AOO

070H

270H

address

MZ-5600.

MI.

-5500.

BIT

100

101

102
103
100
101

102
103

MZ

-5&00

BIT

100
101
102
103

100

101
102
103

area

SIGNAL

----------

WRCT

MOTOR

FOCRST

RDCT

SEr

DIP
DIP

Signel

shown

NAME

,J

SE

SW7
SW8

name

in

1/0

OUT

IN

1/0

the

~

~

High
FOCRST

Den

OUT

~

DIP

SW7

-----

DIP

SWS

IN

table

Oedicated
Oedicated

F

OC
Oedicated
Oedici:!ted casse

(0

SW7 }
SW8

MF 0 • 1

SW7 }
SW8

: SW

FOC

("0"

Reset

OFF

System

reset

- SW

cassette
cassel1e

signal

cassette

, 1 : SW

M/640K

signal

System

below

Write

Motor

(reset

Read

tte

Sense

ON

DIP

alternate

(reset

OFF

"1"

DIP

may

signal

signal

when

signal

signal

and

Switches

with

-

SW~ON

SW (See

differ

(No

(No

one.)

(No
(No

C.PU)

(See

signal

"1'"

separate

use'

use)
use)

page.l

&

CPU)

use'

between

page'

After

Oon't

Input

the

MZ-5500

AFTER

P/O

Indefinite

Input

mode

power

care

mode

on

and

INITIAL

OEFAULT

Initialize

v)

System

switch

Table

S\o11

SW2

SW3
SW4

-- --

--

Switch

SW1
SW2
SW3

l

SWS

2-4-b

OFF

ON

OFF

ON

Table

No.

400

Normal mode

SW3

0

1 0

SW6
SW7
SW8

System

Description
High

resolution
display
rasters)

Medium

display
rasters)

Normally

Seifeheck

Fixed
Fixed

to
to

-

---

2-4-a

raster

SW4

0

8086

operated

Open

to

dip

switch

(400

used

resolution

(200

used

OFF

mode*

ON
OFF

System. dip

OFF

(1 D

10,11)

SWS

0
0

Standard
MZ-80BF

Reserved

user

definition

Factory
setup
OFF

ON
OFF

switch

CRT

8087

definition

200-raster
Selfcheck

MFD

opera

ted

(MZ-S600)

OFF

SW5

ON

OFF

SW6

ON

SW7
SW8

drive

Description
8MHz

SMHz

8087
processor
used

8087.
processor

(MZ-5500)

ON

CRT

mode

(S4B) DT/DD,

CPU

clock

CPU

clock

numerical

not

·
numerical

used

IF02,07,09

Factüry
setup

OFF

'

System
Tables
the

1/0

switches

2-3-a

and

address

of

the

2-3-b.

60H

MZ-5500/5600

As

these

for

all

models,

are

switches

they

25

assigned

are

are

sensed

to

functions

assigned

by

to

the

bit,
IPL

shown

ID2 -ID7

at

power

in

of

on.

3.

:3

-1.

i)

Interrupt

Inter

t-tApt

Circuit
Two

chips
circuits
A

high

on
applies
the

interrupt

Because

be

accepted

When

the
Controller.
second

the

INTA

data

circuit

(;

H-C.t.(,.t

description

of

8259A PIC

are

shown

the

interr"upt

an

interrupt

input

the

INTR

at

any

CPU

receives

To

which

is

sent

bus.

below.

line

time

are

request

to

device.

is

interrogated,

of

the

unless
the
the

8259A

from

the

used

for

line

CPU

it

interrupt,

forces

CPU

the

MZ-5500/5600

of

As

the

state

the

is

asynchronous,

has

been

INTA

the data

via

the

the

8259A

INT

prohibited

i8

8288,

Interrupt

of

the

signal

an

returned

bus

an

8-bit

series,

mask

is

issued

interrupt

by

via

high

vector

and,

Controller

and

priority

to

CPU.

request

the

software.

the

8288

impedance.

is

their

Bus

sent

As

of

can

the

on

L e

ge

n

Timings

cl:

. T

cu

11.

he

y,"",

Jr-Tm

lI-nrT

~

II~

~

iI-IR

1J-filC

--rz

11--

Jr-1r

iT=1i

Jr-T

Tr-T

IlAI

\J

m a r k

U

IHT1I I

sr

!lA'

L-~_""-.J-------'--fTR"T~

re pre

sen

t s t h e

6.

8

kn

....

SI

s~

pu 11u P res

ist

0 r .

IIrT

IIrTA

Fig.3-1

Interrupt

circuit

diagram

2(,

and

timings

ii)

3-2.

mi1

With

two

(1)

The

(2)

Timeout

memory

monitor
unless
and

Handling

(Non-Maskable

the

MZ-5500/5600

purposes:

System

signal
period
If
period
system

Since

software

8086

the

NMl

reset

as
from

system
which
will

the MZ-

or

the

does

with

the

may

be re-

monitor

5500/5600

1/0

bug,

circuit

ready

is

issued

of

user

Interrupt)

series,

not

have

the Z-80.

CTe

is

reset
possibly

initialized

area
it

from

makes

is

provided

signal

to

interrupt

NMl

the

function

Whereas,

to

DMA

hardware-wise,

destruct

with

is

normally

which

the

was

the

epu

epu

no

by
not

at

stoppeu

which

to

the

to
DREQ
read · the

the

NMI

a

non-ready

ready

the

returned

the

same

8086

send

i5

refresh

memory
by

the

signal
in

appearance

ready

within

time to

CPU

the

dynamic

issued

dynamic

is
contents.
software,

system,

is

sjgnal

is

used

in

suspended

retllrned

the

inform a timeout

for

the

RAM

refresh

the

prescribed

RAM

to

refresh
for a certain

Therefore,

instead

accessing

due

.

So,

the

is

forced

predetermined

following

of

the

to

a

timeout

to

tjme
error.

it.

tbe

reset.

return

i)

Hardware

As
slots,
to

°

Since
state
retained
use
or

there

the

the

the

lR-26

are

several

only

the

following

the

8259A

of

interrupt
until

device

hardware

Opec

coll

-o(]---i

interrupt

IR- 26

conditions

applies

the
that

that

ec

request,
epu

can

tor

is

open

the

acknowledges

clear

may

clear

:;>u

signals

for

user's

when

designing

inter rupt
the

interrupt

the

interrupt

it

via

(ex;

A'ioW(

1/0

it.

IR

used

use.

to

the

request

There fore,

the

1/0

Open

-2b

------o(J---!

decode

1

BOH)

for

the

The

the

int~rrupt

CPU

request

port.

collector

MZ-5500/5600

user

must

circuit.

upon

detection

signal

it

is necessary

by a

t5v

Q

I~ltff

IL

-U-

pay

has

to

softwar

expansion

attentior.

oE

Ili gh

be

t o

e commnnd

lssue

at t

hel

" e

lnterrupt

th

beginn"

processi

NT

res

lng

e t

command .

of

the

ng

routin

e.

Force the

th

e

beginning

processing

2?

port

r o

l ow l e

oE

utine.

the

vel

at

interrupt

ii)

Software
The
processing

followingprogramming

using

the

machine

is

required
language.

in

order

to

perform

interrupt

°Set

interrupt
°Clear
O(Execute

°For

the

-Level

-8086

-Normal

-Free

Main

to

the

processing

the

8259A maske

the

MZ-5500/5600 , the

trigger

mode

EOI

mode

nested

top

STI

mode

mode

routine

address

of

routine

command)

following

the

modes

Interrupt

°lnterrupt

0lssue

are

assigned

routine

acknowledge

processing

1

the

EOl command

to

the

8259A PICo

.

to

the

8259A

lnterrupt

(1)

Jnterrupt

The
routine

the

As
address
set
offset:

interrupt

written

Segment
Offsel

top

main

shown

in

routine

address

address

must

of

sequence

be
routine.
in

the

each

100H".

routine

in

14th

0:

100H+4*14

programming

designation

of

the

interrupt

assigned

figure

interrupt
from
The

for

address.

right,

"segment

top

address

the

mode

at

the

routine

IR-26

processing

start

the

top
can

0:

of
must

the

be

be

of

0:

0:

IOOH+4*14

IOOn

Offset
Segment

Offset
Segment

28

(2)

PIC mask

Since
the

the

interrupt

register

IR-26

unless

has

clear

been

the

masked
mask

register

initially,

is

it

does

cleared.

not

permit

to

accept

(3)

PIC mask

The

IR-26

IN

AL,

AND

AL,

OUT

42H,

EOI

generation

At

the

the

end

MOV
OUT
OUT
IRET

Example:

register

should

42H

OBFH

AL

termination

of

the

interrupt

AL,

20H
40H,
30H,

AL
AL

CSEG
ORG

lOOH

1/0

be

programmed

of

the

address:

interrupt

processing

Master

Slave

as

PIC

foliows;

routine,

to

the

PIC

...

....

PICo

32H

42H

there

is a need

of

informjng

INT26:

XOR
MOV
MOV
MOV
MOV

INC

INC
MOV

PUSH

POP

I

CLI

IN
AND
OUT

STI

MOV

OUT

BX,

BS,
BX,
AX,

[BX],
BX
BX

[BX],

CS
DS

AL,
AL,
42H,

DX,
DX,

EX

BX

lOOH+4*14

OFFSET

AX

CS

42H
OBFH

AL

IBOH

AL

INT26

1

Programming
interrupt

J

Assign

J

Clear

1

Interrupt

J

Interrupt

address

the

8080

the

mask

enabled

acknowledge

the

model

register

MOVE
OUT
OUT

IRET

AL,
40H,
30H,

20H

AL
AL

2~

J

EOI

generated

3-3.

The

and
interrupts

when

i)

Sinc e the
high

r equ e

Th

reque
As
dcsi gned

a)

System

MZ-5500/5600

the

1R-25

designing

Hardware

state
st

e re

for

e ,

st

tlle

IR-25

~~en

the

interrupt

is

of

eight

the

8259A

of

an

signal

has

there

by the so

inte rr

as

to

de t cct

interrupt

(lR-25)
expansion
used

for

levels,

interrupt

lnterrurt

interrupt

to

be r e
i s a need
ftwa

re

oga

t e s

t~

elear

specification
slots

system

attention

cireuit.

Controller

request
tained
of

or

the

multiple

e

device

and

port

have
expansion.

until

using

software

with

several

must

issues

input

the

the

deviee

that

interrupt

the

output

interrupt

As

it

be

paid

the

interrupt

(low

on

CPU

reeognizes

that

elears

by a software

interrupt

functions

tsv

supports

to

the

ean

it

request

are

request

the

1/0

elear

on

hardware

multiple

following

to

the

slot),

the

the

the 1/0

polling,

on

input

points

CPU

with

the

interrupt

interrupt.

interrupt

port.

it

the

r/o

comprised.

lines,

As
i s
port.

a

so

b)

When

IR-2S"

,0

1/0

(e>.

AiDW(

using

J!a

(e;t0

f)11

'J1:

0,,-/)

Re.

~-~

deLc

·

:

fCDH

)

the

deviee

D1t

1J

1

0,,15

;oRc

d~~c\~

1(0\4)

that

o~

D

J...-------t

(.

has

the

interrupt

U:'I\:dbr-

~~-------------;;~

clear

;

NT

funetion.

c)

\.Jhen

internal

using

the

register

device

interrupt

that

has

request

the

interrupt

flag

sensing

clear

funetion

funetion.

and

the

ii)

The
machine

Software

following

language.

procedure

is

required

when

interrupt

is

processed

using

the

~1o.lt'\

'Wa.il

~r-j\,«

inre\Tupt

Se

·t

to

fu

prou~'h

;

t\l.~

(.leoy

1ttl

·)et

-to

1~1errupt

olJ

For
Für

1vp

proc.ess;n~

-top

routi0e..

~sLl

t\~

:

top

theMZ-5500/5600,

more

loutj'

ne..

.Jress

0+

-the

rou1ine

acldre5s

~tM

inierrupt

' . / . .

A

Vntl'7~

, • .

OdJ;Q5S

pnx:es5;~

of

-tt~

nxrltne

. t

the

details,

refer

old

/J

. ' .

.J"tertUpt!juJ1<1li1e.rt

I k I .

"terrur~

•

Issu~

tb

~l\1qA

IRE

,

following

to

the

T

müdes

8259A

IY\terrupt

0.(

'

How

€'c{je..

fO[

comMllluJ

~

- - - - - - - -

are

assjgned

specifieation

proce~)iVLj

~-Q.'h

~~

.

~

the

_I

to

sheet.

rOi.ltiV1~

0\

~&

~

,

i\~'\~~

()\~

'

~

.

ih\~

~~

the

'{

~i

V.

8259A

'Io.. ,\'(\1J.-

'

PICo

°L

evel
08086
°Normal

~

Free

Interrupt

(1)

Interrupt
The

the .start

address
offset:
must

written

Segment

Offset

Before

writt~n.

trigger

mode

EOI

nested

~

routine 'programming

top

be

writing

mode

mode

addre~s

address

of
of
100H".

in

0:

100H+4*13

the

eaeh

13th

of

The

address.

the

main

interrupt

designation

the

interrupt

routine.

routine

top

address

address,

mode

be

0:

100H

0:100H+4*13

processing
As

shown

ean

be

of

the

interrupt

sure

to

save

in

set

r------,

Offset
Segment

routine

the

fjgure

in

sequence

routine

the

address

}IR

JIR-I

~

must

-O

be

assigned

right,

from

for

previously

the

"segment

the

at

top

0:

IR-25

31

(2)

(3)

PIe

Since

the

PIe

The

IN

AND

OUT

EOI

At

the

the

mask

IR-25

generation

end

register

the

IR-25

interrupt

mask

AL,
AL,

register

should

42H

ODFR

42H,

AL

termination

of

the

clear

has

unless

1/0

be

of

interrupt

been

masked

the

mask

address:

progranuned

the

interrupt

processing

initially,

register

Master

Slave

as

foliows;

is

PIC

PIC

routine,

to

the

it

does

cleared.

...

32H

....

42R

there

PICo

not

permit

is a need

to

accept

of

informing

HOV

OUT
OUT
IRET

AL,
40H,

30H,

20R

AL
AL

\,

32

Programming example

'

CSEG
ORG
CLI

XOR
MOV
MOV
MOV
MOV
MOV
MOV
ADD

MOV

MOV
MOV
MOV

100H

AX,
DS,
BX,
AX,
CS=INTADR,
AX,

1

[BX],
BX,
AX,
CS:
AX,

[BX],

INTADR+2,

(for

the

AX

AX

100H+4*13
[BX]

AX

OFFSET

AX

2

[BX]

CS

AX

INT25

circuit

AX

example-

Saving
interrupt

):

and

setting

address

INTADR

INT25:

i'

INTA:

PUSH
POp

"

IN
AND
OUT

STI

I

DB

PUSH
PUSH

MOV

IN
AND
JNZ
POP
POP

JMPF

OUT

MOV

OUT
OUT
POP
POP
IRET

CS
DS

Al.,

42H

AL,

ODFH

42H,

AL

0, 0, 0,

AX

DX

DX,

lCOH

AX,

DX

AX,

1

INTA
DX
AX

CS=INTADR

DX,

AX

Interrupt

AL,

20H

40H, AL.

30H,

AL

DX

AX

0

J

8080

Clear

]

1

Interrupt

Interrogate

1

To

J

J

processing

l

next
routlne
Interrupt

EOI

model

the

1

level

genera

.mask

enabled

acknowledge

ted

register

interrupt

interrupt

and

return

3'3

4.

Software

j)

Hardware
One

it

have e

Each
7,

Fig.4-1
controlling
MZ-5500. A

read,
CPU.
acknowledge

the

A

different

circuit

MZ-5500 D..nd

it
accessing

and

timer

chip

has

however,

Z-80

has 3 waits

15

of

four

ight

channels

channel

shows

write,

Input

CPU.

is

timing

waits

the
channels.

are

channels,

timing

of
cycle

CTC

provided

the

Z-80A

are

has

the

specification

the

specification

the

block

control

interrupt

"OEDH"

and

timing

for

MZ-5600, and

for

the

of

the

for

the

HZ-5600.

CTC

is

used

For

the

MZ-S600, two

used.

diagram

4

to

7,

muat

circuit

acknowledge,

ancl "04DH"

thc

illterrupt

control

the

1/0

MZ-5500

for

as

applicable

of

the
be
is

and

to

the
return

IORQ

11Wtr

nArr

nnT

the

software

shown

MZ-5600
omitted
added

interrupt

1/0

cycle

CiC

llroincl

(on1rc'

timer

chips

in

for

to

port

of

Table

the

software

from

t--____._-+----1f---tI41rn"

the

control

return

(260H)

correspond

lASTS

of

the

Z- 80A

4-1.

MZ-5600

timer.
figure
the

cycles

for

.....

"'

CHo-l

~

"

vr

the

MZ-5500

CTC

Channels,

only.

The

for

the

Z-80A

the
to

lt:./TOt

CTC

by

interrupt

"RETI"

.

which

4

CTC

1/0

the

of

RSmC(I!)

eI

oe"':.

and

to

8086

Ch

0

4
5
6

1

2

J

7

1/0
210H

21]

H

212H

21311
21411
215H
216H
217H

adr

Mode
Timer

i

I

Counter

t

t

t

t

Table

Prescale

4--1

Int

1/16

i

i

--------

~

--------

-----------

----...------

Channel

Time

x 2

x

x 16

32
64

87

0

0.832ms-213ms

0

0.052ms-1J.313ms

0

0.832ms-213ms

0

0.832ms-213ms

0

3.328ms-852ms

specification

constant,

9600b/s

1

4800b/s

2

2400b/s

4

8

1200b/s
600b/s
300b/s
150b/s
110b/s

'----+---+4l1'T

~

Fig.4-1

L-t--~"Tmftf

~-+-~m

Block

etc.

Refresh

I58/2ms
RS232C
Ch

A

Tx,

RS232C
Ch

B

Tx,

System
Reserved
Reserved
Reserved
Reserved

ClK/TR("~---'

CH4-7

diagram

timer

"

Rx

Rx

timer

Model

5500/

5600

5600
only

\'

ii)

Interrupt

If

the

aeknowledge

/

the

processing

intcrrupt

be

issued

higher

following

~

ease

proeessing

CPU

is

eyele

of

the MZ-

routine

of

to

priority

deseribes

the

Z-80A,

and

5600,
by

the

MZ-5500/5600,

the

8259A,

at

the

the

the

the

interrupt

there

the

software.

when

end' of

operational

Z- 80A

is

the

it

is

the

CTC

a~tomatieal1y

return

a

need

cycle

of

exeeuting

Besides,

interrupt

possible

interrupt

to
processing

flow.

by

as

the

terminate

accept

exeeutes

its

hardware.

the

interrupt

8259A

manages

command (EOI)

an

interrupt

routine.

the

interrupt

But,

,

the

must

of

The

in

a

~

Interrupt

proce66

....

-'

I

"OV

DX,240H

IN

,

Al,

DX

f

Interrupt

diS

cl,(\nnel

t i (\ ct,i

on

I

"OV

DX.260H

"OV

Al,OEOH

OUT

DX,

MOV

OUT

AL
Al,4
DX.AL

DH

I

.\

Jnterrupt

process

I

"OV

Al,20H

OUT

30H,AL

STJ

,

'-

I

I RET

-....,

,

I

j

~

~

~

Dummy,

Dummy,

EOI

interrupt

interrupt

command

acknowledge

return

cycle

eyele

1ii)

Cheeking

The Z-80A

interrupt
set

in

the

dummy

ean

be

Because

the

veetor

interrupt
CTC
acknowledge

the

AL

interrupt

known

the

from

vector

"08H"

~end~

out

register

aeknowledge

the

"OH"

must

ehannel

the

eycle.

when

state

has

be

set

(MZ-5600

interrupt

Since

th~

MZ-5600

eyele,

of

the

been

set

in

the

only)

vector

the

vector
executes

the

register.

in

the

CTC-2.

35

in

the

is

channel

CTC-l,

Ch 3 Vector

06H

4

08H
OAH

5
6 '

OCH

,

7

OEH

I

l

iv)

Interrupt

The

software

formula.

t = K x T / 19200

~lere,

t:

Interrupt

T: Time

K:

Constant

eyele

timer

Ch

3:

Ch

4:

Ch

5:

Ch

6:

eh

7:

eomputing

interrupt

eyele

faetor

dependent

16

1

16
16

64

...

method

[s]

Value

o

must

eyele

set

be

on

and

must

in

handled

the

time

be

the

CTC

ehannel

faetor

obtained

as

256.

setup

with

the" following

Sinee

used.

Ex:

the

To

generate

Time

To

disable

NOTE:
Range

ehannel 3 is

interrupt

eonstant

MOV
MOV

MOV

MOV
MOV

OUT

OUT

OUT

of

DX,
AL,
DX,
AL,

DX,

interrupt

DX,
AL,
DX,

the

time

216H

OC5H

AL

12

AL

216H
4lH

AL

CT)

already

at

10 x 10-

to

[aetor

every

the

set

used

by

the

lOms

on

3

x 19200 / 16 = 12

ehannel

in

the

6.

CTC

system,

the

ehannel

is

as

ehannels,

6.

foliows:

4

to

7,

must

be

o

to

255

("0"

slgnifies

"256")

I.

3G

5.

Expansion

5-1.

The
i.

nsta11ed

slot

MZ

- 5590/5"hOO eXpatls/Oh

figure

be10w

to

shows

the HZ- SSOO/

slot

the

(MZ-:

condition

sboO

ser'es.

lUD5)

when

the

MZ-1UOS

Expansion

Slot

is

2\

KEY

0

. L

Board
Since

to

which

tab

Slot

1/0

foliows:

·

SL6T

5LoT

M

[Nl

\

inserted
all

insert

shou1d

between

signal

signal

2

~LOPP,(

DISK

)

in
signal
the

board

be

inserted

the

slot-l

1ine

lines

PRLNTER

\ i

the

slot

lines

in

interface

of

the

1/

are

arrangement

any

slot,

in

and

slot-3

board

SLÖT

P.S232C

(A)

~~OO

with

the

slot-l

must

to

be

inserted

~

SLOT

4

RS2

.\2C(BJ

common

exception

or

slot-3.

be

removed.

B/W

for

in

G

~T

all

for

the

131

ll

WLD!'-ll'T

slots,

the

In

this

slot

0

HD

interface
event,

must

· 0

[3

I I

r v

it

is

possible

th~

be

treated

j

board

guide

as

*See

Current

Per

slot

~I

o

OUT~UT

~6e

the

hardware

limit

I.

STTL

the

open

information

for

slot

LSTTL

[>0---

lS245

c<::}--

or

standard

collect

or

(MZ

- 5500

vnn

(+

12V) I VGG

SOmA

x 1 .

equivalent

--

TTl

for

the

for

I

interrupt

terminal

series)

(-12V)

lOmA

and

lACK

arrangement

only

and

board size .

s~

5-1. Expansion

signal

description

(common

for

the MZ- 5S00

and MZ- S600)

nam

Signal
AO

- AI9

DO

- DIS

e

MRDC
MWTC , AMWC

IORC

10WC,

JNTA

AIOWC

IOACC

MAO-MA2

In/Out

Out

ln/Out

Out
Out

Out
Out

Out
Out

Out

Function
°Memory,

IOACC=l:

1/0

Memory

10ACC=O : 1/0

functions

°AO

(DO-D7 ) of

attention

°Pay

issued

°A

16-bit

a t a

data

between the

transfer

°Memory

°Me~ory

°Ihe

MWIC signal
AMWC
high

°During

be

read s ignal.

write signal

signal,

to

low

DH!,-,

timing.

r ead

°r/o

°1/0

write

°Ihe

AIOWC
high

°During

timing
°lnterrupt
°Ihe

the

lOACC~1

IOWC

signal,

to

DMA,

.

signal
1/0.

signal

signal.

signal

low

acknowledge

Ihe

and

lOACC=O.

°Bank

AOOOOH

select

- BFFFFH.

manner:

address

signal

address

the

the

time

CPU

address

same

data

to

it

when

signal

and

bus.

- -

BHE

as

that

an

addressing

which

the

memory

tween the memory

.

sho

the

two

rter

write

of

signals

i s

and

transition

the

se

.

is

shorter

the

two

write

of

signals

and
tl-ansition
these

signal

used

memory

the

signal

to

indicate

1/0

for

Each

decoder

decod

the

bank

er

which

for

invalid

is

used

and

by

one

da

ta

signal.

the

are

by

one

da

ta

the

s

are

from

that

must

must

memory

is

used

represents:

low

address

signal

for

the

or

the

1/0

CPU

is

es

issued

CPU

is

es

ignalt

issued

the

the

be

be

enabled

address,
in

order

ch

anges.

byte

transfer

1/0,

or,

during

clock

tablished

at

clock

tab

lishe

at

CPU.

epu

is

enabled

the

following

may

be

data

DMA.

than

the

at

a

the

same

than

th

.d

e

at

s

the

ame

accessing

with

with

a

XACK

In

HAI

MAO

1

0 I I

1 0 1
0
1

0 1 0

1
0

°Ready

on

signal

the XACK

°Must be

wired-OR.

HA2

1

0 1

1

0 0
0

driven

1

0

0

returned

area

Reserved

Not

used
Not us
Not us

Not

Not

Not
Not

by

of

ed

ed
used
used
used
used

~he

the

from

memory

open

the

device
map

collector

and

which

1/0

to

perform

is

map.

mapped

Signal

name

IR-22-IR-26

.\

In/Out

In

FUllction

°lnterrupt

slot.

IR-22
lR-23
IR-24
IR-25
IR-26

request

For

HD
For ,SFD
Not

used
Not

used
For

user's

input

from

interface

interface

use

the

device

on

the

1/0

DACK2
DREQO,
DACKO,

CLK86,
OSC

RESET
RSTSW

*See

5-3.

1/0

When

port
specification

DREQ3
DACK3

CL4M

the

next

address

an

1/0

address

Out

In

Out

Out

Out
Out

page

setup

port

must

such

°System
DDMA

transfer

°Channel 0 for

standard

°CLK86

isthe

MZ-5500

and

4.9152MHz when

MZ-S600.

°CLK4M

is

°Power-:-on-reset

~The

signal
switch
is

pushed,

for

the

timing

is

to

be

expanded

be

set

as

as

accessing

RAM

floppy

and

It
4MH

is

in

refresh

is

kept

an

the

time

signal.

request

the

and

hard

disko

CPU

clock

8MHz

when

the

is a narrow

and

OSC

signal

forced

low

depressed.

NMI

is

issued

chart.

on

the

expansion

table

of

below

the

ackllowledge

disk

and

which

the

system

switch-5

high

is

14.7456MHz

which

is

while

At

to

in

device

the

channel

is

4.9152HHz
switch-S

is

set

per~od

clock

clock.

normally

the

front

the

moment

the

CPU.

slot

by

reference

to

be

used.

signal.

on

low.

panel

the

the
to

3

with

is

with

of

'

user,

the

for

the

set

off

the

1/3

duty.

RESET

switcll

the

the

I

I

I

Access

tACC<
300ns<

time

300ns

tACC..c::.

550ns<"tACCS

*Because

need

the

more

from

550ns
100;Us

access

st~dy

IORC

time

before

(tACC)

shown

the

Port
180B - lBFH
300H - 3JFH
3COH -3FFH

in

the

actual

address

table

designing.

is

I

just

for

reference,

it

will

31

5-~.

1/0

1)

1/0

slot

read,

CLK~6

IOACC

timings

8MHz,

1

wait

(1/0

address:

180H

-

IBOn)

2)

1/0

CLK~6

IoA

1\0

rORe

DO"DIS

AO-vAI5

[0

DO'"V

BHE

P.C

DIS

read,

c.e.

"'Ab

BHE

8MHz,

T.

"\

TI

3

wails

(1/0

address:

300H

-

33FH)

(

{

I

C

I

)

3)

1/0

l

LI<-

10/\ C C

AO'''ÄI'l

fORe

Do

,,-

DIS

read,

~b

8MHz,

BHE

.

---------------------------

XACK

'

(1/0

address:

~

__~____________

Tw

3COH

- 3FFH)

Iw

~~

---4

Iw

___

--~~

T.w

_____

J

)~-------

4)

1/0

write,

8MHz, I wait

(1/0

address:

180B -

IBOH)

5)

.1

A'fl"A\S}

1}&"-DIS

1/0

LLK)b

IoACC

CL

K

86

IoACC

B

lowC

Arowc

write,

1\

LJLJ

\

~E

D

T~

L--.J

L-J

L--J

L---

,-

C

}

8~~z,

.

1I

3

waits

T

2

(1/0

T~

address:

~

300H - 33FH)

, I

Aft~IS/BHE

IOWC

D C

AroWC

D'O.

-,

DIS

6)

1/0

C,LK

IoAcc

r

A1i

--AJr;

IOWC

write,

~G

J

BHE

8MHz,

Ti

L--l-

.\

TI

XACK

T2.

~----~------------------~I

~

___________________

(1/0

\

address:

3COH -3FFH)

.

L

AIOWC

DO

rv

DI5

XACK

)

(\.,\

5-5.

(1)

1/0

16-bit

port

interfacing

input

port

examples

(1/0

address:

(user's

l80H)

job)

Lsz44

Machine

language

programming

6

6

example:

I ö

Ace.

Aq

A8

A7

Ab

AS

A4-

~

loRe.

(2)

16-bit

°When

~--

A~

A9

A7

Ah

4~

ALt

,ÖW!.. ---td

C

- -

---1

output

only

---Ll

ward

port

write

(1/0

D15

Dra

D7

~

PS

address:

is

done

:f) /5

D8

~

S·

D7

S

D~

320H)

°Word

MOV

IN

°Low

HOV

IN

°High

MOV
IN

°Word

MOV
MOV

OUT

I

input

DX,
AX,

order

DX,
AL,

order

DX,
AL,

output

DX,

M,

DX"

°Insignificant

will

byte

other

be

stored

byte

write

180H

DX
byte

180H

DX

byte

18lH

DX

l80H

--

AX

when

is

input

input

date

in

the

done.

the

,

(3)

~len

Al

A8

117

Ab

-4

~

ALt-

----I

!ö

~-----

BHE

A~

the

high

order

and

low

1)

15

~

DS

order

bytes

are

written

'-f5v-

independently

°Word

°Low

°

M V

6

M V
OUT

MOV
MOV

OUT

High

MOV
MOV
OUT

output

DX,

AA,

D?<.,

order

DX,

AL,

DX,

order

DX,
AL,
DX,

,180H

AX

byte

180H

AL

byte

1.8lH

AL

output

output

6.

DMA

(*1)

6-1.

DMA

control

A

different

and

minimum

HOLD

by

maximum

the

RQ/GT
grant
peripheral

With

and
8237A(*2)
converted
the

conversion

f0110win~

it

Simultaneously,

the

compl

the

HOLD,
continued

the

theMZ-5500/5600,

the

maximum mode

at

the

wywtem

etio

bus

w~its

bus
mode.

the

peripheral

mode,

line,

request.

unit

memory

is
into

circuit

mannet.

end

bus,

n,

r e

for

six
are

thereafter

with

suitable

oE

MZ-5500/5600

privilege

In ,the

the

perfpheral

to

which

~\en

sends a release

the

and

for

for

HOLD

and

in

order

is

rather

When

the

bus

it

is

put

during

leases

HOLD.

clocks.

inserted

as

acquiring
minimum

unit,

the
the

DMAC

DRAM

which

refreshing.

the

HLDA

to

receiving

access

into

In

If

the

for

if

nothing

method

mode,

and

gran

ted
unit
8086
bus

of
interface
complicated,

six

first
sends

has

been

pulse

is

minimum mode

the

cyc1e

the

time

this

epu

c10cks

on

used

8237A

HOLD

or

non-ready

the

8237A
manner,
goes

happenp-d.

is

the

with

sends

the

released

the

for

data

The

of

since

with

the

from

in

executes

into thp-

at , the

used ' for

use

of

the

HLDA

GT

same

hold

the

conversion

the
the

condition

the

by the

the

bus

pulse

from

line.

transfer

request

the

8086.

the

8086

8087

82J7A,

idle

8237A

bus

maximum, and

the

8086

bus

is

8086.

request

on

the
the

must

Coprocessor.

the

cycle,

and

OMA

deprives
cycle

pulse

same

us~,

between

sequence

But

it

be

is

done

8086

and

separated

transfer,

after
accessing

maximum ' mode

requested

In the

RQ

to

line

to

the

the

disk

of

tlle

has

to

be

operate~

As

this

in

the

recogniz
returns

f rom

and,

the CPU

rp-c

of

e i.ving

is

with

in

es
lILDA.

uron

As
2

for
slot),
disk
separately
Although
single

6-2.

Operational

The 8237A

ehannel
provided
channel
reads

(*1):

It

written,

(*2):

It

(*3):

It

four

channel$

the

RAM

it

is

and

the

there

transfer

Programmable

1

is

to

2 i 's

DRAM

by

.

DMA

is a short

and

8237A

is

the

DMA

FDC

i5 a short

are

provided

refresh,
expected
channel

in

regard

are

theory

for

meet

for

means

iIJToo

mode

the
the

refresh

---.fl

to

3

to

several

must

standard
specification

of

=r~

-ro:nT

words

refreshed

controller

words

Don't

for

for

(ur,

and

channels,

use

for

other

the

channel

modes

be

DMA

Controller

of

the

arequest

U

Direet

without

whieh

Floppy

for

the

the

channel
device.

for

used

in

MFD

interface

from

system

at

!8,MS

Memory

intervention

has

four

Disk

8237A;

0

and

3,

0

for

Discussion

3.
the

DMA

order

has

every

DREQ

RAM

.aan~

to

four

in

which

13

nL--___

'\

~~t

~

Aceess

of

independent

Controller.

channel

for

exclusive

transfer

assure

independent

which

to

lORD

mtcroseconds.

the

is

refreshed

1

for

1/0

will

with

proper

the
of

~

which

the

the

memory

CPU.

channels.

the

slot

use

be

the

refreshing.

DMA

DREQ

the

FDC(*3).

MFD,

(expansion

of

the

provided

8237A,

channels.

delay

as

the

is

read,

channel

hard

the

circui.t

The

CTC

The

i s

43

To

HOLl)

c..onversion

(..iru,.l,t

HRQ

HLDA

AO-7

DMAE

A8-15

A16-19

DO-15

16-8

Cvmmand

HRQ
HL[}\

AO

I

A7
ADSTB

DBO

DB7

IOR
JOW

MEMR

MEMW

DREQO
DACRO

DREQS
DACK3

DREQI

DACKI

DACK2

DACK2
READY

C K

DREQO
DACKO
DREQ3

DREQ3

f.f

DACK2

(DRAM

Ta

1/0

)

DREQ

DACK

CTC-I

refre5h cir(.ld)

siot

CLK

R IlY

---"'--1/

_______

--.J

Fig.6-1

D~~

circuit .block

>---+--40

Q

diagram

°DMA

ClK86

( 8!o/H, )

C1

.K37

I ~ WH

~)

HRQ

HlUA

UACK I

READY

([~)

(

1-Hl;

E.

TIlr

channel

1

(SW

is

not

used

for

the

channel

T4

..

rTI

2)

T1I

TW

TW

(TI)

:rnnr

TC~

:J

~

ADR

5!. )

_

I,WA

CPU

v..ddress

l14J(e~!ö

(11

(~EVI,l)-==========-,i~----~============~===================x~

DATA

eWO

-

________

ROY

(8284)

QSince

signal

°The

Upon

.

signal
sjgnal,
released.
enable
The '8237.

some

CPU

"

rece1v1ng

name

clock

(HRQ)

it

·At

signal

DMAC

of

makes

address .signals,
ADSTB
1/0
space

The

ready

However,

at

the

(50H)

DMAC

are

of

the
goes

si~nal

it

I

-1

signal

given

parenthesized

CLK86

of

DREQ

~o

the

the

the

same

(DMAE)

controls

AO

beginning

used

8086

as

CPU.

ready

returned

is 0 wait

r - - - - - - - - - - - - --

names

and

CPU.

CPU

are

DMA

- A7,

A16 -A19

with

with 0 wait

at

the

differs

DMA

between

1s

for

clock

Fig.6-2

from a channel,

As

the

HOLD

in

the

non-ready

time,

of

the

returned

transfer
and

A8

the

DMA

the

DMA

hold

to

of

- AlS
transfer.

in

order

transferred

is

all

time

during

UWA

-,.ri/'--------------,

the

the

MZ-SSOO.

CLK37

DMA

timing

the

are

DMAC

conversion

state

acknowledge

the

DMAC

any

16-bit

which

to

'

cover

automatically

refreshing.

UItAO

CPmII\uoJ

MZ-SSOO

completely

issues

circuit

and

the

signal

to

perform
area

latcl~

Also,

memory

DBO -OB7

lD4 - 7

up

the

ready

attached

and

the

receives

system

(HLDA)

the

(64KB)

1MB

signal,

MZ-S600,

async

hold

the

clocks.

request

this

bus

is

and

the

DMA

transfer.

represented

with

latch

signals

memory

address

but

with 1 wait.

DMA

by

of

the

\1

j

~

6-3.

Use

of

DMA

For

the

MZ-5500/5600

the

channel

open

[or

the
iIlterfac
interface.

The
below) . Attention
direct

eh
Ch
Ch
Ch

e

channel

data

0

1

2

A

3

B

C

D

E

F

G

H

channel

s 1

and 2 are

r/o

slot.

and

the

channel

3,

hOHever,

must

transfer

Hard

disk

MFD

interface

Main memory

Reserved

Reserved

SFD

interface,
Reserved
Reserved
Reserved
Reserved
User

3
series,

already

However,

3

permits
be

with

interface

the

refresh

MFD

four

is

reserved

multiple-DMA

paid

to

main

interface

DMA
used
the

the

memory

h

channels
by

the

channel

for

following

by means

------

~

are

machine,

0

is

the

standard

up

to

~

AEH

r/o
r/o

AEH

r/o

AEl1 to.

r/o

AEH
AEH
AEH
AEH
AEH

to

1/0

1/0

r/o

1/0

provided

channels

used

conditions

to
to

to

to
to
to

eight

of

DHA.

OlH
02H
04H
08H

lOH
20H
40H
80H

for

standard.

the

floppy

levels

when

0

and 3 are

hard

disk

disk

(Table

performing

\.

Since

\,

.

1)

Hardware

(1)

(2)

Only

(3)

DREQ3

(4)

'

(5)

(6)

(7)

(8)

Channel

byte

(channel

it

is

wired-OR.

Provide
input

DREQ3

DREQ3

System

Some
instance).

through

and

must

means

3H

an

data

is

used

transfer

output

the

DACK3

be

maintained

bus,

must

3

DH.J\

port
bit 7 of

are

D8

be

[or

the

mode

provided

is

request)

to

gated

active

- D1S,

D~~

channel.

applicable

must

the

bit

the

r/o

by

the

until

must

to

be

know a

be

7

of

address

above

pulled

for

the

outputted

the

1/0
OAFH.

output

DACK3

DMA

is

up

termination

DMA

transfer.

by

the

open

address

port.

returned.

with a proper

OAEH

(interrupt,

collector

to

permit

resistance.

for

as

I'

\1

ii)

Software

(1)

Since

,

must

(2)

Assign

2 wi

(3)

Bef~re

(4)

64KB

(5)

Assign

the

be

deve10ped

on1y

th

the

the

is

the

the

user

the

master

DMA,

maximum

single

DMA

is

not

by

the

assembler.

channe1 3 for

clear

send

transfer

BOR

that

command,

to

can

at

the

mode

all

the

1/0

be

subjected

for

supported

DMAC.

for

examp

address

the

tl

by

Never

le

to

DMA

the

OS,

reset

.

AEH

to

DMA

at

operation.

and

open

one

the

user

mask

the

time.

the

user

program

chaI'nel

DMA.

.\

4

~

7

Circuit
The

analog

converter,
to

47FFFH

DO

~

D7

example

waveform

and

at

every

-t-5V

is

data

of

100

v-~--------------~ADB

8

converted

32KB

are

transferred

microseconds.

ftß8

tth1

.-------------~AD7

into

the

digital

to

A/D

signal

the

via

main

convert.er

memory

IAl

the

area,

1--_--'

,

A/D

~OOOOH

6&1<

Do

I

DIS

rORl

4McLK

D7

Di~

Arowc

Aq

A~

A7

AG

A5

A4

1~3

A2

(\1

AOO

1'\&

1

'1

8

--------~----~

~DO

Counter

r-------~----~D

Qt------I

'-

a:r:-c<}--

+5V

~R5TSW

D

g

CLR

(}----

}---IR-2G

DREo.

3

DAck,3

RESbl

EOP

Fig.1

Circuit

example

\.

°Software

(in

reference

to

the

circuit

example

in

the

preceding

page)

~\

put

\j

CSEG

ORG

MOV

,

OUT

MOV

OUT

MOV

OUT

OUT

MOV

OUT
OUT

MOV

OUT
MOV
OUT

100B
AL,

0

OAEll,

AL,

07H

OAH,

AL,

50H,

OCH,

AL,

0

06H,
06H,

AL,
07H,
AL,
07B,

AL

AL

40H

AL

AL

AL
AL

OFFH

AL

7FH

AL

;Only

;4

bits

high

are

order

valid

~i

Se t

offset

I

Set

DMA

DMA

add

word

ress

Set

DHA

address

40000H

set

DMA

size

to

start

to

transfel

32KB

Li:

MOV
OUT

MOV
OUT

MOV
OUT

IN

AND

JZ.

i

MOV
OUT

XOR
XOR

INT

END

AL,

47H

OBH,

AL,

03H

OAH,

AL,

80H

OAEB,

AL,

40H

AL,

40B

Li

AL,

0

OAEB,

CX,

CX

DX,

DX

224

.

AL

AL

AL

0

Clear

eH] mask

Enable

J

CH3

DMAC

*1:

IR-26

is

used

simply

as

an

input

port.

4q

7.

Mini-floppy

7-1.

General

Every
mini-floppy
mini-floppy
connector

two
MZ-5521
drive
external
Fig.7-1

0(

HRQ

HLDA

Dltü

--

~---

more

_• . -

~

. bus

description

MZ-5500

on

drives

that

unit

permits

drive

shows

·

DMAC

DA~1

D130

(

DßI1

-

--

disk

series
disk
drive

the

has

unit.

the

-

interface

personal

interface

unjts.

back

for

the· MZ-55ll

two

internal

expansion

block

t:"D

( A Y-J .

(MZ-5500)

which

As

of

the

diagram

(

(f-~DVbl))

{)ALf,

WMU\

psc

DRO

r~

1

R,D

Oß

0 W;

ttdew

1

t1~H

Pß7

WeLt'

SltK

i

P60

1

PB

I-=.J,...::---------..:.-

lO~'

1 LOt\l

100

}

psCr

~q

12

)

computer

can

there

machine,

that

drive

witl,

the

of

YFO

\V(

Lt:.

SYNC

j1

is

equipped

control

up

to

is a mini-floppy

it

permits

has

one

internal

units.

interna!

the

mini-floppy

The MZ-5501

disk

wrc

~()I€-

__

_

_

~&

\'MOUT

IN

-

witll

·a

320KB

a maximum

disk

external

drive

disk

expansion

installation

drive

that

unit

circuit.

.

--

--

-

------~>

(formatted)

of

unit

has

or

WiUIE

INOh~f

-ro.I\c.\(O

'$lPE

"}

WDATA

REAP

M010R

<7f:L

four

and

no

four

I

sn:~

DATA

0"" .)

interface

of

the

internal

PI<OfEcr

W&I'T'E

,

REA()~

'

Dl.~H,TIO/J

f

oN

',

.

The

recorcling

disk

begins
sides

the

is

radius

from 0 and

and
from 1 to
point
tbe

1 t

sec

terms

on

track

penni

t or

of

and

fjg.7-2
1n

the

ID

(track,

the

information

to

read/write

created

(initial

Fig.7-1

divided

(Fig.7-2).

sec

16

on

the

disk

number

ts

to
read/write

sector.

also

shows

field

side,

during
i

zation).

Mini-floppy

surface

into

ends

tor

number

both

is

and

record

is

sec

tor)

in

data.

formatting

of

fo rty

Track
at

are
sides.
represented

the

sector

256 by

is

possible

the

soft

recorded

of

the

this

ID

Tlle

ID

disk

the

mini-floppy

tracks

number

39

on

assig~ed

A

tes

sector.

the

sector.

field

field

interface

along

both

specific

with

number.

in

one

in

address

is

used

is

block

Fig.7-2

sec

tor

diagram

Disk

example

and

software

The

MFD

are

directly
Fig.7-1.
command

software,

The

8237
memory

that

the

(1)

The

VFO/data

(2)

As

CPU.

(3)

As

To

(L,)

Data

control

drive

As

(write,

the

DMAC

to

perform

FDC

DMA

the

the

which

are

unit
controlled
the

read,
FDC
is

reads

request

separator

DMAC

receives

CPU

receives
the
transferred

by

the

has

three

by

side

of

disk

seek)

automatically

used

DMAC

fast

from

signal

DMAC.

to

transfer

DMA

or

(*1).

DRQ,

HRQ,

returns

between

major

the

ßPD765

(front

to

the

contro~

transfer.

writes

(DRQ)

HRQ

the

DACK

actions

Floppy

or

FDC

read/wtite

The

to the

is

issued

(request)

bus

line

to

the

the

memory and

reverse

are

the

following

disko

is

FDC.

of

write,

Disk

side),

specified

MFD

drive

data

from

the

is

sent

opened,

FDD

read,

Controller

track,

from

unit.

between

are

required

FDC

to

from

and

via

FDC

and

seek

(FDC) shown

sector,

the

CPU

the

FDC

in

the

DMAC

the

DMAC

HLDA

is

returned.

under the blls

by

and

to

whjch

in

and

the

the

order

anJ

the

The ~receive

of

window

disk
timer

MFD

incorporated

*1):
Read
pulse,

window,

circuit
delivered
being

«D

DA,TA

Window

the

drive

circtiit.

drive

VFO

data

sent

f)

~

SED
clock

select

output

and

in

that

by

circuit

9420

(*2)

which

in

*2):

they

order

is

the

out

as a da

OlilOG

from

VFO/Data

by

which

is

then

This

Window

must

i>

controls

signal

the

AY-3-8912

from

be

to

obtain

designed

VFO

is

~

the

Separator

the

divided

1s

sent

the

MFD

separated

the

for

rearrollged

ta

signal.

c V

~

MFD

drive

le.

read

data

into

the

MFD

out

Programmable

are

composed
from

data

of a low

that

purpose.

to

f)

_.I-u-LI~~rLJLrL

to

As
signal

the

motor

through

each

tlle

the

FUe

it

internally

is

clock

Sound

of

mid-point

stop
the

the

other

error

Read"

pulse

1/0

is

simplified

fetched

and

signal.

~ort

Generator

data
by

data

the

rate.

of

pulse

input
the

by

incorporates

from

data

which

reliable

lt

window,

pulse

is

(PSG).

and

is
from

the

the

the

the

data

the

hefore

use
the

floppy

and

clock

VFO

MFD

the

,I

51

"

Table

7-1

FDD

specification

Recording
Sec
Tracks
Recording
Track
Recording
Data
Recording
Transfer
Access

Average
Track

Settling

Head

7-2.

HZ-5600

Sincc

driv

tll e MZ-5500
The
addi

of

the

MZ-IFIJ

expansion

WllPn

(lllci

possible

mod

e l

"0"

t C)

th

In

the

djsk

into
the

Track
provided
disk,
from 1 to
side.
number
represent
Iocation.

stored

js

permitted
Fig.7-J
Sec

tor
side,

10

field
reading
ffeld
disk

tors

density

transfer

method

t~me:

to

load

mechanism

MFD

tlle

MZ-5600 '

e ,

the

MFD

interface

tion,

the

machine

mini-floppy

with

using

write

to

as

of

personal

1ll1lSt

e

CP/l"1-86

be

ease

recording

80

tracks

disk

as

numbers

for

respectively.

16

Track

are

used

the

256

in

one

indicates

address

sector)

which

or

writing

is

created

formatting

capacity

surface

(TrI)

density

rate

method

track

(640KB)

MFO

interface

series

HZ-5600

which

the

the

640KB

the

disko

it

is

specifi

and

of

the
surface
along

shown

from 0 to

both

sides

areassigned
number

altogether

specific

bytes

sector,

in

terms

the

information

is

contained

is

searched

at

(initialization).

(formatted)

(HPl)

interface

series

are
for

in

detail.

can

control

has

the

permits

disk

drive

MZ-1F15

mini-floppy

(200)

However,

designed

computers

ed

[or

the

MS-DOS

manuals.

640Kß mode,

is

divided

the

radius

in

Fig.7-3

79

are

of

the

Sec

tor

on

and

the

to

disk

of

data

and

read/write

of

sector.

soft

sector.

(track,

in

for

data.

the

The

time

general

equipped
the

up

expansion

expansion

options.

disk

to

on

read

such

FD

the

of

.

numbers

each

sec

tor

can

be

the

when

ID

of

320KB
16

sectors/track

40

tracks/side

Two

sides
48
5876

(max)

250KB/s
MFM
HFM

93ms
6ms

15ms

None

(head

description

with

MZ-5600

to

four

MFD

of

a

series

units

interface

two

The MZ-5631

disk

drive.

the

MZ-5600,

when

using

the

disk

as

the

MZ-5500.

l~gical

number.

'

Fig.7-3
example

load

large

of

more

the

which

(04OI<B)

time=O)

(MZ-5600)

capacity

is

different

the

HFD ,drives
connector

units

permits

it

is

possible

320~B

has
To
For

disk,
been

read

more

Gap

Disk

and

!

mini-floppy

from

that

and,

on

the"back

of

the

external

internal

to

read

only

reading

created

the

320Kß

details,

256

B

DAT{\

+i~lct

software

disk

for

in

from

by

other

disk,

refer

Cld~

lI

'

'

lT~(J

\t

is

'

0

1

Fig.7-4

The

are
side
read,

shows

MFD

drive

dir~ct~y

of

disk

seek)

automatically

The 8237

f

memory

DMAC

to

the

unit

controlled

(frortt

to

the

~ontrol

is

used

perform

8287

block

has

or

FDC

fast

DUAC

diagram

three

by
reverse
are

the
to

transfer

DMA

of

the

major

the~PD765

actions

side),

specified

MFD

drive

read/write

transfer.

765 FDC

Floppy
track,

from

unit.

MFD

interface.

of

write,

Disk

sector,

the

CPU

data

rend,

Controller

and

command

by

the

software,

between

and

the

seek

(FDC).

(write,

FDC

the

and

which

As

FDC

the

the

'.

The

th

(1)

, I

(2)

(3)

(4)

e

HLDA

HRQ

I

DO-7 '~________

following

disko

The

DMA

request

VFO/data

As

the

separator

DMAC

CPU.

As

the

CPU

To

which

Datfl

control

are

by

the

transferred

DACK

DREQI

AO

l

A7

Fig.7~4

are

requfred

signal

receives

receives

DMACreturns

the

DMAC.

11

--J

~

prcm

5

MFD

interface

in

order

(DRQ)

(*1).

DRQ,

HRQ

HRQ,

the

DACK

between the me

DACK

WR

DATA

DRQ

WCLK~Wrjt~

RD

DATA~

pSG

-

L3------')......J1

block

that

is

issued

(request)

bus · line

to

the

mo

the

from

is
FDC.

r y a

diagram

FDC

is

opened,

nd

PrCc.o\Ylp

(.i((u,L

decK

e

iflUI

YFO

c.ir':uit

Dri"~

s~\e(.t

C~rL.t.Ait

--------'

r e

ads from

the

FDC

sent

from

and

FDD

via

t

to

FDC

Control

WR

RD

SELO
SELI

SEL2

SELS

or

the

the

DMAC

HLDA

und e r the

DATA

DATA

writ

DMAC

is

returned.

t;:'j()(li

es

and

to

to

the

bit

S

The

receive

of

the

HA16632AP VFO/Data

window

drive

timer

MFD

is

clock

which

circuit.

drive

sent

Programmable

circuit

is

·

s~lect

out

through

by

which

then

Sound

from

the

divided

signals,

the

Generator

the

MFD
Separator.
read

into

SE~O

1/0

port

drive

data

the

-

2,

which

(PSG).

to

As

sjgnal

clock

are

is

the

FDC ;is

it

internally

is

fetched

pulse

sent

out

incorporated

and

from

simplified

incorporates

from

data

the

in

the

pulse

FDC
the

by

the use

th

e

floppy

and

and

disk

the

only

AY-3-8912

SET.3

li

s3

f

Table

7-2

640KB

FDD

specification

8.

Recording
Sectors
Tracks
Recording
Track

density

Recording

Data

transfer
Recording
Transfer
Access

Average
Track

time:

"

to

Settling

Revolutions

capacity

surface

density

method

methou

track

(RPM)

(TPI)

rate

(BPI)

640KB

16
80
Two

:

~.

96

5922

250KB/s

MFM

MFM

94ms
3ms

15ms
300

sectors/track

tracks/side

sides

'\

\ '

!;4-

8.

llard
Any
a

MZ-5645).

installed

disk

of

the MZ-S500/S600

formatted

interface

capacity

Especially

via

the

general

of

in

internal . hard

description

series

10.7
the

B
HZ-564S; a mClximum

can

(one

disk

be

interfaced

unit

interface.

is

equipped

with

of

the

standard

two

hard

hard

disks

disk

for

the

can

that

bC'

hns

't

HZ-5631/5641

MZ-564S

10.7HB

HZ-~~ll

*MZ-IF18

The

HZ-S500/560b
Fig.8-1
of

the

I

to

number,

Fig.8-1

address

the

specified

For

better

made

successful

(ECC)

to a burst

In

addition

is

provided
permit
a

whole
unrecoverable
as a physical

So,

tracks
tracks
the

track
the

test

field,
by

the

(with

hard

/2521

is

and

disko

17,

are
sector
also

information

possible.

is

automatically

to

replace

sec

of

track

number

of

however,

user.

an

internal

disk

drive)

_ _~_____

equipped

hard

each

reliability,

with

data

on

tor,

actually

the

surface

Track

assigned,

number,

shows

sector.

If
retrial,

of

to

it,

Track 0 or

data

in
damage
disk

number 2 to

319

hard

cannot

__

with

disk

consists

numbers,

to

and

the

soft

(track,

retrial

recovery

correction

carried

up

to

eleven

alternate

or

case

damage.

in

usable

being
disko

be

there
the

MZ-IFIO*
MZ-IFI8*

~J1Z-1FIO*

the

drive

has

0

represents

head

sector.

head,

was

track

Track 1 to

program

i9

disk

are

318,

used

The ID

created

four

of

to

319,

number

sector)

i6
not

out

bits.

by
an
such

317

with

for.

unit

disk

320

the

In

(with
(without

(with

only.

recording
tracks

are

assigned

specific

(0

to

the

10

which

DiSK

It"lQ.)(

the

hard

the

hard

the

hard

surfaces

developed

location

3).
field

is

normally

P\.(\$~

disk

disk

and

is

interface)

disk

sector

contained

interface)

interface)

as

along the

with

used

shown

numbers,

rfldius

the

track

the secto

to

acc e ss

J ""-'-

:'

-

Tr(ll

in

'ru(

7(1)

~

~

0

\

r

~CII

~

Fig.8-1

example

11

Disk

(physical)

and

so[twClre

sec

tor

S5

(M815546)

00" -

Gr.J<RAr

GENlRA10R

PHE-CCM>

1tN,.

MHA·

.

.-

tIX:-LSI

D

(MBIS550)

MZ-

F

I/

.~~~~

"Tl

l.rr

~

Fig.8-2
MFD,
write,
mode

shows

action

read,

under
interface
in

the

DMA
automatically
starts
error

the

to

has

video

of

and

the

chip

mode,

test
been
unit

the

block

the

hard

seek.

control

internal

then

hy

the

firmware

(ready,
encountered
by

the

diagram
disk
Data

of

drive

transfer

the

register,

the

command

read/write,

during

OS.

of

8237

of

the
is

DMAC.

the

1s

the

seek)

the

hard

divided

with

the

After

data

are
executed
interface.

the

test,

disk

into

host

data

transferred

to

hard

the

condition

interface.

three

is

conducted

are

the

hard
This
disk

firmware

upon

major

set

to

disk

power

is

Similar

actions

in

the

in

the

host

the

M58725

drive

automaticnlly

on.

displnyed

to

of

If

on

the

l)~lA

RAH

any

Table

8-2

640KB

FDD

(physical)

Recording

capacity
Disks
Heads

~ecording

surfaces
Cylinders
Tra.cks
Sec

tors
Track
Recording
Recording
Transfer
Data
Access

density

density

method

method

transfer

time

Average

(TPI)

(BPI)

speed

(including

.. 10.7MB

. '

: 5MB/s

settling

2

4
4

317
317 x 4

17
360
9260,
MFM

MFM

85ms

Minimum 18ms

Maximum 15ms

specification

tracks

sectors/track

maximum

time):

(CP/H-86

t 10.7MB)

(673

x 2

(16

sectors/track)

spec)

tracks)

!/

S'l

9.

Printer
*Common

9-1.

Circuit

Tl\e 8255A
under

tlle
applies

(CPU

interface
for

the

8255A

side)

the

description

is

used
following
is

operated

the

interrupt

MZ-5500

for

mode

and

the

setup.

under

to

the

82ssA

MZ-5600.

parallel

the

CPU.

interface

For

mode-l

the

and

controller

Centronics

the

ACK

wh1ch

interface,

signal

is

from

(Printer

operated

Group A of

the

printer

side)

ID~

~

Hn

1 R-

fRT

~--4--

825SA mode

hiODEl

outr~t

I-

hiODEO

outpvt

f-----.

hiODEO

li1~ut

'---

PAO

I

PA1
PC1
PC6
PCS
PC.
PCS
PC2

pet

PCO
PBO

I

PB1

-

1

ALK

OUT

om

INT

üm

IN

e5

RD

~

RESfT

Atj

AI

FC3

pes-

PAS

~

pA?

PC6

PBS

PB,

PB2

°IOCS

~

~-----~

control

procedure

11 V 11

DATA

BUS),

PE

SElECT

SRES

mark:

STRöBE

,

IV

ACK

lKohms

DATA

pulhip

8

I1

resistor

*Centronics

Printer

interface

interface

method

which

16

popular

worldwide.

Parallel

interface

signal

description

'I

Pin
No.

1
2
3
4
5
6

7

8

9

10

11
12
24
25

*14 - 23:
*18:

Timings

Signal

name

STROßE

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

ACK

BUSY

.

PE

SRES

SELCT

Error

GND

insertion

In/Out
In

In

In
Out
Out
In
Out

protected

Function

The

printer

Data

output

Completion
Data

receive
Paper
Reset
Indicates

(high)

empty
signal

sampies

to

of

enable

(high)

the

the

data

select

data

printer.

or

function

(low)

(receive

at

the

rising

input

enabled)

edge.

conJition

- - - - -

BUSY

,m::

IR-FRT

:f)ATA

~TRöBE

,

I

,

/'Ur-

, 1n

--------n

---

1J

----

~~

9-2.

Handling

As

minor

is

executed

Ho",

BASIC
the

HZ-3500
HZ-5500/5600

NOTE:

The

9-3.

Making a hard

Since

the

printer

control

with

to

send a control

operating

personal

machine

the

printer

language

MZ-5500/5600

with

control
functions
the

control

computer

(BASIC-3)

routine

copy

of

windows

code
are

code

"XX

Transmission

control

PRINT

15

the

video

has

the

overlaid

(function

furni5hed

code

that

(hex)"

code

CllR$ . &XX

required

screen

multiwindow

in

follows

of

the

code)

to

each

Example:
and
pitch
PRINT

for

the

capability,

display

MZ

the

ESC

data

set

CHR$

MZ-2000

screen.

series

c1de

1'0

send

"6"

to

&

it

printer,

(IBll).

the

with

the

1/6"

IB;"6";

series!

can

code

be

control

"IBU"

linefeed

copied

on

°CP/M-86

Push
tiOle
display

th~

°BASIC

the
the

CP/M-86

BASIC-3

and

MS-DOS
[BREAK)
[CAPS]

sereen.

and

ineorporated

GPRINT

incorporated

key

first.

key

is

This

MS-UOS.

hard

blinking.

function

copy

hard

Push

the
This

i5

supported

funetion

copy

[COPY]

will

Hard

function

key

in

the

produce a hard

for

the

applieation

co

[SHIFT] + (BREAK],

then

wait

(COPY]

state

copy

in

of

the

software

which

of

{o

10.

RS232C

Two

channels
MZ-5600
peripheral

(Electronic

(modulator/demodulator)
binary
between
The RS232C

these
printer,
device
not

be

interface

in

order
devices.

dlgital

the

interface

EIA

requirements

plotter,
that
connected

of

RS232C

Industries

da

modem

has

the

interface

to

permit

The RS232C

Association

with

ta

signals,

and

the

data

of

the

to

make

etc.

satisfactorily

However;

interface

are

provided

aserial

the
control

MZ-5500/5600

connection

that

data

is

the
of

communication

signals,

terminal.

attention

conforms

depending

transfer

standards

the

U.S.A.)

has

with

must

on

standard

control

and

been

the

to

the

the

for

with a variety

set

forth

for

interfacing

device,

timing

designed

acoustic

be

paid
RS232C

case.

signals

to

the

MZ-5500 aIld

of

by

EIA

the

and

seriR]

transferred

in

compliance

coupler,

it

that

even

requirements

modem

wi

the

may

th

10-1.

Specification
Input/output
Channels

Code

Baud

Transmission
Transmission
Data

Signal

*BSC

BSC
binary
protocol

control
between

following

transmission,

used

rate

format

level

is a short

data

for

characters

two

signals

method

rnethod

control

words

synchronous

which

stations

they

procedure

aseries
are

are

are

for

Binary

data

used

of

the

provided

not

RS232C

2

channels
Channel A (BSC
Chanriel

JIS

7-channel

J1S

8-channel
110,
9600

Half-duplex
Non-procedure

l

stop
Parity
High:
Low:

Synchronous

cornmunication.

of

standard

for

the

synchronous

data

communication

in

the

supported

bit

B

150,

200,

BPS

bit
option

+5

to

-5

to

control

hardware

by

CP/M-86,

serial

(Channel A and

input/output

conforming)*

code

system

code

of. even,

300,

system

600,

+ISV

-ISV

Communication

It

is

the· charncter
characters
binary

system.

f~)[

the

MS-DOS,

1200,

odd,

which

data

Though

synchronous

and

2400,

B)

and

<lud

transmissi0n

the

RASle.

4800,

non

parity

means thp.

type

*Since

that

I,

the

LSl

Z-80

is

S10

attached

is

used

at

the

for

end

the

of

serial

this

interface,

text.

the

specific<ltion

of

b1

10-2.

(1)

Input/output

Data

input/output

signals

signals

and

control

signals

( 3

)

(2)

Pin

No.

2

3

Contro}

Pin
No.

4

5

Signal
name
Transmit
Receive

signal~

signal

Signal
name
Si.gnal
Send

ground

request

Trallsmit

signal

enable

Signal
symbol
SD(TxD)

RD(RxD)

t

Those

Signal
symbol
SG
RS

(RTS)

CS(CTS)

In/Out

Out

In

in

parentheses

In/Out

Out..

In

Funetion
Output
Input

data

data

are

Funetion

ON

during

OFF

when

completed.

The

signal

output
Data
when
Data

is

transmission

ON.

trnnsmission

when OFF.

NOTE:

turned

Even

OFF
of 2 bytes
sended

until

eompleted

from

'

deviee

the

ElA

symbols.

data

transmission.

trapsmission

with

which

permitted.

is

is

when

of

from

data

the

ON,

transmission

.

is

data

enabled

disabled

signal
a maximum

may

be

1S

is

1 2

6

7

8

9

Receive

Signal
Data

set

Signal

Terminal

enable

ground

ready

ground

ready

READY

(DTR)

SG

DR(DCD)

SG

ER

Out

In

Out

The

signal

whether

ON:

Enabled.

OFF:

The

Disabled.

signal

whether

for

the

ON:

Operation
OFF:
When

Operation

this

during

it

results

The si.

that

the
machine.
ON:

Power

whieh

data

the

operation.

signal

the

gnal

which

powßr

on

input

whieh

devi.ce

enabled

not · enabled.

data
in

input/output,

nn

is

state

indicates

is

enabled.

indieates

is

ready

.

goes

OFF

error.

indicates

on

to

'

the

(3)

Other

contro1

signals

(channe1 A on1y)

Pin
No.

10

11

l4

IS

NOTE:
Not

supported

Signal
name
Carrier

Ca1l

Receive

detect

indicator

signal

element/timing

Transmit

signal

element/timing

by

the

Signal
symbo1
CD

CI

RT

ST2

standard

In/Out
In

In

In

In

software

Function

The

that

by

the

The

reception
from
Input
signal

transmission
Output
signal

transmission

(BASIC,

signal

the

carrier

device.

signal

the

line.

signal

in

signal
in

CP/M-86,

which

indicates
is

which

of

the

indicates

ca

element/timing

the

synchronous

mod

e .

element/timing

the

synchronous

mode.

MS-DOS).

received

II

signal

I,

G3

10-3.

Process

Transmission

outline

Device

in

error

BASIC

Cp/tl

(

mode

MS-DOS

~

RS - ON

mode )

mode

-----,

--

---""'\

1*1

1*

2-

I
I

I

I

,

*1:

~len

*2:

Wh~l\

masked
masked

In

in

RSloff

RET

RE

the

the

1·

-te>

10

DR

es

monitoring
monitoring

cp/t1

115-D0.5

ep/M

M~-POj

mode.
mode.

Transmit
byte

mode

of

one

data

RSlOff

RET

See
See

10

the

the

BASTC

CP/H

CP/M

no

or
or

MS-DOS

MS-DOS

Manual.

Manual.

Receiving

BASIC mode J

CP/H

[

MS-DOS

mode

mode

ho

yes

lAll

the

data.

CP/n

.t15-Das~

shal1
receive

mt1:4·

yes

be

~~il/e.

~

ro\)\

rec.ei"e

O~

th~

1,,1ernn

bv~r

do.tc\

\

CP/H

"S~D

OS

tn'*-

BASIC

NOTES:

1.

Data
But,

2.

Although

the

RET

RET

CP/H mode,

will

the

TO'

+0

be

data
READY

C

F/M

/15 -

DOS

received

input

goes
depression

in

when
OFF

RET .

the
READY

upon

of

1-0

BASIC

divided

is

OFF

occurrence

the

[CIRL-Cl key

mode.

will

of

65

be

inval:f.d.

(1

receive

clears

Error

error

the

Rn

in

error.

1-0

BASIC

10-4.

Wiring

example

(1) MZ-

5500/5600

Signal

SD

RD

es

READY
DR
ER
SC

Others

(2)

MZ-5500/5600

Signal

SO

RD

es

READY
DR
ER

SC

Others

(A)

(A)

to/from

A

name

are

name

are

Pin

5

6

8 8

12

1,

open.

to/from

A B

Pin

2

3

5 5

6 4

8

12 6

1,

open.

MZ-5500/5600

(B)

No.

2 2

3

DC

Pio

DC

=><=

7,

No.

7,

9

MZ-3500

(B)

9

,L

1,

Pin

9,

Dip

3

· 5

6

12

7,

. 1

3

7

8

10

5

6

7

No.

9

No.

switch

B

Signal

SD
RD

es

READY
DR
ER
SG

Signal

SD

RD

es

READY
DR
ER
PO

SG

ON
ON

OFF

name

name

(3)

MZ-5500/S600

(A)

to/from

MZ-IX11

(B)

(acoustic

coupler)

B

Signal

V24

compliance)

name

SD

RD

RS
CS

OR

ER
CD
CI
RT
ST2
SG

I,

Signal

SO

RD

CS

OR

ER
CD
CI
RT
ST2
SG

Others

*:

Use

(4)

MS-5500/5600

(A)

name

are

the

A

Pin

2

3 3

5 5

8

12
10
11
14
15
1,

open.

MZ-IC36

to/from

No.

7

cable.

the

r---

modem

(B)

Pin

4

6

20

8

22
14
15

1,

(CClTT

No.

2

7

Signal

SO

RD

RS
CS

READY
OR
CD
CI

ER
STI

RT
ST2

SG

*Use

the

A

name

,

--

MZ-lC40

Pin

No.

2 2
3
4
5
6

8

10
11
12

'----

13
14

15

7

_lL_

_

cable.

Pin

1,

22
20
24
17

15

3
4

5

6

8

7

No.

B

Signal

SD
RD
RS
CS

OR
CD
CI
ER
STl
RT
ST2

FG,

name

SG

I

I

{;,r7

10-5.

(l)

RS232C

In

°The

Set
sides.

Fl:
F2: 8
F3:
F4:
F5:
F6:
F7:
F8:
F9:
FIO:

the

file

the

sampIe

case

name "ABC.LST"

following

1200

None

2
No
No
No
No

program

of

the

Baud
Ward
Parity
Stop
Send/receive
Send
Echo
Xon/Xoff
Exit
Set

RS232C

example-l

using

rate

length

bits

CS

monitoring

back

is

transferred

the

RSPARM

DR

monitoring

parameter

utility

and

on

exit

CP/M-86.

for

both

transmit

and

receive

Also,

Fl:

F3:
F4:

F9:
FI0:

Now,

eTransmit
eReceive

NOTE:

With

the

command

set

Console

F2:

Console
Auxiliary
Auxiliary

F5 : List

Exit
Assign

transfer

this

list

the

side:

side:

PIP

file

file,

following

IN

OUT

Out

and

the

command,
can

the

IN

OUT

exit

file

A>

A>

be

transfer

using

Input
Key
ON

---

---

---

PIP
PIP

transferred.

device

Port

---

ON

---

---

using

AXO:=A:ABC.
A:

ABC.

only

program

the

A

the

LST=AXI:

the

file

ASSIGN

Port

---

---

---

PIP

command.

LST

composed
To
must

utility.

Output

Screen

B

---

---

J

~

transfer

be

created

ON

of

the

device

Port

---

---

ON

the

ASCII
binary
by

A

the

Port

B

---

---

code . such
file
user.

such

Printer

---

---

ON

as

as

the

°Data

are

eTransmit

10
20
30

40

eReceive

10
20
30
40
50

transferred

side
CHANNEL
X$="ABCDE"
SEND
END

side
CHANNEL
RCV
X$=LEFT$(X$,
DISP
END

0,

X$;"@";

0,
0,

X$,

X$

on BASIC-3.

9600,

9600,

"@"

LEN

"8N2"

"8N2"

X$-l)

(2)

In

Althotigh

the
the

the

case

it
example-l,
RS232C

parameter

of

is

identical
reference

the

example72

to

the

must

setup.

CO/M-86

be

made

to

and

the

BASIC

MZ-3500

programming

manual

example

as

it

for

differs

in

09

11. KEYBOARD AND KEYBOARD INTERFACE

11-1 Keyboard specifications

..

Intelligent

..

63

byte

..

Twokeyroll -over

keyboard

input

containing

buffer.

.

the

BOC49

processor.

~

..

Mode

it

Two

commands

indicators

types

of

.

for

repeat

CAPS

',

functions

and

GRAPH.
can

be

IWN

SI"OP

specified

cl"

.

by

CPU

Special Keys
SHIFT

: Used

case

keys

CAPS

:

LOCK

GRAPH : Selects
CTRL

ALT

Keyboard

1)

2)

Notes : ..

Description

(Al

..

other

..

transferred

(B)

..

Used for

..

Operative

..

If

will

..

If

(no

Used
with
will be

: Used

Used

:

mode

NORMAL

GRAPH

ro
mode

..

If
keyboard
and
that
with

code,
code.

SHIFT

Used

10

keys)

Operation

CAPS

key

used

with

be

reversed

the

CAPS

code

mode:

mode

clear

the

of

key

place

.

of

shift

only

is

transferred

for

uppercase

shift

functions

(F1-Fl0).

10

fix

the

Shift

reversed

Graphie

to

generate

to

generate

:

Selected
the

the

select

CTRL

SH I

FT

every

the

and

special

the

the

SH I

to

the

character

in

the

the

SHIFT

.

key

alone

F1

shift

character

key,

.

mode.

compressed
extended

All

keys

(to

generate

keyboard

byte data

selected

key

or

and

is

placed

keys

operative),

piece

of

first

byte

the

second

keys

keyboard

FT

key

CPU).

selection.

normal

key,

is

to

the

shift

(F

the

on

with

).

keys

ALT

in

data

assigned

in

mode

shift

used,

CPU).

F:!

Fig.

or

ll-F20)

selection.

shift

commands.

the

keyboard

one

byte

the

in

the

mode,

a seco(ld

keys

the

normal

consists

byte

assigned

the

shift

alone

.

and

0.0

1'3

F4

F5 F61..-7 I

11-1

(In

the

to

provide

and

commands.

GRAPH

graphie

operate' the

are

with

to a CTR L ALG

is

invalid (no

normal

operation

for

the

If

normal

are

data).

key

time.

depressed,

mode

the

of

two

to

mode

will

the

function

it

operative

to

mode

exception

the

(used

selection

ca

se

upper

is

used

mode

place

(1

same

the

(CAPS

bytes,

entry

with

code

result

of

is

"-I!

I1'9

1-'10

I

English

type)

(C)

GRAPH

..

Used

to

place

opera

ted,

(operation

..

AU

other

the

normal

(0)

CTRL

key

..

When

this

bytes:

code.

After
keys

..

Operation

assigned).
(E)
.. . After

two

..

Used
..

Effective
..

The

operated_

anormal-mode

Operation

the

remain

ALT

key

the

bytes

to

pertinent

genera

11-2 Keyboard interface

(1) Block

lO~

diagram

11266

JR2

key

the

the

pertinent

of

the

keys

produce

mode.

key

is

of

CTR L key

valid.

of

the

ALT

key

(same

as

te

when

used

code

PCO
PC

J

~---=:'

1'113

IN

~

01::1.

I' (JI.L
UI'

HO"'''

UUWN

f

--+

--

1

keyboard

code

GRAPH

the

operated,

key

the

mode

is

operated,

CTR L key

is

operated,

for

CTAL),

extended

with

other

is

transferred

rs

...

".m

Unil)

';'''':''

I

Fig.

----

I I I I I

8

5

2

.

Graphie

is

valid).

the

same

consists

followed

CAPS

not

valid

data

codes

to

the

l K

iOY

J

:t

!I

6

3

dJ

mode.

to

as

by a CTAL
are

and

.

CPU

CL /

1

•

I

0

in

the

is

transferred

key

alone

codes

entry data
code

keys

alone

command

keys.

11-

2.

(GAAPH)
the

is

entry

+

-

=

When

the

those

of

ignored

SH I

(no

code

consists

when

CPU

in

two

.

FT

is

of

Signal

(2)

Dir;.ection

name

DC

STC

DK

SRK

Key

data

1)

From

CPU

Send

READY

transfer

keyboard

lable

to

keyboard

data

Strobe

and

ACK

None

procedure

to

CPU

11-

signals

1

Keyboard

'READY'

Request

Aequest

ror

Send

to

key

to

Aeceive

to

signal

Send

data)

data

CPU

(strobe

(CPU)

Keyboard:

2)

m:

Repeat

Form

When
r

eads

STC
enable
completes

parity

terminates

tries

nine

CPU

to

.

STC

the

is

set

an

error

the

times.

keyboard

I.

d.c

same

is

set

to

zero, the

result

of

the

to

one,

it

interrupt

the

was

the

data

da 1 d2 1 d' 1 dO

from

data

transfer

detected, the

data

transfer

send

parity

sets

again .

1"·1\

keyboard

check.

OK

to

one

the

CPU,

sequence

keyboard

sequence,

1

When

to

and

.

1f

then

a

liC

src

I

mr

ntr

Ta

set

Keyboard:

CPU:

Keyboard:

CPU:

Keyboard:

(

CPU:

Keyboard:

CPU:

Execution
key

process

disable

both

oe

u 0

0'

I

~

d61

~

d5fdOl

p.nl

u

Fig.

11-

.:3

both

the

and

DR

When

key

other

necessary
completed,
entry

data

OC

is

set
normally
a

time-out

data

send

the

keyboard

the

CPU.

After

acknowledging

CPU

verifies

the

CPU
noise,
routine.

When

waits
mum
occurred,

initialization
0,
one.

Receiving

reQuest
send.

Seeing
waits
Sets
keyboard,
re Quest
send

When

P.ß.

When

zero.

Sets
to
into
is
The
transfer

the

STC

.

and

STe

one

OC.

zero;

CPU

and

STC

until

waiting

keyboard

STC

for

the

STC

STC

to

if

seQuence.

keyboard

to

zero.

the

to

3ms;

occurred,

seQuence.

identifies

It

then

STC

keyboard

the

the

STC

to

then

is

waits

is

to

zero

set

If

no
sets

search,

entry

keyboard

the

CPU.

to

one.

for

sets

SR K to

that

DR

exits

sets

is

set

is

time

routine.

send

Eß,

the

keyboard

is

set

to

be

zero

sets

keyboard

set

to

for

set

again

to

the

result

a

parity

parity

STC

and

code

The

direct

the

When

the

the

STC

to
set
is

control

CPU

to

set

to

STe

one,

STC

read

error

to

one

the

CPU

translation,

data

starts

First.

waiting

keys,

keyboard

OC

zero

the

interrupt,

is

zero. If

transferred

interrupt

to

zero.
one,
to

zero.

500ms.

When

verifying

data

Eß

sets

for

the

one,

to

zero.

read

data

again

for

the

the

to

be

to

one,

P.8.

of

the

error

occurred,

occurred,

to

the ' keyboard

returns

the

keyboard

then

complete

W",it

interrupt,

processing

transferring

it

waits

time

it

is 1ms

exits

is

set

to

to

interrupt

DK

is

data

service

The

maxi

Ir

a

time-out

to

STC=

and

SR K to

STe

to 1 to

next

keyboard

from

to

one

next

reset

to

it

sets

OK

sets

parity

<;heck

UC

L

and

until

.

the

one,

the

one,

the

data

the

to

data

sets

zero.

to

STC

OC

is

1.

the

If

as

SlfK

Fig.

11-

q.

CPU:

is

Keyboard:

is

CPU:

Keyboard:

(

CPU:

­Keyboard:

CPU:

..

(3)

Keyboard

(A)

If

Checking
Connect

system

indicator

(B0C49)

, a ROM

processor

Repeat

the

without

is

five

check

keyboard

the

keyboard

the

keyboard

comes

norm

~heck

(BOC49)

Waits

for

one.

If

OK
identifies
the

seQuence.

one,

the
interrupt
When

the
CPU, it
and

verifies DC=O.

board

identifies
the

interrupt

OK

to

zero.

Verifies
rupting
STC

to

zero

again.
Seeing
reads

data

Sets

STC

STC

to

zero.

Reads

P.ß.

result

of

to

1.

If

to

one;

zero.

The

STC

is

Sets

STC

parity

check.

to

zero

to

terminate
times.

method

is

locked

processor

to

operating

on,

ROM

at

If

all

error

occurred.

is

malfunctioning

up

is

it as a

CPU

the

keyboard

enters

that

the

one

STC

when

to

this

no

parity

if a

keyboard

reset

to

and

the

any

check

the

indicators

to

100ms

still

zero
keyboard

After

sets

oe

keyboard

the

data

If

STC=O as

sequence.

OK

is

keyboard.

to

set

d4,

is

set

to

STC

one

to

to

check

parity

check

error

parity

error

to

zero

one

to

It

then

then

sets

operations.

up:

System

keys . If

for

the

Probably

.

for

0 K

100ms

error

verifying

and

STC

.

is

interrupted

receive

OC

is

noise,

If

OC

zero

70115

The

CPU

then

one,

the

is

reset

to

set

data,

parity,

when

occurred,

occurred,

sets

OK

.

read

the

temporarily

it again

Unit,

then
only

keyboard

come

on,

t~e

to

be set

later,

the

and

exits

that

OK

to

zero,

by

sequence

one,

the

and

exits

is

zero, it sets

after

inter

then

re sets STC

keyboard

zero

. .

then

resets

then

sets

STC

is

it sets

OK

to

zero

when

resul t

of

sets

to

turn

on

the

CAPS

processor

it indicatp.s

keyboard

to

CPU

is

to

the

key·

·

sets

to

the

set

DK

is

the

STC

one,

th e

'71

C:J

D --I-f3 --

F33B

I I I I

[±]I-H+I

6)

Built·in

7)

Single +2 .5

Pin

configuration

clock

to

generator.

+6V

power

supply.

t<

(B)

Same

keys
Cheeking
Conneet
system

key

the

with
held . After
the

keys in
figure.
will go
will
eome
sequently

If

remain

no

If

no

off. If

on,

they

pressed

eontact
operated, the
the

key

cheek

11-3 Key

.

'\..W

t~

~

(11

11

To
cheeked
data
it

is extended

~

fwutH.

IlAlAI

Slngll

1

I

fIoL

II"

f "

___

!JA I A

_____

prevent

twice

is

regarded

t\"YI~

~~Y2

_

__

_ _

search

klY

are

eontaets

keyboard

the

CTRL

making

the

order

defective

any

defective

on.

If a wrong

will 90

.

trouble

CAPS

was

normal.

timing

op.'lIlon

I

eNlllring

---I

ehattering

during

as

to

16.5ms

_

___

----'

Fig.

11-

5

inaperative:

to

the

System

and

ALG (a, c)

sure

all

the

shown

key

contact

contact

key

off

when

exists

when

indicator

_

will

Boun

---4nL-_~;~1-_2_by_I

Fig.11-

and

bounce,

each

search,

correct.

While

if a bounce

Unit,

indicators. come

by

the

exists,

exists,

is

pressed

the

alt

come

..

..

_d._II

b

the

and

the

search

occurs'~

~~-------

keys

arrows

all
alt

and

eorrect

the

on,

___

same

only

and

turn

on

depressed

on,

in

the

the

indicators

the

indicators

the

indicators

key

is

keys

have

indicating

_

___lL

key

data

matching 'key

cycle

is

5.5ms,

the

and

press

above

sub-

been

that

TO

XTALI
XTAU

RESET

SS

JNT

EA

RD

PSEN

WR
ALE
DHO
DDl
OH2
OD3
084

DH5

086
DH7

Vss

20

21

Vcc

Tl

1'27

1'26
1'25
1'24
Pl7
PI6
1'15

1'14

PI3

p

12

1'11
1'10

Voo

PROG

1'23

P22

1'21
1'20

Fig.l1-ß

Pin

functions

1/0

port

(port
(port

latch

store

access

inputs

eon

1)

2)

enable

enable

trol

Pl0-P17:

1/0

P20·P27:

OBO·067:
TO,

Tl:

TFJT:

is

RO:

WR:

ALE

.

PSEN:

RESET:

SS:

EA:
XTAL1,2:
VOO:

port

Oata

bus

Test

Interrupt

Read
Write
Address
Program

Reset

step

Single

External
Ouartz
Standby

lJ

l:'l

I

~A

JA

___

Key

search

sequence

that

for single

taneously

pressed,

are successively

11-4

Eight-bit

Highlights

1)

Single-chip,

2)

6uilt-in

3)

On ·

4)

Interruption

5)

1/0

Oata

chip

port:

bus

2K

128K

8 bits x 2

(serving also

___

fLJl~f.L_

for

key

operation.

key

transferred.

keyboard

8-bit

microprocessor.

x 8

bit

ROM.

x 8

bit

service

capability.

Fig .

two-key

data

processor

RAM.

as

1/0

.......

:

~~1

----::=--::-:c;-:------

11-?

operation

When

for

the

first

port): 8 bits

K~Y2

IJATA

is

th~

two

keys

are

and

second

J..IPD80C49

x 1

same

simul-

as

keys

Keyboard

processor

(80C49)

signal

functions

Table

11-

2

Pin No. Signal

1

2

3

4

5

6

7

B

9

10

11

12

19

20

XTALt

XTAL2

RESET

PSEN

ALE

DBO

DB7

TO

SS

INT

EA

RD

WR

Vss

name

IN/OUT

IN

IN

IN

IN

IN

IN

IN

- N.C

- N.C

-

-

IN

IN

Data

or

READY

Accepts a quartz

Äccepts a Quartz

Initialization

+5V

CPU

GND

N.C

N.C

Returns

GND

input

interrupt

signals

signal

input

signal16MHz)

signal16MHz)

of

BOC49

strobe

input

from

the

from

for

for

ISTC)

keyboard.

the

System

the

internal

the

internaI clock

Description

Unit

"

;

clock

oscillator.

oscillator

.

,

~

21

22

23

24

25

26

27

30

31

32

33

34

35

36

37

38

P20

P21

P22

P23

PROG

VDD

Pl0

P13

P14

P15

P16

P17

P24

.

P25

P26

.

P27

OUT

OUT

OUT

-

- N.C

IN

OUT

OUT

OUT

OUT

-

-

-

-

-

Send

Data

Enables

N.C

+5V

Strobe

CAPS

GRAPH

N.C

N.C

N.C

N.C

N.C

N.C

data

to

the

enable/start

data

send

to

the

keyboard.

indi.!:ator

indicator

System

signal

to

drive

drive

(SRK)

the

signal

signal

Unit

mouse

lOK)

to

ICTS)

".

CPU

_.

...

39

40

Tl

Vcc

IN "

IN

Mouse

+5V

data

power

input

supply

(TX

0)

~~

12. Mouse

The mouse
cursor

s

lJ

rface

be

su

(MZ-IXI0)

is

movement

oE

slIch

pport _d.

a new

is

as

Use

input

controlled

the
it

device,

table.

by

connecting

by

On

a

kind

the

manipulation

the

MZ-5500/5600

to

of

the

pointing

keyboard.

device,

of

series,

the

with

mouse

the

which

on

the

mouse

can

12-1.

°As

surface
center

°The

with
Y

axes)

the

°Including

coordinates,
counted

°The

the
given

U2

reset
read

all

Rt

°As

keyboard

the

°The

in

Operating
the

mouse

of

of

encoder

the

ball

and

rotation

in

value

U2

(4-bit

cycle

internal

as

soon

and

performs

times.

the

U2

of
data
mouse

the

on

next

prfnciple
is

moved

the

desk,

the

mouse

elements

at

right

they

move

of

the

both

counted

reads

is

positive

the

encoder

the

counter

microcomputer)

to

be

counter.

as

the

the

the

~lZ-5500/5600,

the

TXD

handshaked

paragraph.

on

the

the

ball

rotates.

are

in

angle

according

ball.

and

outputs

(U1).

in

U1

is

accumulated

The

U1

value

relative

data

line

has

request

in

with

flat

at

contact

(X

and

to

negative

read

by

in

the

in

is

been

counting

receiving

thci

given

the

keyboard

the

are

the

signal

Fig.12-1

CTRL
of

format.

controller

in

CTRL

Y-axis

thegiven

causes

X-Y

pulse

X-axis

encoder

the

in

the

generator

pulse

cycle

U2

to

timing

of

from

the

send

generator

mouse

the

out

described

NOTES:

1)

HSMOVE

Reads

movement.

2)

MSDIRECT

Real

The

the

time

following

coordinates

mouse

are

data

provided

of

the

input.

for

cursor

the

lOCS

position

module

which

to

control

occurred

by

the

the

mouse.

mouse

'74

TXD

da.te\.

Dutput

i)tart

~rt

,

VI

~

.

DO

Dl

D2

D8

,

D4

D5

D6 D7

,

~~

bit'

-

,

,

--

von

VOL

HGhdsho.ke

CTRL

Löntro\ input

TXD

output

Data

X,Y

SW

request

data

data

1/4800

....

-

l c

TCl

t-

Tn

CTRL

terminated.

whereas

SW
bit)

and ~ coordinates

X
A

and

becomes

condition

is

data
TCL
TCH
TD

(sec)

hQ.r(\..c-ter(

fT

TA

In

no

data

immediately

issued

B.
min
min
max

10/4800

da

ta

request

this

block

.

within

(Relative

500pS

50~lS

750~S

sec)

TB

condition,

is

issued

before

TA

coordinates
Control
Control
Output

± 2 %

rCH

when

and

L
H

data

the
ODe
when

the

TB

pulse
pulse

reply

-.,.

data

data

CTRL

data

are
are

output

blo

output

issued

always
width
width

tim

.\

ck

e

is

is

iSSII

Pc!

(st~rt

as

dat

a

issued.)

Encoder

input

Positive

Ne

gative

·wave

rotation

rctation

form

(X-ENC, Y-ENC)

Direction

·

Direction

in

Phase
Phase

which

Phase

Phase

in

which

A

B

pha

se B

becomes

A

B

phase B becomes

QS

-

-----

positive

-

------

negative

----- H

-----L

wh

----11

----

-----11

--

--

11

en

L

-L

wh

phas

en ph

e A

as

e A

lS

i s

11.

11.

~

~~~~~+-~--------------~KIO

~

X

ENC

~

c

'{ -E NC A

~

c4

+vcc

--------1

r

I :\100 JC(6

: I

L - J

-----L~4_+_~~----------------;1Ri

sW'

•

:~::::W:()=~=::::=:====~8_;

P

0.-1'

~G-:.:::ree..::..:.n-=----+---t--I--;o

~~c.:::e.l:.:..;'O~W~----4~-1

I K

PI

+\'CC

12

Yd

d . E

~o

l6

::

CI>

N

::i

-

ce

C>

:I:

Y B

'r.

Y A

-

:;)

2

eto

15

(Jl

1.

2

8

r-

13

<J3

SHl

:in

He

v

••

10

11

12

13

14

+VCC

Vtid

"

KO

tu

1\2

Ha

K4

K5

Ra

0

..

:r

on

ce

0

:c

.,.

-.

N

:;)

V

8

K7

Rl.:S

••

I.

EX

+-VCC

TXD

-V

er

I

I I S5 I

Ba

I

<':4

j;loopr

I

..J

+VCC

CI

+

10,.,

lOV

_______

15

C2

OD

I)lF

;J;

X

;J;

ca

IOOff

CTRL

+Vcc

GND

GND

Fig.12-2

Mouse

circuit

13.

RTC

(Real

Time

Clock)

13-1.

Operational

As

the

circuit

battery

power

löRD

Iöw~

l~

t

Ir t

real

which

power

off.

CSRrc

time

is

to

Apart

----des

---_t\IA&

----'

1-

l

description

clock
shown
retain

of

the

RP5~1

~

A3

\

J{)tJ

S

D3

is

implemented

in

Fig.2-13-1.

the

clock

RAM

OSe

OUT

oSc.

IN~

can

Ji

and

be

in

the

The

RPSC01

the

data

accessed

r·

I

MZ-5500/5600,

RTC

is

in

the

internal

by

the

user.

f-5V

it

backed

has

RAM

up

the

by

during

the

1 R-

RT(

~""--------'

Fig.13-1

°The

RP5C01

has

the

Although

time

of

WR

signals,

°4-bit
°4-bit
°Internal

years,
°Choice
°All

timer

o±30

seconds
°Possible
°lnternal
°Possible

in

features

the

lORD

because

bidirectional
address . input:

timer
leap
of

the

data

battery

26 x

outp~~

Real

the

figure

shown
RP5C01
and

lOWR

to

year,

24

expressed

adjusting

4-bit

of

time

in

is

accesseQ

is .delayed

the

Table

bus:

AO -A3
keep
month,

hours

backup

RAM

the_

clock

is

the

the

table.

read/write

13-1

time

and

function

alarm

Features

DO -D3

(hours,

day,

12

by

the

siEnal

circuit

LSl

with

via

setup

day
hours

BCD

designed

the

1/0

the

timing

of

minutes,

of

the

(am,

notation

or

16Hz/1Hz

for

address

LS74

the

week)

pm)

the

real

220H
D-flipflop
1s

rather

RPSC01

seconds),

modes

timing

time

clock

to

22FH, the s e

to

create

slow.

calendar

pulse

(100

and

RD

it

tu

and

r

•

?7

•

DUA

QJT

--+-+---i

;c.--+--N

In'(

DUA

name

Pin

CS,

CS

ADJ

AO

-

A3

1m

GND

WR

DO

-

D3

ALARM

OSCIN,
OSCOUT

VCC

QJT

----~-----I

Fig.13-1

Tab]e

Pin

1

,2

3

4,5,6,7

8

9

10

11,12,

13,
15

16,~7

18

RP5COI

No.

14

_.g

access

13-2

RP5C01

Function
For

valid

down

is

connected

lt

has

intervention

reset

it

is

incremented.

Address

the

CPU.

1/0

the

CPU.

OV

control

1/0

RP5COl.
Bidirectional
bus.
Alarm,

32.768KHz

+5V

timing

pin

interfacing

when

CS=H,

detect

the

function

to

zero

within

pin

control

16HzCK,

crystal

supply

names

with

circuit

with

of

the

when

30

to

to

be

input.

input.

data

1HzCK

and

the

CS=L.

of

the

microcomputer.
to
CPU.

it

is
seconds,

59

connected

Low

Low

bus.

pulse

oscillator

functions

external

CS

is

the

device

adjust

With

within

with

for

input

for

input

Connected

output.

device

connected

power

seconds

the

ADJ=H

to

0

the

seconds

the

from

from

with

Open

connection

which

with

supply

without

the

seconds

seconds.

29

address

the

the

the

drain

pins.

becomes

the

and

are

then

bus

RP5C01

to

CPU

CPU

output.

power

CS

are

lf

of

to

the

data

171

OSCOUT

Fig.13-2

°The

RPSCOI
ceramic
divides

°The

CS
the

power

and

Tt2

the

backup

gone

Tr2.

.

time

RPSCOl .

oscillator

it

pin

down

in

inactive

Then

along

:D

(]1

"

()

o .

pin

generates

for

the

detects

condition.
Fig.2-l3-1
battery

f~rst,

the

backup

with

the

IS'

ALARM

configuration

clock
and
counter

a

power

the

pulse
CR
operation.

down,

When

are

active

is

being

then

Tr2.

battery

internal

internally

network

and

power

so

recharged.

This

supplies

RAH.

between

then

is

that

When

isolates

power

sets
on
+SV

by

connecting

OSCIN

the

to

the

is

supplied

power

the

to

the

th

e 32.768KHz

and

OSCOUT,

circuit

personal

is

off,

circuit

to

computer,

to

the

it

on

the

makes

RP5COI, whi c h kee

and

RPSCOi

Tri

right

Tri

ps

and

of

th

p

'i9

d

11

Contents

10

lock
B

bits
4

I

x

13

RAH

f'Same

'""Same

10

01

Mode

assignment

ts

Conten

DO

Dl

D2

D3

10

13

Block

4

x

bits

x x x x

x x x

register
ute

n
1-mi

x

register

register

ute

ur

o
l-h

10-min

x x

x x

register
ek

register

we
of

10-hours

x x

register

register

l-day

10-day

RAM

x

x

x

x

x x x

selector

x x

x

x

x x

unter
co

year

t-Same

MO

register

M1

EN

EN

Timer Alarm Mode

Test

Test

Test

Test

Alarm

~~set

1 0 rSame

Timer

~--,!"~s_e!

--

2

16Hz

ON

3

ON

1Hz

address

internal

RP5COl

13-3

Iable

Contents

DO

D1

I

D2

00

Mode

D3

Contents

- A3

de

AO

Mo

x

counter

counter

cond

ond

l-sec

10-se

0

1

Al~rm

Alarm

Alarm

x

nter

ter

counter

coun

inute
m

lO-minu t e cou

l-

1-hour

2

3

4

Alarm

Al arm day

x

x

x

counter
unter
co

week

of
10-hour

Day

6

5

Alarm

Alarm

x

x

unter
co

counter

-day

l-day

10

7

8

12-hour/24-hour

Leap

x x x

unter
co

nth
mo
l-

y

nter

counter

cou
nth
mo

lO-

l-year

unter
co

10-year

...

9

A

B

C

MO

register

Ml

Alarm Mode

er
m

EN EN

Ti

ter
s

regi

Mode

D

Test Test

Test

Test

Test

E

0

2 1

st er 3
regi

Alarm

reset reset

Timer

16Hz

ON

1Hz

ON

etc.
r,

e
ll

o

et

s

contr

Re

F

read.

always·O·when
and

write

rewhen
ca

is·don't
X

(jj

o

*Mode,

banks

Since

under

00,

which

mode

any

01,

can

registers

mode.

10,

be

11,

has

achieved

are

function

by

writing

assigned

to

to

select

the

the

the

select

same

internal

data

address,

in

register
the
it

can

mode

and

register.

be

revised

RAM

MODE

register

D3
Timer

EN

~

------

*Leap

*12/2

Leap

year
year

l

l

hours

The 24

when

*Reset

DO=O.

controller:

16Hz/lHzCK

CA3,

A2,

All

alarm

Minutes

16HzCK
1HzCK

*Addre,ss

and

Read

*Address

Only

write

*The

can

refer

following

be

to

(A3, A2,

D2
Alarm

EN

------

------

counter:
when D1=DO=0.

selector:

hours

system

With

register

Al,

AO)=(l,l,l,l)=F

registers

above

pulse

pulse

seconds

is

is

0 - D

write

are

E - F

is

possible.

are

used

when

Section

Dl

MI

1

0 0
0

1

1 1

Dl=l,

ON

with

ON

with

possible.

provided
called
3,

Al,

AO)

DO

MO

1

1

0

----

----~

Counted

is

adopted

PM

is

are

reset

are

reset

D2=0.

D3=0.

for

as a subroutine

Software.

(1,1,0,1)

MODEOO:
MODEOI

:

Set
Set

or
or

D

read
read

year.
Write
Write

1:

0:

1:

0:

or

read

ore

ad

Alarm
Alarm
are

Timer

Counte~

up

output
output

disregarded).

to

stops

at

the

RAM

RAM

start.

same

BLOCKiO.

BLOCKli.

enable.
disable

after

time

when DO=l. The It hours

selected.

with

with

the

DO=l.

D1=1.

real

With

time

by

D1=0,

clock

the

machine

time.

alarm,

this.

the

AM

is

related

12/24

(16Hz

year

selected.

languag

hours,

and

is

system

IOCS

e .

leap

1Hz

signals

counted.

is

adopted

modul e . anrl

For

c!,'uli

d

I,

IOCS

name
TIMRD
TU1SET
ONTIM
OFFTIM

Function
Reacls
Sets

the

Enables

Disables

the

real

real

the

the

time

clock.

time

clock.

alarm

interrupt.

alarminj:_e!rupt.

81

I

j

!

13-2.

Total
and

not

~ystem

Se~

Accessing

26

nibbles

11

as

shown

so

large

and

the

flowchart

the

in

those

RTC
internal

in

Table

capacity

Mode

below

internal

RAM

2-13-3,
.

~ 1

for

RAM
are

But,

are

the

provided

they

are

all

RÄMs.

user

accessible.

accessing

in

the

the

battery

for

Mode

methode

RP5C01

backed

10

RTC

are

for

the

up

RAM,

reserved

Mode

though

by

10

the

(2)

(1)

Read

Write

Select
Set

(0,

OA

(X ,x

Write

,0 , ,0

,1,1)

STAAT

mode

, , 0

data

f

STAAT

RAH

register

) -

(X,

0

in

N

block

X,1,0)

RAM

o

NO

[Ex.]

To

write

addre?s

SSUB:

ESUB:

To

read

Mode

of

the

4-bit

OA

of

Mode

CALL
MOV
MOV
OUT

SSUB

DX,22AH

AL,05H

DX,AL

CALL ESUß

HOV

IN

OR
OUT

DX,22DH
AL,DX
AL,03H
DX,AL

RET

HOV

IN

AND
OUT

DX,22DH
AL,DX
AL,OCH
DX,AL

RET

the

4-bit

11

and

to

da

11.

data

store

ta

in

5H

it

in

the

in

the

address
DL.

OA

Select

Set

mode

,

(D.,D.,D"Do)-(X,X,I,O)

OA

(X,X,I,I)

Read

E N

RAM

RAM

block

register

data

NO

*Nibble

CALL
HOV

IN

AND
MOV
CALL

= 4

SSUB
DX,22AH
AL,DX
AL,OFIl
DL,AL

ESUB

bits

14.

PSG
One
eight

(Programmable

channel

o~tave,

I

öl<

[öwl(

()

{ro

IAf!i.

of

Iro,.,

...

rVL

triple

flJC

the

Sound

PSG

chords,

Generator)

is

provided

and

for

it

has

~IJ:t

AY-J-81ll...

BDIR

Bel

the

A

!3

C

the

MZ-5500/5600

following

t----t---t

series

configuration.

+5'1

'

x-r

~~-I!---+

~

J,.

t-5."

to

generate

SF'eak.er-

(3H)

Operational

°The

°Not

figure
address
As

there
cornrnand
as

to
registers
generate

only

has

the
drive
signal

enable

select

Re~et

theory

above

of

230H - 23FH.

are

in

the

have

sound

the

8-bit

(AOOOOH-BFFFFH)

16

above

to

and

PSG

parallel

sfgnal

-----------(1

4HHi

shows

registers

know

been

manage

ineorporates

' I CLÖlk

Fig.14-1

the

AY-3-8912.

in

the

1/0

address.

the

current

prograrnrned,

it

and

1/0

port

(SLO-SL3),

are

sent.

RHn

iA'1G

S

'

DA?

PSG

PSG,

Those

state

eontrol

the

the

sound

on

motor-on

t--Sl2.

J--sL3

cireuit

PSq

control

CPU

which

SL~

SL

M~N

HA61

HAl

~A1.

which

is
registers
and d,ata

is

done

is

therefore

generating

the

signal,

1

can

do

mini-f

be

ne

b

are

in

via

open

funetion,

and

accessed

y

writing

permitted

the

memory.

those

for

loppy

address

registers

other

but,

di

sk

bank

by

the

to

Al.d :ö

the

cont

read

Once

jobs.

it

in

terf nee

selec

5JT

1/0

rol

so

1 h

to

also

t

°Three

mode
the

°The

°pSG

The

For
to

the

MUSIC:
Drives

ElviUSIC:

Data

ZMUSIC:
Similar

sound

to

drive

AUDlO

pin

related
following
detail,

OUT

configuration

PSG

tIte

are

direetly

as

signal

the

speaker

jack

via

10CS

three

refer

Descriptions

PSG

MUSIC.

to

with

set

outputs

the

and

modules

Section

published

the

contents

in

(A,

via

the

emitter

functions

are

provided

Three,

the

ehannel

B,

follower

by

of

C)

from

TA7313

are

shown

for

Software.

GI.

the

musie

A

of

ca3

the

Audio

transistor.

in

the

For

note.

the

PSG

PSG

are

Amplifier

the

next

lOCS

whi

detail

to

generate

ORed

ch contr

and

page.

of

in

the

the

sent.

o l s t

rSG,

sound.

anD10?

through

ll

P

PS

refer

G.

ANALOG

ANALOG
ANALOG

CH

TE

Vec

CH
CH

GND

IO
IOA8
ICA6

IOA4
'CA.

' O
IOAI
IOAO

A7

AI

ST

5V

C

n

B

A

I

7

a

10

II

U

JI

14

iII

m

U

!:I

ZI

n

ZIO

18

11

11

11

16

DAO

DAI
DA!
DA'

DA.
DA5
DA

DA7

LOCK

11

Pin

7 -

15

16

1 7

] 8
19

20

fig.14

No.

1

2

3
4

5

6

14

- 2 AY-3-8912

fable

Signal

ANALOG

name

CH

C

TESTl

VCC
ANALOG
ANALOG

CH

CH

B
A

GND

IOA7

- 0

CLOCK

RESET

A8

BDIR
BC2
BCI

pin

14-1

In/Out

Out

Out
Out

In/Out
In

In

In

In
In
In

configuration

AY-3-8912

Function
Analog
Test

pin

should
+5V

supply
Analog
Analog
OV

1/0

port
Tone
reference

Input
the

start,
Auxi1iary
permit
addition

Bus

.Bus

Bus

These

external
PSG.
manner

signal

output

description

channe1

during

be

unconnected.

output
output

channel

channe1

noise,envelope

input

it

(0)

resets

of

a 10w

address

a memory

to

the

direction

control
control

bus

control

and

Signals

by

the

1

2

internal

are

PSG.

chip

generator

(2MHz)

signal

bit
space
area

signals

decoded

C

manufacture

B

A

to

this

all

registers.

which

is

expansion

specified

control

bus

operation

the

in

which

timing

line

provided

in

by

DA7 -DAO.

all

following

of

at

to

the

BC2

BDIR

\

0

Bel

0 0

PSG

function

INACTIVE

The PSG/CPU

inactive

and

becomes

bus

DA7-DAO

high

impedance.

Pin

No.

Signal

name'

Inlaut

Function

21

-28

DA7 -DAO

In/Out

BDIR

BC2

0 1

0

1

0

1

0

1

0
0

1
1 1 0

1 1

In

the

data

register

array

mode.

In

the

address

select

comp!~s~

the

the

BCl

PSG
LATCH
Indicates
retains
address

the
INACTIVE

0

READ

1

Data
current
on
LATCH

0

INACTIVE

1

WRITE

Indicates
retains
register
current

1

LATCH

mode,

corresponds

bits,

mode,

register

ad~!ess

function

ADDRESS

the
to

PSG.

FROM
in

the
address

the

PSG/CPU

ADDRESS

Ta

PSG

the

latched

\.

address.

ADDRESS

B7 -BO

DA3 -DAO

number

i!1P~~t

that

register

be

PSG

register

that

data

and

_ .

the

latched

are

bus.

the

in
at

to

the

in

the

are
DA7 -DA4

bus

at

sent

bus

the
the

data

used

in

to

to

I

~5

15.
The
MZ-5600

Video

video

display

display

which

circuit

features

circuit

the

is

basically

following.

the

same

for

both

the

MZ-5500

and

15-1.

Features
°Bit
°The

map

~PD7220

controller.
°Meets
°Possible

the

Window

°Possible

display

faster
°Incorporation

input

etc.

pr

e s e

alt

has

192KB

°The

hardware

01

ncorporates

~Possible

[Color
(Color

°Possible

0,
°Possible
°Possible
°Possible
°Possible

hardware

method,

resolution

to

to

cycle

access

pe

rmits

However,

nt.

96KB

when

to

mode)

CRT)

I J

and

of

th~

video

complete

Graphie

Display

of

640 x 400,

perform 'multiple

Controller

access

is

from

of

the

divided

the

the

external

(WOC)

CPU

superimposition

of

the

option

character

the

handle

both

the

the

video

is

generator

pallet

eight

Table

to

2.

to
to
to
to

by

make

assign
make

specify
change

means

choice

~

eight

choice

priority

any

of

aisplay

graphie

video

into

to

software

RAH
used.

function

colors

15-1

of

tones

of

color

the

pallet

circuit

display

Controller

640 x 200,

window

of

the

RAM

the

the

display

hardware.

from

GDC

video

clock

on

sucl1

and

as a standard

is

not

and

color

and

eight

Mode

eight

specification

colors

for

eight

for

to

border
desired

any

function.

(GDC)

either

cycle

RAM

input

as

TV

the

provided

the

of

other

is

used

320 X 400,

up

to

the

and

the
with
and

less

the

broadcasting,

hardware

equipment

as

priority

monochrome

for

each

background

colors.

four

colors

sev~n

for

the

and

320 x 200

four

CPU

windows

or

CPU

cycle,

waits.

externa~

dc

not

and

can

standard.

function.

tone.

dot

for

color

(200-raster

and

colors

video

the

GDC.

vertical

VTR,

support

be

,

three

of

each

any

in

dots.

by

means

it

video

it

expanded

planes

window.

eRT

only)

one

color.

terms

display

As

the

permits

sync

disk,

at

of

the

of

to

of

(Monochrome

°Possible

0,

1,

and

°Possible
°Possjble
°Possible
°Possible

hardware

[Monochrome

°Possible
°Possible

CRT

to

2.
to
to
to

to

by

mode)
to
to

tone)

make

assign

make

specify

change

means

overlay
reverse

choice

eight

choice

priority

any

of

planes,
any

the

of

eight

stages

of

eight

tone

pallet

0,

window.

for

to

1,

colors

of

the
border
desired

any

of

function.

and

for

each

background

tones.

four

other

2.

(200-raster

tones

seven

dot

for

for

each

and

tones

three

any

in

planes

window.

eRT

only)

one

tone.

terms

of

of

the

Table

15-2

Maximum

screen

frames

by

the

hardware

Hemory
size

640x400
color

96KB

192KB

MZ-5500/5600

400

,,,,,.r

displ-v

1ß"

---,

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VS

-U

U17m••::

VIDEO

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d i

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2

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6

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4

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timings

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18

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16.09ms

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color

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4

24.86 K Hz

56.49Hz

15.699KH.

640x200

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12

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color

8

320x200
B/W

12
24

HS W i

V I DEO

VS I 12739rns-U

2..42ms .• '

VIDEO

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a

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b

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640x200 320x200

c

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the

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the

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MZ1D14
MZ1D18

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base

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3

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of

Others

14.32

1.79

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base

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320x200

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HZ1D14
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Others

7.16

1.79

Unit:

15-2.

i)

MHz

Use

of

Video
To
written
bit
has
and

the

shows
(8

(16

S

IOCS*

NOTE-1
Tne
WOC.
hardware
data
address,
display

ec

make

bits)

tion

RJ.M

position
to
window

word

bits).

wh

:

display

Only

should

data
in

be

video

started

display

displayed

the

video

on

the

to

controller

will

th

e memory map

and

Three,

en

be

one

word

As

many

Software,

programming

address

the

low

to

read

be

three

read

30000H - 3FFFFH

to

distort.

circuit

on
RAM.
display
display

setup.

displayed

of

the

(16

IOCS

by

is

set' by

otder

data

is

directed

the

video

A

single

screen.

can

Sixteen

from

video

bits),

modules

for

more

the

machine

the

15

bits

for

(GDC) , for

(software

screen,

bit

be

specified

left
RAM.

and

the

are

provided

details.

language.

SCROLL

of

the

displaying

by

VDS

control)

of

From

bits

to

The

GDC

of

the

each

the

video

what

in

of

right

CPU

accesses

for

It

is

command

address

from

the

display

independent

RAM

location

unit

the

in

of

bit

their

accesses

in
displaying,
recommended

of

the

(GDC)

planes,

WDC.

address

dot

corresponds

of

the

word

0

to

the

order.

in

unit

unit

GDC

and

are

uecoded

0,

1,

However,

may

using

of

of

one

refer

to

use

VMA

and

giving

has

to

vi.deo

the

bit

Fig.l5-l

one

word

to

of

by

2.

cause

to

be
one
RAM

GDC~

15

of

byte

the

the
the

Which

the
the

·

·

NOTE-2:
When

the

CPU

accesses
DFFFFH, E8000H - EFFFFH,
expansion

XA

CK

from the

is

VRAH'

not

HI

does

returned.
chip

(CRT

NOTE-3 :
DMA

i8

not

permitted

not

possible
VRAM.
bi

ts

And, do

of

the

to

make

not

DMA,

set

as

malfur:ction.

jj)

GDC

(~PD7220)

Since
sync
of
address

Also,

is

the

are

the

SYNC

130H

see

attached

GDC

is

generated

command
is

also

NEC

~PD7220

at

the

used

from

end

the

expansion

NMI

not

exist.

However,

controller

for

the

direct

the

i t may

for

the

of

the

contained

GDC

User's

of

this

VRAM

loading

VRAM

cause

the

GDC.

GDC.

will

not

(Normally,

for

the

LSI)

area

area

CRT

controller,

Table

The

in

the

Manual

text.

VRAM

area

be

expansion

even

of . COOOOH

and

saving

OCH,

the

VRAM

15-3

value

table.

for

of

applied

NMI

if

the

ODH,

to

·

See

the

C8000H - CFFFFH, D8000H -

to

the

CPU

even

is

automatically

VRAM,

VRAM

- EFFFFH,

from

emd

the· floppy

OEH

be

af f ec

horizontal

shows

set

the

i.n

Table

detail

XACK
does

in

list

the

15-4

of

the

ted

sync

1/0

the

is

not

so

high

or

and

of

for

GDC.

applied

returned

exist.)

that,
disk

result

parameters

port

others.

if

it

to

order

vertical

of

the

Summary

the

if

is

the

4

in

;'~IOCS

:

Short

used

subroutine

words

to

control

*Gnc:

Short

MZ-5500/5600.

*VRAM:

Video

words

RAM.

by

for

for

the

1/0

Contrc;>l

the

machine

Graphie

hardware.

language.

Display

System

The

Controller

which

user

indicates
can

use

vuPD7220)

the

it

I

when

j

which

software

called

is

used

module

as

for

the

a

CPU

Unit: 8 bits

32KB

GDC

PLANE2
EXPANSION

E8000 14000

EOOOO

D8000

DOOOO

C8000

COOOO

---------------

PLANE2

PLANEl

EXPANSION

..

_-------------

PLANEl

PLANEO

EXPANSION

--------------

PLANEO

'

10000

00000

08000

04000

00000

UNIT:

I

J

16

16KW

,\

bits

EXPANSION:

Expansion

Fig.l5-1

VRAM

VRAM

memory

$5~

map

d

Table

15-3

GDC

setup

Resolution
Display
H

display
HFP
HS
HBP
V

display

VFP

VS
VBP

130

H

Others

IDI3:

NOTE-I:
Set

NOTE-2:
Set
Set
Set

MZIDI3

to

to
to
to

(H

1 )

L/R=1 (2

IM=l

by

double

DGD=1

by

640x400
ID14,14,1811D13,14,1811DI3,14,18

0

---

IDI4:

lines),by

the

SCROLL

value

the

I 320x400 I

40

400 200

34 38
4

I
I

NOTE-2

MZIDI4

the

command.

of

640

dots

VECTW

command.

5
4
5

6
8

CSRFORM

mode

640x200

0 I

I

J

NOTE~l

IDIB:

MZID1B

conunand.

by

the

PITCH

Others

40

6
4
7

21

3

---

command.

320x200
1D13,14,16

---

---

---

---

---

---

---

---

---

---

Others

40

6

4

7

200

21

3

38

5

NOTE-2

~

For

graphics

CAUTION:

320x200 mode

and

is

display,

not

applicable

refer

to

the}APD7220

for

the

User's

ID13, ID14,

Manual.

and

IDI8.

qo

iii)

Window

controller

(LZ90E07,

LZ9lF07)

cGeneral

The window
desired

A

description

controller

location

v-

RA

t1

Fig.lS-2

of

of

the

B

the

WDC

displ,ays

display

~

a

rectangular

screen

Here,
A, B, C,

window

as

shown

rectangular

area

in

Fig.l i -2.

eR

T

and D are

from

areas

called

the

of

VRAM

Background

in

the

color

°Features

(1)

A maximum

(2)

Euch window

windows.

(3)

When
overlaid

(4)

It

use

°WDC

registers

(1)

RNO

Register

IX x x x !

(2)

Priority
Priority

there

is

possible

of

register

of

four

ean

ar

display

the

window

number

RNO

register
is

set

l 8

have

.e

three

td

(1/0

(0 -12)

to

bits--7

windows

its

VRAM

of

two

make

funetion.

address

RNO=O-12

direct

(1/0

address

window.

can
priority

planes,

or

three

110H)

is

be

output

set.

displayed.

specified,

it

planes.

112H)

is

of

possible

the

inputted

and,

it

to

allows

display

address

overlay

by

plane

without

of

or

the

RNO=O

I

PWO IPWl!

.

\

\...-------

pW21

PW3

!

of

the
the

windm.,;r

the

window 1

the

window 0

window ' 3

2

.,

\

.L-

Pr~ority

.'---

\

Prl0rity
Priority
Priority

of
of
of

q,\

°The

an
°All
°lhe

the

priority

opposite

priority
windm.J
address

3 among

to

tho~e

must

function

from

the

of

be

different

i5

GDC

all

BASIC.)

not

is

has

the

highest

each

other.

e~fective

directly

when

sent

priority.

all

priorities

out.

(Be

careful

are

set

as

to

it

is

0 and

P

°Window

VMA*1

RNO

1

2

3

4

~

.

5
6

7

8

9

10

11

12

°Register

The

priori

each

register

one

automatical1y

register

and

VDS*2

8

VMAOL

VHAOH
x x x x
VMA1L

VMAIH

x x x

VMA2L

VMA2H

x x x

VMA3L

VMA3H

x x x

setup

ty

(1/0

are

bits

xlVDSO

x xlVDS1

xlvnS2

x

x xlVDS3

Fig.1,5-3

register

number

each

address

set

to

Bias

Bias

VRAM

Bias
Bias
VRAM
Bias
Bias
V
Bias
Bias
VRAM

and

to

RNO

time

112H)

window.

address,
address,
data
address,
address,

data

address,
address,

data

RAH

address,

address,

data

the

register.
written,

select

select

select

select

window

low

high

low

high

low

high

low

high

register

Since

only

J

J

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11

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discussing
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Fig.15-4

for

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the

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NOTE-1 :
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Fig.15-5

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NOTE-2:
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NOTE-3:
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Fig.15-?

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